20GHz large dynamic range logarithmic detector
By designing a 20GHz large dynamic range logarithmic detector, employing a limiting amplifier, rectifier, and adder module, and adding DC offset cancellation and temperature compensation modules, the area and power consumption issues in detector bandwidth expansion were solved, realizing a high-performance communication system with wide bandwidth and low power consumption.
Patent Information
- Application Number
- CN202511644465.5
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-11-11
- Publication Date
- 2026-02-17
AI Technical Summary
Existing detectors, when used to extend the bandwidth of limiting amplifiers, suffer from problems such as increased area, higher power consumption, and more complex structure, making it difficult to meet the needs of high-performance communication systems.
A 20GHz large dynamic range logarithmic detector was designed, employing a limiting amplifier module, a rectifier module, and an adder module, and incorporating a DC offset cancellation module, a temperature compensation module, and a bandgap reference module. Wide bandwidth and low power consumption are achieved using SiGe HBT devices.
It achieves a 50dB dynamic range in a wide frequency range of 1GHz to 20GHz, and features low power consumption, high gain, and good temperature consistency, meeting the requirements of high-performance communication systems.
Smart Images
Figure CN121547066A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of broadband detector technology, and in particular to a 20GHz large dynamic range logarithmic detector. Background Technology
[0002] Logarithmic detector technology is a technique that converts radio frequency (RF) power signals logarithmically to baseband. Detector devices can be used as standalone detector chips in signal processing, broadcasting, television, radar, handheld electronic devices, and other fields, or as sub-modules in RF analog front-ends to convert RF input power signals into baseband signals.
[0003] With the development of the electronic information industry and the advancement of 5G, especially the development of electronic products, the requirements for parameters such as accuracy, sensitivity and dynamic range of receiving equipment are becoming increasingly higher. As a key module of the receiver, the detector determines important factors such as the receiver's sensitivity and bandwidth, which affects the performance of the entire communication system.
[0004] The bandwidth performance of a detector is determined by the bandwidth of the cascaded limiting amplifier within it. Currently, various techniques have been researched both domestically and internationally to extend the bandwidth performance of limiting amplifiers, but these have introduced other problems, such as sacrificing area, reducing low-frequency gain, increasing power consumption, and increasing structural complexity. With the development of electronic information technology, higher demands are being placed on the trade-offs between various indicators such as circuit area, power consumption, and integration density. Traditional structures can no longer guarantee the realization of high-performance detector circuits. Therefore, it is essential to design broadband limiting amplifiers and broadband large dynamic range detectors in the system. Summary of the Invention
[0005] The purpose of this invention is to provide a 20GHz large dynamic range logarithmic detector to solve the problems in the background art.
[0006] To address the aforementioned technical problems, this invention provides a 20GHz large dynamic range logarithmic detector, comprising:
[0007] The limiting amplifier module limits and amplifies the input signal;
[0008] Several rectifier modules convert the input signal of the limiting amplifier module into a detection current;
[0009] The adder module summarizes the detected current from the rectifier module and converts it into a voltage output through a resistor.
[0010] In one embodiment, the 20GHz large dynamic range logarithmic detector further includes a DC offset cancellation module, a temperature compensation module, a bandgap reference module, and a bias module; wherein,
[0011] The DC offset cancellation module is used to adjust and reduce the DC level error of the differential signal of the limiting amplifier module;
[0012] The temperature compensation module is connected to the adder module to improve the temperature consistency of the output of the 20GHz large dynamic range logarithmic detector.
[0013] The bandgap reference module and the bias module provide stable bias voltage and current for the limiting amplifier module, the rectifier module, the DC offset elimination circuit and the temperature compensation module.
[0014] In one embodiment, the limiting amplifier module includes a first NPN bipolar transistor to a twenty-second NPN bipolar transistor, a first resistor to a thirty-ninth resistor, and a first capacitor;
[0015] The base of the first NPN bipolar transistor is connected to the positive differential input port INP. Its collector is simultaneously connected to the second terminal of the first resistor and the base of the third NPN bipolar transistor. Its emitter is simultaneously connected to the collectors of the thirteenth and fourteenth NPN bipolar transistors. The base of the second NPN bipolar transistor is connected to the negative differential input port INP. Its collector is simultaneously connected to the second terminal of the second resistor and the base of the fourth NPN bipolar transistor. Its emitter is simultaneously connected to the collectors of the thirteenth and fourteenth NPN bipolar transistors. The base of the third NPN bipolar transistor is simultaneously connected to the collector of the first NPN bipolar transistor and the second terminal of the first resistor. Its collector is simultaneously connected to the second terminal of the fifth resistor and the first differential input port INP. The positive output port VOP1 is connected to the first terminal of the ninth resistor and the base of the seventh NPN bipolar transistor. The emitter is connected to the first terminal of the seventh resistor. The second terminals of the ninth and tenth resistors are both connected to the positive power supply terminal VDD. The base of the fourth NPN bipolar transistor is simultaneously connected to the collector of the second NPN bipolar transistor and the second terminal of the second resistor. The collector is simultaneously connected to the second terminal of the sixth resistor, the first differential output negative port VON1, the second terminal of the tenth resistor, and the base of the eighth NPN bipolar transistor. The emitter is connected to the first terminal of the eighth resistor. The second terminals of the seventh and eighth resistors are simultaneously connected to the collectors of the fifteenth and sixteenth NPN bipolar transistors. The fifth NPN bipolar transistor... The base of the sixth NPN bipolar transistor is connected to both the second terminal of the third resistor and the first terminal of the fifth resistor. Its collector is connected to the positive power supply terminal VDD, and its emitter is connected to the first terminal of the first resistor. The first terminal of the third resistor is also connected to the positive power supply terminal VDD. The base of the seventh NPN bipolar transistor is connected to the first terminal of the ninth resistor, the first differential output positive port VOP1, the second terminal of the fifth resistor, and the collector of the third NPN bipolar transistor. Its collector is connected to the positive power supply terminal VDD, and its emitter is connected to the second differential output positive port VO. P2 and the first terminal of the eleventh resistor; the base of the eighth NPN bipolar transistor is simultaneously connected to the second terminal of the tenth resistor, the first differential output negative port VON1, the second terminal of the sixth resistor, and the collector of the fourth NPN bipolar transistor, with the collector connected to the positive power supply terminal VDD, and the emitter simultaneously connected to the second differential output negative port VON2 and the first terminal of the twelfth resistor; the base and collector of the ninth NPN bipolar transistor are both connected to the positive power supply terminal VDD, and the emitter is connected to the first terminal of the thirteenth resistor, with the second terminal of the thirteenth resistor connected to the first terminal of the fifteenth resistor; the base and collector of the tenth NPN bipolar transistor are both connected to the positive power supply terminal VDD, and the emitter is connected to the first terminal of the fourteenth resistor, with the second terminal of the fourteenth resistor connected to the output port VO;The base of the eleventh NPN bipolar transistor is connected to the first terminal of the seventeenth resistor. Its collector is simultaneously connected to the bias current IBIAS, the first terminal of the first capacitor, and the base of the twelfth NPN bipolar transistor. Its emitter is connected to the first terminal of the twenty-eighth resistor. The base of the twelfth NPN bipolar transistor is simultaneously connected to the first terminal of the first capacitor, the bias current IBIAS, and the collector of the eleventh NPN bipolar transistor. Its collector is connected to the positive power supply terminal VDD. Its emitter is simultaneously connected to the second terminal of the seventeenth resistor, the first terminal of the eighteenth resistor, and the first terminal of the twenty-ninth resistor. The base of the thirteenth NPN bipolar transistor is connected to the second terminal of the eighteenth resistor. Its collector is connected to the collector of the fourteenth NPN bipolar transistor. Its emitter is connected to the negative power supply terminal GND through the thirtieth resistor. The fourteenth NPN... The base of an N-type bipolar transistor is connected to the second terminal of the nineteenth resistor, the collector is connected to the collector of the thirteenth NPN bipolar transistor, and the emitter is connected to the negative power supply GND through the thirty-first resistor. The base of the fifteenth NPN bipolar transistor is connected to the second terminal of the twentieth resistor, the collector is connected to the collector of the sixteenth NPN bipolar transistor, and the emitter is connected to the negative power supply GND through the thirty-second resistor. The base of the sixteenth NPN bipolar transistor is connected to the second terminal of the twenty-first resistor, the collector is connected to the collector of the fifteenth NPN bipolar transistor, and the emitter is connected to the negative power supply GND through the thirty-third resistor. The base of the seventeenth NPN bipolar transistor is connected to the second terminal of the twenty-second resistor, the collector is simultaneously connected to the collector of the eighteenth NPN bipolar transistor and the second terminal of the eleventh resistor, and the emitter is connected to... The base of the eighteenth NPN bipolar transistor is connected to the second terminal of the twenty-third resistor, and its collector is simultaneously connected to the collector of the seventeenth NPN bipolar transistor and the second terminal of the eleventh resistor. The emitter is connected to the negative terminal of the power supply GND through the thirty-fifth resistor. The base of the nineteenth NPN bipolar transistor is connected to the second terminal of the twenty-fourth resistor, and its collector is simultaneously connected to the collector of the twentieth NPN bipolar transistor and the second terminal of the twelfth resistor. The emitter is connected to the negative terminal of the power supply GND through the thirty-sixth resistor. The base of the twentieth NPN bipolar transistor is connected to the second terminal of the twenty-fifth resistor, and its collector is simultaneously connected to the collector of the nineteenth NPN bipolar transistor and the second terminal of the twelfth resistor. The emitter is connected to the negative terminal of the power supply GND through the thirty-seventh resistor. The base of the 21-type NPN bipolar transistor is connected to the second terminal of the 26th resistor, the collector is connected to the second terminal of the 15th resistor, and the emitter is connected to the negative power supply terminal GND through the 38th resistor. The base of the 22-type NPN bipolar transistor is connected to the second terminal of the 27th resistor, the collector is connected to the second terminal of the 16th resistor, and the emitter is connected to the negative power supply terminal GND through the 39th resistor. The first terminal of the 16th resistor is connected to the output port VO. The first terminals of the 18th, 19th, 20th, 21st, 22nd, 23rd, 24th, 25th, 26th, and 27th resistors are interconnected.
[0016] In one embodiment, the DC offset cancellation module includes a 23rd NPN bipolar transistor to a 38th NPN bipolar transistor, a 40th resistor to a 57th resistor, and a second capacitor to a fifth capacitor;
[0017] The base of the 23rd NPN bipolar transistor is connected to the output voltage signal VM of the last stage limiting amplifier module, the collector is connected to the positive power supply VDD, and the emitter is connected to the first terminal of the 42nd resistor. The base of the 24th NPN bipolar transistor is connected to the output voltage signal VP of the last stage limiting amplifier module, the collector is connected to the positive power supply VDD, and the emitter is connected to the second terminal of the 43rd resistor. The base of the 25th NPN bipolar transistor is connected to the second terminal of the 42nd resistor, the collector is connected to both the second terminal of the 40th resistor and the first terminal of the 44th resistor, and the emitter is connected to the collector of the 34th NPN bipolar transistor. The base of the 26th NPN bipolar transistor is connected to the first terminal of the 43rd resistor, and the collector is connected to the 41st resistor. The second terminal of the NPN transistor and the first terminal of the forty-fifth resistor are connected, with the emitter connected to the collector of the thirty-fourth NPN bipolar transistor. The first terminals of the forty and forty-first resistors are both connected to the positive power supply terminal VDD. The base of the twenty-seventh NPN bipolar transistor is connected to the second terminal of the forty-fourth resistor, and its collector outputs the current signal IOP from the DC offset cancellation module. Its emitter is connected to the first terminal of the forty-sixth resistor. The base of the twenty-eighth NPN bipolar transistor is connected to the second terminal of the forty-fifth resistor, and its collector outputs the current signal IOM from the DC offset cancellation module. Its emitter is connected to the first terminal of the forty-seventh resistor. The base of the twenty-ninth NPN bipolar transistor is connected to the reference current Iref, its collector is connected to the positive power supply terminal VDD, and its emitter is simultaneously connected to the thirty-ninth NPN bipolar transistor. The base of the NPN bipolar transistor, the base of the 31st NPN bipolar transistor, and the first terminal of the 50th resistor are connected, with the second terminal of the 50th resistor connected to the negative power supply GND. The bases of the 30th and 31st NPN bipolar transistors are interconnected. The collectors of both the 30th and 31st NPN bipolar transistors are connected to the reference current Iref. The emitter of the 30th NPN bipolar transistor is connected to the negative power supply GND through the 48th resistor, and the emitter of the 31st NPN bipolar transistor is connected to the negative power supply GND through the 49th resistor. The bases of the 32nd, 33rd, and 34th NPN bipolar transistors, and the 35th... The bases of the NPN transistors 36, 37, and 38 are all connected to the emitter of the NPN transistor 29. The collector of the NPN transistor 32 is connected to the first terminal of the resistor 42, and its emitter is connected to the negative power supply terminal GND through the resistor 51. The collector of the NPN transistor 33 is connected to the second terminal of the resistor 43, and its emitter is connected to the negative power supply terminal GND through the resistor 52. The collector of the NPN transistor 34 is simultaneously connected to the emitters of the NPN transistors 25 and 26, and its emitter is connected to the negative power supply terminal GND through the resistor 53.The collectors of the 35th, 36th, 37th, and 38th NPN bipolar transistors are connected together to the second terminals of the 46th and 47th resistors. The emitter of the 35th NPN bipolar transistor is connected to the negative power supply terminal GND through the 54th resistor; the emitter of the 36th NPN bipolar transistor is connected to the negative power supply terminal GND through the 55th resistor; the emitter of the 37th NPN bipolar transistor is connected to the negative power supply terminal GND through the 56th resistor; and the emitter of the 38th NPN bipolar transistor is connected to the negative power supply terminal GND through the 57th resistor.
[0018] The first terminal of the second capacitor is connected to the first terminal of the forty-fourth resistor, and the second terminal of the second capacitor is connected to the negative power supply terminal GND; the first terminal of the third capacitor is connected to the second terminal of the forty-fourth resistor, and the second terminal of the third capacitor is connected to the negative power supply terminal GND; the first terminal of the fourth capacitor C4 is connected to the first terminal of the forty-fifth resistor, and the second terminal of the fourth capacitor is connected to the negative power supply terminal GND; the first terminal of the fifth capacitor is connected to the second terminal of the forty-fifth resistor, and the second terminal of the fifth capacitor is connected to the negative power supply terminal GND.
[0019] In one embodiment, the temperature compensation module includes a first PMOS transistor to a ninth PMOS transistor and a first NMOS transistor to an eighth NMOS transistor; wherein,
[0020] The source terminals of the first to ninth PMOS transistors are all connected to the positive power supply terminal VDD. The gate terminals of the first, second, third, and fourth PMOS transistors are interconnected. The drain terminal of the first PMOS transistor is connected to the drain terminal of the first NMOS transistor. The drain terminal of the second PMOS transistor is connected to the bias current Ibias1. The drain terminal of the third PMOS transistor is connected to the bias current Ibias2. The drain terminal of the fourth PMOS transistor is connected to the bias current Ibias3.
[0021] The gates of the fifth PMOS transistor, the sixth PMOS transistor, the seventh PMOS transistor, the eighth PMOS transistor, and the ninth PMOS transistor are interconnected. The drain of the fifth PMOS transistor is connected to the drain of the second NMOS transistor. The drain of the sixth PMOS transistor is connected to the bias current Ibias_LA1. The drain of the seventh PMOS transistor is connected to the bias current Ibias_LA2. The drain of the eighth PMOS transistor is connected to the bias current Ibias_LA3. The drain of the ninth PMOS transistor is connected to the bias current Ibias_LA4.
[0022] The gate of the first NMOS transistor is connected to the enable signal EN1, and its source is connected to the drain of the fourth NMOS transistor. The gate and drain of the third NMOS transistor and the gate of the fourth NMOS transistor are connected to the reference current Iref. The sources of the third NMOS transistor and the fourth NMOS transistor are both connected to the negative power supply GND. The gate of the second NMOS transistor is connected to the enable signal EN2, and its source is connected to the drain of both the seventh and eighth NMOS transistors. The gate and drain of the sixth NMOS transistor and the gate of the seventh NMOS transistor are connected to the IPTAT current. The gate of the eighth NMOS transistor is connected to the gate of both the fifth and fourth NMOS transistors. The drain of the fifth NMOS transistor is connected to the IPTAT current. The sources of the fifth, sixth, seventh, and eighth NMOS transistors are all connected to the negative power supply GND.
[0023] In one embodiment, the 20GHz large dynamic range logarithmic detector is fabricated based on a SiGe HBT device design.
[0024] The 20GHz large dynamic range logarithmic detector provided by this invention has the following beneficial effects:
[0025] (1) The present invention adopts a broadband, two-stage amplification limiting amplifier structure, which has lower power consumption and higher gain compared with the traditional structure, and has a good trade-off between area, power consumption and performance.
[0026] (2) The present invention adopts a DC offset calibration and temperature compensation module structure. After verification, the temperature consistency of the detector output curve is good after temperature compensation.
[0027] (3) This invention is based on the design and fabrication of SiGe HBT devices, giving full play to the advantage of the high characteristic frequency of HBT devices. It has been verified that a wideband detector with a wide frequency of 1GHz to 20GHz, a dynamic range of 50dB, and small temperature drift can be realized. Attached Figure Description
[0028] Figure 1 This is a schematic diagram of the structure of the 20GHz large dynamic range logarithmic detector provided by the present invention;
[0029] Figure 2 This is a circuit diagram of the limiting amplifier module in a 20GHz large dynamic range logarithmic detector;
[0030] Figure 3 This is a circuit diagram of the DC offset calibration module in a 20GHz large dynamic range logarithmic detector;
[0031] Figure 4 This is a circuit diagram of the temperature compensation module in a 20GHz large dynamic range logarithmic detector. Detailed Implementation
[0032] The following detailed description, in conjunction with the accompanying drawings and specific embodiments, provides a further detailed explanation of the 20GHz large dynamic range logarithmic detector proposed in this invention. The advantages and features of this invention will become clearer from the following description. It should be noted that the accompanying drawings are all in a very simplified form and use non-precise scales, and are only used to facilitate and clarify the illustration of the embodiments of this invention.
[0033] This invention provides a 20GHz large dynamic range logarithmic detector, the structure of which is as follows: Figure 1 As shown, the system includes a limiting amplifier module (LA), a rectifier module (DET), and an adder module (Σ). Specifically, the LA limits and amplifies the input signal VIN; the DET converts the input signal of the LA into a detection current; and the Σ sums the detection current of the DET and converts it into a voltage VO output via a resistor. Furthermore, the 20GHz large dynamic range logarithmic detector of this invention also includes a DC offset cancellation module, a temperature compensation module, a bandgap reference module, and a bias module. The DC offset cancellation module adjusts and reduces the DC level error of the differential signal of the LA; the temperature compensation module is connected to the Σ and is used to improve the temperature consistency of the 20GHz large dynamic range logarithmic detector output; the bandgap reference module and the bias module provide stable bias voltage and current for the LA, DET, DC offset cancellation circuit, and temperature compensation module.
[0034] Figure 2This is a schematic diagram of the circuit structure of LA. LA includes NPN bipolar transistors N1 to NPN bipolar transistors N22, resistors R1 to R39, and capacitor C1. The base of NPN bipolar transistor N1 is connected to the positive differential input port INP, its collector is connected to both the second terminal of resistor R1 and the base of NPN bipolar transistor N3, and its emitter is connected to both the collectors of NPN bipolar transistors N13 and N14. The base of NPN bipolar transistor N2 is connected to the negative differential input port INN, its collector is connected to both the second terminal of resistor R2 and the base of NPN bipolar transistor N4, and its emitter is connected to both the collectors of NPN bipolar transistors N13 and N14. The base of NPN bipolar transistor N3 is connected to both the collector of NPN bipolar transistor N1 and the second terminal of resistor R1, and its collector is connected to both the second terminal of resistor R5 and the first differential input port. The positive output port VOP1, the first terminal of resistor R9, and the base of NPN bipolar transistor N7 are connected together. The emitter is connected to the first terminal of resistor R7. The second terminals of resistor R9 and R10 are both connected to the positive power supply terminal VDD. The base of NPN bipolar transistor N4 is simultaneously connected to the collector of NPN bipolar transistor N2 and the second terminal of resistor R2. The collector is simultaneously connected to the second terminal of resistor R6. The first differential output negative port VON1, the second terminal of resistor R10, and the base of NPN bipolar transistor N8 are connected together. The emitter is connected to the first terminal of resistor R8. The second terminals of resistors R7 and R8 are simultaneously connected to the collectors of NPN bipolar transistors N15 and N16. NPN bipolar transistor N... The base of NPN bipolar transistor N5 is connected to the second terminal of resistor R3 and the first terminal of resistor R5. Its collector is connected to the positive power supply terminal VDD, and its emitter is connected to the first terminal of resistor R1. The first terminal of resistor R3 is also connected to the positive power supply terminal VDD. The base of NPN bipolar transistor N6 is connected to the second terminal of resistor R4 and the first terminal of resistor R6. Its collector is connected to the positive power supply terminal VDD, and its emitter is connected to the first terminal of resistor R2. The first terminal of resistor R4 is also connected to the positive power supply terminal VDD. The base of NPN bipolar transistor N7 is connected to the first terminal of resistor R9, the first differential output positive port VOP1, the second terminal of resistor R5, and the collector of NPN bipolar transistor N3. Its collector is connected to the positive power supply terminal VDD, and its emitter is connected to the second differential output positive port VOP1. 2. The base of NPN bipolar transistor N8 is connected to the second terminal of resistor R10, the first differential output negative port VON1, the second terminal of resistor R6, and the collector of NPN bipolar transistor N4, which is connected to the positive terminal of the power supply VDD. The emitter is connected to the second differential output negative port VON2 and the first terminal of resistor R12. The base and collector of NPN bipolar transistor N9 are both connected to the positive terminal of the power supply VDD. The emitter is connected to the first terminal of resistor R13, and the second terminal of resistor R13 is connected to the first terminal of resistor R15. The base and collector of NPN bipolar transistor N10 are both connected to the positive terminal of the power supply VDD. The emitter is connected to the first terminal of resistor R14, and the second terminal of resistor R14 is connected to the output port VO.The base of NPN bipolar transistor N11 is connected to the first terminal of resistor R17, and its collector is simultaneously connected to the bias current IBIAS, the first terminal of capacitor C1, and the base of NPN bipolar transistor N12. Its emitter is connected to the first terminal of resistor R28. The base of NPN bipolar transistor N12 is simultaneously connected to the first terminal of capacitor C1, the bias current IBIAS, and the collector of NPN bipolar transistor N11. Its collector is connected to the positive terminal VDD of the power supply. Its emitter is simultaneously connected to the second terminal of resistor R17, the first terminal of resistor R18, and the first terminal of resistor R29. The base of NPN bipolar transistor N13 is connected to the second terminal of resistor R18, and its collector is connected to the collector of NPN bipolar transistor N14. Its emitter is connected to the negative terminal GND of the power supply through resistor R30. The base of NPN bipolar transistor N14 is connected to the second terminal of resistor R19, its collector is connected to the collector of NPN bipolar transistor N13, and its emitter is connected to the negative power supply GND through resistor R31; the base of NPN bipolar transistor N15 is connected to the second terminal of resistor R20, its collector is connected to the collector of NPN bipolar transistor N16, and its emitter is connected to the negative power supply GND through resistor R32; the base of NPN bipolar transistor N16 is connected to the second terminal of resistor R21, its collector is connected to the collector of NPN bipolar transistor N15, and its emitter is connected to the negative power supply GND through resistor R33; the base of NPN bipolar transistor N17 is connected to the second terminal of resistor R22, and its collector is simultaneously connected to the collector of NPN bipolar transistor N18 and the second terminal of resistor R11. The base of NPN bipolar transistor N18 is connected to the second terminal of resistor R23, and its collector is simultaneously connected to the collector of NPN bipolar transistor N17 and the second terminal of resistor R11. The emitter is connected to the negative power supply terminal GND through resistor R35. The base of NPN bipolar transistor N19 is connected to the second terminal of resistor R24, and its collector is simultaneously connected to the collector of NPN bipolar transistor N20 and the second terminal of resistor R12. The emitter is connected to the negative power supply terminal GND through resistor R36. The base of NPN bipolar transistor N20 is connected to the second terminal of resistor R25, and its collector is simultaneously connected to the collector of NPN bipolar transistor N19 and the second terminal of resistor R12. The emitter is connected to the negative power supply terminal GND through resistor R37. The base of NPN bipolar transistor N21 is connected to the second terminal of resistor R26, the collector to the second terminal of resistor R15, and the emitter is connected to the negative power supply terminal GND through resistor R38; the base of NPN bipolar transistor N22 is connected to the second terminal of resistor R27, the collector to the second terminal of resistor R16, and the emitter is connected to the negative power supply terminal GND through resistor R39; the first terminal of resistor R16 is connected to the output port VO; the first terminals of resistors R18, R19, R20, R21, R22, R23, R24, R25, R26, and R27 are interconnected.
[0035] Figure 3This is a schematic diagram of the DC offset cancellation module, including NPN bipolar transistors N23 to NPN bipolar transistor N38, resistors R40 to R57, and capacitors C2 to C5. The base of NPN bipolar transistor N23 is connected to the output voltage signal VM of the last stage LA, its collector is connected to the positive power supply VDD, and its emitter is connected to the first terminal of resistor R42. The base of NPN bipolar transistor N24 is connected to the output voltage signal VP of the last stage LA, its collector is connected to the positive power supply VDD, and its emitter is connected to the second terminal of resistor R43. The base of NPN bipolar transistor N25 is connected to the second terminal of resistor R42, its collector is connected to both the second terminal of resistor R40 and the first terminal of resistor R44, and its emitter is connected to the collector of NPN bipolar transistor N34. The base of NPN bipolar transistor N26 is connected to the first terminal of resistor R43, and its collector is connected to both the second terminal of resistor R41 and the first terminal of resistor R42. The first terminal of resistor R45 has its emitter connected to the collector of NPN bipolar transistor N34; the first terminals of resistors R40 and R41 are both connected to the positive power supply terminal VDD; the base of NPN bipolar transistor N27 is connected to the second terminal of resistor R44, its collector outputs the current signal IOP from the DC offset cancellation module, and its emitter is connected to the first terminal of resistor R46; the base of NPN bipolar transistor N28 is connected to the second terminal of resistor R45, its collector outputs the current signal IOM from the DC offset cancellation module, and its emitter is connected to the first terminal of resistor R47; the base of NPN bipolar transistor N29 is connected to the reference current Iref, its collector is connected to the positive power supply terminal VDD, and its emitter is also connected to the NPN bipolar transistor... The base of N30, the base of NPN bipolar transistor N31, and the first terminal of resistor R50 are connected, with the second terminal of resistor R50 connected to the negative power supply GND. The bases of NPN bipolar transistors N30 and N31 are interconnected. The collectors of both NPN bipolar transistors N30 and N31 are connected to the reference current Iref. The emitter of NPN bipolar transistor N30 is connected to the negative power supply GND through resistor R48, and the emitter of NPN bipolar transistor N31 is connected to the negative power supply GND through resistor R49. The bases of NPN bipolar transistors N32, NPN bipolar transistor N33, and NPN bipolar transistor N34 are connected to the negative power supply GND. The bases of NPN bipolar transistors N35, N36, N37, and N38 are all connected to the emitter of NPN bipolar transistor N29. The collector of NPN bipolar transistor N32 is connected to the first terminal of resistor R42, and its emitter is connected to the negative power supply terminal GND through resistor R51. The collector of NPN bipolar transistor N33 is connected to the second terminal of resistor R43, and its emitter is connected to the negative power supply terminal GND through resistor R52. The collector of NPN bipolar transistor N34 is connected to the emitters of both NPN bipolar transistors N25 and N26, and its emitter is connected to the negative power supply terminal GND through resistor R53.The collectors of NPN bipolar transistors N35, NPN bipolar transistors N36, NPN bipolar transistors N37, and NPN bipolar transistors N38 are connected to the second terminals of resistors R46 and R47. The emitter of NPN bipolar transistor N35 is connected to the negative power supply terminal GND through resistor R54; the emitter of NPN bipolar transistor N36 is connected to the negative power supply terminal GND through resistor R55; the emitter of NPN bipolar transistor N37 is connected to the negative power supply terminal GND through resistor R56; and the emitter of NPN bipolar transistor N38 is connected to the negative power supply terminal GND through resistor R57. The first terminal of capacitor C2 is connected to the first terminal of resistor R44, and the second terminal of capacitor C2 is connected to the negative power supply terminal GND; the first terminal of capacitor C3 is connected to the second terminal of resistor R44, and the second terminal of capacitor C3 is connected to the negative power supply terminal GND; the first terminal of capacitor C4 is connected to the first terminal of resistor R45, and the second terminal of capacitor C4 is connected to the negative power supply terminal GND; the first terminal of capacitor C5 is connected to the second terminal of resistor R45, and the second terminal of capacitor C5 is connected to the negative power supply terminal GND.
[0036] Figure 4This is a schematic diagram of the circuit structure of the temperature compensation module, including PMOS transistors P1 to P9 and NMOS transistors M1 to M8. The source terminals of PMOS transistors P1 to P9 are all connected to the positive power supply terminal VDD. The gate terminals of PMOS transistors P1, P2, P3, and P4 are interconnected. The drain terminal of PMOS transistor P1 is connected to the drain terminal of NMOS transistor M1, the drain terminal of PMOS transistor P2 is connected to the bias current Ibias1, the drain terminal of PMOS transistor P3 is connected to the bias current Ibias2, and the drain terminal of PMOS transistor P4 is connected to the bias current Ibias3. The gates of PMOS transistors P5, P6, P7, P8, and P9 are interconnected. The drain of PMOS transistor P5 is connected to the drain of NMOS transistor M2. The drain of PMOS transistor P6 is connected to the bias current Ibias_LA1. The drain of PMOS transistor P7 is connected to the bias current Ibias_LA2. The drain of PMOS transistor P8 is connected to the bias current Ibias_LA3. The drain of PMOS transistor P9 is connected to the bias current Ibias_LA4. The gate of NMOS transistor M1 is connected to the enable signal EN1, and its source is connected to the drain of NMOS transistor M4. The gate and drain of NMOS transistor M3 and the gate of NMOS transistor M4 are connected to the reference current Iref. The sources of NMOS transistor M3 and NMOS transistor M4 are both connected to the negative power supply GND. The gate of NMOS transistor M2 is connected to the enable signal EN2, and its source is connected to the drain of NMOS transistor M7 and NMOS transistor M8. The gate and drain of NMOS transistor M6 and the gate of NMOS transistor M7 are connected to the IPTAT current. The gate of NMOS transistor M8 is connected to the gate of NMOS transistor M5 and the gate of NMOS transistor M4. The drain of NMOS transistor M5 is connected to the IPTAT current. The sources of NMOS transistor M5, NMOS transistor M6, NMOS transistor M7, and NMOS transistor M8 are all connected to the negative power supply GND.
[0037] The LA of this invention employs a two-stage negative feedback operational amplifier to boost the gain of the limiting amplifier. Each LA stage is connected via an emitter follower. This design allows for better setting of the input DC point and isolates the output and input of each amplifier stage, enabling pole extrapolation and increasing bandwidth. The DET can detect frequencies greater than 20GHz, thus ensuring the wideband performance of the detector.
[0038] The 20GHz large dynamic range logarithmic detector of this invention is designed and fabricated using 0.18μm SiGe HBT devices. In this embodiment, the power supply voltage is 3.3V, the bandgap reference module output voltage is 1.2V, the LA gain is 14dB, and the dynamic range within a ±3dB error range is above 50dB when the input frequency is from 1GHz to 20GHz; the detector output temperature consistency is within a ±1dB error range when the input frequency is from 1GHz to 20GHz.
[0039] The 20GHz large dynamic range logarithmic detector proposed in this invention is suitable for the design of high-frequency, high-performance detectors from 1GHz to 20GHz. It can achieve a trade-off between wide bandwidth, large dynamic range, low power consumption, and low chip area performance based on the existing mature SiGe HBT process platform.
[0040] The above description is merely a description of preferred embodiments of the present invention and is not intended to limit the scope of the present invention in any way. Any changes or modifications made by those skilled in the art based on the above disclosure shall fall within the protection scope of the claims.
Claims
1. A 20GHz large dynamic range logarithmic detector, characterized in that, include: The limiting amplifier module limits and amplifies the input signal; Several rectifier modules convert the input signal of the limiting amplifier module into a detection current; The adder module summarizes the detected current from the rectifier module and converts it into a voltage output through a resistor.
2. The 20GHz large dynamic range logarithmic detector as described in claim 1, characterized in that, The 20GHz large dynamic range logarithmic detector also includes a DC offset cancellation module, a temperature compensation module, a bandgap reference module, and a bias module; among which... The DC offset cancellation module is used to adjust and reduce the DC level error of the differential signal of the limiting amplifier module; The temperature compensation module is connected to the adder module to improve the temperature consistency of the output of the 20GHz large dynamic range logarithmic detector. The bandgap reference module and the bias module provide stable bias voltage and current for the limiting amplifier module, the rectifier module, the DC offset elimination circuit and the temperature compensation module.
3. The 20GHz large dynamic range logarithmic detector as described in claim 1, characterized in that, The limiting amplifier module includes a first NPN bipolar transistor to a twenty-second NPN bipolar transistor, a first resistor to a thirty-ninth resistor, and a first capacitor; The base of the first NPN bipolar transistor is connected to the positive differential input port INP. Its collector is simultaneously connected to the second terminal of the first resistor and the base of the third NPN bipolar transistor. Its emitter is simultaneously connected to the collectors of the thirteenth and fourteenth NPN bipolar transistors. The base of the second NPN bipolar transistor is connected to the negative differential input port INP. Its collector is simultaneously connected to the second terminal of the second resistor and the base of the fourth NPN bipolar transistor. Its emitter is simultaneously connected to the collectors of the thirteenth and fourteenth NPN bipolar transistors. The base of the third NPN bipolar transistor is simultaneously connected to the collector of the first NPN bipolar transistor and the second terminal of the first resistor. Its collector is simultaneously connected to the second terminal of the fifth resistor and the first differential input port INP. The positive output port VOP1 is connected to the first terminal of the ninth resistor and the base of the seventh NPN bipolar transistor. The emitter is connected to the first terminal of the seventh resistor. The second terminals of the ninth and tenth resistors are both connected to the positive power supply terminal VDD. The base of the fourth NPN bipolar transistor is simultaneously connected to the collector of the second NPN bipolar transistor and the second terminal of the second resistor. The collector is simultaneously connected to the second terminal of the sixth resistor, the first differential output negative port VON1, the second terminal of the tenth resistor, and the base of the eighth NPN bipolar transistor. The emitter is connected to the first terminal of the eighth resistor. The second terminals of the seventh and eighth resistors are simultaneously connected to the collectors of the fifteenth and sixteenth NPN bipolar transistors. The fifth NPN bipolar transistor... The base of the sixth NPN bipolar transistor is connected to both the second terminal of the third resistor and the first terminal of the fifth resistor. Its collector is connected to the positive power supply terminal VDD, and its emitter is connected to the first terminal of the first resistor. The first terminal of the third resistor is also connected to the positive power supply terminal VDD. The base of the seventh NPN bipolar transistor is connected to the first terminal of the ninth resistor, the first differential output positive port VOP1, the second terminal of the fifth resistor, and the collector of the third NPN bipolar transistor. Its collector is connected to the positive power supply terminal VDD, and its emitter is connected to the second differential output positive port VO. P2 and the first terminal of the eleventh resistor; the base of the eighth NPN bipolar transistor is simultaneously connected to the second terminal of the tenth resistor, the first differential output negative port VON1, the second terminal of the sixth resistor, and the collector of the fourth NPN bipolar transistor, with the collector connected to the positive power supply terminal VDD, and the emitter simultaneously connected to the second differential output negative port VON2 and the first terminal of the twelfth resistor; the base and collector of the ninth NPN bipolar transistor are both connected to the positive power supply terminal VDD, and the emitter is connected to the first terminal of the thirteenth resistor, with the second terminal of the thirteenth resistor connected to the first terminal of the fifteenth resistor; the base and collector of the tenth NPN bipolar transistor are both connected to the positive power supply terminal VDD, and the emitter is connected to the first terminal of the fourteenth resistor, with the second terminal of the fourteenth resistor connected to the output port VO;The base of the eleventh NPN bipolar transistor is connected to the first terminal of the seventeenth resistor. Its collector is simultaneously connected to the bias current IBIAS, the first terminal of the first capacitor, and the base of the twelfth NPN bipolar transistor. Its emitter is connected to the first terminal of the twenty-eighth resistor. The base of the twelfth NPN bipolar transistor is simultaneously connected to the first terminal of the first capacitor, the bias current IBIAS, and the collector of the eleventh NPN bipolar transistor. Its collector is connected to the positive power supply terminal VDD. Its emitter is simultaneously connected to the second terminal of the seventeenth resistor, the first terminal of the eighteenth resistor, and the first terminal of the twenty-ninth resistor. The base of the thirteenth NPN bipolar transistor is connected to the second terminal of the eighteenth resistor. Its collector is connected to the collector of the fourteenth NPN bipolar transistor. Its emitter is connected to the negative power supply terminal GND through the thirtieth resistor. The fourteenth NPN... The base of an N-type bipolar transistor is connected to the second terminal of the nineteenth resistor, the collector is connected to the collector of the thirteenth NPN bipolar transistor, and the emitter is connected to the negative power supply GND through the thirty-first resistor. The base of the fifteenth NPN bipolar transistor is connected to the second terminal of the twentieth resistor, the collector is connected to the collector of the sixteenth NPN bipolar transistor, and the emitter is connected to the negative power supply GND through the thirty-second resistor. The base of the sixteenth NPN bipolar transistor is connected to the second terminal of the twenty-first resistor, the collector is connected to the collector of the fifteenth NPN bipolar transistor, and the emitter is connected to the negative power supply GND through the thirty-third resistor. The base of the seventeenth NPN bipolar transistor is connected to the second terminal of the twenty-second resistor, the collector is simultaneously connected to the collector of the eighteenth NPN bipolar transistor and the second terminal of the eleventh resistor, and the emitter is connected to... The base of the eighteenth NPN bipolar transistor is connected to the second terminal of the twenty-third resistor, and its collector is simultaneously connected to the collector of the seventeenth NPN bipolar transistor and the second terminal of the eleventh resistor. The emitter is connected to the negative terminal of the power supply GND through the thirty-fifth resistor. The base of the nineteenth NPN bipolar transistor is connected to the second terminal of the twenty-fourth resistor, and its collector is simultaneously connected to the collector of the twentieth NPN bipolar transistor and the second terminal of the twelfth resistor. The emitter is connected to the negative terminal of the power supply GND through the thirty-sixth resistor. The base of the twentieth NPN bipolar transistor is connected to the second terminal of the twenty-fifth resistor, and its collector is simultaneously connected to the collector of the nineteenth NPN bipolar transistor and the second terminal of the twelfth resistor. The emitter is connected to the negative terminal of the power supply GND through the thirty-seventh resistor. The base of the 21-type NPN bipolar transistor is connected to the second terminal of the 26th resistor, the collector is connected to the second terminal of the 15th resistor, and the emitter is connected to the negative power supply terminal GND through the 38th resistor. The base of the 22-type NPN bipolar transistor is connected to the second terminal of the 27th resistor, the collector is connected to the second terminal of the 16th resistor, and the emitter is connected to the negative power supply terminal GND through the 39th resistor. The first terminal of the 16th resistor is connected to the output port VO. The first terminals of the 18th, 19th, 20th, 21st, 22nd, 23rd, 24th, 25th, 26th, and 27th resistors are interconnected.
4. The 20GHz large dynamic range logarithmic detector as described in claim 1, characterized in that, The DC offset cancellation module includes the twenty-third NPN bipolar transistor to the thirty-eighth NPN bipolar transistor, the fortieth resistor to the fifty-seventh resistor, and the second capacitor to the fifth capacitor; The base of the 23rd NPN bipolar transistor is connected to the output voltage signal VM of the last stage limiting amplifier module, the collector is connected to the positive power supply VDD, and the emitter is connected to the first terminal of the 42nd resistor. The base of the 24th NPN bipolar transistor is connected to the output voltage signal VP of the last stage limiting amplifier module, the collector is connected to the positive power supply VDD, and the emitter is connected to the second terminal of the 43rd resistor. The base of the 25th NPN bipolar transistor is connected to the second terminal of the 42nd resistor, the collector is connected to both the second terminal of the 40th resistor and the first terminal of the 44th resistor, and the emitter is connected to the collector of the 34th NPN bipolar transistor. The base of the 26th NPN bipolar transistor is connected to the first terminal of the 43rd resistor, and the collector is connected to the 41st resistor. The second terminal of the NPN transistor and the first terminal of the forty-fifth resistor are connected, with the emitter connected to the collector of the thirty-fourth NPN bipolar transistor. The first terminals of the forty and forty-first resistors are both connected to the positive power supply terminal VDD. The base of the twenty-seventh NPN bipolar transistor is connected to the second terminal of the forty-fourth resistor, and its collector outputs the current signal IOP from the DC offset cancellation module. Its emitter is connected to the first terminal of the forty-sixth resistor. The base of the twenty-eighth NPN bipolar transistor is connected to the second terminal of the forty-fifth resistor, and its collector outputs the current signal IOM from the DC offset cancellation module. Its emitter is connected to the first terminal of the forty-seventh resistor. The base of the twenty-ninth NPN bipolar transistor is connected to the reference current Iref, its collector is connected to the positive power supply terminal VDD, and its emitter is simultaneously connected to the thirty-ninth NPN bipolar transistor. The base of the NPN bipolar transistor, the base of the 31st NPN bipolar transistor, and the first terminal of the 50th resistor are connected, with the second terminal of the 50th resistor connected to the negative power supply GND. The bases of the 30th and 31st NPN bipolar transistors are interconnected. The collectors of both the 30th and 31st NPN bipolar transistors are connected to the reference current Iref. The emitter of the 30th NPN bipolar transistor is connected to the negative power supply GND through the 48th resistor, and the emitter of the 31st NPN bipolar transistor is connected to the negative power supply GND through the 49th resistor. The bases of the 32nd, 33rd, and 34th NPN bipolar transistors, and the 35th... The bases of the NPN transistors 36, 37, and 38 are all connected to the emitter of the NPN transistor 29. The collector of the NPN transistor 32 is connected to the first terminal of the resistor 42, and its emitter is connected to the negative power supply terminal GND through the resistor 51. The collector of the NPN transistor 33 is connected to the second terminal of the resistor 43, and its emitter is connected to the negative power supply terminal GND through the resistor 52. The collector of the NPN transistor 34 is simultaneously connected to the emitters of the NPN transistors 25 and 26, and its emitter is connected to the negative power supply terminal GND through the resistor 53.The collectors of the 35th, 36th, 37th, and 38th NPN bipolar transistors are connected together to the second terminals of the 46th and 47th resistors. The emitter of the 35th NPN bipolar transistor is connected to the negative power supply terminal GND through the 54th resistor; the emitter of the 36th NPN bipolar transistor is connected to the negative power supply terminal GND through the 55th resistor; the emitter of the 37th NPN bipolar transistor is connected to the negative power supply terminal GND through the 56th resistor; and the emitter of the 38th NPN bipolar transistor is connected to the negative power supply terminal GND through the 57th resistor. The first terminal of the second capacitor is connected to the first terminal of the forty-fourth resistor, and the second terminal of the second capacitor is connected to the negative power supply terminal GND; the first terminal of the third capacitor is connected to the second terminal of the forty-fourth resistor, and the second terminal of the third capacitor is connected to the negative power supply terminal GND; the first terminal of the fourth capacitor C4 is connected to the first terminal of the forty-fifth resistor, and the second terminal of the fourth capacitor is connected to the negative power supply terminal GND; the first terminal of the fifth capacitor is connected to the second terminal of the forty-fifth resistor, and the second terminal of the fifth capacitor is connected to the negative power supply terminal GND.
5. The 20GHz large dynamic range logarithmic detector as described in claim 2, characterized in that, The temperature compensation module includes a first PMOS transistor to a ninth PMOS transistor and a first NMOS transistor to an eighth NMOS transistor; wherein... The source terminals of the first to ninth PMOS transistors are all connected to the positive power supply terminal VDD. The gate terminals of the first, second, third, and fourth PMOS transistors are interconnected. The drain terminal of the first PMOS transistor is connected to the drain terminal of the first NMOS transistor. The drain terminal of the second PMOS transistor is connected to the bias current Ibias1. The drain terminal of the third PMOS transistor is connected to the bias current Ibias2. The drain terminal of the fourth PMOS transistor is connected to the bias current Ibias3. The gates of the fifth PMOS transistor, the sixth PMOS transistor, the seventh PMOS transistor, the eighth PMOS transistor, and the ninth PMOS transistor are interconnected. The drain of the fifth PMOS transistor is connected to the drain of the second NMOS transistor. The drain of the sixth PMOS transistor is connected to the bias current Ibias_LA1. The drain of the seventh PMOS transistor is connected to the bias current Ibias_LA2. The drain of the eighth PMOS transistor is connected to the bias current Ibias_LA3. The drain of the ninth PMOS transistor is connected to the bias current Ibias_LA4. The gate of the first NMOS transistor is connected to the enable signal EN1, and its source is connected to the drain of the fourth NMOS transistor. The gate and drain of the third NMOS transistor and the gate of the fourth NMOS transistor are connected to the reference current Iref. The sources of the third NMOS transistor and the fourth NMOS transistor are both connected to the negative power supply GND. The gate of the second NMOS transistor is connected to the enable signal EN2, and its source is connected to the drain of both the seventh and eighth NMOS transistors. The gate and drain of the sixth NMOS transistor and the gate of the seventh NMOS transistor are connected to the IPTAT current. The gate of the eighth NMOS transistor is connected to the gate of both the fifth and fourth NMOS transistors. The drain of the fifth NMOS transistor is connected to the IPTAT current. The sources of the fifth, sixth, seventh, and eighth NMOS transistors are all connected to the negative power supply GND.
6. The 20GHz large dynamic range logarithmic detector as described in any one of claims 1-5, characterized in that, The 20GHz large dynamic range logarithmic detector is designed and fabricated based on SiGe HBT devices.