Synchronous data crosstalk effect optimization method and system and electronic equipment

Abstract

The invention provides a synchronous data crosstalk effect optimization method and system and electronic equipment. The method comprises the following steps: respectively measuring a jump edge jitter range of a victim channel and a jump edge jitter range of an applicator channel; any channel is selected from the victim channel and the applicator channel, and a first delay module is additionally arranged at the sending end of the selected channel; a second delay module is additionally arranged at the tail of the other unselected channel; configuring the first time delay module and the second time delay module based on the jump edge jitter range of the victim channel and the jump edge jitter range of the applier channel; and performing crosstalk effect optimization on the synchronous data of the two channels based on the configured first delay module and second delay module. The method can solve the problems that an existing synchronous data crosstalk effect optimization scheme is high in responsible degree and poor in optimization effect.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of high-speed digital signal transmission, and more particularly to a method and system for optimizing crosstalk effect of synchronous data and an electronic device. BACKGROUND

[0002] Synchronous high-speed digital signals are widely used in modern digital signal systems, such as high-speed interfaces and communication systems. Figure 1 Figure 1 is a schematic diagram of a high-speed parallel digital signal system. As shown in Figure 1, the transmission of parallel digital signals between module A and module B is implemented through a plurality of parallel channels, wherein the parallel paths (i.e., parallel channels) can be designed as passive metal traces or as signal paths including intermediate-stage buffers. Figure 1

[0003] With the advancement of chip manufacturing processes, integrated circuits can process digital signals at increasingly high speeds. Moreover, with the advancement of chip manufacturing processes, the integration level of the processes is increasingly high, and the overall size used is increasingly small. In addition, the voltage VDD used by the entire system is also designed to be increasingly small to improve power consumption.

[0004] However, while people enjoy the technological dividend of increased data throughput and stronger data processing capabilities, engineers need to solve increasingly severe high-speed digital signal crosstalk problems. Specifically, on the one hand, changes in data rates make the UI (unit interval) increasingly short, causing the robustness of crosstalk signals to continue to decline. On the other hand, the continuously decreasing voltage VDD also leads to more severe clock data jitter.

[0005] When high-speed parallel digital signals are synchronous data, as shown in Figure 2, because the data of each path is triggered by the clock of the same clock domain, the transition edges of the data of each path are aligned. When there is crosstalk between the channels, the crosstalk signal of the aggressor (the crosstalk originating channel) will be coupled to the victim (the crosstalk receiving channel) at the transition edge time, and the susceptibility of the transition edge time exactly worsens the data jitter itself. Figure 2 For example, when channel A and channel B are used to transmit parallel synchronous digital signals, and there is crosstalk between channel A and channel B; if at a certain transition edge time, the data of channel B does not change, then the transition edge of channel A does not change. If the data of channel B changes and is consistent with the direction of the transition of channel A, then the transition speed of channel A increases, and the timing of the transition edge becomes earlier. If the data of channel B changes and is opposite to the direction of the transition of channel A, then the transition speed of channel A decreases, and the timing of the transition edge becomes later. Therefore, as shown in Figure 3, the crosstalk signal of channel A will be coupled to the transition edge of channel B at the time of the transition edge of channel B, and the crosstalk signal of channel B will be coupled to the transition edge of channel A at the time of the transition edge of channel A.

[0006] Figure 3 ​​As shown, when two channels emit different data patterns, crosstalk between them can cause the data jitter of the received signal to deteriorate, and errors to occur in the receiving.

[0007] There are two existing solutions to the crosstalk problem (not limited to synchronous data). The first is a passive solution, the core of which is to "minimize the impact of crosstalk". For example, the distance between the mutually crosstalk channels is increased, the mutual coupling capacitance is reduced, and the crosstalk is reduced or even eliminated. Alternatively, a shielding line is added between the mutually crosstalk channels to reduce the direct impact between them, thereby reducing or even eliminating crosstalk. The other is an active solution, the core of which is not to seek to reduce crosstalk itself, but to compensate for the victim channel by applying a forward compensation. For example, if the amount of coupling from the applicator channel to the victim channel is +X, then an artificial -X coupling can be created to superimpose on the victim channel to achieve compensation for the victim channel.

[0008] However, for the existing passive solution, both the distance increase and the shielding line are affected by the physical space layout, and it is difficult to fully implement. For example, the distance increase solution is usually used to slightly reduce crosstalk. Since the space for high-speed parallel lines in the system is limited, it is not possible to be infinitely far apart, and a large amount of crosstalk remains. The shielding line solution also needs to compromise between parasitic capacitance and physical layout space, making it difficult to completely eliminate crosstalk. In the existing active solution, although the compensation circuit applies an -X influence to offset the crosstalk signal itself for the victim channel, the victim channel has additional parasitic capacitance of the compensation circuit added to the original circuit, which affects the high-speed signal bandwidth. In addition, the victim channel needs to build a module with a driving capability of -X, which itself increases a large amount of power consumption and chip area. Thirdly, in order to accurately quantify the required driving capability X, a high-performance active compensation solution also requires a corresponding crosstalk amount detection module, which further increases the design complexity.

[0009] From the above two existing solutions, there is an urgent need for a solution that can effectively design simply and effectively reduce the crosstalk effect between digital signal channels. SUMMARY

[0010] In view of the above problems, the purpose of the present application is to provide a synchronous data crosstalk effect optimization system to solve the problem of high responsibility and poor optimization effect of the existing synchronous data crosstalk effect optimization scheme.

[0011] The synchronous data crosstalk effect optimization method provided by the present application comprises: respectively measuring the transition edge jitter range of the victim channel and the transition edge jitter range of the applicator channel; Choose either the victim channel or the perpetrator channel, add a first delay module to the sending end of the selected channel, and add a second delay module to the end of the other unselected channel; The first delay module and the second delay module are configured based on the jitter range of the transition edge of the victim channel and the jitter range of the transition edge of the attacker channel; Based on the configured first delay module and second delay module, crosstalk effect optimization is performed on the digital data in the victim channel and the digital data in the attacker channel.

[0012] In addition, an alternative approach is to optimize the crosstalk effect of the digital data in the victim channel and the digital data in the perpetrator channel based on the configured first delay module and second delay module, including: The digital signal in the selected channel is delayed based on the configured first delay module so that the transition edges of the digital signal in the selected channel and the digital signal in the unselected channel are staggered; and the digital signal in the unselected channel is delayed based on the configured second delay module so that the transition edges of the digital signal in the selected channel and the digital signal in the unselected channel are restored to alignment.

[0013] Alternatively, the transition edge jitter range may include the transition edge rise time and the transition edge jitter time.

[0014] Alternatively, the delay values ​​of the first delay module and the second delay module can be equal.

[0015] Alternatively, during the configuration of the first delay module and the second delay module based on the jitter range of the transition edge of the victim channel and the jitter range of the transition edge of the attacker channel: The delay value is set such that the jitter range of the victim channel and the jitter range of the attacker channel do not overlap at all.

[0016] Alternatively, an optional approach is to define the jitter range of the victim channel as F1, the jitter range of the attacker channel as F2, and the delay value as D. Then, during the configuration of the first delay module and the second delay module based on the jitter ranges of the victim channel and the attacker channel, the delay value satisfies the following constraint: Where N is a non-negative integer and UI is the unit interval.

[0017] Alternatively, N=0; and F1 and F2 can both be obtained through simulation or testing.

[0018] On the other hand, the present invention also provides a synchronous data crosstalk effect optimization system, including a jitter measurement unit, a delay module setting unit, a delay module configuration unit, and a signal processing unit; wherein, the jitter measurement unit is used to measure the jitter range of the jump edge of the victim channel and the jitter range of the jump edge of the attacker channel respectively. The delay module setting unit is used to select one of the victim channel and the perpetrator channel, add a first delay module at the sending end of the selected channel, and add a second delay module at the end of the other unselected channel; The delay module configuration unit is used to configure the first delay module and the second delay module based on the jitter range of the jump edge of the victim channel and the jitter range of the jump edge of the attacker channel; The signal processing unit is configured to delay the digital signal in the selected channel based on the configured first delay module, so that the transition edges of the digital signal in the selected channel and the digital signal in the unselected channel are staggered; and to delay the digital signal in the unselected channel based on the configured second delay module, so that the transition edges of the digital signal in the selected channel and the digital signal in the unselected channel are restored to alignment.

[0019] Furthermore, the present invention also provides an electronic device, comprising: a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the computer program to implement the steps of the aforementioned method for optimizing the synchronous data crosstalk effect.

[0020] Furthermore, the present invention also provides a computer-readable storage medium storing instructions that, when executed on an electronic device, cause the electronic device to perform the aforementioned method for optimizing synchronous data crosstalk effects.

[0021] Furthermore, the present invention also provides a synchronous digital signal system, including at least two parallel channels, wherein the crosstalk effect of any two parallel channels is optimized based on the aforementioned synchronous data crosstalk effect optimization method.

[0022] Compared with the prior art, the synchronous data crosstalk effect optimization method, system, and electronic device provided by the present invention have the following advantages: The synchronous data crosstalk effect optimization method provided by this invention is essentially a passive solution. Compared with previous active compensation methods, this solution significantly reduces implementation difficulty, power consumption, and area overhead, thus substantially lowering costs. Compared to conventional passive solutions, this solution can optimize crosstalk effects for high-speed synchronous digital signals with very small space overhead (delay modules are typically small in area), and can almost completely eliminate the impact of crosstalk on jitter.

[0023] To achieve the foregoing and related objectives, one or more aspects of the invention include the features which will be described in detail below and specifically pointed out in the claims. The following description and accompanying drawings illustrate certain exemplary aspects of the invention. However, these aspects indicate only a few of the various ways in which the principles of the invention can be used. Furthermore, the invention is intended to include all such aspects and their equivalents. Attached Figure Description

[0024] Other objects and results of the invention will become more apparent and readily understood with reference to the following description taken in conjunction with the accompanying drawings and the contents of the claims, and with a more complete understanding of the invention. In the drawings: Figure 1 A schematic diagram of an existing high-speed parallel digital signal system; Figure 2 This is a schematic diagram of a high-speed parallel digital signal system when the high-speed parallel digital signal is synchronous data. Figure 3 This is a schematic diagram of a high-speed parallel digital signal system when two channels transmit different data codes. Figure 4 A schematic diagram of a model for optimizing the synchronous data crosstalk effect according to an embodiment of the present invention; Figure 5 A flowchart of a method for optimizing the crosstalk effect of synchronous data provided in an embodiment of the present invention; Figure 6 This is a schematic diagram of a synchronous data crosstalk effect optimization system provided according to an embodiment of the present invention; Figure 7 This is a schematic diagram of an electronic device provided according to an embodiment of the present invention. Detailed Implementation

[0025] In the following description, numerous specific details are set forth for illustrative purposes and to provide a thorough understanding of one or more embodiments. However, it will be apparent that these embodiments may also be implemented without these specific details. In other instances, well-known structures and devices are shown in block diagram form for ease of description of one or more embodiments.

[0026] The embodiments of this invention can be applied to electronic devices such as computer systems / servers, which can operate with a wide range of other general-purpose or special-purpose computing system environments or configurations. Examples of well-known computing systems, environments, and / or configurations suitable for use with electronic devices such as computer systems / servers include, but are not limited to: personal computer systems, server computer systems, thick clients, handheld or laptop devices, microprocessor-based systems, set-top boxes, programmable consumer electronics, networked personal computers, minicomputer systems, mainframe computer systems, and distributed cloud computing environments including any of the above systems, etc.

[0027] Computer systems / servers and other electronic devices can be described in the general context of computer-executable instructions executed by the computer system. Typically, program modules can include routines, programs, object programs, components, logic, data structures, etc., which perform specific tasks or implement specific abstract data types. Computer systems / servers and other electronic devices can be implemented in distributed cloud computing environments, where tasks are executed by remote processing devices linked through communication networks. In distributed cloud computing environments, program modules can reside on local or remote computing system storage media, including storage devices.

[0028] It should be understood that the terminology used in this invention is merely for describing particular embodiments and is not intended to limit the invention. Furthermore, with respect to numerical ranges in this invention, it should be understood that each intermediate value between the upper and lower limits of the range is also specifically disclosed. Every smaller range between any stated value or intermediate value within a stated range, and any other stated value or intermediate value within said range, is also included in this invention. The upper and lower limits of these smaller ranges may be independently included or excluded from the range.

[0029] Various modifications and variations can be made to the specific embodiments described in this specification without departing from the scope or spirit of the invention, as will be apparent to those skilled in the art. Other embodiments derived from this specification will also be readily apparent to those skilled in the art. This application specification and embodiments are merely exemplary.

[0030] The following details the specific process of the synchronous data crosstalk effect optimization method provided by this invention.

[0031] Figure 4 This is a schematic diagram of a model for optimizing the synchronous data crosstalk effect according to an embodiment of the present invention. Figure 5 This is a flowchart of the synchronous data crosstalk effect optimization method provided according to an embodiment of the present invention, combined with... Figure 4 and Figure 5 It can be seen that the synchronous data crosstalk effect optimization method provided by the present invention includes: S110: Measure the jitter range of the jump edge in the victim channel and the jitter range of the jump edge in the attacker channel, respectively.

[0032] Specifically, for both the victim channel and the perpetrator channel, the transition edge jitter range includes the transition edge rise time and the transition edge jitter time, and the sum of the transition edge rise time and the transition edge jitter time is the value of the transition edge jitter range.

[0033] S120: Select one of the victim channel and the perpetrator channel, add a first delay module to the sending end of the selected channel; and add a second delay module to the end of the other unselected channel.

[0034] It should be noted that by adding a delay module at the transmitting end (after) of one of the victim channel and the perpetrator channel, the transition edges of the internal signals of the two channels can be directly staggered at the initial position of the channel (near the transmitting end), thereby eliminating the influence of crosstalk signals on the transition edges and effectively avoiding the deterioration of jitter. At the same time, in order to ensure that the receiving end can still receive the two synchronized signals correctly, a delay module of the same size needs to be added at the end of the other channel so that the transition edges of the internal signals of the two channels are aligned before entering the receiving end, ensuring that the receiving end receives the correct signal.

[0035] S130: Configure the first delay module and the second delay module based on the jitter range of the transition edge of the victim channel and the jitter range of the transition edge of the attacker channel.

[0036] Specifically, in order to ensure that the transition edges of the signals ultimately input to the receiver from the two channels (the attacker channel and the victim channel) are aligned and synchronized, the delay values ​​of the first delay module of the selected channel and the second delay module of the unselected channel need to be equal.

[0037] Furthermore, to ensure that the two signals do not crosstalk each other at the transition edge position, during the configuration of the first delay module and the second delay module based on the transition edge jitter range of the victim channel and the transition edge jitter range of the exertor channel: The delay value is set such that the jitter range of the victim channel and the jitter range of the attacker channel do not overlap at all.

[0038] In the actual design process, assuming the jitter range of the victim channel's transition edge is F1, the jitter range of the attacker channel's transition edge is F2, and the delay value is D; then, in the process of configuring the first delay module and the second delay module based on the jitter ranges of the victim channel and the attacker channel's transition edge, the delay value satisfies the following constraint: Where N is a non-negative integer, and UI is the built-in unit interval of the delay module.

[0039] It should be noted that, considering system overhead and performance optimization, N should be as small as possible, with 0 being the optimal value. In addition, to obtain the jitter range of the victim channel and the jitter range of the attacker channel, the jitter range of the victim channel and the jitter range of the attacker channel can be obtained through simulation or testing.

[0040] S140: Based on the configured first delay module and second delay module, perform crosstalk effect optimization on the digital data in the victim channel and the digital data in the attacker channel (both are synchronous data).

[0041] Specifically, the process of optimizing the crosstalk effect of the synchronized data of the two channels based on the configured first delay module and the second delay module includes: delaying the digital signal in the selected channel based on the configured first delay module so that the transition edges of the digital signal in the selected channel and the digital signal in the unselected channel are staggered; and delaying the digital signal in the unselected channel based on the configured second delay module so that the transition edges of the digital signal in the selected channel and the digital signal in the unselected channel are restored to alignment.

[0042] It should be noted that the synchronous data crosstalk effect optimization method provided by this invention is explained using a pair of channels as an example. Since the impact and analysis of crosstalk are performed in pairs, combining "perpetrator and victim," in practical applications, for multi-channel parallel circuits, the synchronous data crosstalk effect optimization method provided by this invention can be used to optimize each channel in pairs. For example, the synchronous data crosstalk effect optimization method provided by this invention is applied to synchronous digital signal systems, which include multiple (at least two) parallel channels. Any two parallel channels in the synchronous digital signal system can have their crosstalk effects optimized using the synchronous data crosstalk effect optimization method provided by this invention.

[0043] The synchronous data crosstalk effect optimization method provided by this invention uses a delay module added to the transmission path to create a skew (delay difference) between the path signals, so that the crosstalk effect avoids the transition edge, thereby eliminating the deterioration of the transition edge jitter by the crosstalk signal. At the same time, the same delay module is used before the receiving end to restore the synchronization of the synchronization signal, ensuring the timing requirements of the receiving end.

[0044] Figure 6This is a block diagram of the synchronous data crosstalk effect optimization system of the present invention. The synchronous data crosstalk effect optimization system 400 provided by the present invention is based on a synchronous data crosstalk effect optimization method and can be installed in electronic devices. Depending on the functions implemented, such as... Figure 6 As shown, the synchronous data crosstalk effect optimization system 400 may include: a jitter measurement unit 410, a delay module setting unit 420, a delay module configuration unit 430, and a signal processing unit 440. The unit described in this invention can also be called a module, which mainly refers to a series of computer program segments that can be executed by the processor of an electronic device and can perform a fixed function, and are stored in the memory of the electronic device.

[0045] In this embodiment, the functions of each module / unit are as follows: The jitter measurement unit 410 is used to measure the jitter range along the transition edge of the victim channel and the jitter range along the transition edge of the attacker channel, respectively. The delay module setting unit 420 is used to select one of the victim channel and the perpetrator channel, add a first delay module at the sending end of the selected channel, and add a second delay module at the end of the other unselected channel; The delay module configuration unit 430 is used to configure the first delay module and the second delay module based on the jitter range of the jump edge of the victim channel and the jitter range of the jump edge of the attacker channel; The signal processing unit 440 is configured to perform delay processing on the digital signal in the selected channel based on the configured first delay module, so that the transition edges of the digital signal in the selected channel and the digital signal in the unselected channel are staggered; and to perform delay processing on the digital signal in the unselected channel based on the configured second delay module, so that the transition edges of the digital signal in the selected channel and the digital signal in the unselected channel are restored to alignment.

[0046] It should be noted that the embodiments of the synchronous data crosstalk effect optimization system and the embodiments of the synchronous data crosstalk effect optimization method described above can be used for reference, and will not be elaborated here.

[0047] Figure 7 This is a schematic diagram of the electronic device used in the present invention to implement the synchronous data crosstalk effect optimization system.

[0048] like Figure 7 As shown, the electronic device 1 may include a processor 10, a memory 11 and a bus, and may also include a computer program stored in the memory 11 and executable on the processor 10, such as a synchronous data crosstalk effect optimization program 12.

[0049] The memory 11 includes at least one type of readable storage medium, including flash memory, portable hard drive, multimedia card, card-type memory (e.g., SD or DX memory), magnetic memory, magnetic disk, optical disk, etc. In some embodiments, the memory 11 can be an internal storage unit of the electronic device 1, such as the portable hard drive of the electronic device 1. In other embodiments, the memory 11 can also be an external storage device of the electronic device 1. Furthermore, the memory 11 can include both internal and external storage units of the electronic device 1. The memory 11 can be used not only to store application software and various types of data installed on the electronic device 1, such as program code, but also to temporarily store data that has been output or will be output.

[0050] In some embodiments, the processor 10 may be composed of integrated circuits, such as a single packaged integrated circuit or multiple integrated circuits with the same or different functions, including combinations of one or more central processing units (CPUs), microprocessors, digital processing chips, graphics processors, and various control chips. The processor 10 is the control unit of the electronic device, connecting various components of the entire electronic device through various interfaces and lines. It executes programs or modules stored in the memory 11 (e.g., synchronous data crosstalk effect optimization programs) and calls data stored in the memory 11 to perform various functions of the electronic device 1 and process data.

[0051] The bus can be a Peripheral Component Interconnect Standard (PCI) bus or an Extended Industry Standard Architecture (EISA) bus, etc. This bus can be divided into an address bus, a data bus, a control bus, etc. The bus is configured to enable communication between the memory 11 and at least one processor 10, etc.

[0052] Figure 7 Only electronic devices with components are shown; it will be understood by those skilled in the art that... Figure 7 The structure shown does not constitute a limitation on the electronic device 1, and may include fewer or more components than shown, or combine certain components, or have different component arrangements.

[0053] For example, although not shown, the electronic device 1 may also include a power supply (such as a battery) to power the various components. Preferably, the power supply can be logically connected to the at least one processor 10 through a power management device, thereby enabling functions such as charging management, discharging management, and power consumption management. The power supply may also include one or more DC or AC power supplies, recharging devices, power fault detection circuits, power converters or inverters, power status indicators, and other arbitrary components. The electronic device 1 may also include various sensors, Bluetooth modules, Wi-Fi modules, etc., which will not be described in detail here.

[0054] Furthermore, the electronic device 1 may also include a network interface. Optionally, the network interface may include a wired interface and / or a wireless interface (such as a Wi-Fi interface, a Bluetooth interface, etc.), which is typically used to establish communication connections between the electronic device 1 and other electronic devices.

[0055] Optionally, the electronic device 1 may further include a user interface, which may be a display, an input unit (such as a keyboard), or, optionally, a standard wired interface or a wireless interface. In some embodiments, the display may be an LED display, a liquid crystal display, a touch-sensitive liquid crystal display, or an organic light-emitting diode touchscreen, etc. The display may also be appropriately referred to as a screen or display unit, used to display information processed in the electronic device 1 and to display a visual user interface.

[0056] It should be understood that the embodiments described are for illustrative purposes only and do not limit the scope of protection of the present invention.

[0057] The synchronization data crosstalk effect optimization program 12 stored in the memory 11 of the electronic device 1 is a combination of multiple instructions. When run in the processor 10, it can realize the synchronization data crosstalk effect optimization method.

[0058] Furthermore, if the modules / units integrated in the electronic device 1 are implemented as software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. The computer-readable medium may include: any entity or device capable of carrying the computer program code, a recording medium, a USB flash drive, a portable hard drive, a magnetic disk, an optical disk, a computer memory, or a read-only memory.

[0059] In the several embodiments provided by this invention, it should be understood that the disclosed devices, systems, and methods can be implemented in other ways. For example, the system embodiments described above are merely illustrative; for instance, the division of modules is only a logical functional division, and other division methods may be used in actual implementation.

[0060] It should be noted that, in this document, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, apparatus, article, or method that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, apparatus, article, or method. Unless otherwise specified, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, apparatus, article, or method that includes that element.

[0061] As referred above Figures 1 to 7 The synchronous data crosstalk effect optimization system according to the present invention is described by way of example. However, those skilled in the art will understand that various modifications can be made to the synchronous data crosstalk effect optimization system proposed in the present invention without departing from the scope of the invention. Therefore, the scope of protection of the present invention should be determined by the contents of the appended claims.

Claims

1. A method of optimizing for synchronization data crosstalk effects, characterized in that, The method comprises the following steps: measuring the jitter range of the victim channel and the jitter range of the aggressor channel respectively; adding a first delay module at the sending end of the selected channel in either the victim channel or the aggressor channel; adding a second delay module at the end of the unselected channel; configuring the first delay module and the second delay module based on the jitter range of the victim channel and the jitter range of the aggressor channel; optimizing the crosstalk effect of the digital data in the victim channel and the digital data in the aggressor channel based on the configured first delay module and the configured second delay module.

2. The method according to claim 1, wherein the process of optimizing the crosstalk effect of the digital data in the victim channel and the digital data in the aggressor channel based on the configured first delay module and the configured second delay module comprises: delaying the digital signal in the selected channel based on the configured first delay module so that the digital signal in the selected channel is staggered with the digital signal in the unselected channel; and delaying the digital signal in the unselected channel based on the configured second delay module so that the digital signal in the selected channel is aligned with the digital signal in the unselected channel.

3. The method according to claim 2, wherein the jitter range comprises a rising time and a jitter time; and / or the delay value of the first delay module is equal to the delay value of the second delay module.

4. The method according to claim 3, wherein in the process of configuring the first delay module and the second delay module based on the jitter range of the victim channel and the jitter range of the aggressor channel: the delay value is set so that the jitter range of the victim channel and the jitter range of the aggressor channel are completely overlapped.

5. The method according to claim 4, wherein the jitter range of the victim channel is F1, the jitter range of the aggressor channel is F2, and the delay value is D; in the process of configuring the first delay module and the second delay module based on the jitter range of the victim channel and the jitter range of the aggressor channel, the delay value satisfies the following constraint:

6. The method according to claim 5, wherein the preset parameter is 0; and / or the jitter range of the victim channel and the jitter range of the aggressor channel are obtained by simulation or testing. The device comprises a jitter measurement unit, a delay module setting unit, a delay module configuring unit, and a signal processing unit, wherein: the jitter measurement unit is used to measure the jitter range of the victim channel and the jitter range of the aggressor channel respectively; ​ ​ ; where N is a predetermined parameter, N is a non-negative integer, and UI is a unit interval. ​ ​ ​ 7. A system for optimizing the effects of crosstalk in synchronous data, characterized by ​ ​ The delay module setting unit is configured to add a first delay module at a sending end of a selected one of the victim channel and the aggressor channel, and add a second delay module at an end of the other one of the victim channel and the aggressor channel; The delay module configuration unit is configured to configure the first delay module and the second delay module based on a jitter range of the victim channel and a jitter range of the aggressor channel; The signal processing unit is configured to perform delay processing on a digital signal in the selected channel based on the configured first delay module, so that the digital signal in the selected channel is staggered with a digital signal in the other channel in terms of a jitter edge; and perform delay processing on the digital signal in the other channel based on the configured second delay module, so that the digital signal in the selected channel is aligned with the digital signal in the other channel in terms of the jitter edge.

8. An electronic device comprising: A memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor implements the steps of the synchronization data crosstalk effect optimization method according to any one of claims 1 to 6 when executing the computer program.

9. A computer-readable storage medium having stored therein instructions, the computer-readable storage medium comprising: The instructions, when executed on an electronic device, cause the electronic device to perform the synchronization data crosstalk effect optimization method according to any one of claims 1 to 6.

10. A synchronous digital hierarchy comprising at least two parallel paths; characterized by, The synchronization data crosstalk effect optimization method according to any one of claims 1 to 6 optimizes crosstalk effects of any two parallel channels. The synchronization data crosstalk effect optimization method according to any one of claims 1 to 6 optimizes crosstalk effects of any two parallel channels.

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