Asynchronous data communication cache control system between satellite-borne processor and communication controller
By using AC logic devices to build an access control arbitration circuit in the onboard computer, the problem of asynchronous data sharing and interaction between the processor and the communication controller was solved, realizing large-capacity caching and efficient communication, improving system reliability and reducing costs.
Patent Information
- Application Number
- CN202511665524.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-11-13
- Publication Date
- 2026-02-17
AI Technical Summary
In existing technologies, asynchronous data sharing and interaction between the processor and communication controller of spaceborne computers suffer from the problem that large data volume caching requirements cannot be met, and dual-port RAM is large in size and small in capacity, which cannot effectively solve timing mismatch and access conflicts.
A highly reliable and low-cost AC logic device is used to build an access control arbitration circuit between the processor, communication controller and shared data memory. Through the design of bus driver and interface, asynchronous data sharing and exchange between the processor and communication controller can be realized, avoiding timing mismatch and access conflict.
It implements a large-capacity data cache between the processor and the communication controller, avoiding timing mismatches and access conflicts, improving the reliability and processing efficiency of the communication system, and reducing component and maintenance costs.
Smart Images
Figure CN121547426A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of aerospace technology, and in particular to an asynchronous data communication buffer control system between a spaceborne processor and a communication controller. Background Technology
[0002] With the development of aerospace technology, the amount of communication data between various subsystems on a satellite has increased significantly, requiring the design of communication systems with higher transmission rates for onboard computers. When designing high-speed onboard communication systems, it is urgent to solve the problem of asynchronous data sharing and interaction of large amounts of data between the computer's processor and communication controller.
[0003] Currently, to avoid conflicts when the processor and communication controller simultaneously access the shared data storage area, dual-port RAM (DPRAM) is typically used for data caching. DPRAM has two independent data, address, and control buses, and integrates access arbitration logic, allowing two devices to access data simultaneously. However, current domestically produced aerospace-grade DPRAMs are large in size and small in capacity, failing to meet the large data caching requirements of onboard computers.
[0004] Therefore, there is an urgent need for an asynchronous data communication buffer control system between the onboard processor and the communication controller to solve the above problems. Summary of the Invention
[0005] This invention provides an asynchronous data communication buffer control system between a spaceborne processor and a communication controller, which enables asynchronous data sharing and exchange between the processor and the communication controller, avoiding timing mismatches and access conflicts. The technical solution is as follows: In a first aspect, embodiments of the present invention provide an asynchronous data communication cache control system between a spaceborne processor and a communication controller, the system comprising: a processor, a communication controller, a shared data memory, a first bus driver, and a second bus driver; The input terminals of the first bus driver and the second bus driver are respectively connected to the processor, and the output terminals are respectively connected to the bus of the shared data memory; when the bus driver is enabled, the processor can access the shared data memory. The processor includes multiple external memory interfaces, general-purpose interfaces, and interrupt input interfaces; the communication controller includes multiple communication memory interfaces, host interfaces, arbitration signal interfaces, and interrupt output interfaces. Each of the communication memory interfaces is connected to the bus of the shared data storage device to enable the communication memory to access the shared data storage device; Each of the host interfaces is connected to an external memory interface with a corresponding function to configure the communication controller; each of the arbitration signal interfaces is connected to a general interface with a corresponding function to arbitrate access permissions to the shared data memory bus; the interrupt output interface is connected to the interrupt input interface to transmit the data reception status of the communication controller.
[0006] Secondly, embodiments of the present invention also provide an asynchronous data communication buffer control method between a spaceborne processor and a communication controller, applicable to any of the above-mentioned possible control systems, the method comprising: The input terminals of the first bus driver and the second bus driver are respectively connected to the processor, and the output terminals are respectively connected to the bus of the shared data storage; by setting the enable state of the bus driver, the access permissions of the processor to the shared data storage are controlled. Each of the communication memory interfaces is connected to the bus of the shared data storage device to control the access permissions of the communication memory to the shared data storage device; The host interface of the communication controller is connected to the corresponding external memory interface of the processor to enable the processor to configure the communication controller; Each arbitration signal interface of the communication controller is connected to the corresponding general interface of the processor to arbitrate access permissions to the shared data memory bus; The interrupt output interface of the communication controller is connected to the interrupt input interface of the processor to transmit the data reception status of the communication controller.
[0007] This invention provides an asynchronous data communication buffer control system between an onboard processor and a communication controller. Utilizing highly reliable and low-cost AC logic devices, an access control arbitration circuit is established between the general-purpose processor, the communication controller, and the shared data memory. This circuit matches the timing of the processor and communication controller's access to the shared data memory while simultaneously establishing a handshake mechanism between the processor and the communication controller, and an access control mechanism for the shared data memory. Ultimately, this enables the processor and communication controller to efficiently share the data, address, and control buses of the shared data memory on demand and in a time-sharing manner, avoiding timing mismatches and access conflicts, and achieving asynchronous data sharing and exchange between the processor and the communication controller. Attached Figure Description
[0008] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0009] Figure 1 This is a schematic diagram of an asynchronous data communication buffer control system between a spaceborne processor and a communication controller, provided in an embodiment of the present invention. Figure 2 This is a schematic diagram of an asynchronous data communication buffer control system between a spaceborne processor and a communication controller, provided in another embodiment of the present invention. Detailed Implementation
[0010] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are some embodiments of the present invention, but not all embodiments. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without creative effort are within the scope of protection of the present invention.
[0011] The following describes the specific implementation of the above concept.
[0012] Please refer to Figure 1 The present invention provides an asynchronous data communication buffer control system between a spaceborne processor and a communication controller, the system comprising: Processor, communication controller, shared data memory, first bus driver and second bus driver; The input terminals of the first bus driver and the second bus driver are respectively connected to the processor, and the output terminals are respectively connected to the bus of the shared data memory; when the bus driver is enabled, the processor can access the shared data memory. The processor includes multiple external memory interfaces, general-purpose interfaces, and interrupt input interfaces; the communication controller includes multiple communication memory interfaces, a host interface, an arbitration signal interface, and interrupt output interfaces. Each communication memory interface is connected to the bus of the shared data memory to enable the communication memory to access the shared data memory; Each host interface is connected to the corresponding external memory interface to configure the communication controller; each arbitration signal interface is connected to the corresponding general interface to arbitrate access permissions to the shared data memory bus; the interrupt output interface is connected to the interrupt input interface to transmit the data reception status of the communication controller.
[0013] In this embodiment, a highly reliable and low-cost AC logic device is used to build an access control arbitration circuit between the general-purpose processor, the communication controller, and the shared data memory (single-port SPSRAM). This circuit matches the timing of the processor and communication controller's access to the shared data memory while establishing a handshake mechanism between the processor and the communication controller, as well as an access control mechanism for the shared data memory. Ultimately, this enables the processor and communication controller to efficiently share the data, address, and control buses of the shared data memory on demand and in a time-sharing manner, avoiding timing mismatches and access conflicts, and achieving asynchronous data sharing and exchange between the processor and the communication controller.
[0014] In some implementations, the external memory interface, the communication memory interface, and the host interface all include a read interface, a write interface, a data interface, an address interface, and a chip select interface; The processor allocates corresponding external memory address spaces to the communication controller and shared data memory through the address interface and chip select interface, implements read / write access control of the internal configuration registers and communication channels of the communication controller through the read interface and write interface, indicates the data required for the operation of the communication controller through the data interface, and identifies devices that can be connected to the shared data memory bus through the general interface.
[0015] The connection relationships between the interfaces are described in detail below using specific embodiments, such as... Figure 2 As shown: (1) For the processor, the read interface, write interface, data interface and address interface in the external memory interface (EMIF interface) are respectively denoted as: CPU_OE*, CPU_WE*, CPU_D<31:0>, CPU_RA<23:2>; In addition, there are two chip select interfaces, one corresponding to the communication controller, denoted as CPU_CS0*, and the other corresponding to the shared data memory, denoted as CPU_CS1*.
[0016] (2) For the communication controller, the read interface, write interface, data interface, address interface and chip select interface of each communication memory interface (COMI interface) are respectively denoted as: CPU_COMI_OE*, CPU_COMI_WE*, CPU_COMI_D<31:0>, CPU_COMI_RA<23:2>, CPU_COMI_CS0*; (3) For the communication controller, the read interface, write interface, data interface, address interface and chip select interface of each host interface (HOCI interface) are respectively denoted as: CPU_HOCI_OE*, CPU_HOCI_WE*, CPU_HOCI_D<31:0>, CPU_HOCI_RA<17:0>, CPU_HOCI_CS0*.
[0017] As shown in the diagram, the chip select interfaces CPU_HOCI_CS0* and CPU_CS0* are connected, CPU_HOCI_OE* is connected to CPU_OE*, CPU_HOCI_WE* is connected to CPU_WE*, CPU_D<31:0> is connected to CPU_HOCI_D<31:0>, and CPU_RA<23:2> is connected to CPU_HOCI_RA<17:0>. When the CPU_CS0* signal is valid, the processor can access the internal registers and communication channels of the communication controller through the external memory interface. Thus, the processor can directly operate the communication channel of the communication controller through the configuration interface to send and receive data packets. However, although this eliminates the need for external shared data memory for data storage, the processor requires frequent interaction with the communication controller, and the size of communication data packets is limited, severely restricting the processing efficiency of the onboard computer.
[0018] Therefore, this application requires the addition of a shared data memory between the processor and the communication controller, and improvements to the connection management of the control system.
[0019] In some implementations, the shared data memory includes a control bus, an address bus, and a data bus; the chip select interface CPU_COMI_CS0*, read interface CPU_COMI_OE*, and write interface CPU_COMI_WE* in the communication memory interface are respectively connected to the control bus; the address interface CPU_COMI_RA<23:2> in the communication memory interface is connected to the address bus; and the data interface CPU_COMI_D<31:0> in the communication memory interface is connected to the data bus.
[0020] In some implementations, a first bus driver is used to drive the address bus and control bus of the shared data memory; a second bus driver is used to drive the data bus of the shared data memory. The processor's chip select interface CPU_CS1*, read interface CPU_OE*, write interface CPU_WE*, and address interface CPU_RA<23:2> are respectively connected to the address bus and control bus through the first bus driver U1; The processor's data interface CPU_D<31:0> is connected to the address bus and control bus via the second bus driver U2.
[0021] With the above improvements, each COMI interface of the communication controller is directly connected to the control, address, and data buses of the shared data memory. In addition, in order to avoid conflicts when the processor and the communication controller access the shared data memory at the same time, the data lines, address lines, and control lines of the processor's EMIF interface are connected to the shared data memory through the corresponding bus drivers.
[0022] In addition, both the first bus driver and the second bus driver include an enable pin (EN*); the processor's general interface also includes an enable interface CPU_GPIO[2]*; The enable terminal of the first bus driver is controlled by the enable signal of the enable interface; The enable terminal of the second bus driver is controlled by the AND signal obtained by the enable signal of the enable interface and the chip select signal of the processor's chip select interface CPU_CS1*. When the enable pin of the bus driver is low, it is in the enabled state, and the signal from the corresponding interface of the processor is transmitted from the input pin of the bus driver to the output pin and output to the corresponding bus of the shared data memory. When the enable pin of the bus driver is high, it is in the disabled state, and the signal from the corresponding interface of the processor cannot be output to the corresponding bus of the shared data memory.
[0023] In some implementations, the processor's general-purpose interface includes an active interface CPU_GPIO[1] and a passive interface CPU_GPIO[0]; the arbitration signal interface includes a requested interface CCU_COCI connected to the active interface and a request interface CCU_COCO connected to the passive interface; The processor and communication controller arbitrate access permissions to the shared data memory bus in the following manner: Before the communication controller accesses the shared data memory, it determines whether the following conditions are met: All requested interfaces are in a low-level state; if this condition is met, the communication controller is allowed to access the shared data memory; if not, the communication controller is not allowed to access the shared data memory. When the communication controller wants to access the shared data memory, it sets the request interface to high level to ask the processor whether it agrees to release the access right of the shared data memory. If it agrees, the processor sets the active interface to low level, allowing the communication controller to access the shared data memory. If it does not agree, the processor sets the active interface to high level, and does not allow the communication controller to access the shared data memory.
[0024] By adopting the above method, this embodiment can avoid conflicts between the processor's EMIF interface and the communication controller's COMI interface. That is, the processor's EMIF interface signal of the bus driver and the COMI interface signal of the communication controller cannot be effective at the same time. When one is effective, the other must be in a high-impedance state, thereby preventing the processor and the communication controller from accessing the shared data memory at the same time.
[0025] In some implementations, the communication controller and processor store and transmit external communication data in the following manner: After the processor is powered on, it sets the start address register of the receive data buffer and the start address register of the transmit data buffer of the communication channel through the external memory interface corresponding to the host interface of the communication controller. When the communication controller receives bus communication data and has access rights, it stores the data in the shared data memory starting from the beginning address of the receive data buffer. When the communication ends, it writes the storage address of the last byte of the data packet into the end address register of the receive data buffer and generates a receive data interrupt signal. The interrupt signal is then sent to the interrupt input interface for processing through the interrupt output interface. When the processor receives an interrupt signal, it sets the active interface from low to high, and after N nop instructions, it sets the enable interface from high to low. When the requested interface of the communication controller receives a high-level signal, after completing the current read / write operation on the shared data memory, it sets each communication memory interface to high impedance and relinquishes bus control. At this time, the processor reads the end address register of the receive data buffer of the communication controller through the external memory interface to obtain the end address of the receive data, and then reads the communication data between the start address and the end address of the receive data from the shared data memory.
[0026] When the processor needs the communication controller to send communication data, it raises the active interface from low to high and, after N nop instructions, raises the enable interface from high to low. After gaining access to the shared data memory, it stores the data packets to be sent through the communication controller, starting from the beginning address of the transmit data buffer, into the shared data memory, and writes the storage address of the last byte of the data packet into the end address register of the transmit data buffer of the communication controller. After completing the above operations, the processor raises the enable interface from low to high and raises the active interface from high to low, so that the communication controller can gain access to the shared data memory, read data from the transmit data buffer of the shared data memory, and send it outward.
[0027] In this implementation, the data packet can be in 32-bit format or other formats; this application does not specifically limit its usage. Furthermore, when the processor receives an interrupt signal, it sets the active interface from low to high, and after N nop instructions, it sets the enable interface from high to low because: When the CCU_COCI pin of the communication controller receives a high level, its COMI interface will not immediately become high-impedance. Instead, it will only be set to high-impedance after the current access to the shared data memory is completed. To prevent conflicts between the processor address lines and control lines passing through the first bus driver U1 and the address lines and control lines of the communication controller's COMI interface, the first bus driver U1 needs to be enabled only after the communication controller's COMI interface becomes high-impedance. Furthermore, N is a natural number, determined by the processor and communication controller's clock frequency and timing design, and is not specifically limited in this application.
[0028] In summary, this application overcomes the capacity limitations of aerospace-grade DSP RAM, enabling the cache memory between the processor and communication controller to reach the MB level, thus achieving large-capacity communication cache. Furthermore, due to the increased capacity of the shared data memory between the processor and communication controller, frequent interaction between them is unnecessary, effectively solving the atomicity and integrity issues of asynchronous communication data frames by trading capacity for time. Finally, by using AC logic devices instead of FPGAs to implement the timing control and arbitration logic for shared data memory access, component costs, FPGA code development, maintenance, and management costs can be significantly reduced, while increasing the reliability of the communication system.
[0029] The present invention also provides an asynchronous data communication buffer control method between a spaceborne processor and a communication controller, applicable to the control system in any of the above embodiments, the method comprising: The input terminals of the first bus driver and the second bus driver are connected to the processor, and the output terminals are connected to the bus of the shared data memory. The access permissions of the processor to the shared data memory are controlled by setting the enable state of the bus driver. Each communication memory interface is connected to the bus of the shared data memory to control the access permissions of the communication memory to the shared data memory; The host interface of the communication controller is connected to the corresponding external memory interface of the processor to enable the processor to configure the communication controller. Each arbitration signal interface of the communication controller is connected to the corresponding general interface of the processor to arbitrate access permissions to the shared data memory bus; Connect the interrupt output interface of the communication controller to the interrupt input interface of the processor to transmit the data reception status of the communication controller.
[0030] In some implementations, the method further includes: The processor address interface and chip select interface are used to allocate the address space corresponding to the external memory to the communication controller; The processor's read and write interfaces enable read / write access to the internal configuration registers and communication channels of the communication controller. The processor's data interface indicates the data required for the communication controller's operation; The processor's general-purpose interface identifies devices that can be connected to the shared data memory bus.
[0031] In some implementations, the method further includes: Connect the chip select interface, read interface, and write interface in the communication memory interface to the control bus of the shared data memory respectively; Connect the address interface in the communication memory interface to the address bus of the shared data memory; Connect the data interface in the communication memory interface to the data bus of the shared data memory.
[0032] It should be noted that the control method provided in this embodiment and the control system provided in the above embodiment are based on the same inventive concept, and therefore have the same beneficial effects, which will not be elaborated here.
[0033] Finally, it should be noted that in this document, relational terms such as first, second, third, and fourth are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.
[0034] The above description is only a preferred embodiment of this application. It should be noted that for those skilled in the art, several improvements and modifications can be made without departing from the principle of this application, and these improvements and modifications should also be considered within the scope of protection of this application.
Claims
1. An asynchronous data communication buffer control system between a space-borne processor and a communication controller, characterized by, The system comprises a processor, a communication controller, a shared data memory, a first bus driver and a second bus driver; The input ends of the first bus driver and the second bus driver are connected with the processor respectively, and the output ends are connected with the bus of the shared data memory respectively; when the bus driver is in the enabled state, the access of the processor to the shared data memory is realized; The processor comprises a plurality of external memory interfaces, a general interface and an interrupt input interface; the communication controller comprises a plurality of communication memory interfaces, host interfaces, arbitration signal interfaces and an interrupt output interface; Each of the communication memory interfaces is connected with the bus of the shared data memory respectively, so as to realize the access of the communication memory to the shared data memory; Each of the host interfaces is hung on the external memory interface of the corresponding function respectively, so as to realize the configuration of the communication controller; each of the arbitration signal interfaces is connected with the general interface of the corresponding function, so as to realize the arbitration of the access right of the shared data memory bus; the interrupt output interface is connected with the interrupt input interface, so as to transmit the receiving state of the communication controller.
2. The system of claim 1, wherein, The external memory interface, the communication memory interface and the host interface all comprise a read interface, a write interface, a data interface, an address interface and a chip select interface; The processor allocates the corresponding processor external memory address space for the communication controller and the shared data memory through the address interface and the chip select interface, realizes the read / write access of the internal configuration register and the communication channel of the communication controller through the read interface and the write interface, and indicates the data required by the operation of the communication controller through the data interface; The general interface is used to determine the device which can be connected with the bus of the shared data memory.
3. The system of claim 2, wherein, The shared data memory comprises a control bus, an address bus and a data bus; the chip select interface, the read interface and the write interface in the communication memory interface are hung on the control bus respectively; the address interface in the communication memory interface is hung on the address bus; The data interface in the communication memory interface is hung on the data bus.
4. The system of claim 3, wherein, The first bus driver is used to drive the address bus and the control bus of the shared data memory; the second bus driver is used to drive the data bus of the shared data memory; The chip select interface, the read interface, the write interface and the address interface of the processor are hung on the address bus and the control bus through the first bus driver respectively; The data interface of the processor is hung on the data bus of the shared data memory through the second bus driver.
5. The system of claim 3, wherein, The first bus driver and the second bus driver both comprise an enable end; the general interface of the processor comprises an enable interface; The enable end of the first bus driver is controlled by the enable signal of the enable interface; The enable end of the second bus driver is controlled by the signal obtained by the logical AND operation of the enable signal of the enable interface and the chip select signal of the chip select interface of the processor; When the enable terminal of the bus driver is in low level state, the bus driver is in enabled state, the signal corresponding to the interface of the processor is transmitted from the input terminal to the output terminal of the bus driver and output to the corresponding bus of the shared data memory; when the enable terminal of the bus driver is in high level state, the bus driver is in disabled state, the signal corresponding to the interface of the processor cannot be output to the corresponding bus of the shared data memory, and the output terminal of the bus driver is in high impedance state.
6. The system of claim 3, wherein, The general interface of the processor comprises an active interface and a passive interface; the arbitration signal interface comprises a requested interface connected with the active interface and a request interface connected with the passive interface; The processor and the communication controller realize arbitration of the bus access right of the shared data memory in the following manner: Before the communication controller accesses the shared data memory, it is judged whether the following condition is met: the requested interface is in low level state; if yes, the communication controller is allowed to access the shared data memory; if not, the communication controller is not allowed to access the shared data memory; When the communication controller wants to access the shared data memory, the request interface is set to high level to inquire whether the processor agrees to release the access right of the shared data memory; If yes, the processor sets the active interface to low level state to allow the communication controller to access the shared data memory; if not, the processor sets the active interface to high level state to not allow the communication controller to access the shared data memory.
7. The system of claim 6, wherein, The communication controller and the processor realize storage and transmission of external communication data in the following manner: After the processor is powered on, the processor sets the start address register of the receiving data buffer area and the start address register of the transmitting data buffer area of the communication channel of the communication controller through the external memory interface corresponding to the host interface of the communication controller; When the communication controller receives bus communication data and has access right, the data is stored in the shared data memory from the start address of the receiving data buffer area; When the communication ends, the last byte storage address of the data packet is written into the end address register of the receiving data buffer area, and a receiving data interrupt signal is generated and transmitted to the interrupt input interface of the processor through the interrupt output interface; After the processor receives the interrupt signal, the active interface is set from low to high, and after N nop instructions, the enable interface is set from high to low; after the requested interface of the communication controller receives the high level signal, the read and write operation of the shared data memory is completed, and each communication memory interface is changed to high impedance to give up the bus control right; at this time, the processor reads the end address register of the receiving data buffer area of the communication controller through the external memory interface to obtain the end address of the receiving data, and then reads the receiving data between the start address and the end address of the receiving data from the shared data memory. When the processor needs the communication controller to send communication data, the active interface is set from low to high, and after N nop instructions, the enable interface is set from high to low, the shared data memory access right is obtained, and the data packet to be sent through the communication controller is stored in the shared data memory from the start address of the sending data buffer, and the last byte of the data packet is stored in the end address register of the sending data buffer of the communication controller; after the above operations are completed, the processor sets the enable interface from low to high, and sets the active interface from high to low, so that the communication controller obtains the access right of the shared data memory, reads data from the shared data memory and sends it out.
8. A method for controlling buffering of asynchronous data communications between a space-borne processor and a communication controller, characterized by, The method is applied to the system of any one of claims 3-7, and the method comprises: The input terminals of the first bus driver and the second bus driver are connected with the processor respectively, and the output terminals are connected with the bus of the shared data memory respectively; the access right of the shared data memory by the processor is controlled by setting the enable state of the bus driver; Each communication memory interface is connected with the bus of the shared data memory respectively, so as to control the access right of the shared data memory by the communication memory; The host interface of the communication controller is hung on the corresponding external memory interface of the processor, so as to realize the configuration of the processor to the communication controller; Each arbitration signal interface of the communication controller is connected with the corresponding general interface of the processor respectively, so as to realize the arbitration of the access right of the shared data memory bus; The interrupt output interface of the communication controller is connected with the interrupt input interface of the processor, so as to transmit the receiving state of the communication controller.
9. The method of claim 8, wherein, The method further comprises: The external memory corresponding address space of the communication controller is allocated by using the chip select interface and the address interface of the processor; The read / write access to the internal configuration register and communication channel of the communication controller is realized by the read interface and the write interface of the processor; The data required by the operation of the communication controller is indicated by the data interface of the processor; The device which can be connected with the shared data memory bus is determined by the general interface of the processor.
10. The method of claim 9, wherein, The method further comprises: The chip select interface, the read interface and the write interface in the communication memory interface are hung on the control bus of the shared data memory respectively; The address interface in the communication memory interface is hung on the address bus of the shared data memory; The data interface in the communication memory interface is hung on the data bus of the shared data memory.