Semiconductor device and method of manufacturing the same

Abstract

The present disclosure relates to the technical field of semiconductor, and provides a semiconductor device and a manufacturing method thereof. The semiconductor device comprises a substrate, a first shallow trench isolation structure and a first overlay mark structure. The substrate comprises a chip area and a scribe lane area. The chip area is formed with a first trench, and the scribe lane area is formed with a second trench. The first shallow trench isolation structure is located in the first trench of the chip area and comprises a first insulating layer in contact with the inner wall of the first trench. The top surface of the first insulating layer is higher than the surface of the substrate, which can improve the topography of the first shallow trench isolation structure before deposition of the high-k dielectric layer of the peripheral transistor, and avoid the problem of short circuit of adjacent gates. The first overlay mark structure is located in the second trench of the scribe lane area and comprises a first filling layer in contact with the inner wall of the second trench. The top surface of the first filling layer is higher than the surface of the substrate, which can improve the optical measurement signal intensity and contrast of the first overlay mark structure, and is beneficial to improving the overlay accuracy.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and in particular to semiconductor devices and methods of manufacturing the same. Background Technology

[0002] Dynamic Random Access Memory (DRAM) has become an indispensable type of memory in modern computers and electronic devices due to its high storage density, high-speed data access, and suitability for large-scale integration. As semiconductor manufacturing processes continue to miniaturize, the precision requirements for manufacturing processes are becoming increasingly stringent. Issues such as overlay accuracy and the surface morphology of shallow trench isolation structures have become key challenges for improving the performance of high-density memories. Summary of the Invention

[0003] In view of the above, this disclosure provides a semiconductor device and a method for manufacturing the same.

[0004] Some embodiments of this disclosure provide a semiconductor device, including:

[0005] A substrate, the substrate including a chip region and a dicing region, the chip region having a first trench extending from the surface of the substrate to the interior, and the dicing region having a second trench extending from the surface of the substrate to the interior;

[0006] A first shallow trench isolation structure is located within the first trench of the chip region, and the first shallow trench isolation structure includes a first insulating layer that contacts the inner wall of the first trench.

[0007] The first set of marking structures is located in the second groove of the cutting channel area, and the first set of marking structures includes a first filling layer that contacts the inner wall of the second groove;

[0008] Wherein, the top surface of the first insulating layer is higher than the surface of the substrate, and the top surface of the first filling layer is higher than the surface of the substrate.

[0009] Some embodiments of this disclosure provide a method for manufacturing a semiconductor device, including:

[0010] A substrate is provided, the substrate including a chip region and a dicing region;

[0011] A first trench extending from the substrate surface to the interior is formed in the chip region, and a second trench extending from the substrate surface to the interior is formed in the dicing region;

[0012] A first shallow trench isolation structure is formed in the first trench, the first shallow trench isolation structure including a first insulating layer in contact with the inner wall of the first trench, the top surface of the first insulating layer being higher than the substrate surface;

[0013] A first set of marking structures is formed in the second trench. The first set of marking structures includes a first filling layer that contacts the inner wall of the second trench. The top surface of the first filling layer is higher than the surface of the substrate.

[0014] In the semiconductor device provided in this disclosure, the top surface of the first insulating layer in the first shallow trench isolation structure is higher than the substrate surface. This can mitigate the consumption of the first insulating layer by the etching steps before the formation of the high-k (k is the dielectric constant) dielectric layer in the subsequent peripheral transistors, providing sufficient window for these etching steps. It also reduces the risk of depressions forming on the top surface of the first shallow trench isolation structure before the high-k dielectric layer deposition, improving the problem of short circuits between adjacent gates and thus enhancing the reliability and electrical performance of the semiconductor device. Furthermore, by utilizing the fact that the top surface of the first filling layer in the first set of marking structures formed simultaneously with the first shallow trench isolation structure is higher than the substrate surface, the intensity of the optical measurement signal can be increased, as can the contrast between the first set of marking structures and the substrate in the optical measurement signal. This improves the overlay accuracy. Therefore, using the overlay marking structure for overlay alignment when forming word line trenches can improve the positional accuracy of the word lines relative to the active region, ensuring the effective contact area between the memory node plug and the active region, and ultimately improving the performance of the semiconductor device. Attached Figure Description

[0015] Figure 1a A schematic diagram of a storage cell array provided in an embodiment of this disclosure;

[0016] Figure 1b A schematic diagram of a peripheral region provided in an embodiment of this disclosure;

[0017] Figure 1c for Figure 1b A schematic diagram of the second isolation structure in the diagram;

[0018] Figure 2 A schematic diagram of a semiconductor device provided in an embodiment of this disclosure;

[0019] Figure 3 Schematic diagram of a semiconductor device provided in the embodiments of this disclosure Figure 2 ;

[0020] Figure 4 A schematic diagram of the first shallow trench isolation structure and the first set of marking structures provided in the embodiments of this disclosure;

[0021] Figure 5A schematic diagram of the peripheral region including the second shallow trench isolation structure provided in an embodiment of this disclosure;

[0022] Figure 6 Schematic diagram of a semiconductor device provided in the embodiments of this disclosure Figure 3 ;

[0023] Figure 7 A schematic diagram of the third and fourth shallow trench isolation structures provided in the embodiments of this disclosure;

[0024] Figure 8 A schematic flowchart illustrating a method for manufacturing a semiconductor device according to an embodiment of this disclosure;

[0025] Figure 9 A schematic diagram of the manufacturing process of a semiconductor device provided in this disclosure embodiment;

[0026] Figure 10 A schematic diagram of the manufacturing process of the semiconductor device provided in the embodiments of this disclosure. Figure 2 ;

[0027] Figure 11 A schematic diagram of the manufacturing process of the semiconductor device provided in the embodiments of this disclosure. Figure 3 ;

[0028] Figure 12 A schematic diagram of the manufacturing process of the semiconductor device provided in the embodiments of this disclosure. Figure 4 ;

[0029] Figure 13 A schematic diagram of the manufacturing process of the semiconductor device provided in the embodiments of this disclosure. Figure 5 ;

[0030] Figure 14 A schematic diagram of the manufacturing process of the semiconductor device provided in the embodiments of this disclosure. Figure 6 ;

[0031] Figure 15 A schematic diagram of the manufacturing process of the semiconductor device provided in the embodiments of this disclosure. Figure 7 ;

[0032] Figure 16 A schematic diagram of the manufacturing process of the semiconductor device provided in the embodiments of this disclosure. Figure 8 ;

[0033] Figure 17 A schematic diagram of the manufacturing process of the semiconductor device provided in the embodiments of this disclosure. Figure 9 ;

[0034] Figure 18 A schematic diagram of the manufacturing process of the semiconductor device provided in the embodiments of this disclosure. Figure 10 ;

[0035] Figure 19 A schematic diagram of the manufacturing process of the semiconductor device provided in the embodiments of this disclosure. Figure 10 one;

[0036] Figure 20 A schematic diagram of the manufacturing process of the semiconductor device provided in the embodiments of this disclosure. Figure 10 two;

[0037] Figure 21 A schematic diagram of the manufacturing process of the semiconductor device provided in the embodiments of this disclosure. Figure 10 three;

[0038] Figure 22 A schematic diagram of the manufacturing process of the semiconductor device provided in the embodiments of this disclosure. Figure 10 Four;

[0039] Figure 23 A schematic diagram of the manufacturing process of the semiconductor device provided in the embodiments of this disclosure. Figure 10 five;

[0040] Figure 24 A schematic diagram of the manufacturing process of the semiconductor device provided in the embodiments of this disclosure. Figure 10 six;

[0041] Figure 25 A schematic diagram of the manufacturing process of the semiconductor device provided in the embodiments of this disclosure. Figure 10 seven. Detailed Implementation

[0042] Exemplary embodiments of the present disclosure will now be described in more detail with reference to the accompanying drawings. While exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be implemented in various forms and should not be limited to the specific embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.

[0043] In the description of this disclosure, it should be understood that the terms “length,” “width,” “depth,” “upper,” “lower,” “outer,” etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, and are only for the convenience of describing this disclosure and simplifying the description, and are not intended to indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this disclosure.

[0044] Figure 1a This is a schematic diagram of a memory cell array provided in an embodiment of the present disclosure, wherein the X and Y directions are perpendicular to each other and both parallel to the substrate surface, and the Z direction is perpendicular to the substrate surface. Figure 1aAs shown, a first isolation structure 12 is formed within the substrate of the array region. The first isolation structure 12 isolates multiple first active regions 11 within the substrate, and the multiple first active regions 11 are arranged in an array. A word line trench 20 extends from the substrate surface into the substrate, extending along the X direction through the multiple first active regions 11 and the first isolation structure 12 located between adjacent first active regions 11. Word lines are formed within the word line trench 20, and the word lines extend continuously along the X direction within the word line trench 20. The first active regions 11 and the word lines located within the first active regions 11 are used to form transistors for memory cells. Figure 1a As shown, the first active region 11 is located at both ends of the word line trench 20, contacting the bit line plug 31 and the memory node plug 32 respectively. The bit line plug 31 is connected to the bit line, and the memory node plug 32 is connected, for example, to a capacitor. As the feature size of the first active region 11 continues to decrease, the requirements for overlay accuracy during the fabrication of the word line trench 20 become increasingly stringent. Overlay accuracy is a performance indicator that measures the alignment deviation between two patterns formed by consecutive photolithography processes. Poor overlay accuracy will affect the positional accuracy of the word line trench 20 within the first active region 11, potentially reducing the effective contact area between the memory node plug 32 and the first active region 11, or reducing the effective contact area between the bit line plug 31 and the first active region 11, thus adversely affecting the performance of the semiconductor device.

[0045] Figure 1b This is a schematic diagram of the peripheral area provided in an embodiment of the present disclosure. Figure 1c for Figure 1b A partial sectional view of the second isolation structure along the XZ plane. It should be noted that... Figure 1b The gate oxide layer was hidden to clearly indicate the location of the second isolation structure. For example... Figure 1b As shown, a second isolation structure 13 is formed within the substrate of the peripheral region, isolating multiple second active regions 14 within the substrate. A first gate 22-1 is located above the second isolation structure 13 between the two second active regions 14 and extends along the X direction. A second gate 22-2 is arranged side-by-side with the first gate 22-1 along the Y direction, and the second gate 22-2 is also located above the second isolation structure 13 between the two second active regions 14. In some embodiments, a high-k dielectric layer is provided between the gate 22 and the gate oxide layer 23 on the substrate surface. The high-k dielectric layer is prepared by first forming a high-k dielectric material 24 and then patterning it, and the gate 22 is prepared by first forming a gate material 22′ and then patterning it.

[0046] like Figure 1c and 1bAs shown, after the gate oxide layer 23 is formed, if there are deep depressions or open voids on the top surface of the second isolation structure 13, high-k dielectric material 24 and gate material 22' may remain there during the gate fabrication process. The residual high-k dielectric material 24 may contaminate the metal of the subsequent layer, and the residual gate material 22' may come into contact with two adjacent gates 22, causing the two adjacent gates 22 to short-circuit through the residual gate material 22' on the top of the second isolation structure 13, which will adversely affect the performance of the semiconductor device.

[0047] In view of this, embodiments of the present disclosure provide a semiconductor device for improving overlay accuracy and improving the morphology of the isolation structure. Figure 2 A schematic diagram of a semiconductor device provided in an embodiment of this disclosure is shown below. Figure 2 The semiconductor device includes a substrate 100, a first shallow trench isolation structure 310, and a first set of marking structures 410. The substrate 100 includes a chip region and a dicing region. The chip region has a first trench 210 extending from the surface of the substrate 100 to its interior, and the dicing region has a second trench 220 extending from the surface of the substrate 100 to its interior. The first shallow trench isolation structure 310 is located within the first trench 210 of the chip region and includes a first insulating layer 311 in contact with the inner wall of the first trench 210. The first set of marking structures 410 is located within the second trench 220 of the dicing region and includes a first filling layer 411 in contact with the inner wall of the second trench 220. The top surface 311a of the first insulating layer 311 is higher than the substrate surface 100a, and the top surface 411a of the first filling layer 411 is higher than the substrate surface 100a. For example, the substrate 100 includes a plurality of chip regions arranged in an array, with dicing regions between adjacent chip regions. The chip area is used to form memory cell arrays and peripheral circuits, etc. The dicing area is used to form overlay marks, test circuits, and dummy conductive lines, etc.

[0048] like Figure 2 As shown, a plurality of first shallow trench isolation structures 310 are formed within the substrate 100 of the chip region. Each first shallow trench isolation structure 310 includes a first insulating layer 311, the side of which contacts the substrate 100. For example, the first shallow trench isolation structure 310 may be made of a single material, meaning the first insulating layer 311 can fill the first trench 210. Alternatively, the first shallow trench isolation structure may be a composite structure including multiple layers of different materials; that is, in addition to the first insulating layer 311, other material layers may also be included. For example, the material of the first insulating layer includes silicon oxide.

[0049] In this embodiment, the top surface 311a of the first insulating layer 311 in the first shallow trench isolation structure 310 is higher than the substrate surface 100a. This can cope with the consumption of the first insulating layer by the etching steps before the formation of the high-k dielectric layer of the peripheral transistor, providing sufficient window for these etching steps, and reducing the risk of the top surface of the first shallow trench isolation structure forming a depression before the deposition of the high-k dielectric layer, reducing the problem of short circuit between adjacent gates, which is beneficial to improving the reliability and electrical performance of semiconductor devices.

[0050] Figure 3 Schematic diagram of a semiconductor device provided in the embodiments of this disclosure Figure 2 Several first sets of markings are formed within the substrate of the dicing zone. Figure 3 A schematic diagram of the first set of markings in the cutting channel area is shown. (See diagram.) Figure 3 As shown, the first set of markings includes multiple marking arrays 400, each marking array 400 including multiple strip patterns arranged at intervals, such as multiple first set of marking structures 410 arranged side by side with equal spacing and width. It should be noted that in other embodiments, the first set of markings may also adopt other geometric patterns, such as cross-shaped or meander-shaped patterns, and this disclosure does not impose excessive limitations on this. In different embodiments, the first set of markings may include one or more first set of marking structures 410. Figure 2 The two first set of marking structures 410 in the middle can be Figure 3 A partial cross-sectional view of the marker array 400 along the direction indicated by the arrow.

[0051] See back Figure 2 The first overlay marking structure 410 includes a first filling layer 411, the side of which contacts the substrate 100. In this embodiment, the top surface 411a of the first filling layer 411 is higher than the substrate surface 100a, which can improve the intensity of the optical measurement signal and the contrast between the overlay marking and the substrate in the optical measurement signal, thereby improving the overlay accuracy. Furthermore, the top surface of the first filling layer being higher than the substrate surface can effectively support the top edge of the first trench, reducing the risk of deformation of the top edge of the first trench, thus maintaining a good morphology of the edge of the first overlay marking, which is beneficial for improving the contrast of the optical measurement signal and improving the overlay accuracy. Therefore, using overlay markings for overlay alignment when forming word line trenches can improve the positional accuracy of the word lines relative to the active region, ensure the effective contact area between the memory node plug and the active region, and improve the performance of the semiconductor device.

[0052] In some embodiments, see Figure 2The first shallow trench isolation structure 310 further includes a barrier layer 312 and a second insulating layer 313. The barrier layer 312 is located on the surface of the first insulating layer 311, and the second insulating layer 313 is located on the surface of the barrier layer 312 and fills the remaining space of the first trench 210. The top surface 313a of the second insulating layer 313 is higher than the substrate surface 100a, and the top surface of the barrier layer 312 is lower than the top surface 311a of the first insulating layer 311 and the top surface 313a of the second insulating layer 313.

[0053] For example, the first insulating layer 311 includes a bottom wall and two side walls connected to opposite ends of the bottom wall and extending vertically toward the substrate surface 100a. The cross-section of the first insulating layer 311 is generally U-shaped. A barrier layer 312 is located inside the U-shape of the first insulating layer 311, and the barrier layer 312 is located on the bottom wall and two side wall surfaces of the first insulating layer 311. The cross-section of the barrier layer 312 is also generally U-shaped. A second insulating layer 313 is located inside the U-shape of the barrier layer 312 and fills the entire space inside the U-shape of the barrier layer 312.

[0054] The first insulating layer 311 is used to improve interface characteristics and repair etching damage on the inner wall of the first trench 210 to reduce leakage current. The first insulating layer 311 also serves as a buffer layer between the substrate 100 and the barrier layer 312, relieving stress between them. The barrier layer 312 effectively blocks the lateral diffusion of impurity atoms (such as boron, oxygen, and phosphorus) to prevent contamination between the active regions on both sides of the first shallow trench isolation structure 310, which could adversely affect the performance of the semiconductor device. The second insulating layer 313 fills the remaining space in the first trench 210. The second insulating layer 313 works in conjunction with the first insulating layer 311 to relieve internal stress in the barrier layer 312. Furthermore, the second insulating layer 313 can be made of a material with good adhesion to the barrier layer 312 to improve the bonding quality and prevent interface delamination. The first shallow trench isolation structure 310 adopts a composite layer structure consisting of a first insulating layer 311, a barrier layer 312, and a second insulating layer 313. This can avoid the excessive erosion of the first shallow trench isolation structure 310 caused by the planarization treatment of the thick oxide when the first shallow trench isolation structure 310 is formed by a single thick oxide in the relevant embodiments.

[0055] For example, the first insulating layer 311 is made of silicon oxide, the barrier layer 312 is made of silicon nitride, and the second insulating layer 313 is made of silicon oxide.

[0056] For example, the density of the first insulating layer 311 is greater than that of the second insulating layer 313. The high density of the first insulating layer 311 can ensure the interface quality between the first insulating layer 311 and the substrate 100, effectively passivating surface defects of the substrate 100 within the first trench 210. The relatively low density of the second insulating layer 313 can alleviate the overall stress of the first shallow trench isolation structure 310.

[0057] In this embodiment, the top surface 313a of the second insulating layer 313 is higher than the surface of the substrate 100. This can cope with the consumption of the second insulating layer by the etching steps before the formation of the high-k dielectric layer of the peripheral transistor, provide sufficient window for these etching steps, and effectively improve the top morphology of the first shallow trench isolation structure 310, reduce the problem of short circuit between adjacent gates, and help improve the reliability and electrical performance of semiconductor devices.

[0058] For example, the second insulating layer 313 is made of the same material as the first insulating layer 311. During the fabrication process, the second insulating layer 313 and the first insulating layer 311 are etched simultaneously, so the top surface of the second insulating layer 313 is substantially flush with the top surface of the first insulating layer 311. In one specific embodiment, the top surface of the first insulating layer 311 is 15 nm to 25 nm higher than the surface of the substrate 100, and the top surface of the second insulating layer 313 is 15 nm to 25 nm higher than the surface of the substrate 100. When the height difference between the top surfaces of the first insulating layer 311 and the second insulating layer 313 and the surface of the substrate 100 is within the above range, it is sufficient to cope with the consumption of the first insulating layer 311 and the second insulating layer 313 by the growth and etching processes before the formation of the subsequent high-k dielectric layer. If the top surfaces of the first insulating layer 311 and the second insulating layer 313 are too high, the etching time needs to be extended to consume the excessive portion, which will lead to waste and extended process cycle.

[0059] like Figure 2 As shown, the top surface of the barrier layer 312 is recessed relative to the top surface of the first insulating layer 311 and the top surface of the second insulating layer 313. For example, the top surface of the barrier layer 312 is flush with the substrate surface 100a, but may also be slightly higher or lower than the substrate surface 100a, without particular limitation. Exemplarily, the height difference between the top surface of the barrier layer 312 and the top surfaces of the first insulating layer 311 and the second insulating layer 313 is greater than 0 nm and less than or equal to 10 nm. Thus, in the subsequent etching step before fabricating the high-k dielectric layer of the peripheral transistor, such as when cleaning the substrate surface, after consuming part of the first insulating layer 311, the barrier layer 312, and the second insulating layer 313, the recess can be essentially eliminated, improving the short-circuit problem of adjacent gates caused by the recess. That is, adjacent gates can be effectively isolated, improving the performance of the semiconductor device.

[0060] Figure 4This is a schematic diagram of a first shallow trench isolation structure and a first set of marking structures provided in an embodiment of this disclosure. In some embodiments, such as Figure 4 As shown, the first shallow trench isolation structure 310 further includes at least one first semiconductor layer 314, which is located between the barrier layer 312 and the first insulating layer 311, and / or between the barrier layer 312 and the second insulating layer 313; wherein the top surface of the first semiconductor layer 314 is not higher than the top surface of the first insulating layer 311.

[0061] For example, a first semiconductor layer 314 can be disposed between the barrier layer 312 and the first insulating layer 311, or between the barrier layer 312 and the second insulating layer 313, or both between the barrier layer 312 and the first insulating layer 311 and between the barrier layer 312 and the second insulating layer 313. In the first shallow trench isolation structure 310, the first semiconductor layer 314 can act as a charge buffer layer to trap some electrons. Since the change in surface potential after the first semiconductor layer 314 traps electrons is relatively small, the hot electron-induced punch-through (HELP) effect can be improved while maintaining the performance of the semiconductor device.

[0062] For example, the top surface of the first semiconductor layer 314 is not higher than the top surface of the first insulating layer 311, and further, the top surface of the first semiconductor layer 314 is not higher than the top surface of the barrier layer 312. In one specific embodiment, the top surface of the first semiconductor layer 314 can be flush with the surface of the substrate 100. This way, after subsequent etching that consumes part of the first insulating layer 311, the barrier layer 312, the first semiconductor layer 314, and the second insulating layer 313, the top surface of the first shallow trench isolation structure 310 is essentially flush, which can eliminate the adverse effects of the top surface depression and improve the performance of the semiconductor device. For example, the material of the first semiconductor layer 314 includes, but is not limited to, polysilicon, silicon-germanium, and germanium.

[0063] In some embodiments, such as Figure 2 As shown, the top surface of the first set of marking structures 410 has a plurality of grooves 430. The grooves 430 extend along the length direction of the first set of marking structures 410, and the plurality of grooves 430 are symmetrically arranged about the center line perpendicular to the width direction.

[0064] In this embodiment, the groove 430 on the top surface of the first set of marking structures 410 can enhance light scattering and reduce the effective reflectivity of the area where the first set of marking structures 410 is located, making the area darker in the image. This improves the contrast of the optical measurement between the area and the substrate 100, enhances the optical measurement signal, and helps improve the overlay accuracy. Furthermore, the symmetrical arrangement of the multiple grooves 430 can maintain the symmetry of the first set of marking structures 410. Symmetry has many advantages, such as offsetting the systematic deviation of the measurement system, which can more accurately extract the alignment offset, thus improving the overlay accuracy.

[0065] In some embodiments, the first set of marking structures 410 further includes a second filling layer 412 and a third filling layer 413. The second filling layer 412 is located on the surface of the first filling layer 411, and the third filling layer 413 is located on the surface of the second filling layer 412 and fills the remaining space of the second trench 220. The top surface 413a of the third filling layer 413 is higher than the substrate surface 100a, and the top surface of the second filling layer 412 is lower than the top surface 411a of the first filling layer 411 and the top surface 413a of the third filling layer 413.

[0066] like Figure 2 and Figure 4 As shown, the first filling layer 411 includes a bottom wall and two side walls connected to the opposite ends of the bottom wall and extending vertically toward the substrate surface 100a, with the side walls extending to protrude beyond the substrate surface 100a. The cross-section of the first filling layer 411 is approximately U-shaped. The second filling layer 412 is located inside the U-shape of the first filling layer 411, and is situated on the bottom wall and two side wall surfaces of the first filling layer 411. The cross-section of the second filling layer 412 is also approximately U-shaped. The third filling layer 413 is located inside the U-shape of the second filling layer 412 and fills the entire space within the U-shape of the second filling layer 412. The first set of marking structures 410 is a symmetrical structure, symmetrically arranged with a center line perpendicular to the width direction as the axis of symmetry.

[0067] In this embodiment, the top surface of the second filling layer 412 is recessed relative to the top surfaces of the first filling layer 411 and the third filling layer 413, thereby forming two symmetrical grooves 430. This can improve the contrast of optical measurements, enhance the signal of optical measurements, and facilitate improved overlay accuracy.

[0068] In some embodiments, the third filler layer 413 is made of the same material as the first filler layer 411. During the fabrication process, the third filler layer 413 and the first filler layer 411 are etched simultaneously, so the top surface of the third filler layer 413 is flush with the top surface of the first filler layer 411. In one specific embodiment, the top surface of the first filler layer 411 is 15 nm to 25 nm above the substrate surface, and the top surface of the third filler layer 413 is also 15 nm to 25 nm above the substrate surface.

[0069] In some embodiments, the first filler layer 411 and the first insulating layer 311 are made of the same material, have the same thickness, and their top surfaces are flush with each other; and / or, the second filler layer 412 and the barrier layer 312 are made of the same material, have the same thickness, and their top surfaces are flush with each other; and / or, the third filler layer 413 and the second insulating layer 313 are made of the same material, have the same thickness, and their top surfaces are flush with each other.

[0070] For example, the first filler layer 411 is made of silicon oxide, the second filler layer 412 is made of silicon nitride, and the third filler layer 413 is made of silicon oxide. For example, in the process, the first filler layer 411 and the first insulating layer 311 are obtained by simultaneously depositing and etching silicon oxide layers in the first trench 210 and the second trench 220. Therefore, the first filler layer 411 and the first insulating layer 311 have the same material, thickness, and flush top surfaces. Similarly, the second filler layer 412 and the barrier layer 312 are obtained by simultaneously depositing and etching silicon nitride layers. The third filler layer 413 and the second insulating layer 313 are obtained by simultaneously depositing and etching silicon oxide layers.

[0071] In this embodiment, the first shallow trench isolation structure 310 and the first set of marking structures 410 are fabricated simultaneously, which simplifies the process and helps reduce costs and shorten the cycle time. Simultaneously, considering the performance requirements of both the first shallow trench isolation structure 310 and the first set of marking structures 410, it is proposed that the silicon oxide layer be higher than the substrate surface, while the silicon nitride layer be flush with the substrate surface 100a. This creates a stepped structure on the top surfaces of both layers, consisting of a high silicon oxide layer and a low silicon nitride layer. On one hand, this stepped structure can improve the contrast of optical measurements of the first set of markings and enhance the optical measurement signal, thereby improving overlay accuracy. On the other hand, the increased silicon oxide layer can cope with the consumption of silicon oxide layer in subsequent etching steps. Through this ingenious design, synergistic optimization is achieved.

[0072] In some embodiments, such as Figure 4 As shown, the first set of marking structures 410 further includes at least one second semiconductor layer 414, which is located between the second filling layer 412 and the first filling layer 411, and / or between the second filling layer 412 and the third filling layer 413; wherein the top surface of the second semiconductor layer 414 is not higher than the top surface of the first filling layer 411.

[0073] Since the first marking structure 410 and the first shallow trench isolation structure 310 are fabricated simultaneously, in this embodiment, when the first semiconductor layer 314 is disposed between the barrier layer 312 and the first insulating layer 311, the second semiconductor layer 414 is disposed between the second filling layer 412 and the first filling layer 411. When the first semiconductor layer 314 is disposed between the barrier layer 312 and the second insulating layer 313, the second semiconductor layer 414 is disposed between the second filling layer 412 and the third filling layer 413. The top surface of the second semiconductor layer 414 is flush with that of the first semiconductor layer 314, and the second semiconductor layer 414 and the first semiconductor layer 314 are made of the same material and have the same thickness. For example, the material of the second semiconductor layer 414 includes, but is not limited to, polycrystalline silicon, silicon-germanium, germanium, etc.

[0074] In some embodiments, the semiconductor device further includes a second set of markings located in the dicing region, above the first set of markings, and situated in the same area as the first set of markings, forming a diffraction-based overlay (DBO). The overlay error between the word line trenches and the active region in the array region is represented by measuring the displacement between the central portions of the first and second set of marking images. The second set of markings includes a second marking structure identical to the first marking structure 410, comprising a striped pattern.

[0075] Figure 5 A schematic diagram of the peripheral region including a second shallow trench isolation structure provided for embodiments of this disclosure. In some embodiments, such as Figure 4 and Figure 5 As shown, the chip region includes a peripheral region, and the first shallow trench isolation structure 310 is located in the peripheral region. The semiconductor device also includes a second shallow trench isolation structure 320, located within the substrate 100 of the peripheral region. The second shallow trench isolation structure 320 is made of the same material as the first insulating layer 311, and the top surface 320a of the second shallow trench isolation structure 320 is higher than the substrate surface 100a. Wherein, as... Figure 3 As shown, the first shallow trench isolation structure 310 defines a plurality of transistor regions 110 arranged along a first direction D1 within the substrate 100, and the second shallow trench isolation structure 320 defines a plurality of peripheral active regions 111 arranged along the first direction D1 in at least a portion of the transistor regions 110. The first direction D1 is parallel to the substrate surface 100a.

[0076] The first direction D1 can be any direction parallel to the substrate surface 100a, such as the X direction or the Y direction, and this disclosure does not limit it.

[0077] The chip area also includes an array area, which forms an array of memory cells, and a peripheral area, which forms peripheral circuitry coupled to the memory cell array. The peripheral circuitry includes circuitry that directly operates the memory cell array, such as word line drivers, sensitive amplifiers, and I / O (input / output) gate circuits. The peripheral circuitry also includes control logic, interface circuitry, power management circuitry, built-in memory self-test (MBIST) circuitry, and various buffer circuits. For example, transistors, capacitors, diodes, etc., constituting these circuits can be formed in the substrate 100 of the peripheral area and the dielectric layer on the substrate 100 using metal-oxide-semiconductor (MODS) technology. Furthermore, a shallow trench isolation structure needs to be formed in the substrate 100 of the peripheral area to isolate circuits with different functions and / or to isolate high-voltage devices from low-voltage devices.

[0078] The first shallow trench isolation structure 310 and the second shallow trench isolation structure 320 belong to the shallow trench isolation structures of the outer area. For example... Figure 3 As shown, the first shallow trench isolation structure 310 can isolate multiple transistor regions 110 arranged along the first direction D1 within the substrate 100. For example, transistors of the same type can be formed within the same transistor region 110; for instance, all transistors within the same transistor region 110 can be PMOS (Positive channel Metal Oxide Semiconductor) transistors, or all can be NMOS (Negative channel Metal Oxide Semiconductor) transistors. The transistor types of two adjacent transistor regions 110 can be the same or different. Figure 5 As shown, the width of the first shallow trench isolation structure 310 along the first direction D1 is greater than the width of the second shallow trench isolation structure 320 along the first direction D1. That is, the width of the first shallow trench isolation structure 310 is larger, and the first shallow trench isolation structure 310 can provide strong electrical isolation for high-voltage modules (such as power management and charge pumps), prevent high-voltage breakdown, and reduce electric field interference between adjacent devices.

[0079] The second shallow trench isolation structure 320 can isolate multiple peripheral active regions 111 within the transistor region 110, each peripheral active region 111 being used to form one or more transistors. While ensuring basic electrical isolation, the second shallow trench isolation structure 320 has a smaller width, making it suitable for high-integration regions (such as logic cells and cache areas), thus minimizing device spacing and increasing chip density. In practical applications, the first shallow trench isolation structure 310 or the second shallow trench isolation structure 320 can be set between adjacent peripheral active regions 111 based on a trade-off between isolation strength, area efficiency, and process complexity; this disclosure does not impose excessive limitations in this regard.

[0080] like Figure 5 As shown, the top surface 320a of the second shallow trench isolation structure 320 is higher than the substrate surface 100a. This can help to cope with the consumption of the second shallow trench isolation structure 320 by the growth and etching processes before the formation of the subsequent high-k dielectric layer. This can improve the depression on the top surface of the second shallow trench isolation structure 320 after the gate oxide layer is fabricated, reduce the risk of gate short circuit introduced by the depression, and thus improve the performance of the semiconductor device.

[0081] For example, the second shallow trench isolation structure 320 is composed of a single material. The second shallow trench isolation structure 320 is made of the same material as the first insulating layer 311 in the first shallow trench isolation structure 310. This is because the second shallow trench isolation structure 320 and the first insulating layer 311 are fabricated simultaneously during the manufacturing process. For example, the top surface 320a of the second shallow trench isolation structure 320 is flush with the top surface 311a of the first insulating layer 311. For example, the material of the second shallow trench isolation structure 320 includes at least one of silicon oxide, silicon carbide, etc.

[0082] Figure 6 Schematic diagram of a semiconductor device provided in the embodiments of this disclosure Figure 3 , Figure 7 This is a schematic diagram of the third and fourth shallow trench isolation structures provided in the embodiments of this disclosure. Figure 7 The middle array area is Figure 6 The diagram shows a partial cross-sectional view of the array region along line bb′. In some embodiments, such as... Figure 6 and Figure 7 As shown, the semiconductor device also includes a third shallow trench isolation structure 330 and a fourth shallow trench isolation structure 340, both of which are located in the substrate 100 of the array region. The third shallow trench isolation structure 330 includes a third insulating material, and the fourth shallow trench isolation structure 340 includes a fourth insulating layer 342 and a third insulating layer 341 located on the sidewalls and bottom of the fourth insulating layer 342. The third shallow trench isolation structure 330 and the fourth shallow trench isolation structure 340 define a plurality of active regions 120 arranged in an array within the substrate 100 of the array region.

[0083] like Figure 6As shown, a third shallow trench isolation structure 330 and a fourth shallow trench isolation structure 340 are formed within the substrate 100 of the array region. The third shallow trench isolation structure 330 and the fourth shallow trench isolation structure 340 isolate multiple active regions 120 within the substrate 100 of the array region, and the multiple active regions 120 are arranged in an array. In this embodiment, the active region 120 includes a first drain region, a source region, and a second drain region that are sequentially spaced along its extension direction. A word line is formed within the substrate 100 between the source region and each drain region, thereby forming two transistors sharing a common source region using one active region 120. Figure 6 The solid line box in the image shows the location of the word line trench 20 subsequently formed within the substrate 100, within which word lines are formed. Figure 6 As shown, multiple word line trenches 20 extending along the second direction D2 are formed in the substrate 100. Each active region 120 is traversed by two word line trenches 20 arranged side by side along the third direction D3. The orthographic projections of the source region and the drain region on the substrate surface 100a are located on both sides of the orthographic projection of the word line trenches 20 on the plane. Bit line plugs are provided on the source region, and memory node plugs are provided on each drain region.

[0084] In this embodiment, the second direction D2 and the third direction D3 are perpendicular to each other and both parallel to the substrate surface 100a. The second direction D2 can be any direction parallel to the substrate surface 100a, such as the X direction or the Y direction. The direction indicated by the second direction D2 and the first direction D1 can be the same, and this disclosure does not limit this.

[0085] During the fabrication of the word line trench 20, measurements are performed using a first set of markings and a second set of markings, and the measurement results are fed back to the lithography machine for compensation and correction. By making the top surface of the first filling layer 411 in the first set of marking structure 410 higher than the substrate surface, the contrast of optical measurements between the substrate 100 and the markings can be improved, thereby enhancing the optical measurement signal of the markings. Enhanced optical measurement signal can improve the resolution of position detection, i.e., improve the overlay accuracy, thus more accurately determining the position of the word line trench 20 in the active region 120. This improves the problem of reduced drain area caused by word line trench 20 offset affecting the effective contact area with the memory node plug, ensuring that each drain region in the active region 120 has a satisfactory contact area with the memory node plug, thereby improving the performance of the semiconductor device.

[0086] For example, the top surfaces of the third shallow trench isolation structure 330 and the fourth shallow trench isolation structure 340 are flush with the substrate surface 100a. If the third shallow trench isolation structure 330 and the fourth shallow trench isolation structure 340 protrude relative to the substrate surface 100a, they will intersect with the active region 120 (refer to...). Figure 6The top surface forms a step. This uneven surface can lead to poor word line morphology and uneven electrical performance. In this embodiment, the top surfaces of the third shallow trench isolation structure 330 and the fourth shallow trench isolation structure 340 are flush with the substrate surface 100a to reduce the impact on word line morphology and performance. For example, the top surfaces of the third shallow trench isolation structure 330 and the fourth shallow trench isolation structure 340 are flush with the substrate surface 100a to obtain good word line morphology and word line electrical performance.

[0087] The third shallow trench isolation structure 330 includes a third insulating material, which is the same material as the third insulating layer 341. For example, the third insulating material is the same material as the first insulating layer 311, and may include at least one of silicon oxide, silicon oxycarbide, etc. The fourth shallow trench isolation structure 340 includes a fourth insulating layer 342 and a third insulating layer 341. The third insulating layer 341 includes a bottom wall and two side walls connected to opposite ends of the bottom wall and extending vertically toward the substrate surface 100a. The cross-section of the third insulating layer 341 is generally U-shaped. The fourth insulating layer 342 occupies the entire space within the U-shape of the third insulating layer 341. For example, the material of the fourth insulating layer 342 includes at least one of silicon nitride, silicon oxynitride, etc.

[0088] In this embodiment, improving the silicon oxide layer in the first shallow trench isolation structure 310, the second shallow trench isolation structure 320, and the first overlay marking structure 410 achieves dual optimization. On the one hand, the optical measurement signal of the overlay marking is significantly enhanced, and experiments have shown that it can significantly improve the overlay accuracy between word lines in the array region and the active region 120. On the other hand, sufficient process windows are provided in the peripheral region for the etching step before the subsequent gate oxide layer preparation and for the growth of the gate oxide layer, and the depression problem of the second shallow trench isolation structure is effectively improved and the probability of open voids is reduced.

[0089] This disclosure also provides a method for manufacturing a semiconductor device. Figure 8 This is a schematic flowchart illustrating a method for manufacturing a semiconductor device according to an embodiment of this disclosure. Figure 8 As shown, the method for manufacturing this semiconductor device includes:

[0090] S100: Provides a substrate, which includes a chip area and a dicing area;

[0091] S200: A first trench extending from the substrate surface to the interior is formed in the chip region, and a second trench extending from the substrate surface to the interior is formed in the dicing region;

[0092] S300: A first shallow trench isolation structure is formed in the first trench, the first shallow trench isolation structure including a first insulating layer in contact with the inner wall of the first trench, the top surface of the first insulating layer being higher than the substrate surface;

[0093] S400: A first set of marking structures is formed in the second trench. The first set of marking structures includes a first filling layer that contacts the inner wall of the second trench. The top surface of the first filling layer is higher than the substrate surface.

[0094] In the semiconductor device manufacturing method provided in this disclosure, the top surface of the first insulating layer in the first shallow trench isolation structure is higher than the substrate surface. This can mitigate the consumption of the first insulating layer by the etching steps before the formation of the high-k dielectric layer in the subsequent peripheral transistors, providing sufficient window space for these etching steps. Furthermore, it reduces the risk of depressions forming on the top surface of the first shallow trench isolation structure before the deposition of the high-k dielectric layer, improving the problem of short circuits between adjacent gates and thus enhancing the reliability and electrical performance of the semiconductor device. In the first overlay marking structure, the top surface of the first filling layer is higher than the substrate surface, which can increase the intensity of the optical measurement signal of the overlay marking and improve the contrast of the optical measurement signal, thereby improving the overlay accuracy.

[0095] It should be understood that Figure 8 The steps shown are not exclusive; other steps may be performed before, after, or between any of the steps shown. Figure 8 The steps shown can be adjusted in order according to actual needs. Figures 9 to 25 This is a schematic diagram illustrating the manufacturing process of a semiconductor device provided in an embodiment of this disclosure. The following is in conjunction with... Figures 9 to 25 The manufacturing process of the semiconductor device disclosed herein is described in detail.

[0096] See Figure 9 A substrate 100 is provided, comprising a chip region and a dicing region, wherein the chip region includes an array region and a peripheral region. For example, the substrate 100 may be made of silicon (Si), germanium (Ge), silicon-germanium (SiGe), silicon carbide (SiC), silicon-on-insulator (SOI), germanium-on-insulator (GOI), III-V compounds (e.g., GaN, GaAs, InAs, etc.), or any other suitable semiconductor material. In this embodiment, the substrate 100 is a silicon substrate.

[0097] In some embodiments, such as Figure 9 As shown, the method for manufacturing a semiconductor device further includes: before step S200, forming a third trench 230 and a fourth trench 240 in the substrate of the array region, wherein the width of the fourth trench 240 is greater than the width of the third trench 230, and the substrate of the array region is defined by the third trench 230 and the fourth trench 240 to define a plurality of active regions 120; forming a third insulating material 610, wherein the third insulating material 610 fills the third trench 230 and is located on the inner wall of the fourth trench 240 and the surface of the substrate; and depositing a fourth insulating material 620 on the surface of the third insulating material 610, wherein the fourth insulating material 620 fills the remaining space of the fourth trench 240.

[0098] For example, the third trench 230 and the fourth trench 240 can be formed simultaneously. For instance, photolithography and etching processes are performed sequentially to simultaneously form the third trench 230 and the fourth trench 240 within the substrate 100. The third trench 230 and the fourth trench 240 isolate multiple active regions 120 within the substrate 100 of the array region. The active regions 120 can... Figure 6 The third insulating material 610 is then deposited in an array. Next, processes such as atomic layer deposition (ALD) and chemical vapor deposition (CVD) can be used to deposit the third insulating material 610 until the third trench 230 is filled. Since the width of the fourth trench 240 is greater than that of the third trench 230, the third insulating material 610 uniformly covers the inner wall of the fourth trench 240. Furthermore, the third insulating material 610 also uniformly covers the top surface of the active region 120, the peripheral region, and the substrate 100 surface of the diced area of ​​the array region. The third insulating material 610 can be silicon oxide.

[0099] Next, a fourth insulating material 620 can be deposited on the surface of the third insulating material 610 using processes such as atomic layer deposition, chemical vapor deposition, and remote plasma-assisted nitridation (RPN) until the remaining space of the fourth trench 240 is filled. At this point, the substrate 100 in the peripheral region and the dicing region has a stacked third insulating material 610 and a fourth insulating material 620. The fourth insulating material 620 can be silicon nitride.

[0100] It should be noted that the above is only for obtaining... Figure 9 This is one exemplary embodiment of the semiconductor structure shown. In other embodiments, other fabrication processes may also be used to obtain the structure. Figure 9 The semiconductor structure shown is as follows: For example, a third trench is first formed and filled with a third insulating material, then a fourth trench is formed and a third insulating material is deposited again, and then a fourth insulating material is deposited on the surface of the re-deposited third insulating material.

[0101] See Figure 10Step S200 is executed to form a first trench 210 and a second trench 220. For example, a first trench 210 and a fifth trench 250 are formed in the peripheral region, penetrating the fourth insulating material 620 and the third insulating material 610 and extending into the substrate 100. Simultaneously, a second trench 220 is formed in the dicing region, penetrating the fourth insulating material 620 and the third insulating material 610 and extending into the substrate 100. The first trench 210 defines a plurality of transistor regions arranged along a first direction within the substrate 100 in the peripheral region. The fifth trench 250 defines a plurality of peripheral active regions arranged along the first direction in at least a portion of the transistor regions; the first direction is parallel to the substrate surface. The fifth trench 250 is used to form a second shallow trench isolation structure, and the width of the fifth trench 250 is smaller than the width of the first trench 210.

[0102] See Figure 11 A first insulating material 630 is deposited, filling the fifth trench 250. The first insulating material 630 is located on the inner wall of the first trench 210 and the inner wall of the second trench 220, and covers the fourth insulating material 620. For example, atomic layer deposition, chemical vapor deposition, or other processes can be used to deposit the first insulating material 630, which covers the... Figure 10 The surfaces exposed in the array region, peripheral region, and cleavage region of the semiconductor structure shown. The first insulating material 630 may be silicon oxide.

[0103] See also Figure 11 A barrier material 640 is deposited on the surface of the first insulating material 630. For example, the barrier material 640 can be deposited using processes such as atomic layer deposition, chemical vapor deposition, or remote plasma nitriding, and the barrier material 640 uniformly covers the surface of the first insulating material 630. Specifically, the barrier material 640 uniformly covers the surface of the first insulating material 630 in the array region, peripheral region, and dicing region. It is worth noting that the barrier material 640 does not completely fill the first trench 210 and the second trench 220. The barrier material 640 can be silicon nitride.

[0104] Next, a second insulating material 650 is deposited on the surface of the barrier material 640, filling the remaining space of the first trench 210 and the second trench 220. For example, atomic layer deposition, chemical vapor deposition, or other processes can be used to deposit the second insulating material 650 until the remaining space of the first trench 210 and the second trench 220 is filled. At this point, the second insulating material 650 also uniformly covers the entire exposed surface of the barrier material 640 in the array region, peripheral region, and cutaway region. The second insulating material 650 on the barrier material 640 has a relatively large thickness to ensure that the second insulating material 650 completely fills the first trench 210 and the second trench 220. The second insulating material 650 can be silicon oxide.

[0105] See Figure 12 A first planarization is performed on the second insulating material 650 until the barrier material 640 is exposed. The planarization process includes at least one of grinding, chemical mechanical polishing (CMP), and etching. For example, chemical mechanical polishing can be performed on the second insulating material 650, terminating at the surface of the barrier material 640. At this point, the top surface of the remaining second insulating material 650 within the first trench 210 and the second trench 220 is substantially flush with the top surface of the barrier material 640.

[0106] See Figure 13 A second planarization is performed on the second insulating material 650, the barrier material 640, and the first insulating material 630 until the fourth insulating material 620 is exposed. For example, an etchant with a low selectivity for etching silicon oxide and silicon nitride can be used to simultaneously perform dry etching on the second insulating material 650, the barrier material 640, and the first insulating material 630, stopping when the fourth insulating material 620 is exposed. Dry etching enables more precise and uniform overall material removal, resulting in a smoother surface after the second planarization and preventing deep depressions on the top surface of the second insulating material 650 within the first trench 210 and the second trench 220.

[0107] See Figure 13 and Figure 14 The fourth insulating material 620 and the barrier material 640 are etched until the third insulating material 610 is exposed. In some embodiments, when the third shallow trench isolation structure and the fourth shallow trench isolation structure of the array region are fabricated simultaneously with the first shallow trench isolation structure of the peripheral region, the fourth insulating material 620 and the barrier material 640 should continue to be etched until the fourth insulating material 620 in the fourth trench 240 is no higher than the surface of the substrate 100. At this time, the remaining fourth insulating material in the fourth trench 240 forms the fourth insulating layer 342. For example, the top surface of the barrier material 640 in the first trench 210 and the second trench 220 is flush with the top surface of the fourth insulating layer 342, and the remaining barrier material 640 in the first trench 210 and the second trench 220 respectively forms the barrier layer 312 and the filling layer 412.

[0108] In this embodiment, both the fourth insulating material 620 and the barrier material 640 are silicon nitride, so they can be etched simultaneously. For example, the fourth insulating material 620 and the barrier material 640 can be wet-etched until the third insulating material 610 of the array region, peripheral region and diced region is exposed, and the top surface of the fourth insulating material 620 in the fourth trench 240 is flush with the surface of the substrate 100.

[0109] See Figure 14 and Figure 15The third insulating material 610 is etched until the substrate 100 is exposed. In some embodiments, when the third shallow trench isolation structure and the fourth shallow trench isolation structure of the array region are fabricated simultaneously with the first shallow trench isolation structure of the peripheral region, the third insulating material 610 should continue to be etched until the third insulating material 610 in the third trench 230 and the third insulating material 610 in the fourth trench 240 are not higher than the surface of the substrate 100. At this time, the remaining third insulating material in the third trench 230 forms the third shallow trench isolation structure 330. The remaining third insulating material in the fourth trench 240 forms the third insulating layer 341, and the fourth shallow trench isolation structure includes the third insulating layer 341 and the fourth insulating layer 342.

[0110] It should be noted that since the first insulating material 630, the second insulating material 650, and the third insulating material 610 are the same, the first insulating material 630 and the second insulating material 650 are etched simultaneously when the third insulating material 610 is etched. However, the top surfaces of the first insulating material 630 and the second insulating material 650 after etching are still higher than the surface of the substrate 100. After this step, the remaining first insulating material in the fifth trench 250 forms the second shallow trench isolation structure 320, the remaining first insulating material and the second insulating material in the first trench 210 form the first insulating layer 311 and the second insulating layer 313, respectively, and the remaining first insulating material and the second insulating material in the second trench 220 form the first filling layer 411 and the third filling layer 413, respectively. The first shallow trench isolation structure includes the first insulating layer 311, the barrier layer 312, and the second insulating layer 313, and the first set of marking structures includes the first filling layer 411, the second filling layer 412, and the third filling layer 413.

[0111] The semiconductor device manufacturing method provided in this embodiment simultaneously fabricates the first to fourth shallow trench isolation structures 340 and the first set of marking structures, which can significantly save process time and reduce costs. Furthermore, by optimizing the execution order of each step, the silicon oxide layer in the first shallow trench isolation structure 320 in the peripheral region and the first set of marking structures in the dicing region is higher than the surface of the substrate 100, achieving multiple performance optimizations. At the same time, the top surfaces of the third and fourth shallow trench isolation structures in the array region are kept flush with the surface of the substrate 100 to reduce the impact on word lines and ensure the performance of the memory cell array.

[0112] In some embodiments, the method for manufacturing a semiconductor device further includes: forming a mask layer on the substrate surface of the array region and the substrate surface of the dicing region; forming a first photoresist layer having a second set of marking structure patterns on the mask layer; measuring the overlay accuracy between the second set of marking structures and the first set of marking structures; exposing the first photoresist layer after development; forming a plurality of first openings that expose the mask layer in the first photoresist layer after development; etching a plurality of active regions, a plurality of third shallow trench isolation structures and a plurality of fourth shallow trench isolation structures based on the first openings of the array region to form word line trenches, the word line trenches extending along a second direction and passing through the active regions, the third shallow trench isolation structures and the fourth shallow trench isolation structures.

[0113] See Figure 16 A mask layer 710 is formed on the surface of the substrate 100 in the array region, peripheral region, and dicing region. The mask layer 710 includes a plurality of sub-mask layers stacked vertically. The mask layer shown in this embodiment includes five sub-mask layers, from bottom to top: a first sub-mask layer 711, a second sub-mask layer 712, a third sub-mask layer 713, a fourth sub-mask layer 714, and a fifth sub-mask layer 715. The materials of these sub-mask layers can be selected from combinations of carbon layers, polysilicon layers, silicon oxynitride layers, silicon carbide nitride layers, silicon oxycarbonate layers, silicon nitride layers, and silicon oxide layers. Next, a first photoresist layer 810 is formed on the mask layer 710.

[0114] like Figure 16 As shown, the first photoresist layer 810 has a second set of marking patterns in the dicing area. The second set of markings is formed by projecting this pattern onto the substrate 100. Correspondingly, the opening regions between adjacent first photoresist layers 810 are projected onto the substrate 100 to form the second set of marking structures. At this time, a metrology machine is used to measure the second set of markings and the first set of markings in the substrate 100. After measurement, the first photoresist layer 810 is exposed and developed to transfer the pattern on the mask to the first photoresist layer 810. The developed first photoresist layer includes multiple first openings 811 exposing the mask layer 710. The first openings 811 located in the array region correspond to the positions of the word line trenches 20. Figure 16 As shown, since the mask layer 710 adopts a composite layer structure, it can improve the unevenness of the substrate surface, making the top surface of the mask layer 710 relatively flat, and the pattern in the first photoresist layer 810 is transferred into the substrate with high quality.

[0115] See Figure 17 The mask layer 710 is etched based on multiple first openings 811 to transfer the opening pattern in the first photoresist layer 810 into the mask layer 710. When the opening pattern is transferred to a portion of a sub-mask layer within the mask layer 710, for example... Figure 17In the third sub-mask layer 713, a protective layer 820 is formed on the top surface of the sub-mask layer (e.g., the third sub-mask layer 713) in the peripheral region and the dicing region. For example, the material of the protective layer 820 is photoresist, so that the protective layer 820 can cover the peripheral region and the dicing region and only expose the array region through the exposure and development steps. The process is simple and does not affect the opening pattern in the mask layer.

[0116] See Figure 18 The patterned third sub-mask layer 713 includes a mask opening 720 corresponding to the first opening 811. Based on the mask opening 720 in the third sub-mask layer 713 within the array region, the second sub-mask layer 712 and the first sub-mask layer 711 are sequentially etched to expose the active region 120, and the active region 120, the third shallow trench isolation structure 330, and the fourth shallow trench isolation structure 340 are further etched to form a word line trench 20 in the substrate 100 of the array region. For example, the word line trench 20 extends along a second direction and passes through multiple active regions 120, multiple third shallow trench isolation structures 330, and multiple fourth shallow trench isolation structures 340.

[0117] After the character line groove 20 is formed, the protective layer 820 can be removed by sequentially performing exposure and development.

[0118] See Figure 18 and Figure 19 A gate dielectric layer 910 is formed on the inner wall surface of the word line groove 20, and a word line 920 is formed on the surface of the gate dielectric layer 910, filling the lower section space of the word line groove 20. A word line isolation layer 930 is formed on the top surface of the word line 920, filling the remaining space of the word line groove 20.

[0119] In some embodiments, the method of manufacturing a semiconductor device further includes: forming a gate structure on a transistor region in a peripheral region, a first shallow trench isolation structure, and a second shallow trench isolation structure, the gate structure including a high-k dielectric layer and a gate located on the high-k dielectric layer, wherein the gate structure extends along a first direction and is located on at least two peripheral active regions within the transistor region and on a second shallow trench isolation structure between adjacent peripheral active regions; and / or, the gate structure is located on at least two peripheral active regions of different transistor regions and on a first shallow trench isolation structure between adjacent transistor regions.

[0120] See Figure 20A first isolation layer 730 is formed on the surface of the substrate 100 in the peripheral region. The first isolation layer 730 covers a plurality of peripheral active regions 111, a plurality of first shallow trench isolation structures 310, and a plurality of second shallow trench isolation structures 320. A second photoresist layer 830 is formed on the surface of the first isolation layer 730 and exposed. Then, the second photoresist layer 830 is developed, and the developed second photoresist layer 830 has a plurality of second openings 831.

[0121] See Figure 21 The first isolation layer 730 is wet-etched along the second opening 831, exposing the peripheral active region 111 for forming the PMOS transistor, and the first shallow trench isolation structure 310 and the second shallow trench isolation structure 320 located between these peripheral active regions 111. For ease of description, the peripheral active region for forming the PMOS transistor is referred to as the PMOS peripheral active region in this disclosure.

[0122] See also Figure 21 The multiple PMOS peripheral active regions 111 exposed by the second opening 831 are cleaned using a cleaning solution. For example, SC1 cleaning solution, which is a mixture of ammonia (NH4OH), hydrogen peroxide (H2O2), and deionized water, can be used to remove silicon oxide formed by natural oxidation on the substrate surface. SC2 cleaning solution, which is a mixture of hydrochloric acid (HCl), hydrogen peroxide (H2O2), and deionized water, is used to remove metal impurity ions.

[0123] When removing the silicon oxide from the surface of the PMOS peripheral active region 111 using a cleaning solution, the first insulating layer 311 and the second insulating layer 313 in the second shallow trench isolation structure 320 and the first shallow trench isolation structure 310 are simultaneously etched because they are composed of silicon oxide. For example, by controlling cleaning parameters such as cleaning time and number of cleaning cycles, the top surfaces of the cleaned second shallow trench isolation structure 320, the first insulating layer 311, and the second insulating layer 313 can be made to be no lower than the top surface of the cleaned PMOS peripheral active region 111.

[0124] It is worth noting that the etching rate of the cleaning solution on the PMOS peripheral active region 111 itself is very low, while the etching rate on silicon oxide is relatively high. Therefore, after cleaning, the height difference between the top surface of the second shallow trench isolation structure 320, the first insulating layer 311, and the second insulating layer 313 and the top surface of the PMOS peripheral active region 111 is smaller than before cleaning. Furthermore, the height difference that may still exist after cleaning is within a controllable range and will not affect the subsequent fabrication of the high-k dielectric layer and gate of the PMOS transistor.

[0125] See Figure 21 and Figure 22A silicon-germanium layer 150 is epitaxially grown on the surface of the active region 111 surrounding the PMOS after cleaning. Then, a second isolation layer 740 is formed on the surface of the silicon-germanium layer 150 and the cleaned first shallow trench isolation structure 310 and second shallow trench isolation structure 320.

[0126] See also Figure 21 and Figure 22 The second photoresist layer 830 is then removed. Next, a third photoresist layer 840 is formed on the surface of the second isolation layer 740 in the peripheral region and the remaining first isolation layer 730.

[0127] The second isolation layer 740 and the remaining first isolation layer are wet-etched along the third opening 841 in the third photoresist layer 840, exposing the peripheral active region 111 for forming the NMOS transistor, and the first shallow trench isolation structure 310 and the second shallow trench isolation structure 320 located between these peripheral active regions 111. For ease of description, the peripheral active region for forming the NMOS transistor is referred to as the NMOS peripheral active region in this disclosure.

[0128] The multiple NMOS peripheral active regions 111 exposed by the third opening 841, as well as the first shallow trench isolation structure 310 and the second shallow trench isolation structure 320 between adjacent NMOS peripheral active regions 111, are cleaned using a cleaning solution. After cleaning, the top surfaces of the second shallow trench isolation structure 320, the first insulating layer 311, and the second insulating layer 313 are not lower than the top surfaces of the cleaned NMOS peripheral active regions. However, after cleaning, the height difference between the top surfaces of the second shallow trench isolation structure 320, the first insulating layer 311, and the second insulating layer 313 and the top surfaces of the NMOS peripheral active regions 111 is smaller than before cleaning, and the height difference that may still exist after cleaning is within a controllable range and will not affect the subsequent fabrication of the high-k dielectric layer and gate of the NMOS transistor.

[0129] See Figure 23 The NMOS peripheral active region 111 exposed by the third opening 841 is oxidized by an in-situ water vapor process to form a first gate oxide layer 950 on the surface of the NMOS peripheral active region. For example, the height difference between the top surface of the first gate oxide layer 950 and the top surfaces of the cleaned second shallow trench isolation structure 320, the first insulating layer 311 and the second insulating layer 313 is less than or equal to a preset value.

[0130] See Figure 23 and Figure 24The third photoresist layer 840 and the second isolation layer 740 are removed to expose the silicon-germanium layer 150 on the PMOS peripheral active region 111. The silicon-germanium layer 150 or the silicon-germanium layer 150 and the PMOS peripheral active region 111 are oxidized by in-situ water vapor process to form a second gate oxide layer 960. The height difference between the surface of the second gate oxide layer 960 and the top surface of the cleaned second shallow trench isolation structure 320, the first insulating layer 311 and the second insulating layer 313 between the adjacent PMOS peripheral active regions 111 is less than or equal to a preset value.

[0131] See Figure 25 A high-k dielectric material is formed on the top surfaces of the first gate oxide layer 950, the second gate oxide layer 960, and the cleaned first shallow trench isolation structure 310 and second shallow trench isolation structure 320. A gate material is formed on the surface of the high-k dielectric material. Photolithography and etching processes are performed sequentially to pattern the high-k dielectric material and gate material, forming a high-k dielectric layer (not shown in the figure) and a gate 22, respectively. The gate structure includes a gate 22 and a high-k dielectric layer. It should be noted that... Figure 25 The first gate oxide layer 950 and the second gate oxide layer 960 are hidden to clearly show the first shallow trench isolation structure 310 and the second shallow trench isolation structure 320.

[0132] like Figure 25 As shown, the gate structure (including gate 22 and a high-k dielectric layer) extends along a first direction and is located on at least two peripheral active regions 111 within transistor region 110 and on a second shallow trench isolation structure 320 between adjacent peripheral active regions 111. The gate structure may also be located on at least two peripheral active regions 111 of different transistor regions 110 and on a first shallow trench isolation structure 310 between adjacent transistor regions 110.

[0133] In this embodiment, after the gate oxide layer (first gate oxide layer 950 and / or second gate oxide layer 960) is fabricated, the top surfaces of the first shallow trench isolation structure and the second shallow trench isolation structure are not lower than the top surface of the gate oxide layer, and the top surfaces of the first shallow trench isolation structure and the second shallow trench isolation structure are relatively flat, which can avoid the residue of gate material and high-k dielectric material, and is conducive to improving the performance of semiconductor devices.

[0134] In some embodiments, the thickness of the first gate oxide layer 950 and / or the second gate oxide layer 960 is less than or equal to 7 nm, which is more conducive to improving peripheral region transistors with a gate oxide layer thickness of less than or equal to 7 nm in the embodiments of this disclosure.

[0135] This disclosure also provides an electronic device, including and / or employing the aforementioned semiconductor devices. For example, the electronic device includes a storage device, a smartphone, a computer, a tablet computer, an artificial intelligence device, a wearable device, or a power bank, etc. The storage device may include memory in a computer, etc., and this application does not limit its scope.

[0136] The methods disclosed in the several method embodiments provided in this disclosure can be arbitrarily combined without conflict to obtain new method embodiments.

[0137] The above description is merely a specific embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any changes or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure.

Claims

1. A semiconductor device, characterized in that, include: A substrate, the substrate including a chip region and a dicing region, the chip region including a peripheral region, the peripheral region having a first trench extending from the surface of the substrate to the interior, and the dicing region having a second trench extending from the surface of the substrate to the interior. A first shallow trench isolation structure is located within the first trench of the chip region. The first shallow trench isolation structure includes a first insulating layer, a barrier layer, and a second insulating layer that are in contact with the inner wall of the first trench. The barrier layer is located on the first insulating layer, and the second insulating layer is located on the barrier layer. The first set of marking structures is located in the second groove of the cutting channel area. The first set of marking structures includes a first filling layer, a second filling layer and a third filling layer that are in contact with the inner wall of the second groove. The second filling layer is located on the first filling layer and the third filling layer is located on the second filling layer. A second shallow trench isolation structure is located in the substrate of the peripheral region, and the second shallow trench isolation structure is made of the same material as the first insulating layer. Wherein, the top surface of the first insulating layer is higher than the surface of the substrate and the top surface of the barrier layer, and forms a step with the surface of the substrate and the top surface of the barrier layer respectively; the top surface of the first filling layer is higher than the surface of the substrate and the top surface of the second filling layer, and forms a step with the surface of the substrate and the top surface of the second filling layer respectively; the top surface of the second shallow trench isolation structure is higher than the surface of the substrate.

2. The semiconductor device according to claim 1, characterized in that, The second insulating layer fills the remaining space in the first trench; The top surface of the barrier layer is lower than the top surface of the second insulating layer.

3. The semiconductor device according to claim 2, characterized in that, The top surface of the first insulating layer is 15 nm to 25 nm higher than the surface of the substrate.

4. The semiconductor device according to claim 2, characterized in that, The first shallow trench isolation structure further includes at least one first semiconductor layer, which is located between the barrier layer and the first insulating layer and / or between the barrier layer and the second insulating layer; Wherein, the top surface of the first semiconductor layer is not higher than the top surface of the first insulating layer.

5. The semiconductor device according to claim 2, characterized in that, The third filling layer fills the remaining space in the second trench; the top surface of the second filling layer is lower than the top surface of the third filling layer.

6. The semiconductor device according to claim 5, characterized in that, The top surface of the first filling layer is 15 nm to 25 nm above the substrate surface; and / or, The top surface of the third filling layer is flush with the top surface of the first filling layer.

7. The semiconductor device according to claim 5, characterized in that, The first set of marking structures further includes at least one second semiconductor layer, which is located between the second filling layer and the first filling layer, and / or between the second filling layer and the third filling layer; wherein the top surface of the second semiconductor layer is not higher than the top surface of the first filling layer.

8. The semiconductor device according to claim 5, characterized in that, The first filling layer and the first insulating layer are made of the same material, have the same thickness, and have their top surfaces flush with each other. And / or, the second filler layer is made of the same material and has the same thickness as the barrier layer, and their top surfaces are flush with each other; And / or, the third filler layer is made of the same material and has the same thickness as the second insulating layer, and their top surfaces are flush with each other.

9. The semiconductor device according to claim 1, characterized in that, The first shallow trench isolation structure defines a plurality of transistor regions arranged along a first direction within the substrate, and the second shallow trench isolation structure defines a plurality of peripheral active regions arranged along the first direction in at least a portion of the transistor regions. The first direction is parallel to the substrate surface.

10. The semiconductor device according to claim 1, characterized in that, The chip region further includes an array region, and the semiconductor device further includes: A third shallow trench isolation structure is located in the substrate of the array region, and the third shallow trench isolation structure includes a third insulating material; A fourth shallow trench isolation structure is located in the substrate of the array region. The fourth shallow trench isolation structure includes a fourth insulating layer and a third insulating layer located on the sidewalls and bottom of the fourth insulating layer. The top surfaces of the third shallow trench isolation structure and the fourth shallow trench isolation structure are flush with the substrate surface, and the third shallow trench isolation structure and the fourth shallow trench isolation structure define a plurality of active regions arranged in an array within the substrate of the array region.

11. The semiconductor device according to claim 1, characterized in that, The semiconductor device further includes: The second set of marking structures is located in the cutting channel area; wherein the second set of marking structures is located above the first set of marking structures, and both the first set of marking structures and the second set of marking structures include strip patterns.

12. A method for manufacturing a semiconductor device, characterized in that, include: A substrate is provided, the substrate including a chip region and a dicing region, the chip region including a peripheral region; A first trench and a fifth trench are formed in the peripheral region, extending from the substrate surface to the interior; and a second trench is formed in the dicing region, extending from the substrate surface to the interior. A first shallow trench isolation structure is formed in the first trench. The first shallow trench isolation structure includes a first insulating layer in contact with the inner wall of the first trench, a barrier layer located on the first insulating layer, and a second insulating layer located on the barrier layer. The top surface of the first insulating layer is higher than the substrate surface and the top surface of the barrier layer, and forms steps with the substrate surface and the top surface of the barrier layer, respectively. A second shallow trench isolation structure is formed in the fifth trench. The second shallow trench isolation structure is made of the same material as the first insulating layer, and the top surface of the second shallow trench isolation structure is higher than the substrate surface. A first set of marking structures is formed in the second trench. The first set of marking structures includes a first filling layer in contact with the inner wall of the second trench, a second filling layer on the first filling layer, and a third filling layer on the second filling layer. The top surface of the first filling layer is higher than the substrate surface and the top surface of the second filling layer, and forms steps with the substrate surface and the top surface of the second filling layer, respectively.

13. The method for manufacturing a semiconductor device according to claim 12, characterized in that, The chip area also includes an array area; The manufacturing method further includes: A third trench and a fourth trench are formed in the substrate of the array region, the width of the fourth trench being greater than the width of the third trench, and the substrate of the chip region is defined by the third trench and the fourth trench to define a plurality of active regions; A third insulating material is deposited, which fills the third trench and is located on the inner wall of the fourth trench and on the surface of the substrate; A fourth insulating material is deposited on the surface of the third insulating material, the fourth insulating material filling the remaining space of the fourth trench; The fourth insulating material is etched, while the fourth insulating material within the fourth trench is retained to form a fourth insulating layer; The third insulating material is etched, and the third insulating material in the third trench is retained to form a third shallow trench isolation structure, and the third insulating material in the fourth trench is retained to form a third insulating layer; the fourth shallow trench isolation structure includes the third insulating layer and the fourth insulating layer.

14. The method for manufacturing a semiconductor device according to claim 12 or 13, characterized in that, The formation of the first shallow trench isolation structure and the first set of marking structures includes: A third insulating material and a fourth insulating material are stacked on the substrate surface in the peripheral region and the dicing region; wherein the first trench and the second trench penetrate the third insulating material and the fourth insulating material and extend into the substrate; A first insulating material is deposited, which is located on the inner wall of the first trench and the inner wall of the second trench, and covers the fourth insulating material; Deposit a barrier material on the surface of the first insulating material; A second insulating material is deposited on the surface of the barrier material, the second insulating material filling the remaining space of the first trench and the second trench; A first planarization is performed on the second insulating material until the barrier material is exposed; A second planarization is performed on the second insulating material, the barrier material, and the first insulating material until the fourth insulating material is exposed; The fourth insulating material and the barrier material are etched until the third insulating material is exposed; the remaining barrier material in the first trench forms the barrier layer, and the remaining barrier material in the second trench forms the second fill layer; The third insulating material, the first insulating material, and the second insulating material are etched until the substrate is exposed; the remaining first insulating material and the second insulating material in the first trench form the first insulating layer and the second insulating layer, respectively, and the remaining first insulating material and the second insulating material in the second trench form the first filling layer and the third filling layer, respectively.

15. The method for manufacturing a semiconductor device according to claim 14, characterized in that, The formation of the second shallow trench isolation structure includes: A fifth trench is formed in the peripheral region, penetrating the fourth insulating material and the third insulating material and extending into the substrate, the width of the fifth trench being smaller than the width of the first trench; wherein the first trench defines a plurality of transistor regions arranged along a first direction within the substrate in the peripheral region, and the fifth trench defines a plurality of peripheral active regions arranged along the first direction in at least a portion of the transistor regions; the first direction is parallel to the substrate surface; During the deposition of the first insulating material, the first insulating material fills the fifth trench; After etching the third insulating material, the first insulating material, and the second insulating material, the remaining first insulating material in the fifth trench forms the second shallow trench isolation structure.

16. The method for manufacturing a semiconductor device according to claim 15, characterized in that, The manufacturing method further includes: A gate structure is formed on the transistor region, the first shallow trench isolation structure, and the second shallow trench isolation structure in the peripheral region. The gate structure includes a high-k dielectric layer and a gate located on the high-k dielectric layer, where k is the dielectric constant. The gate structure extends along the first direction and is located on at least two peripheral active regions within the transistor region and on the second shallow trench isolation structure between adjacent peripheral active regions. And / or, the gate structure is located on at least two peripheral active regions of different transistor regions and on the first shallow trench isolation structure between adjacent transistor regions.

17. The method for manufacturing a semiconductor device according to claim 13, characterized in that, The manufacturing method further includes: A mask layer is formed on the substrate surface of the array region and the substrate surface of the dicing region, and a first photoresist layer having a second set of marking structure patterns is formed on the mask layer; After measuring the overlay accuracy between the second set of marking structures and the first set of marking structures, the first photoresist layer is exposed. The first photoresist layer after exposure is developed, and a plurality of first openings exposing the mask layer are formed in the developed first photoresist layer. Based on the first opening of the array region, a plurality of active regions, a plurality of third shallow trench isolation structures, and a plurality of fourth shallow trench isolation structures are etched to form word line trenches. The word line trenches extend along a second direction and pass through the active regions, the third shallow trench isolation structures, and the fourth shallow trench isolation structures. The second direction is parallel to the substrate surface.

18. A semiconductor device, characterized in that, include: A substrate, the substrate including a chip region and a dicing region, the chip region including a peripheral region, the peripheral region having a first trench extending from the surface of the substrate to the interior, and the dicing region having a second trench extending from the surface of the substrate to the interior. A first shallow trench isolation structure is located within the first trench of the chip region, and the first shallow trench isolation structure includes a first insulating layer that contacts the inner wall of the first trench. The first set of marking structures is located in the second groove of the cutting channel area, and the first set of marking structures includes a first filling layer that contacts the inner wall of the second groove; Wherein, the top surface of the first insulating layer is higher than the surface of the substrate, and the top surface of the first filling layer is higher than the surface of the substrate; A second shallow trench isolation structure is located in the substrate of the peripheral region. The second shallow trench isolation structure is made of the same material as the first insulating layer, and the top surface of the second shallow trench isolation structure is higher than the substrate surface. The first shallow trench isolation structure defines a plurality of transistor regions arranged along a first direction within the substrate, and the second shallow trench isolation structure defines a plurality of peripheral active regions arranged along the first direction in at least a portion of the transistor regions; the first direction is parallel to the surface of the substrate.

19. The semiconductor device according to claim 18, characterized in that, The first shallow trench isolation structure also includes: A barrier layer is located on the surface of the first insulating layer; A second insulating layer is located on the surface of the barrier layer and fills the remaining space of the first trench; The top surface of the second insulating layer is higher than the surface of the substrate, and the top surface of the barrier layer is lower than the top surfaces of the first insulating layer and the second insulating layer.

20. The semiconductor device according to claim 19, characterized in that, The top surface of the first insulating layer is 15 nm to 25 nm higher than the surface of the substrate.

21. The semiconductor device according to claim 19, characterized in that, The first shallow trench isolation structure further includes at least one first semiconductor layer, which is located between the barrier layer and the first insulating layer and / or between the barrier layer and the second insulating layer; Wherein, the top surface of the first semiconductor layer is not higher than the top surface of the first insulating layer.

22. The semiconductor device according to claim 19, characterized in that, The first set of marking structures also includes: The second filler layer is located on the surface of the first filler layer; The third filling layer is located on the surface of the second filling layer and fills the remaining space of the second trench; The top surface of the third filling layer is higher than the substrate surface, and the top surface of the second filling layer is lower than the top surfaces of the first filling layer and the third filling layer.

23. The semiconductor device according to claim 22, characterized in that, The top surface of the first filling layer is 15 nm to 25 nm above the substrate surface; and / or, The top surface of the third filling layer is flush with the top surface of the first filling layer.

24. The semiconductor device according to claim 22, characterized in that, The first set of marking structures further includes at least one second semiconductor layer, which is located between the second filling layer and the first filling layer, and / or between the second filling layer and the third filling layer; wherein the top surface of the second semiconductor layer is not higher than the top surface of the first filling layer.

25. The semiconductor device according to claim 22, characterized in that, The first filler layer and the first insulating layer are made of the same material, have the same thickness, and have their top surfaces flush with each other. And / or, the second filler layer is made of the same material and has the same thickness as the barrier layer, and their top surfaces are flush with each other; And / or, the third filler layer is made of the same material and has the same thickness as the second insulating layer, and their top surfaces are flush with each other.

26. The semiconductor device according to claim 18, characterized in that, The chip region further includes an array region, and the semiconductor device further includes: A third shallow trench isolation structure is located in the substrate of the array region, and the third shallow trench isolation structure includes a third insulating material; A fourth shallow trench isolation structure is located in the substrate of the array region. The fourth shallow trench isolation structure includes a fourth insulating layer and a third insulating layer located on the sidewalls and bottom of the fourth insulating layer. The top surfaces of the third shallow trench isolation structure and the fourth shallow trench isolation structure are flush with the substrate surface, and the third shallow trench isolation structure and the fourth shallow trench isolation structure define a plurality of active regions arranged in an array within the substrate of the array region.

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