Semiconductor structure and forming method thereof

Abstract

A semiconductor structure is provided. The semiconductor structure includes a channel member disposed over a substrate, a gate structure wrapping the channel member, an internal spacer adjacent the gate structure, and a source / drain feature adjoining the channel member. One of the internal spacers includes an intermediate dielectric portion and a shielding dielectric portion covering a surface of the intermediate dielectric portion. A dielectric constant of the shielding dielectric portion is greater than a dielectric constant of the intermediate dielectric portion. The embodiment of the invention also relates to a semiconductor structure and a forming method thereof.

Description

Technical Field

[0001] Embodiments of this application relate to semiconductor structures and methods of forming the same. Background Technology

[0002] The semiconductor integrated circuit (IC) industry has experienced exponential growth. Technological advancements in IC materials and design have yielded multiple generations of ICs, each featuring smaller and more complex circuitry than the previous generation. Throughout IC development, functional density (i.e., the number of interconnect devices per chip area) has generally increased, while geometry (i.e., the smallest component (or line) that can be created using manufacturing processes) has decreased. This miniaturization typically provides benefits through increased production efficiency and reduced associated costs. However, such miniaturization also increases the complexity of handling and manufacturing ICs.

[0003] Recently, multi-gate transistors have been introduced in an attempt to improve gate control by increasing gate-channel coupling, reducing off-state current, and mitigating short-channel effect (SCE). One such multi-gate transistor that has been introduced is the FinFET (Fin Field-Effect Transistor). FinFETs are named for their fin-like structure, which extends from the substrate forming it and is used to form the FET channel. Another type of multi-gate transistor (introduced in part to address some performance challenges associated with FinFET configurations) is the gate-wrapped device, such as the gate-all-around (GAA) transistor. Gate-wrapped devices are named for their gate structure, which extends entirely around the channel region, providing access to the channel on all four sides. The channel of a gate-wrapped device has multiple vertically spaced horizontal nanowires, nanosheets, and / or nanoribbons. Gate-wrapped devices are compatible with conventional complementary metal-oxide-semiconductor (CMOS) processes, and their structure allows them to scale significantly while maintaining gate control and mitigating SCE.

[0004] In multi-gate devices (such as wrapped-gate devices), internal spacers have been used to reduce capacitance and leakage between the gate structure and the source / drain components. While current methods for forming wrapped-gate devices with internal spacers are generally sufficient to meet their intended purpose, they continue to present challenges in device fabrication and performance and are not satisfactory in every respect. For example, etching processes, such as those used for channel release and for source / drain formation, can damage the internal spacers. Summary of the Invention

[0005] Some embodiments of this application provide a semiconductor structure including: a channel member disposed on a substrate; a gate structure enclosing the channel member; internal spacers adjacent to the gate structure, wherein one of the internal spacers includes an intermediate dielectric portion and a shielding dielectric portion covering a surface of the intermediate dielectric portion, and the dielectric constant of the shielding dielectric portion is greater than the dielectric constant of the intermediate dielectric portion; a source / drain member adjacent to the channel member; a contact etch stop layer (CESL) located above the source / drain member; and an interlayer dielectric (ILD) layer located above the contact etch stop layer, wherein the dielectric constant of the contact etch stop layer is greater than the dielectric constant of the interlayer dielectric layer.

[0006] Other embodiments of this application provide a method for forming a semiconductor structure, comprising: alternately stacking channel layers and sacrificial layers on a substrate to form a semiconductor stack; patterning the semiconductor stack to form a fin structure protruding from the substrate; forming source / drain trenches in the fin structure; laterally recessing the sacrificial layers in the fin structure to form grooves, wherein the grooves located at opposite ends of one of the sacrificial layers are spaced apart from each other along a direction; forming internal spacers in the grooves, wherein one of the internal spacers includes an intermediate dielectric portion and a shielding dielectric portion covering a surface of the intermediate dielectric portion, and the dielectric constant of the shielding dielectric portion is greater than the dielectric constant of the intermediate dielectric portion; forming source / drain components in the source / drain trenches; forming a contact etch stop layer over the source / drain components; and forming an interlayer dielectric (ILD) layer over the contact etch stop layer, wherein the thickness of the contact etch stop layer along the direction is less than the thickness of the interlayer dielectric layer.

[0007] Some embodiments of this application provide a method for forming a semiconductor structure, comprising: forming a fin structure including a stack on top of a substrate, the stack including a channel layer interleaved with a sacrificial layer, the substrate protruding from a substrate, the fin structure including a channel region and a source / drain region; forming a dummy gate stack over the channel region of the fin structure; depositing a gate spacer layer over the dummy gate stack; and forming a source / drain trench by recessing the source / drain region of the fin structure, wherein the source / drain trench exposes the channel layer and the sacrificial layer. Sidewalls; selectively and partially recessing the sacrificial layer in the fin structure to form a groove; forming internal spacers in the groove, wherein one of the internal spacers includes a shielding layer covering the surface of the intermediate layer, and the dielectric constant of the shielding layer is greater than the dielectric constant of the intermediate layer; forming source / drain components in the source / drain trench; forming a contact etch stop layer above the source / drain components; and forming an interlayer dielectric (ILD) layer above the contact etch stop layer, wherein the source / drain components are partially embedded in the substrate and below the interlayer dielectric layer. Attached Figure Description

[0008] Various aspects of the embodiments of this disclosure will be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard industry practice, the various components are not drawn to scale. In fact, for clarity of discussion, the dimensions of the various components may be arbitrarily increased or decreased.

[0009] Figure 1 This is a flowchart illustrating a method for forming a semiconductor structure from a workpiece according to some embodiments of the present disclosure.

[0010] Figure 2 This is a partial perspective view of a semiconductor structure at an intermediate stage according to some embodiments of the present disclosure.

[0011] Figure 3A , Figure 3B , Figure 3C , Figure 3D , Figure 3E , Figure 3F , Figure 3G , Figure 3H , Figure 3I , Figure 3J , Figure 3K , Figure 3L , Figure 3M , Figure 3N and Figure 3O It shows the basis Figure 1 Partial cross-sectional views of the semiconductor structure fabrication process at various intermediate stages in some embodiments of the method described above.

[0012] Figure 4 It is based on energy dispersive X-ray spectroscopy (EDX) analysis of the relative concentrations of several atomic substances relative to the position of the internal spacers of the exemplary structure according to some embodiments.

[0013] Figure 5A , Figure 5B and Figure 5C This is a partial cross-sectional view of a semiconductor structure at an intermediate stage after the formation of intermediate dielectric portions of internal spacers, according to some embodiments of the present disclosure.

[0014] Figure 6A , Figure 6B and Figure 6C This is a partial cross-sectional view showing a semiconductor structure at an intermediate stage after the formation of internal spacers, according to some embodiments of the present disclosure. Detailed Implementation

[0015] The following disclosure provides numerous different embodiments or instances for implementing various features of the provided subject matter. Specific examples of elements and arrangements are described below to simplify embodiments of this disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first component on or over a second component may include embodiments where the first and second components are in direct contact, and may also include embodiments where an additional component may be formed between the first and second components, such that the first and second components are not in direct contact. Furthermore, reference numerals and / or characters may be repeated in various instances of embodiments of this disclosure. This repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0016] Furthermore, for ease of description, this document uses spatial relative terms such as “below,” “lower,” “above,” “upper,” and “on top” to describe the relationship between one element or component and another (or other elements or components) as shown in the figures. In addition to the orientations depicted in the figures, spatial relative terms are intended to include different orientations of the device during use or operation. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptors used herein can be interpreted accordingly.

[0017] As used herein, terms such as “first,” “second,” and “third” describe individual elements, components, regions, layers, and / or sections, but these elements, components, regions, layers, and / or sections should not be limited by these terms. These terms may be used only to distinguish one element, component, region, layer, or section from another. Terms such as “first,” “second,” and “third,” when used herein, do not imply any order or sequence unless the context clearly indicates otherwise.

[0018] While the numerical ranges and parameters illustrating the broad scope of embodiments of this disclosure are approximate, the numerical values ​​described in specific embodiments are reported as precisely as possible. However, any numerical value inherently includes some error, necessarily caused by the standard deviation found in the corresponding test measurement. Furthermore, as used herein, the terms “substantially,” “about,” or “approximately” generally mean a value or range that can be considered by one of ordinary skill in the art. Alternatively, the terms “substantially,” “about,” or “approximately” mean within an acceptable standard error of the average value as considered by one of ordinary skill in the art. One of ordinary skill in the art will understand that acceptable standard errors can vary depending on the technology. Except in operational / working instances, or unless otherwise expressly stated, all numerical ranges, quantities, values, and percentages disclosed herein, such as the amount of material used for them, duration, temperature, operating conditions, ratios of quantities, etc., should be understood to be modified by the terms “substantially,” “about,” or “approximately” in all instances. Therefore, unless indicated to the contrary, the numerical parameters set forth in embodiments of this disclosure and the appended claims are approximate values ​​that can vary as needed. At a minimum, each numerical parameter should be interpreted at least in view of the number of significant figures reported and by applying common rounding techniques. A range may be expressed in this document as a distance from one endpoint to another or between two endpoints. All ranges disclosed herein include endpoints unless otherwise stated.

[0019] This disclosure generally relates to semiconductor structures and methods of manufacturing thereof, and more specifically to the formation of internal spacers during the fabrication of multi-gate semiconductor structures, such as gate-wrapped transistors. In a gate-wrapped transistor, the gate of the transistor is formed entirely around the channel, such that the channel is surrounded or wrapped by the gate. Such transistors have the advantage of improved gate-to-channel electrostatic control, which also mitigates leakage current. Gate-wrapped transistors include internal spacers and external gate sidewall spacers (or simply gate spacers). Internal spacers are typically formed by additional processes relative to the gate spacers. Internal spacers are formed between channel layers and serve to reduce capacitance and leakage between the gate structure and the source / drain components. The purpose of this disclosure is to provide robust internal spacers and methods of manufacturing. The internal spacers of the embodiments have the advantage of preventing etch damage and reducing parasitic capacitance between the gate structure and the source / drain components, thereby improving the reliability and electrical performance of the semiconductor structure. Source / drain components may refer to the source or drain, individually or jointly, depending on the context.

[0020] Various aspects of embodiments of the present disclosure will now be described in more detail with reference to the accompanying drawings. In this regard, Figure 1 This is a flowchart illustrating a method 100 for forming a semiconductor structure from a workpiece according to an embodiment of the present disclosure. Figure 2This is a partial perspective view of a semiconductor structure at an intermediate stage according to some embodiments. The nanosheet field-effect transistor is exemplary to illustrate the semiconductor structure in some embodiments; however, embodiments of this disclosure are not limited to nanosheet field-effect transistors.

[0021] Method 100 is merely an example and is not intended to limit the embodiments of this disclosure to what is expressly shown in method 100. Additional steps may be provided before, during, and after method 100, and for additional embodiments of the method, some of the described steps may be replaced, eliminated, or rearranged. For simplicity, not all steps are described in detail herein. The following is in conjunction with... Figure 2 Description method 100, Figure 2 This is a perspective view of workpiece 200. Because workpiece 200 will be manufactured into a semiconductor structure, it can be referred to herein as semiconductor structure 200. Furthermore, Figure 2 , Figures 3A to 3O , Figures 5A to 5C and Figures 6A to 6C The directions D1, D2, and D3 are perpendicular to each other. Throughout the embodiments of this disclosure, the same reference numerals denote the same components unless otherwise stated.

[0022] In some embodiments, such as Figure 2 As shown, the semiconductor structure 200 includes a fin structure 210 protruding from a substrate 202. Each fin structure 210 includes a sacrificial layer 206 and a channel layer 208 alternately stacked over the substrate 202. A plurality of dummy gate stacks 215 extend across the fin structure 210 and are longitudinally oriented along the D2 direction. In some embodiments, the extension direction of the fin structure 210 is perpendicular to the extension direction of the dummy gate stacks 215. Source / drain regions are formed on opposite sides of the dummy gate stacks 215. A channel layer 208 is formed between the source / drain regions over the substrate 202. Isolation members 211 are formed on opposite sides of the fin structure 210. The isolation members 211 may be flush with the top surface of the fin substrate 210B. Each dummy gate stack 215 may include a dummy dielectric layer 212 on the fin structure 210 and a dummy electrode layer 214 on the dummy dielectric layer 212.

[0023] Figure 2 A reference cross section, used in later figures, is also shown. Cross section AA is along the longitudinal axis of fin structure 210 (e.g., in direction D1), for example, perpendicular to the longitudinal axis along the dummy gate stack 215 (e.g., in direction D2). For clarity, subsequent figures refer to reference cross section AA.

[0024] Figures 3A to 3O It shows the basis Figure 1 Partial cross-sectional views of the fabrication of semiconductor structures at various intermediate stages in some embodiments of method 100. Figure 3AIt is along Figure 2 The cross-sectional view taken from section AA extends along the longitudinal direction of fin structure 210. (Reference) Figure 1 , Figure 2 and Figure 3A Method 100 includes block 102, wherein a workpiece 200 having a plurality of fin structures 210 protruding from a substrate 202 is provided, and a plurality of dummy gate stacks 215 are positioned across the fin structures 210. In some embodiments, the fin structures 210 are longitudinally oriented along a D1 direction, and the dummy gate stacks 215 are longitudinally oriented along a D2 direction. The D1 direction may be perpendicular to the D2 direction. The fin structure 210 may include two fins, one located in an n-type region (where an n-type transistor will be formed) and the other located in a p-type region (where a p-type transistor will be formed). Optionally, the fin structure 210 may include two fins, both located in the n-type region or both located in the p-type region.

[0025] In some embodiments, substrate 202 may be a semiconductor substrate such as a silicon (Si) substrate. Substrate 202 may include various doping configurations as known in the art depending on design requirements. In embodiments where the semiconductor device is p-type, an n-well (not shown) may be formed on a portion of substrate 202 in a p-type region. In some embodiments, the n-type dopant used to form the n-well may include phosphorus (P) or arsenic (As). In embodiments where the semiconductor device is n-type, a p-well may be formed on a portion of substrate 202 in an n-type region. In some embodiments, the p-type dopant used to form the p-well may include boron (B) or gallium (Ga). Suitable doping methods may include ion implantation and / or diffusion processes of the dopant. Substrate 202 may also include other semiconductors such as germanium (Ge), silicon carbide (SiC), silicon germanium (SiGe), or diamond. Optionally, substrate 202 may include compound semiconductors and / or alloy semiconductors. In addition, the substrate 202 may include an epitaxial layer (epi layer), which may be strained for performance enhancement, may include a silicon-on-insulator (SOI) or germanium-on-insulator (GeOI) structure, and / or may have other suitable enhancement components.

[0026] In some embodiments, each of the fin structures 210 includes alternating layers on top of the fin substrate 210B. Formation of the fin structure 210 may include: depositing a stack (not shown) on the substrate 202 in an epitaxial growth process; and patterning the stack and the top portion of the substrate 202 to form a plurality of stacks 205. Each of the stacks 205 includes the fin structure 210. Because the fin substrate 210B is formed by patterning the top portion of the substrate 202, the fin substrate 210B can still be considered as the top portion of the substrate 202, depending on the context.

[0027] The stack 205 includes sacrificial layers 206 interleaved with channel layers 208. Sacrificial layers 206 and channel layers 208 comprise different material compositions. In some embodiments, sacrificial layer 206 comprises a semiconductor composition, such as silicon germanium (SiGe) or another suitable semiconductor material. In some embodiments, sacrificial layer 206 comprises a dielectric composition, such as oxide or another suitable interposer material, and sacrificial layer 206 may be referred to as a sacrificial dielectric interposer. In some embodiments, channel layer 208 comprises the semiconductor composition silicon (Si). While the three layers of sacrificial layer 206 and the three layers of channel layer 208 are arranged alternately in the exemplary embodiments, this is merely for illustrative purposes and is not intended to limit the scope beyond what is specifically recited in the claims. It will be understood that any number of epitaxial layers (i.e., sacrificial layers 206 and channel layers 208) may be formed in the stack 205. The number of layers depends on the desired number of channel components for the semiconductor structure 200. In some embodiments, the number of channel layers 208 is between 1 and 20.

[0028] In some embodiments, all sacrificial layers 206 may have a substantially uniform thickness between about 3 nm and about 10 nm, and all channel layers 208 may have a substantially uniform thickness between about 3 nm and about 15 nm. The thicknesses of the sacrificial layers 206 and the channel layers 208 may be the same or different. As described in more detail below, channel layers 208 or portions thereof may be used as channel members for subsequently formed multi-gate devices, and the thickness of the channel layers 208 may be determined based on device performance considerations. In some embodiments, the sacrificial layers 206 in the channel regions are eventually removed and used to define the vertical distance between adjacent channel layers 208 of subsequently formed multi-gate devices. The thickness of the sacrificial layers 206 is determined based on device performance considerations.

[0029] The layers in stack 205 can be deposited using molecular beam epitaxy (MBE), vapor deposition (VPE), and / or another suitable epitaxial growth process. Therefore, stack 205 is also referred to as epitaxial stack 205. As described above, in at least some embodiments, sacrificial layer 206 comprises an epitaxially grown silicon-germanium (SiGe) layer, and channel layer 208 comprises an epitaxially grown silicon (Si) layer. In some embodiments, sacrificial layer 206 and channel layer 208 are substantially free of dopants. That is, sacrificial layer 206 and channel layer 208 may have a diameter from approximately 0 cm⁻¹. -3 Up to 1×10 17 cm -3 The non-inherent dopant concentration. No intentional doping was performed during the epitaxial growth process used to form the sacrificial layer 206 and the channel layer 208.

[0030] In some embodiments, the fin structure 210 may be patterned from the stack 205 and the substrate 202 using photolithography and etching processes. The photolithography process may include photoresist coating (such as spin coating), soft baking, mask alignment, exposure, post-exposure baking, photoresist development, rinsing, drying (such as spin drying and / or hard baking), other suitable photolithography techniques, and / or combinations thereof. In some embodiments, the etching process may include dry etching (such as reactive ion etching (RIE)), wet etching, and / or another etching method. In some embodiments, dual patterning or multiple patterning processes may be used to define the fin structure 210 having a spacing, for example, smaller than that achievable using a single, direct photolithography process. For example, in one embodiment, a material layer (not shown) is formed and patterned using a photolithography process over the substrate 202. Spacers are formed alongside the patterned material layer using a self-aligned process. The material layer is then removed, and the remaining spacers or mandrels may then be used to pattern the fin structure 210 by etching the top portions of the stack 205 and the substrate 202.

[0031] Furthermore, the workpiece 200 (or semiconductor structure 200) includes an isolation component 211 deposited in a trench between the opposing sidewalls of two adjacent fin structures 210. Figure 2 In some embodiments, isolation member 211 is formed in a trench to isolate fin structure 210 from adjacent fin structures. Isolation member 211 may also be referred to as shallow trench isolation (STI) member 211. In some exemplary methods for forming isolation member 211, a dielectric layer is first deposited over substrate 202 to fill the trench. In some embodiments, the dielectric layer may include silicon oxide, silicon nitride, silicon oxynitride, fluorine-doped silicate glass (FSG), a low-k dielectric material, another suitable material, and / or combinations thereof. In various instances, the dielectric layer may be deposited using chemical vapor deposition (CVD), subatmospheric pressure CVD (SACVD), flowable CVD, spin coating, and / or another suitable process. The deposited dielectric material is then thinned and planarized, for example, by chemical mechanical polishing (CMP). The planarized dielectric layer is further recessed or pulled back by dry etching, wet etching, and / or combinations thereof to form STI member 211. After the planarized dielectric layer is recessed, the fin structure 210 rises above the STI component 211. The recessed top surface of the STI component 211 can be flush with the top surface of the fin substrate 210B.

[0032] After defining the fin structure 210, a plurality of dummy gate stacks 215 are formed over the fin structure 210. The dummy gate stacks 215 may include a dummy dielectric layer 212 and a dummy electrode layer 214 on the dummy dielectric layer 212. The formation of the dummy gate stacks 215 may include depositing layers of the dummy gate stacks 215 and patterning these layers. In some embodiments, a dummy dielectric material, a dummy electrode material, and a gate top hard mask layer (not shown) may be blanket-deposited over the substrate 202, covering the fin structure 210 and the isolation member 211.

[0033] In some embodiments, a dummy dielectric material may be formed on the fin structure 210 using a CVD process, an atomic layer deposition (ALD) process, an oxygen plasma oxidation process, or another suitable process. The dummy dielectric material may include silicon oxide or another suitable dielectric material. In some embodiments, a dummy electrode material may be deposited over the dummy dielectric material using a CVD process, an ALD process, or another suitable process. The dummy electrode material may include polysilicon. For patterning purposes, a gate-top hard mask layer may be deposited on the dummy electrode material using a CVD process, an ALD process, or another suitable process. The gate-top hard mask layer may then be used as a patterning mask to pattern the dummy electrode material and the dummy dielectric material to form a dummy gate stack 215. For example, the patterning process may include a photolithography process (such as photolithography or e-beam lithography), which may also include photoresist coating (such as spin coating), soft baking, mask alignment, exposure, post-exposure baking, photoresist development, rinsing, drying (such as spin drying and / or hard baking), another suitable photolithography technique, and / or combinations thereof. In some embodiments, the etching process may include dry etching (such as RIE etching), wet etching, and / or another etching method.

[0034] A dummy gate stack 215 is formed over a corresponding channel region 210C of the fin structure 210. In some embodiments, a gate replacement process (or post-gate process) is employed, wherein the dummy gate stack 215 serves as a placeholder structure to undergo various processes and is removed and replaced by a functional gate structure. A transistor is formed at the intersection of the fin structure 210 and the functional gate structure. In an exemplary embodiment, with the dummy gate stack 215 formed over the fin structure 210, the fin structure 210 is divided into a channel region 210C located below the dummy gate stack 215 and a source / drain region 210S / D between the channel region 210C. Figure 3A As shown, the channel region 210C is disposed between the two source / drain regions 210S / D along the D1 direction. Furthermore, the dummy gate stacks 215 are separated from each other by the gate pitch GS along the D1 direction. The gate width Wg of the dummy gate stacks 215 along the D1 direction and the spacing Pgd between adjacent dummy gate stacks 215 are also... Figure 3AThe dummy gate stack 215 formed in the channel region 210C can have a uniform gate width Wg.

[0035] refer to Figure 1 and Figure 3B Method 100 includes block 104, wherein a gate spacer layer 218 is deposited on the sidewalls of a dummy gate stack 215. The gate spacer layer 218 may be a single layer or multiple layers. In some embodiments, one layer of the gate spacer layer 218 may include silicon carbonitride, silicon carbon oxide, silicon carbonitride, or silicon nitride. The gate spacer layer 218 may be deposited over the dummy gate stack 215 using a process such as CVD, subatmospheric pressure CVD (SACVD), ALD, or another suitable process.

[0036] In some embodiments, the gate spacer layer 218 includes a first gate spacer 216 and a second gate spacer 217 disposed above the first gate spacer 216, such as Figure 3B As shown in the diagram. The first gate spacer 216 may comprise silicon oxynitride, and the second gate spacer 217 may comprise silicon nitride. The formation of the gate spacer layer 218 may include conformally depositing a first gate spacer material (not shown) and conformally depositing a second gate spacer material (not shown) on the first gate spacer material, followed by patterning these gate spacer materials. The term "conformal" may be used herein to conveniently describe layers having a substantially uniform thickness over various regions. In some embodiments, the patterning process may include removing excess portions of the second gate spacer material and the first gate spacer material, including the top portion above the top surface 214a of the dummy electrode layer 214 and the bottom portion above the topmost channel layer 208. Figure 3B As shown, the remaining portions of the first gate spacer material and the second gate spacer material can be referred to as the first gate spacer 216 and the second gate spacer 217, respectively. In some embodiments, after the patterning process, the top surface 214a of the dummy electrode layer 214 and the top surface 208a of the topmost sacrificial layer 208 are exposed. The gate spacer layer 218 can also be referred to as the gate spacer 218.

[0037] refer to Figure 1 and Figure 3CMethod 100 includes block 106, wherein a fin structure 210 in the source / drain region 210S / D is recessed to form a source / drain trench 220. In some embodiments, the source / drain region 210S / D not covered by the dummy gate stack 215 and the gate spacer layer 218 is etched by a dry etching process or another suitable etching process to form the source / drain trench 220. For example, the dry etching process may utilize oxygen-containing gases, fluorine-containing gases (such as CF4, SF6, CH2F2, CHF3 and / or C2F6), chlorine-containing gases (such as Cl2, CHCl3, CCl4 and / or BCl3), bromine-containing gases (such as HBr and / or CHBr3), iodine-containing gases, another suitable gas, plasma, and / or combinations thereof. In some embodiments, the fin structure 210 is recessed to expose the sidewalls 206s of the sacrificial layer 206 and the sidewalls 208s of the channel layer 208. In some implementations, the source / drain trench 220 extends below the stack 205 into the fin substrate 210B.

[0038] refer to Figure 1 and Figure 3D Method 100 includes block 108, wherein the sacrificial layer 206 is laterally recessed to form a plurality of grooves 232 in the fin structure 210. In some embodiments, the operation in block 108 may include selective and partial removal of the sacrificial layer 206 to form grooves 232 between adjacent channel layers 208. In some embodiments, the sacrificial layer 206 exposed in the source / drain trench 220 is selectively and laterally etched to form the grooves 232, while the exposed portions of the gate spacer layer 218, the fin substrate 210B (substrate 202), and the channel layers 208 are substantially left unetched. Figure 3D As shown, the grooves 232 at opposite ends of each of the sacrificial layers 206 are separated from each other along the first direction D1.

[0039] In embodiments where the channel layer 208 is primarily composed of silicon (Si) and the sacrificial layer 206 is primarily composed of silicon-germanium (SiGe), selectively recessing the sacrificial layer 206 can be implemented using a selective wet etching process or a selective dry etching process. In some embodiments, a single etching process is performed to laterally recess the sacrificial layer 206. In some embodiments, selectively and partially recessing the sacrificial layer 206 includes a SiGe oxidation process followed by SiGe oxide removal. In this embodiment, the SiGe oxidation process may include the use of ozone. In some other embodiments, a selective dry etching process may include the use of one or more fluorine-based etchants, such as fluorine gas or hydrofluorocarbons. A selective wet etching process may include APM etching (e.g., an ammonium hydroxide-hydrogen peroxide-water mixture).

[0040] After the grooves 232 are formed, the top surface 232a of each groove 232 is defined by the exposed bottom portion of the channel layer 208 above the groove 232, and the bottom surface 232b of each groove 232 is defined by the exposed top portion of another channel layer 208 located below the groove 232. Figure 3D As shown, the top surface 232a of the groove 232 is not parallel to the bottom surface 232b of the groove 232. In some embodiments, each of the grooves 232 has a vertical dimension that increases toward the source / drain trench 220. Therefore, the internal spacers subsequently formed in the grooves 232 can serve as barriers to prevent the formation of undesirable seams by etching through the channel layer during the etching process for channel release. In some embodiments, the vertical dimension D of the groove 232 is... RA (For example, in the D3 direction) larger than the vertical dimension D of the groove 232 RB (For example, in the D3 direction). In some embodiments, the vertical dimension D of the groove 232 RB It is essentially equal to the thickness Ts of one of the sacrificial layers 206.

[0041] Next, in some embodiments, reference is made to Figures 3E to 3I Method 100 includes block 110, wherein an internal spacer 240 is formed in a recess 232. Operations in block 110 may include suitable deposition and etching processes for forming an internal spacer in one of the recesses 232, comprising an intermediate dielectric portion 242 and a shielding dielectric portion 240-1 covering the surface of the intermediate dielectric portion 242. Furthermore, in some embodiments, the dielectric constant of the shielding dielectric portion 240-1 is greater than the dielectric constant of the intermediate dielectric portion 242, which will be described in more detail below.

[0042] refer to Figure 3E In some embodiments, a first dielectric material layer 2410 is conformally deposited on the sidewalls and bottom of the source / drain trench 220. Specifically, as Figure 3E As shown, a first dielectric material layer 2410 is conformally deposited on the exposed sidewalls 218s of the gate spacer layer 218, the exposed sidewalls 208s of the channel layer 208, the exposed sidewalls 206s of the sacrificial layer 206, and the bottom of the source / drain trench 220. Furthermore, the first dielectric material layer 2410 is conformally deposited on the exposed inner sidewalls of the recess 232. After the deposition of the first dielectric material layer 2410, the original spacing of the recess 232 is partially occupied by the first dielectric material layer 2410, and the remaining spacing in the recess 232 is referred to as the first cavity 234. In some embodiments, the thickness T1 of the first dielectric material layer 2410 deposited in the source / drain trench 220 and the recess 232 is substantially uniform.

[0043] In some embodiments, the first dielectric layer 2410 comprises one or more materials having a non-low dielectric constant (non-low k). Specifically, the first dielectric layer 2410 may have a dielectric constant of about 3.0 to about 8.0, about 3.0 to about 7.5, about 3.0 to about 7.0, about 3.0 to about 6.5, or about 3.0 to about 6.0. In some embodiments, the first dielectric layer 2410 has a dielectric constant of about 5.0 to about 8.0, about 5.0 to about 7.5, about 5.0 to about 7.0, about 5.0 to about 6.5, or about 5.0 to about 6.0. In some embodiments, the first dielectric layer 2410 has a dielectric constant of about 5 or another suitable dielectric constant. These values ​​are provided for illustrative purposes only and are not intended to be limiting.

[0044] Furthermore, in some embodiments, the first dielectric material layer 2410 includes silicon, oxygen, and at least one of carbon and nitrogen.

[0045] In some embodiments where the first dielectric material layer 2410 includes carbon, the carbon concentration ([C]) is less than about 15%.

[0046] In some embodiments where the first dielectric material layer 2410 includes nitrogen, the nitrogen concentration ([N]) is in the range of about 15% to about 30%.

[0047] In some embodiments where the first dielectric material layer 2410 includes oxygen, the oxygen concentration ([O]) is in the range of about 30% to about 50%.

[0048] In some embodiments where the first dielectric material layer 2410 includes carbon, oxygen, and other elements, the carbon concentration ([C]) is less than about 15%, and the oxygen concentration is in the range of about 30% to about 50%.

[0049] In some embodiments where the first dielectric layer 2410 includes nitrogen, oxygen and other elements, the nitrogen concentration ([N]) is in the range of about 15% to about 30%, and the oxygen concentration ([O]) is in the range of about 30% to about 50%.

[0050] In some embodiments where the first dielectric layer 2410 includes nitrogen, carbon, oxygen and other elements, the nitrogen concentration ([N]) is in the range of about 15% to about 30%, the carbon concentration ([C]) is less than about 15%, and the oxygen concentration ([O]) is in the range of about 30% to about 50%.

[0051] In some embodiments, the total concentration of nitrogen and carbon is less than the concentration of oxygen ([O]) in the first dielectric material layer 2410, and can be expressed as nitrogen ([N]) + carbon ([C]) < oxygen ([O]).

[0052] In some embodiments, the comparison between the concentrations of carbon ([C]), nitrogen ([N]), silicon ([Si]), and oxygen ([O]) in the first dielectric material layer 2410 can be expressed as follows:

[0053] Carbon (C) < Nitrogen (N) < Silicon (Si) < Oxygen (O).

[0054] In some embodiments, the first dielectric material layer 2410 comprises about 15% to about 30% nitrogen and less than 50% oxygen, allowing the first dielectric material layer 2410 to be referred to as a hard film for forming portions of the internal spacers in some embodiments.

[0055] In some embodiments, the first dielectric material 2410 comprises one or more non-low-k dielectric materials, such as silicon nitride, silicon oxynitride, and silicon carbonitride, or any other suitable dielectric material. In some embodiments, the first dielectric material 2410 is deposited using CVD, plasma-enhanced chemical vapor deposition (PECVD), SACVD, ALD, or another suitable method. In one embodiment, the first dielectric material 2410 is deposited using ALD.

[0056] Next step, refer to Figure 3F In some embodiments, a second dielectric material layer 2420 is conformally deposited on the first dielectric material layer 2410, wherein the second dielectric material layer 2420 is deposited in the first cavity 234. Figure 3E In some embodiments, a second dielectric material layer 2420 is conformally deposited on a first dielectric material layer 2410 and has a similar cross-sectional shape to the first dielectric material layer 2410. After the second dielectric material layer 2420 is deposited, the spacing of the first cavity 234 is partially occupied by the second dielectric material layer 2420, and the remaining spacing in the first cavity 234 is referred to as the second cavity 236. The second cavities 236 are recessed between adjacent vertically stacked channel layers 208.

[0057] In some embodiments, the thickness T2 of the second dielectric material layer 2420 deposited in the first cavity 234 of the source / drain trench 220 and the recess 232 is substantially uniform. In some embodiments, the thickness ratio of thickness T2 to thickness T1 is approximately at least 2 or greater than 2. In some embodiments, the thickness ratio of thickness T2 to thickness T1 is in the range of approximately 2 to approximately 3. In some embodiments, the thickness ratio of thickness T2 to thickness T1 is approximately 2.

[0058] Furthermore, according to the embodiment, the dielectric constant of the second dielectric material layer 2420 is less than the dielectric constant of the first dielectric material layer 2410.

[0059] In some embodiments, the second dielectric layer 2420 comprises one or more low-k dielectric materials. Specifically, the second dielectric layer 2420 has a dielectric constant (k value) of about 3.9 or less. In some embodiments, the second dielectric layer 2420 has a dielectric constant of about 2.0 to about 3.9. In some embodiments, the second dielectric layer 2420 has a dielectric constant of about 2.0 to about 3.5. In some embodiments, the second dielectric layer 2420 has a dielectric constant of about 2.0 to about 3.0. In some embodiments, the second dielectric layer 2420 has a dielectric constant of about 2.5 to about 3.9. In some embodiments, the second dielectric layer 2420 may have a dielectric constant of about 3.0 to about 3.9. In some embodiments, the second dielectric layer 2420 has a dielectric constant of about 3 or another suitable dielectric constant. These values ​​are provided for illustrative purposes only and are not intended to be limiting.

[0060] In addition, in some embodiments, the second dielectric material layer 2420 includes silicon, oxygen, and optionally carbon and / or nitrogen.

[0061] In some embodiments where the second dielectric material layer 2420 includes carbon and other elements, the carbon concentration ([C]) is less than about 10%.

[0062] In some embodiments where the second dielectric material layer 2420 includes nitrogen, the nitrogen concentration ([N]) is less than about 10%.

[0063] In some embodiments where the second dielectric material layer 2420 includes oxygen, the oxygen concentration ([O]) is greater than about 50%.

[0064] In some embodiments where the second dielectric material layer 2420 includes nitrogen, carbon, oxygen and other elements, the nitrogen concentration ([N]) is less than about 10%, the carbon concentration ([C]) is less than about 10%, and the oxygen concentration ([O]) is greater than about 50%.

[0065] In some embodiments, the total concentration of nitrogen and carbon is less than the concentration of oxygen ([O]) in the second dielectric material layer 2420, and can be expressed as nitrogen ([N]) + carbon ([C]) < oxygen ([O]).

[0066] In some embodiments, the total concentration of nitrogen, carbon, and silicon in the second dielectric layer 2420 is less than the concentration of oxygen ([O]) in the second dielectric layer 2420, and can be expressed as follows:

[0067] Nitrogen ([N]) + Carbon ([C]) + Silicon ([Si]) < Oxygen ([O]).

[0068] In some embodiments, the second dielectric layer 2420 includes more than 50% oxygen, less than about 10% nitrogen and / or carbon, allowing the second dielectric layer 2420 to be referred to as a soft film.

[0069] In some embodiments, the second dielectric layer 2420 comprises one or more low-k dielectric materials selected from the group consisting of porous silica, carbon-doped silica, fluorine-doped silica, and another suitable low-k (e.g., k < 3.9) dielectric material. In some embodiments, the second dielectric layer 2420 is deposited using CVD, plasma-enhanced chemical vapor deposition (PECVD), SACVD, ALD, or another suitable method. In one embodiment, the second dielectric layer 2420 is deposited using ALD.

[0070] Next step, refer to Figure 3G In some embodiments, a portion of the second dielectric layer 2420 is removed, and the remaining portion of the second dielectric layer 2420 in the recess 232 forms an intermediate dielectric portion 242. In some embodiments, the second dielectric layer 2420 is selectively etched to expose the first dielectric layer 2410 on the sidewalls 218s of the gate spacer layer 218 and the sidewalls 208s of the channel layer 208.

[0071] In addition, such as Figure 3G As shown, the side surfaces 242S1, top surface 242a, and bottom surface 242b of each intermediate dielectric portion 242 are covered by a first dielectric material layer 2410, while the side surfaces 242S2 of the intermediate dielectric portion 242 in the groove 232 are exposed and face the source / drain trench 220.

[0072] Next step, refer to Figure 3H In some embodiments, a third dielectric material layer 2430 is conformally deposited in the source / drain trench 220. Specifically, the third dielectric material layer 2430 is deposited on the first dielectric material layer 2410 and covers the intermediate dielectric portion 242.

[0073] In some embodiments, the third dielectric layer 2430 comprises one or more materials having a non-low dielectric constant (non-low k). Specifically, the third dielectric layer 2430 may have a dielectric constant of about 3.0 to about 8.0, about 3.0 to about 7.5, about 3.0 to about 7.0, about 3.0 to about 6.5, or about 3.0 to about 6.0. In some embodiments, the third dielectric layer 2430 has a dielectric constant of about 5.0 to about 8.0, about 5.0 to about 7.5, about 5.0 to about 7.0, about 5.0 to about 6.5, or about 5.0 to about 6.0. In some embodiments, the third dielectric layer 2430 has a dielectric constant of about 5 or another suitable dielectric constant. These values ​​are provided for illustrative purposes only and are not intended to be limiting.

[0074] In some embodiments, the third dielectric layer 2430 comprises one or more non-low-k dielectric materials, such as silicon nitride, silicon oxynitride, and silicon carbonitride, or any other suitable dielectric material. In some embodiments, the third dielectric layer 2430 is deposited using CVD, plasma-enhanced chemical vapor deposition (PECVD), SACVD, ALD, or another suitable method. In one embodiment, the third dielectric layer 2430 is deposited using ALD.

[0075] Furthermore, in some embodiments, the third dielectric material layer 2430 includes silicon, oxygen, and at least one of carbon and nitrogen.

[0076] In some embodiments where the third dielectric material layer 2430 includes carbon, the carbon concentration ([C]) is less than about 15%.

[0077] In some embodiments where the third dielectric material layer 2430 includes nitrogen, the nitrogen concentration ([N]) is in the range of about 15% to about 30%.

[0078] In some embodiments where the third dielectric material layer 2430 includes oxygen, the oxygen concentration ([O]) is in the range of about 30% to about 50%.

[0079] In some embodiments where the third dielectric material layer 2430 includes carbon, oxygen, and other elements, the carbon concentration ([C]) is less than about 15%, and the oxygen concentration is in the range of about 30% to about 50%.

[0080] In some embodiments where the third dielectric material layer 2430 includes nitrogen, oxygen and other elements, the nitrogen concentration ([N]) is in the range of about 15% to about 30%, and the oxygen concentration ([O]) is in the range of about 30% to about 50%.

[0081] In some embodiments where the third dielectric material layer 2430 includes nitrogen, carbon, oxygen and other elements, the nitrogen concentration ([N]) is in the range of about 15% to about 30%, the carbon concentration ([C]) is less than about 15%, and the oxygen concentration ([O]) is in the range of about 30% to about 50%.

[0082] In some embodiments, the total concentration of nitrogen and carbon is less than the concentration of oxygen ([O]) in the third dielectric material layer 2430, and can be expressed as nitrogen ([N]) + carbon ([C]) < oxygen ([O]).

[0083] In some embodiments, the comparison between the concentrations of carbon ([C]), nitrogen ([N]), silicon ([Si]), and oxygen ([O]) in the third dielectric material layer 2430 can be expressed as follows:

[0084] Carbon (C) < Nitrogen (N) < Silicon (Si) < Oxygen (O).

[0085] In some embodiments, the third dielectric material layer 2430 comprises about 15% to about 30% nitrogen and less than 50% oxygen, allowing the third dielectric material layer 2430 to serve as another hard film for forming another portion of the internal spacers in some embodiments.

[0086] Furthermore, in some embodiments, the third dielectric layer 2430 and the first dielectric layer 2410 comprise the same element at the same or different concentrations. For example, the third dielectric layer 2430 and the first dielectric layer 2410 may comprise silicon, oxygen, and at least one of carbon and nitrogen, and the third dielectric layer 2430 and the first dielectric layer 2410 have different oxygen concentrations, less than about 50% or in the range of about 30% to about 50%. Furthermore, in some embodiments, the third dielectric layer 2430 and the first dielectric layer 2410 comprise different combinations of elements, wherein the third dielectric layer 2430 and the first dielectric layer 2410 exhibit hard film properties.

[0087] Furthermore, in some embodiments, the third dielectric layer 2430 and the first dielectric layer 2410 comprise different non-low-k dielectric materials having a dielectric constant greater than about 3.0 (e.g., about 3.0 to about 8.0) or greater than about 5.0 (e.g., about 5.0 to about 8.0). In some embodiments, the third dielectric layer 2430 and the first dielectric layer 2410 comprise the same non-low-k dielectric material having a dielectric constant of about 3.0 (e.g., about 3.0 to about 8.0) or greater than about 5.0 (e.g., about 5.0 to about 8.0).

[0088] Next step, refer to Figure 3IIn some embodiments, portions of the first dielectric layer 2410 and the third dielectric layer 2430 are removed by etching, exposing the sidewalls 218s of the gate spacer layer 218 and the sidewalls 208s of the channel layer 208 in the source / drain trench 220. The remaining portion of the first dielectric layer 2410 forms an inner dielectric segment 241 in a corresponding recess 232. The remaining portion of the third dielectric layer 2430 forms an outer dielectric segment 243. The outer dielectric segment 243 serves as a sealing assembly to cover the intermediate dielectric portion 242.

[0089] Furthermore, in some embodiments, the internal spacer 240 has a sidewall 240S2 that is substantially flush with the sidewall 208s of the channel layer 208. In an exemplary embodiment, the sidewall 240S2 of the internal spacer 240 is substantially flush with the sidewall 218s of the gate spacer layer 218. Specifically, the sidewall 241S2 of the internal dielectric segment 241 is substantially flush with the sidewall 243S2 of the external dielectric segment 243. The sidewall 243S2 of the external dielectric segment 243 and the sidewall 241S2 of the internal dielectric segment 241 are collectively referred to as the sidewall 240S2 of the internal spacer 240. It should be noted that the sidewall 240S2 may also be referred to as the second surface 240S2 of the internal spacer 240 in the description later, such as... Figure 3O As shown in the image.

[0090] like Figure 3I As shown, in some embodiments, the inner dielectric segment 241 and the outer dielectric segment 243 are collectively referred to as the shielding dielectric portion 240-1 covering the surface of the intermediate dielectric portion 242. The shielding dielectric portion 240-1 and the intermediate dielectric portion 242 are collectively referred to as the inner spacer 240 between adjacent channel layers 208.

[0091] In some embodiments, the dielectric constant of the shielding dielectric portion 240-1 is greater than the dielectric constant of the intermediate dielectric portion 242. That is, the dielectric constant of the inner dielectric segment 241 is greater than the dielectric constant of the intermediate dielectric portion 242, and the dielectric constant of the outer dielectric segment 243 is greater than the dielectric constant of the intermediate dielectric portion 242. Furthermore, the dielectric constant of the inner dielectric segment 241 may be the same as or different from the dielectric constant of the outer dielectric segment 243.

[0092] In some embodiments, the hardness of the shielding dielectric portion 240-1 is greater than the hardness of the intermediate dielectric portion 242. That is, the hardness of the inner dielectric segment 241 is greater than the hardness of the intermediate dielectric portion 242, and the hardness of the outer dielectric segment 243 is greater than the hardness of the intermediate dielectric portion 242. The hardness of the inner dielectric segment 241 may be the same as or different from the hardness of the outer dielectric segment 243.

[0093] In some embodiments, each of the internal spacers 240 has a vertical dimension that increases toward the source / drain trench 220. The top surface of one (or each) of the internal spacers 240 is not parallel to the bottom surface of one (or each) of the internal spacers 240. For example, the top surface 242a of one (or each) of the intermediate dielectric portions 242 is not parallel to the bottom surface 242b of the intermediate dielectric portion 242. Figure 3I As shown, the vertical dimension W1 of the side surface 241S1 of the inner dielectric segment 241 is smaller than the vertical dimension W2 of the side surface 243S1 of the outer dielectric segment 243. The vertical dimension W2 is smaller than the vertical dimension W3 of the side surface 243S2 of the outer dielectric segment 243. Furthermore, the combination of the inner dielectric segment 241 and the outer dielectric segment 243 provides a rigid shell to prevent the formation of undesirable seams by etching through the channel layer 208 (e.g., along the D1 direction) during the etching process for channel release.

[0094] Furthermore, according to exemplary methods of some embodiments, the inner dielectric segment 241 covers the top surface 243a and bottom surface 243b of the outer dielectric segment 243. Therefore, the junction of the inner dielectric segment 241 and the outer dielectric segment 243 further enhances the etch resistance of the inner spacer 240 in subsequent processes. For example, the top portion 240TE and the bottom portion 204BE of the inner spacer 240 each include a portion of the inner dielectric segment 241 and a portion of the outer dielectric segment 243. When the sacrificial layer 206 is selectively removed by etching to release the channel layer 208, the top portion 240TE and the bottom portion 204BE of the inner spacer 240 form a thicker segment comprising a non-low-k dielectric material and act as a solid barrier to stop lateral etching. In some embodiments, the top portion 240TE of the inner spacer 240 is located above the level of the top surface 206a of the channel layer 206, and the bottom portion 204BE of the inner spacer 240 is located below the level of the bottom surface 206b of the channel layer 206. Therefore, the top portion 240TE and bottom portion 204BE of the internal spacer 240 effectively prevent the formation of undesirable seams by etching through the channel layer 208 during the channel release process, thereby solving the conventional problem of metal being squeezed out through the seams to form leakage paths after the replacement gate is formed. Thus, the semiconductor structure fabricated by the method of the embodiment has a robust internal spacer 240.

[0095] Still referencing Figure 3I In some embodiments, the thickness T1 of the inner dielectric segment 241 (in the first direction D1) is less than the thickness T2 of the intermediate dielectric portion 242 (in the first direction D1), and the thickness T3 of the outer dielectric segment 243 (in the first direction D1) is less than the thickness T2 of the intermediate dielectric portion 242. Furthermore, the thickness T1 may be equal to or different from the thickness T3.

[0096] In some embodiments, the thickness ratio of thickness T2 to thickness T1 is approximately at least 2 or greater than 2. In some embodiments, the thickness ratio of thickness T2 to thickness T1 is in the range of approximately 2 to approximately 3. In some embodiments, the thickness ratio of thickness T3 to thickness T1 is approximately at least 2 or greater than 2. In some embodiments, the thickness ratio of thickness T3 to thickness T1 is in the range of approximately 2 to approximately 3. In some embodiments, the intermediate dielectric portion 242 comprises one or more low-k dielectric materials, and the volume of the intermediate dielectric portion 242 is at least half the total volume of the internal spacer 240. Therefore, the internal spacer 240 of the embodiments has the advantage of reducing the parasitic capacitance between the source / drain components subsequently formed in the source / drain trench 220 and the gate structure subsequently formed by replacing the sacrificial layer 208.

[0097] refer to Figure 1 , Figure 3J and Figure 3K Method 100 includes block 112, wherein a source / drain component 264 is formed in a source / drain trench 220. The operations in block 112 may include suitable epitaxial processes for growing a substrate epitaxial layer 262 and growing the source / drain component 264 over the substrate epitaxial layer 262, which will be described in more detail below.

[0098] refer to Figure 3J In some embodiments, after forming internal spacers 240 at opposite ends of sacrificial layer 206, a substrate epitaxial layer 262 is deposited at the bottom of each of the source / drain trenches 220. The formation of the substrate epitaxial layer 262 reduces the depth of the source / drain trenches 220 and facilitates the growth of the source / drain components 264 in subsequent processes.

[0099] In some embodiments, the epitaxial substrate 262 comprises the same material as the substrate 202 and the channel layer 208, such as silicon (Si), except for doping conditions (doping elements and / or doping concentration). For example, the epitaxial substrate 262 is made of undoped silicon, the substrate 202 is made of doped silicon, and the channel layer 208 is made of undoped or doped silicon. In some embodiments, the epitaxial substrate 262 comprises the same material as the sacrificial layer 206, such as silicon-germanium (SiGe), but with a different germanium (Ge) content. In some other embodiments, the epitaxial substrate 262, the channel layer 208, and the sacrificial layer 206 are made of different semiconductor materials. In various embodiments, the epitaxial substrate 262 is free of dopants, wherein, for example, no intentional doping is performed during the epitaxial growth process. By comparison, the substrate 202 may be lightly doped and have a higher doping concentration than the epitaxial substrate 262.

[0100] Furthermore, the epitaxial layer 262 provides a high-resistance path from the source / drain region to the substrate 202, thereby suppressing leakage current in the substrate 202 (i.e., through the finned substrate 210B). The inner spacer 240 restricts the vertical growth of the epitaxial layer 262 because epitaxial growth may not occur from the dielectric surface. The epitaxial layer 262 may exhibit planar growth as it reaches the bottom inner spacer 240. Therefore, in some embodiments, the epitaxial layer 262 may partially overlap with the bottom portion of the bottom inner spacer 240, but not grow vertically beyond the top surface of the bottom inner spacer 240. For simplicity and clarity, the epitaxial layer 262 flush with the bottom surface of the bottom inner spacer 240 is depicted in the figures.

[0101] Suitable epitaxial processes for growing the substrate epitaxial layer 262 may include vapor phase epitaxy (VPE), molecular beam epitaxy (MBE), selective CVD, and / or another suitable process. Various deposition parameters can be adjusted to selectively deposit semiconductor material on the exposed semiconductor surface in the source / drain trench 220, such as deposition gas composition, carrier gas composition, deposition gas flow rate, carrier gas flow rate, deposition time, deposition pressure, deposition temperature, source power, RF bias voltage, DC bias voltage, RF bias power, DC bias power, other suitable deposition parameters, or combinations thereof. In some embodiments, when forming the substrate epitaxial layer 262, the workpiece 200 is exposed to a deposition mixture comprising DCS and / or SiH4 (silicon-containing precursor), H2 (carrier precursor), and HCl (etchant-containing precursor). In some embodiments, the selective CVD process is performed at a deposition temperature of about 600°C to about 750°C. In some embodiments, the selective CVD process is performed at a deposition pressure of about 10 Torr to about 100 Torr. In some embodiments, a bottom-up deposition process is performed such that the substrate epitaxial layer 262 grows from the exposed semiconductor surface at the bottom of the source / drain trench 220, but not from the exposed end portions of the channel layer 208. In some embodiments, post-deposition etching is performed after a selective CVD process to remove any semiconductor material, if any, that may remain on the end portions of the channel layer 208. Post-deposition etching includes dry etching, wet etching, other suitable etching processes, or combinations thereof.

[0102] refer to Figure 3K In some embodiments, the source / drain component 264 is formed in the source / drain trench 220. In some embodiments, the source / drain component 264 may also be referred to as the doped epitaxial layer 264. Sometimes, the term "source / drain component" includes the doped epitaxial layer 264 and the underlying substrate epitaxial layer 262.

[0103] In this embodiment, forming the source / drain component 264 includes epitaxially growing a semiconductor layer using an MBE process, a chemical vapor deposition process, and / or other suitable epitaxial growth processes. The source / drain component 264 may include phosphorus- or arsenic-doped silicon for n-type transistors. The source / drain component 264 may include boron-doped silicon-germanium for p-type transistors. The source / drain component 264 covers the substrate epitaxial layer 262 and contacts the internal spacer 240. Furthermore, the source / drain component 264 contacts the sidewalls 208s of the channel layer 208. The source / drain component 264 may be grown vertically beyond the top surface of the topmost internal spacer 240 and the topmost channel layer 208.

[0104] In some embodiments, when the process for forming the substrate epitaxial layer 262 and the source / drain components 264 is performed, the outer dielectric segment 243 of the inner spacer 240 (which has a higher dielectric constant and greater hardness than the intermediate dielectric portion 242) prevents source / drain etching process damage.

[0105] Next step, refer to Figure 1 , Figure 3L , Figure 3M , Figure 3N and Figure 3O Method 100 includes block 114, in which further processes are performed. Such further processes may include, for example, depositing a contact etch stop layer (CESL) 266 over the structure and depositing an interlayer dielectric (ILD) layer 268 over the CESL 266. Figure 3L (as shown); Remove dummy gate stack 215 (as shown) Figure 3M (as shown); selectively remove the sacrificial layer 206 in the trench region to release the trench layer 208 as a trench component (as shown); Figure 3N (as shown); and a gate structure 274 is formed above the channel region. Figure 3O (As shown in the illustration). The components, materials, and manufacturing methods in some exemplary embodiments will now be described in more detail.

[0106] In some embodiments, CESL 266 is formed prior to the formation of ILD layer 268. CESL 266 may comprise silicon nitride, silicon oxynitride, and / or another material known in the art. CESL 266 may be formed by an ALD process, a plasma-enhanced chemical vapor deposition (PECVD) process, and / or another suitable deposition process. Figure 3L As shown, CESL 266 is formed on the top surface 264a of the source / drain component 264.

[0107] Then, ILD layer 268 is deposited over CESL 266. In some embodiments, the thickness of CESL 266 along the first direction D1 is less than the thickness of ILD layer 268. Furthermore, source / drain components comprising the doped epitaxial layer 264 and the underlying substrate epitaxial layer 262 are partially embedded in the substrate 202 and beneath ILD layer 268. ILD layer 268 may comprise materials such as tetraethyl orthosilicate (TEOS) oxide, undoped silicate glass, or doped silicon oxide, such as borosilicate glass (BPSG), fused silica glass (FSG), phosphosilicate glass (PSG), boron-doped silicon glass (BSG), and / or another suitable dielectric material. ILD layer 268 may be deposited by a PECVD process or another suitable deposition technique. In some embodiments, the structure may be annealed after formation of ILD layer 268 to improve the integrity of ILD layer 268. After depositing CESL 266 and ILD layer 268, a planarization process is performed on ILD layer 268 and CESL 266 to remove excess portions above the top surface of dummy gate stack 215, thereby exposing dummy gate stack 215. The planarization process may include a chemical mechanical planarization (CMP) process. The exposure of dummy gate stack 215 allows for its removal and release of channel layer 208.

[0108] In some embodiments, the dielectric constant of CESL 266 is greater than the dielectric constant of ILD layer 268. In some embodiments, the dielectric constant of shielding dielectric portion 240-1 is greater than the dielectric constant of ILD layer 268. Furthermore, the dielectric constant of the shielding dielectric portion may be the same as or greater than the dielectric constant of CESL.

[0109] In some embodiments, such as Figure 3M As shown, the exposed dummy gate stack 215 is removed to form a gate trench 270 over the channel layer 208. Removal of the dummy gate stack 215 may include one or more etching processes selectively targeting the material of the dummy gate stack 215. For example, removal of the dummy gate stack 215 may be performed using selective wet etching, selective dry etching, or a combination thereof. After removal of the dummy gate stack 215, the sidewalls of the channel layer 208 and the sacrificial layer 206 in the channel region are exposed in the gate trench 270.

[0110] In some embodiments, such as Figure 3NAs shown, after removing the dummy gate stack 215, method 100 may include the selective removal of the sacrificial layer 206 between the channel layers 208. The selective removal of the sacrificial layer 206 releases the channel layers 208 to form channel members (also designated 208). Furthermore, the selective removal of the sacrificial layer 206 leaves a gap 272 between the channel members 208. The selective removal of the sacrificial layer 206 may be implemented by selective dry etching, selective wet etching, or another selective etching process. A selective dry etching process may include the use of one or more fluorine-based etchants, such as fluorine gas or hydrofluorocarbons. A selective wet etching process may include APM etching (e.g., an ammonia hydroxide-hydrogen peroxide-water mixture).

[0111] In some embodiments, such as Figure 3O As shown, method 100 may include further operations to form a gate structure 274 to enclose each of the channel members 208. In some embodiments, the gate structure 274 is formed within the gate trench 270 and extends into the spacer 272 left by removing the sacrificial layer 206. In some embodiments, the gate structure 274 contacts the internal dielectric segment 241 of the internal spacer 240.

[0112] In some embodiments, the gate structure 274 includes a gate dielectric layer 275 and a gate electrode layer 277 above the gate dielectric layer 275. The gate dielectric layer 275 may include one or more high-k gate dielectric materials. In some embodiments, the dielectric constant of the gate dielectric layer 275 is greater than the dielectric constant of the inner dielectric segment 241. In some embodiments, the dielectric constant of the gate dielectric layer 275 is greater than the dielectric constant of the outer dielectric segment 243. Furthermore, in some embodiments, the intermediate dielectric portion 242 includes one or more low-k dielectric materials, and the volume of the intermediate dielectric portion 242 is more than half the total volume of the inner spacer 240. Therefore, the inner spacer 240 of the embodiments has the advantage of preventing etch damage and reducing parasitic capacitance between the source / drain components 264 and the gate structure 274.

[0113] The high-K dielectric material used to form the gate dielectric layer 275 may include a dielectric material having a dielectric constant higher than that of silicon oxide (approximately 3.9). The high-K gate dielectric layer may include hafnium oxide, titanium oxide (TiO2), hafnium zirconium oxide (HfZrO), tantalum oxide (Ta2O5), hafnium silicon oxide (HfSiO4), zirconium oxide (ZrO2), zirconium silicon oxide (ZrSiO2), lanthanum oxide (La2O3), aluminum oxide (Al2O3), zirconium oxide (ZrO), yttrium oxide (Y2O3), SrTiO3 (STO), BaTiO3 (BTO), BaZrO, hafnium lanthanum oxide (HfLaO), lanthanum silicon oxide (LaSiO), aluminum silicon oxide (AlSiO), hafnium tantalum oxide (HfTaO), hafnium titanium oxide (HfTiO), (Ba,Sr)TiO3 (BST), silicon nitride (SiN), silicon oxynitride (SiON), combinations thereof, or other suitable materials. The high-k gate dielectric layer can be formed by ALD, physical vapor deposition (PVD), CVD, oxidation, and / or another suitable method. In one embodiment, the gate dielectric layer 275 is formed using a highly conformal deposition process such as ALD to ensure that a gate dielectric layer with a uniform thickness is formed around each channel layer 208.

[0114] Furthermore, although not explicitly shown in the figures, gate dielectric layer 275 may include an interface layer and a high-k gate dielectric layer. The interface layer may include a dielectric material such as silicon oxide, hafnium silicate, or silicon oxynitride. The interface layer may be formed by chemical oxidation, thermal oxidation, atomic layer deposition (ALD), chemical vapor deposition (CVD), and / or another suitable method.

[0115] The gate electrode layer 277 of the gate structure 274 may include one or more conductive material layers, such as polysilicon, aluminum, copper, titanium, tantalum, tungsten, cobalt, molybdenum, tantalum nitride, nickel silicide, cobalt silicide, TiN, WN, TiAl, TiAlN, TaCN, TaC, TaSiN, metal alloys, another suitable material, and / or combinations thereof. The gate electrode layer 277 may be formed by ALD, PVD, CVD, e-beam evaporation, or another suitable process. In some embodiments, a gate dielectric material layer and a gate electrode material layer are deposited over the top surface 266a of the CESL 266 and the top surface 268a of the ILD layer 268. Then, an excess amount of the gate dielectric material layer and the gate electrode material layer formed over the ILD layer 268 is planarized using, for example, a CMP process until the CESL 266 and the ILD layer 268 are exposed. Thus, the gate structure 274 can provide a substantially flat top surface. Furthermore, the gate structure 274 includes portions between channel members 208 in the channel region.

[0116] In some embodiments, the gate structure 274 further includes a power function adjustment layer 276 disposed between the gate dielectric layer 275 and the gate electrode layer 277 to enhance device performance. The power function adjustment layer 276 may include one or more power function metal layers. In some embodiments, the power function adjustment layer 276 is made of one or more conductive materials, such as a single layer of TiN, TaN, TaAlC, TiC, TaC, Co, Al, TiAl, HfTi, TiSi, TaSi, or TiAlC, or a multilayer of two or more of these materials. The power function adjustment layer 276 may be formed by ALD, PVD, CVD, e-beam evaporation, or another suitable process.

[0117] Based on the foregoing description, and according to some embodiments, the semiconductor structure 200 has several advantages. In some embodiments, when the sacrificial layer 206 is selectively removed by etching to release the channel layer 208 ( Figure 3N When the internal spacer 240 has an internal dielectric segment 241 (which has a higher dielectric constant and greater rigidity than the intermediate dielectric portion 242), it prevents channel release damage, thereby improving the reliability of the semiconductor structure 200.

[0118] In some embodiments, the internal spacer 240 formed by the exemplary method described above has a trapezoidal cross-section, which prevents the formation of undesirable leakage paths between the gate structure 274 and the source / drain components 264, thereby promoting improved reliability of the semiconductor structure 200. Specifically, as Figure 3O As shown, one or each of the internal spacers 240 has a first surface 240S1 adjacent to the gate structure 274 and a second surface 240S2 adjacent to the source / drain component 264. The first surface 240S1 may contact the gate structure 274, and the second surface 240S2 may contact the source / drain component 264. In some embodiments, the first surface 240S1 has an internal dimension D. A And the second surface 240S2 has an outer dimension D B The internal dimension D of the internal spacer 240 A It can be substantially equal to or greater than the thickness Tg of the portion of the gate structure 274 located between two adjacent channel members 208. External dimension D B Larger than internal dimension D A Therefore, the junction of the inner dielectric segment 241 and the outer dielectric segment 243 (i.e., the top portion 240TE of the inner spacer 240 above the level of the top surface 206a of the channel layer 206 and the bottom portion 240BE of the inner spacer 240 below the level of the bottom surface 206b of the channel layer 206, as described above) further enhances the etch resistance of the inner spacer 240 in subsequent processes.

[0119] Furthermore, in some embodiments, the intermediate dielectric portion 242 comprises one or more low-k dielectric materials, and the dielectric constant of the intermediate dielectric portion 242 is less than the dielectric constant of the shell formed by the inner dielectric segment 241 and the outer dielectric segment 243. Additionally, the volume of the intermediate dielectric portion 242 is more than half the total volume of the inner spacer 240. Therefore, the inner spacer 240 of the embodiments has the advantage of reducing the parasitic capacitance between the source / drain components 264 subsequently formed in the source / drain trench 220 and the gate structure 274 subsequently formed by replacing the sacrificial layer 206.

[0120] Figure 4 It is based on energy dispersive X-ray spectroscopy (EDX) analysis of the relative concentrations of several atomic substances relative to the position of the internal spacers of the exemplary structure according to some embodiments.

[0121] Analysis shows the corresponding concentrations of oxygen [O], nitrogen [N], carbon [C], silicon [Si], titanium [Ti], aluminum [Al], and hafnium [Hf] relative to the positions of the inner dielectric segment 241, intermediate dielectric portion 242, and outer dielectric segment 243 of the inner spacer 240. As shown in the EDX analysis, the intermediate dielectric portion 242 is an oxygen-rich portion and can be considered as a porous film. The oxygen signal peak in the EDX distribution is located within the intermediate dielectric portion 242. As shown in the EDX analysis, each of the inner dielectric segment 241 and the outer dielectric segment 243 has a higher carbon concentration than the intermediate dielectric portion 242. Furthermore, the nitrogen concentration of the intermediate dielectric portion 242 is relatively lower than that of the inner dielectric portion 241 and the outer dielectric portion 243. According to some embodiments, the inner dielectric segment 241 and the outer dielectric segment 243 of the inner spacer can be referred to as hard films having one or more non-low-k dielectric materials, while the intermediate dielectric portion 242 can be referred to as a porous film having one or more low-k dielectric materials.

[0122] Figure 5A , Figure 5B and Figure 5C This is a partial cross-sectional view of a semiconductor structure at an intermediate stage after the formation of intermediate dielectric portions of internal spacers, according to some embodiments of the present disclosure.

[0123] Figure 5A yes Figure 3G A partially enlarged cross-sectional view of the intermediate dielectric portion 242. Figure 5A Zhongyu Figure 3G Parts / components that are completely identical are represented by the same reference numerals. Figure 5A Details and references regarding the arrangement, materials, and manufacturing methods of those similar or identical parts / assemblies shown. Figures 3A to 3G The points discussed are essentially the same and will not be repeated here.

[0124] In some embodiments, the intermediate dielectric portion 242 includes a side 242S1 that contacts the first dielectric material layer 2410 and a side 242S2 that is exposed and faces the source / drain trench 220. The side 242S2 is a flat surface and is substantially perpendicular to the extension direction of the channel layer 208 (e.g., the D1 direction). In some embodiments, the thickness of the intermediate dielectric portion 242 is at least twice that of the first dielectric material layer 2410, which will later be patterned to form... Figure 3I The internal dielectric segment 241 is located within the middle dielectric portion. The thickness of the intermediate dielectric portion 242 can be measured in the D1 direction from the distance between the sides 242S1 and 242S2. The thicker the intermediate dielectric portion 242, the greater the reduction in parasitic capacitance between the source / drain component 264 (which is subsequently formed in the source / drain trench 220) and the gate structure 274 (which is formed by replacing the sacrificial layer 206), such as... Figure 3O As shown in the image.

[0125] Figure 5B This illustrates an alternative embodiment of the intermediate dielectric portion 242'. Figure 5B Zhongyu Figure 5A Parts or components that are similar to or identical to each other are indicated by similar or identical reference numerals. Figure 5B Details and references regarding the arrangement, materials, and manufacturing methods of those similar or identical parts / assemblies shown. Figures 3A to 3G The points discussed are essentially the same and will not be repeated here.

[0126] In some embodiments, the intermediate dielectric portion 242' includes a side 242S1 that contacts the first dielectric material layer 2410 and a side 242S2' that is exposed and faces the source / drain trench 220. Figure 5A The intermediate dielectric portion 242 and Figure 5B The difference between the intermediate dielectric portions 242' in the middle is that, Figure 5B The side surface 242S2' is a concave side surface. The concave side surface 242S2' has a vertical dimension W2' extending between two adjacent channel layers 208. Figure 5B The vertical dimension W2' in the middle is greater than Figure 5A The vertical dimension W2 in the comparison. That is, when comparing... Figure 5A The intermediate dielectric portion 242 and Figure 5B In the intermediate dielectric portion 242' (both have the same thickness T2 along the virtual centerline in the D1 direction), the intermediate dielectric portion 242' with concave side 242S2' has a larger volume. This further reduces the parasitic capacitance between the source / drain component 264 (which is subsequently formed in the source / drain trench 220) and the gate structure 274 (which is formed by replacing the sacrificial layer 206).

[0127] Figure 5C This illustrates an alternative embodiment of the intermediate dielectric portion 242". Figure 5C Zhongyu Figure 5A Parts or components that are similar to or identical to each other are indicated by similar or identical reference numerals. Figure 5C Details and references regarding the arrangement, materials, and manufacturing methods of those similar or identical parts / assemblies shown. Figures 3A to 3G The points discussed are essentially the same and will not be repeated here.

[0128] In some embodiments, the intermediate dielectric portion 242" includes a side 242S1 that contacts the first dielectric material layer 2410 and a side 242S2 that is exposed and faces the source / drain trench 220". Figure 5A The intermediate dielectric portion 242 and Figure 5C The difference between the intermediate dielectric portion 242” and the other portion is that, Figure 5C Side 242S2” is a convex side. In this exemplary embodiment, Figure 5C The convex side 242S2” and Figure 5B The concave side 242S2' has the same vertical dimension W2' extending between two adjacent channel layers 208. When... Figure 5C The intermediate dielectric portion 242” in the middle and Figure 5A The intermediate dielectric portion 242 and Figure 5B When compared to the intermediate dielectric portion 242', it was observed that the intermediate dielectric portion 242" with convex side surface 242S2" has a larger volume. This further reduces the parasitic capacitance between the source / drain component 264 (which is subsequently formed in the source / drain trench 220) and the gate structure 274 (which is formed by replacing the sacrificial layer 206).

[0129] Figure 6A , Figure 6B and Figure 6C This is a partial cross-sectional view showing a semiconductor structure at an intermediate stage after the formation of internal spacers, according to some embodiments of the present disclosure.

[0130] Figure 6A yes Figure 3I Enlarged cross-sectional view of the internal spacer 240. Figure 6A Zhongyu Figure 3I Parts / components that are completely identical are represented by the same reference numerals. Figure 6A Details and references regarding the arrangement, materials, and manufacturing methods of those similar or identical parts / assemblies shown. Figures 3A to 3I The points discussed are essentially the same and will not be repeated here.

[0131] In some embodiments, each of the internal spacers 240 includes an internal dielectric segment 241, an intermediate dielectric portion 242, and an external dielectric segment 243. In some embodiments, the external dielectric segment 243 includes a side 243S1 that contacts the intermediate dielectric portion 242 and a side 243S2 that is exposed and faces the source / drain trench 220. Sides 243S1 and 243S2 are flat surfaces and are substantially perpendicular to the extension direction of the channel layer 208 (e.g., the D1 direction). In some embodiments, the thickness of the intermediate dielectric portion 242 is at least twice that of the internal dielectric segment 241 and at least twice that of the external dielectric segment 243. The thicker the intermediate dielectric portion 242, the greater the reduction in parasitic capacitance between the source / drain component 264 (which is subsequently formed in the source / drain trench 220) and the gate structure 274 (which is formed by replacing the sacrificial layer 206), such as Figure 3O As shown in the diagram. Furthermore, the thicker the external dielectric segment 243, the greater the resistance to damage from the source / drain etching process.

[0132] Figure 6B This is an alternative embodiment showing the internal spacer 240'. Figure 6B Zhongyu Figure 6A Parts / components that are completely identical are represented by the same reference numerals. Figure 6B Details and references regarding the arrangement, materials, and manufacturing methods of those similar or identical parts / assemblies shown. Figures 3A to 3I The points discussed are essentially the same and will not be repeated here.

[0133] In some embodiments, each of the internal spacers 240' includes an internal dielectric segment 241, an intermediate dielectric portion 242', and an external dielectric segment 243'. In some embodiments, the external dielectric segment 243' includes a side surface 243S1' that contacts the intermediate dielectric portion 242' and a side surface 243S2 that is exposed and faces the source / drain trench 220. Side surface 243S1' is a convex surface, and side surface 243S2 is a flat surface. Figure 6B As shown, the outer dielectric segment 243' has a thicker middle section with improved resistance to prevent damage from the source / drain etching process.

[0134] Figure 6C This is an optional embodiment showing the internal spacer 240". Figure 6C Zhongyu Figure 6A Parts / components that are completely identical are represented by the same reference numerals. Figure 6C Details and references regarding the arrangement, materials, and manufacturing methods of those similar or identical parts / assemblies shown. Figures 3A to 3I The points discussed are essentially the same and will not be repeated here.

[0135] In some embodiments, each of the internal spacers 240” includes an internal dielectric segment 241, an intermediate dielectric portion 242”, and an external dielectric segment 243”. In some embodiments, the external dielectric segment 243” includes a side 243S1” that contacts the intermediate dielectric portion 242” and a side 243S2 that is exposed and faces the source / drain trench 220. Side 243S1” is a concave surface, and side 243S2 is a flat surface. Figure 6C As shown, the outer dielectric segment 243” has a thicker end, creating a thicker junction between the inner dielectric segment 241 and the outer dielectric segment 243”, such as the top portion 240”TE and the bottom portion 240”BE of the inner spacer 240” as described above. In some embodiments, the top portion 240”TE of the inner spacer 240” is positioned above the level of the top surface 206a of the channel layer 206, and the bottom portion 240”BE of the inner spacer 240” is positioned below the level of the bottom surface 206b of the channel layer 206, thereby improving resistance to prevent damage from the source / drain etching process. Furthermore, the top portion 240”TE and the bottom portion 240”BE of the inner spacer 240” also prevent the formation of undesirable seams extending to the source / drain components during the channel release process and the formation of leakage paths between the metal gate and the source / drain components after the deposition of the gate structure (e.g., including a metal gate) to enclose the channel layer.

[0136] In implementation, based on process conditions such as source / drain etching processes and channel release etching processes, a suitable method for configuring the internal spacers can be selected from the exemplary embodiments provided above.

[0137] While not intended to be limiting, one or more embodiments of this disclosure provide numerous benefits for semiconductor structures and their formation. For example, embodiments of this disclosure provide internal spacers interleaved with channel members, and one of the internal spacers includes an intermediate dielectric portion and a shielding dielectric portion covering the surface of the intermediate dielectric portion. The shielding dielectric portion includes an internal dielectric segment and an external dielectric segment connecting the two ends of the internal dielectric segment. Furthermore, the dielectric constant of the shielding dielectric portion is greater than that of the intermediate dielectric portion. Therefore, the external dielectric segment with a larger dielectric constant effectively prevents damage from source / drain etching processes. The internal dielectric segment with a larger dielectric constant effectively prevents damage from channel release etching processes. Thus, the reliability and electrical performance of the semiconductor structure of the embodiments are greatly improved.

[0138] In one exemplary aspect, embodiments of this disclosure relate to a semiconductor structure. The semiconductor structure includes: a channel member disposed on a substrate; a gate structure enclosing the channel member; an internal spacer adjacent to the gate structure; source / drain members adjacent to the channel member; a contact etch stop layer located above the source / drain members; and an interlayer dielectric layer located above the CESL. One of the internal spacers includes an intermediate dielectric portion and a shielding dielectric portion covering a surface of the intermediate dielectric portion. The dielectric constant of the shielding dielectric portion is greater than the dielectric constant of the intermediate dielectric portion. The dielectric constant of the CESL is greater than the dielectric constant of the ILD layer.

[0139] In some embodiments, the thickness of the intermediate dielectric portion is greater than the thickness of the shielding dielectric portion along the longitudinal direction of the channel member. In some embodiments, the intermediate dielectric portion and the channel member are separated by the shielding dielectric portion. In some embodiments, the oxygen concentration of the intermediate dielectric portion is greater than the oxygen concentration of the shielding dielectric portion. In some embodiments, the combination of carbon and nitrogen concentrations in the intermediate dielectric portion is less than the combination of carbon and nitrogen concentrations in the shielding dielectric portion. In some embodiments, the shielding dielectric portion includes an inner dielectric segment and an outer dielectric segment. The inner dielectric segment covers the top, inner, and bottom surfaces of the intermediate dielectric portion. The inner surface is positioned adjacent to the gate structure. The outer dielectric segment connects to the inner dielectric segment and covers the outer surface of the intermediate dielectric portion. In some embodiments, each of the inner and outer dielectric segments has higher etch resistance than the intermediate dielectric portion. In some embodiments, the gate structure includes a gate dielectric layer and a metal gate electrode located on the gate dielectric layer. The dielectric constant of the inner dielectric segment is less than the dielectric constant of the gate dielectric layer, and the dielectric constant of the outer dielectric segment is less than the dielectric constant of the gate dielectric layer. In some embodiments, the inner dielectric segment covers the top and bottom surfaces of the outer dielectric segment.

[0140] In another exemplary aspect, embodiments of this disclosure relate to a method. The method includes: alternately stacking channel layers and sacrificial layers on a substrate in a vertical direction to form a semiconductor stack; patterning the semiconductor stack to form a fin structure protruding from the substrate; forming source / drain trenches in the fin structure; laterally recessing the sacrificial layers in the fin structure to form grooves; forming internal spacers in the grooves; forming source / drain components in the source / drain trenches; forming a contact etch stop layer over the source / drain components; and forming an interlayer dielectric (ILD) layer over the CESL. The grooves located at opposite ends of one of the sacrificial layers are spaced apart from each other in the direction. The thickness of the CESL in the direction is less than the thickness of the ILD layer. One of the internal spacers includes an intermediate dielectric portion and a shielding dielectric portion covering a surface of the intermediate dielectric portion, and the dielectric constant of the shielding dielectric portion is greater than the dielectric constant of the intermediate dielectric portion.

[0141] In some embodiments, forming one of the internal spacers includes: forming an internal dielectric segment on a sidewall of one of the recesses; forming an intermediate dielectric portion on the internal dielectric segment of one of the recesses; and forming an external dielectric segment on the intermediate dielectric portion of one of the recesses.

[0142] In some embodiments, forming an internal spacer includes: conformally depositing a first dielectric material layer on the exposed sidewalls of a channel layer in a source / drain trench and on the sidewalls of a recess, wherein the first dielectric material layer defines a first cavity in one of the recesses; conformally depositing a second dielectric material layer on the first dielectric material layer and recessing the second dielectric material layer in the first cavity; and removing a portion of the second dielectric material layer, wherein the remaining portion of the second dielectric material layer in the recess forms an intermediate dielectric portion. In some embodiments, the dielectric constant of the first dielectric material layer is greater than the dielectric constant of the second dielectric material. In some embodiments, after forming the intermediate dielectric portion, the remaining spacer in one of the recesses is referred to as a second cavity, and forming the internal spacer further includes: conformally depositing a third dielectric material layer on the first dielectric material layer and the intermediate dielectric portion, wherein the third dielectric material layer fills the second cavity. In some embodiments, the method further includes: removing a portion of the third dielectric material layer and a portion of the first dielectric material layer, wherein the remaining portion of the first dielectric material forms an internal dielectric segment in the recess, and the remaining portion of the third dielectric material forms an external dielectric segment in the recess. In some embodiments, the oxygen concentration of the intermediate dielectric portion is greater than the oxygen concentration of the shielding dielectric portion.

[0143] In another exemplary aspect, embodiments of this disclosure relate to a method. The method includes: forming a fin structure including a stack on top of a substrate. The stack includes a channel layer interleaved with a sacrificial layer. A substrate protrudes from a substrate. The fin structure includes a channel region and a source / drain region. The method further includes: forming a dummy gate stack over the channel region of the fin structure; depositing a gate spacer layer over the dummy gate stack; forming a source / drain trench by recessing the source / drain regions of the fin structure; forming a contact etch stop layer over the source / drain components; and forming an interlayer dielectric (ILD) layer over the CESL. The source / drain components are partially embedded in the substrate and beneath the ILD layer. The source / drain trench exposes the sidewalls of the channel layer and the sacrificial layer. The method further includes: selectively and partially recessing the sacrificial layer in the fin structure to form a trench; forming an internal spacer in the trench; and forming source / drain components in the source / drain trench. One of the internal spacers includes a shielding layer covering the surface of an intermediate layer. The dielectric constant of the shielding layer is greater than that of the intermediate layer.

[0144] In some embodiments, a shielding layer separates the intermediate layer of the internal spacers from the source / drain components. In some embodiments, the method further includes: removing dummy gate stacks to release the channel layer; selectively removing the sacrificial layer; and forming a gate structure that encloses the channel layer. The dielectric constant of the gate dielectric layer of the gate structure is greater than the dielectric constant of the shielding layer. In some embodiments, the shielding layer separates the intermediate layer of the internal spacers from the gate dielectric layer of the gate structure.

[0145] Some embodiments of this application provide a semiconductor structure including: a channel member disposed on a substrate; a gate structure enclosing the channel member; internal spacers adjacent to the gate structure, wherein one of the internal spacers includes an intermediate dielectric portion and a shielding dielectric portion covering a surface of the intermediate dielectric portion, and the dielectric constant of the shielding dielectric portion is greater than the dielectric constant of the intermediate dielectric portion; a source / drain member adjacent to the channel member; a contact etch stop layer (CESL) located above the source / drain member; and an interlayer dielectric (ILD) layer located above the contact etch stop layer, wherein the dielectric constant of the contact etch stop layer is greater than the dielectric constant of the interlayer dielectric layer.

[0146] In some embodiments, the thickness of the intermediate dielectric portion is greater than the thickness of the shielding dielectric portion along the longitudinal direction of the channel member. In some embodiments, the intermediate dielectric portion and the channel member are separated by the shielding dielectric portion. In some embodiments, the oxygen concentration of the intermediate dielectric portion is greater than the oxygen concentration of the shielding dielectric portion. In some embodiments, the combination of carbon and nitrogen concentrations of the intermediate dielectric portion is less than the combination of carbon and nitrogen concentrations of the shielding dielectric portion. In some embodiments, the shielding dielectric portion includes: an inner dielectric segment covering a top surface, an inner surface, and a bottom surface of the intermediate dielectric portion, wherein the inner surface is positioned adjacent to the gate structure; and an outer dielectric segment connecting the inner dielectric segment and covering an outer surface of the intermediate dielectric portion. In some embodiments, each of the inner dielectric segment and the outer dielectric segment has higher etch resistance than the intermediate dielectric portion. In some embodiments, the gate structure includes a gate dielectric layer and a metal gate electrode located on the gate dielectric layer, wherein the dielectric constant of the inner dielectric segment is less than the dielectric constant of the gate dielectric layer, and the dielectric constant of the outer dielectric segment is less than the dielectric constant of the gate dielectric layer. In some embodiments, the inner dielectric segment covers the top and bottom surfaces of the outer dielectric segment.

[0147] Other embodiments of this application provide a method for forming a semiconductor structure, comprising: alternately stacking channel layers and sacrificial layers on a substrate to form a semiconductor stack; patterning the semiconductor stack to form a fin structure protruding from the substrate; forming source / drain trenches in the fin structure; laterally recessing the sacrificial layers in the fin structure to form grooves, wherein the grooves located at opposite ends of one of the sacrificial layers are spaced apart from each other along a direction; forming internal spacers in the grooves, wherein one of the internal spacers includes an intermediate dielectric portion and a shielding dielectric portion covering a surface of the intermediate dielectric portion, and the dielectric constant of the shielding dielectric portion is greater than the dielectric constant of the intermediate dielectric portion; forming source / drain components in the source / drain trenches; forming a contact etch stop layer over the source / drain components; and forming an interlayer dielectric (ILD) layer over the contact etch stop layer, wherein the thickness of the contact etch stop layer along the direction is less than the thickness of the interlayer dielectric layer.

[0148] In some embodiments, forming one of the internal spacers includes: forming an internal dielectric segment on a sidewall of one of the recesses; forming an intermediate dielectric portion on the internal dielectric segment in one of the recesses; and forming an external dielectric segment on the intermediate dielectric portion in one of the recesses, wherein the internal dielectric segment and the external dielectric segment form the shielding dielectric portion. In some embodiments, forming the internal spacer includes: conformally depositing a first dielectric material layer on the exposed sidewall of the channel layer in the source / drain trench and on the sidewall of the recess, wherein the first dielectric material layer defines a first cavity in the recess; conformally depositing a second dielectric material layer on the first dielectric material layer, wherein the second dielectric material layer is recessed in the first cavity; and removing a portion of the second dielectric material layer, wherein the remaining portion of the second dielectric material layer in the recess forms the intermediate dielectric portion. In some embodiments, the dielectric constant of the first dielectric material layer is greater than the dielectric constant of the second dielectric material layer. In some embodiments, after forming the intermediate dielectric portion, the remaining spacer in one of the grooves is referred to as a second cavity, and forming the internal spacer further includes conformally depositing a third dielectric material layer on the first dielectric material layer and the intermediate dielectric portion, wherein the third dielectric material layer fills the second cavity. In some embodiments, the method further includes removing portions of the third dielectric material layer and the first dielectric material layer to expose the sidewalls of the channel layer, wherein the remaining portion of the first dielectric material forms an internal dielectric segment in the groove, and the remaining portion of the third dielectric material forms an external dielectric segment in the groove. In some embodiments, the oxygen concentration of the intermediate dielectric portion is greater than the oxygen concentration of the shielding dielectric portion.

[0149] Some embodiments of this application provide a method for forming a semiconductor structure, comprising: forming a fin structure including a stack on top of a substrate, the stack including a channel layer interleaved with a sacrificial layer, the substrate protruding from a substrate, the fin structure including a channel region and a source / drain region; forming a dummy gate stack over the channel region of the fin structure; depositing a gate spacer layer over the dummy gate stack; and forming a source / drain trench by recessing the source / drain region of the fin structure, wherein the source / drain trench exposes the channel layer and the sacrificial layer. Sidewalls; selectively and partially recessing the sacrificial layer in the fin structure to form a groove; forming internal spacers in the groove, wherein one of the internal spacers includes a shielding layer covering the surface of the intermediate layer, and the dielectric constant of the shielding layer is greater than the dielectric constant of the intermediate layer; forming source / drain components in the source / drain trench; forming a contact etch stop layer above the source / drain components; and forming an interlayer dielectric (ILD) layer above the contact etch stop layer, wherein the source / drain components are partially embedded in the substrate and below the interlayer dielectric layer.

[0150] In some embodiments, the shielding layer separates the intermediate layer of the internal spacer from the source / drain components. In some embodiments, the method further includes: removing the dummy gate stack to release the channel layer; selectively removing the sacrificial layer; and forming a gate structure enclosing the channel layer, wherein the dielectric constant of the gate dielectric layer of the gate structure is greater than the dielectric constant of the shielding layer. In some embodiments, after forming the gate structure, the shielding layer separates the intermediate layer of the internal spacer from the gate dielectric layer of the gate structure.

[0151] The foregoing outlines features of several embodiments to enable those skilled in the art to better understand various aspects of the embodiments of this disclosure. Those skilled in the art should understand that they can readily use the embodiments of this disclosure as a base to design or modify other processes and structures for performing the same purposes and / or achieving the same advantages as the embodiments described herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of the embodiments of this disclosure, and that various changes, substitutions, and modifications can be made to them herein without departing from the spirit and scope of the embodiments of this disclosure.

Claims

1. A semiconductor structure, comprising: The channel component is disposed on the substrate; Gate structure, enclosing the channel component; An internal spacer, adjacent to the gate structure, wherein one of the internal spacers includes an intermediate dielectric portion and a shielding dielectric portion covering the surface of the intermediate dielectric portion, and the dielectric constant of the shielding dielectric portion is greater than the dielectric constant of the intermediate dielectric portion; Source / drain components are adjacent to the channel components; A contact etch stop layer is located above the source / drain components; and An interlayer dielectric layer is located above the contact etch stop layer, wherein the dielectric constant of the contact etch stop layer is greater than the dielectric constant of the interlayer dielectric layer.

2. The semiconductor structure according to claim 1, wherein, Along the longitudinal direction of the channel member, the thickness of the intermediate dielectric portion is greater than the thickness of the shielding dielectric portion.

3. The semiconductor structure according to claim 1, wherein, The intermediate dielectric portion and the channel component are separated by the shielding dielectric portion.

4. The semiconductor structure according to claim 1, wherein, The oxygen concentration in the intermediate dielectric portion is greater than the oxygen concentration in the shielding dielectric portion.

5. The semiconductor structure according to claim 1, wherein, The combined carbon and nitrogen concentrations of the intermediate dielectric portion are less than the combined carbon and nitrogen concentrations of the shielding dielectric portion.

6. The semiconductor structure according to claim 1, wherein, The shielding dielectric portion includes: An internal dielectric segment covering the top, inner, and bottom surfaces of the intermediate dielectric portion, wherein the inner surface is positioned adjacent to the gate structure; and An external dielectric segment connects to the internal dielectric segment and covers the outer surface of the intermediate dielectric portion.

7. The semiconductor structure according to claim 6, wherein, The inner dielectric segment and the outer dielectric segment each have higher etch resistance than the intermediate dielectric portion.

8. The semiconductor structure according to claim 6, wherein, The gate structure includes a gate dielectric layer and a metal gate electrode located on the gate dielectric layer. The dielectric constant of the inner dielectric segment is less than the dielectric constant of the gate dielectric layer, and the dielectric constant of the outer dielectric segment is less than the dielectric constant of the gate dielectric layer.

9. A method for forming a semiconductor structure, comprising: Alternating stacking of channel layers and sacrificial layers on a substrate to form a semiconductor stack; The semiconductor stack is patterned to form a fin-shaped structure protruding from the substrate; Source / drain trenches are formed in the fin-shaped structure; The sacrificial layer in the fin structure is laterally recessed to form a groove, wherein the grooves located at opposite ends of one of the sacrificial layers are spaced apart from each other along the direction; An internal spacer is formed in the groove, wherein one of the internal spacers includes an intermediate dielectric portion and a shielding dielectric portion covering the surface of the intermediate dielectric portion, and the dielectric constant of the shielding dielectric portion is greater than the dielectric constant of the intermediate dielectric portion. Source / drain components are formed in the source / drain trench; A contact etch stop layer is formed above the source / drain components; and An interlayer dielectric layer is formed above the contact etch stop layer. Wherein, the thickness of the contact etch stop layer along the direction is less than the thickness of the interlayer dielectric layer.

10. A method for forming a semiconductor structure, comprising: A fin structure is formed including a stack on top of a substrate, the stack including a channel layer interleaved with a sacrificial layer, the substrate protruding from the substrate, and the fin structure including a channel region and a source / drain region; A dummy gate stack is formed above the channel region of the fin-shaped structure; A gate spacer layer is deposited over the dummy gate stack; Source / drain trenches are formed by recessing the source / drain regions of the fin structure, wherein the source / drain trenches expose the sidewalls of the channel layer and the sacrificial layer; The sacrificial layer in the fin structure is selectively and partially recessed to form a groove; An internal spacer is formed in the groove, wherein one of the internal spacers includes a shielding layer covering the surface of the intermediate layer, and the dielectric constant of the shielding layer is greater than the dielectric constant of the intermediate layer; Source / drain components are formed in the source / drain trench; A contact etch stop layer is formed above the source / drain components; and An interlayer dielectric layer is formed above the contact etch stop layer. The source / drain components are partially embedded in the substrate and beneath the interlayer dielectric layer.

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