LDMOS and forming method thereof

Abstract

The invention discloses an LDMOS and a forming method thereof, and the method comprises the steps: providing a substrate which is internally provided with a drift region; forming a gate structure on the drift region; and performing ion implantation processing on the drift region on one side of the gate structure at a preset implantation angle to form a body region. After a gate structure is formed on a drift region in a substrate, in the process of performing ion implantation on the drift region on one side of the gate structure to form a body region, ion implantation processing is performed at a preset implantation angle, so that the stability of a formed LDMOS channel can be effectively improved, and the variation range of threshold voltage of the formed LDMOS can be effectively reduced.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing, and in particular to an LDMOS and a method for forming the same. Background Technology

[0002] There are two main types of DMOS transistors: vertical double-diffused MOS (VDMOS) and lateral double-diffused MOS (LDMOS). Among them, LDMOS is widely used in the industry because it is easier to be compatible with complementary metal-oxide-semiconductor (CMOS) processes.

[0003] With the rapid expansion of the analog power IC market, reducing the cost and power consumption of IC products is becoming increasingly important, especially for widely used low-voltage (5V to 30V) NLDMOS. The channel of an NLDMOS is formed by the diffusion bandgap between different types of doped regions, making its threshold voltage Vt susceptible to various factors. Gate size, gate oxide thickness, and implantation process can all cause fluctuations in the NLDMOS threshold voltage, and these variations are difficult to control during the manufacturing process.

[0004] Therefore, how to reduce the fluctuation of the LDMOS threshold voltage and ensure its stability is an urgent problem to be solved. Summary of the Invention

[0005] The problem addressed by this invention is how to reduce the fluctuation of the LDMOS threshold voltage and ensure its stability.

[0006] To address the above problems, the present invention provides a method for forming an LDMOS, comprising:

[0007] A substrate is provided, which has a drift region; a gate structure is formed on the drift region; and ion implantation is performed on the drift region on one side of the gate structure at a preset implantation angle to form a body region.

[0008] Optionally, the injection angle is greater than 0° and less than 15°.

[0009] Optionally, the step of performing ion implantation on the drift region on one side of the gate structure at a preset implantation angle to form a body region includes: performing a first ion implantation with a first energy to form a first doped region in the drift region on one side of the gate structure; performing a second ion implantation with a second energy to form a second doped region in the drift region on one side of the gate structure, wherein the second energy is less than the first energy; wherein, in at least one of the steps of performing the first ion implantation with the first energy and performing the second ion implantation with the second energy, the ion implantation is performed at a preset implantation angle.

[0010] Optionally, the step of performing the first ion implantation with a first energy includes: forming a first mask that exposes the source region location between adjacent gate structures; and performing the first ion implantation on the source region location exposed by the first mask with a first energy.

[0011] Optionally, in the step of forming the first mask, the thickness of the first mask is... to Within the range.

[0012] Optionally, in the step of forming the first mask, the first mask at least covers the top surface of the gate structure.

[0013] Optionally, in the step of forming the first mask, the first mask also covers the sidewall surface of the gate structure.

[0014] Optionally, the step of performing ion implantation on the drift region on one side of the gate structure at a preset implantation angle to form a body region further includes: removing the first mask after performing a first ion implantation on the source region exposed by the first mask with a first energy and before performing a second ion implantation with a second energy.

[0015] Optionally, the step of performing a second ion implantation with a second energy includes: forming a second mask, the second mask exposing at least one drift region on one side of the gate structure; and performing a second ion implantation on the drift region exposed by the second mask with a second energy.

[0016] Optionally, in the step of forming the second mask, the thickness of the second mask is... to Within the range.

[0017] Optionally, in the step of forming the second mask, the second mask also exposes at least a portion of the gate structure.

[0018] Optionally, at least one of the first and second masks may be made of photoresist.

[0019] Optionally, in the step of forming a gate structure on the drift region, at least two discrete gate structures are formed on the drift region; in the step of performing ion implantation on the drift region on one side of the gate structure at a preset implantation angle to form a body region, the drift region between two adjacent gate structures is subjected to ion implantation at a preset implantation angle to form a body region.

[0020] Optionally, in the step of providing the substrate, the drift region is an N-type doped region; in the step of performing ion implantation treatment on the drift region on one side of the gate structure at a preset implantation angle to form a body region, the body region is a P-type doped region.

[0021] Accordingly, the present invention also provides an LDMOS, which is formed by the formation method of the present invention.

[0022] Compared with the prior art, the technical solution of the present invention has the following advantages:

[0023] In the technical solution of the present invention, after forming a gate structure on the drift region in the substrate, ion implantation is performed on the drift region on one side of the gate structure to form a body region. Ion implantation is performed at a preset implantation angle, which can effectively improve the stability of the formed LDMOS channel and effectively reduce the variation of the threshold voltage of the formed LDMOS.

[0024] In an optional embodiment of the present invention, in the step of performing the first ion implantation with a first energy, the thickness of the first mask formed is... to Within the range; in the step of performing the second ion implantation with the second energy, the thickness of the second mask formed is within to Within the range. The thickness of the first mask and the second mask are relatively small, and the depth-to-width ratio is small, which can effectively increase the doping concentration of the bulk region formed by ion implantation, and is beneficial to further improve the stability of the threshold voltage of the formed LDMOS. Attached Figure Description

[0025] Figures 1 to 6 This is a cross-sectional structural schematic diagram of each step in an embodiment of the LDMOS formation method of the present invention;

[0026] Figure 7 This describes the threshold voltage deviation of the LDMOS formed in an embodiment of the LDMOS formation method of the present invention. Detailed Implementation

[0027] As can be seen from the background technology, the LDMOS formed by the existing technology has the problems of poor threshold voltage stability and large fluctuation.

[0028] To solve the technical problem, the present invention provides a method for forming an LDMOS, comprising:

[0029] A substrate is provided, which has a drift region; a gate structure is formed on the drift region; and ion implantation is performed on the drift region on one side of the gate structure at a preset implantation angle to form a body region.

[0030] The present invention provides a method for forming a body region by performing ion implantation in the drift region on one side of the gate structure after forming a gate structure in the drift region of the substrate. The ion implantation is performed at a preset implantation angle, which can effectively improve the stability of the formed LDMOS channel and effectively reduce the variation of the threshold voltage of the formed LDMOS.

[0031] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0032] refer to Figures 1 to 6 The diagram shows a cross-sectional view of each step in an embodiment of the LDMOS formation method of the present invention.

[0033] The method for forming an LDMOS includes: providing a substrate 110, the substrate 110 having a drift region 101; forming a gate structure 110 on the drift region 101; and performing ion implantation on the drift region 101 on one side of the gate structure 101 at a preset implantation angle to form a body region 130.

[0034] The technical solution of the LDMOS formation method embodiment of the present invention will be described in detail below with reference to the accompanying drawings.

[0035] like Figure 1 As shown, a substrate 110 is provided first.

[0036] Substrate 110 is used to provide a process operation surface and mechanical support.

[0037] Specifically, substrate 110 is a silicon substrate, and the material of substrate 110 is silicon. For example, the material of substrate 110 may be selected from monocrystalline silicon, polycrystalline silicon, or amorphous silicon. In other embodiments, the material of the substrate may also be selected from silicon, germanium, gallium arsenide, or silicon-germanium compounds; the substrate may also be selected from materials having an epitaxial layer or a silicon-on-epitaxy layer structure; the substrate may also be other semiconductor materials.

[0038] The substrate 110 has a drift region 111. The drift region 111 is used to withstand a large voltage drop to improve the breakdown voltage performance of the formed LDMOS.

[0039] In some embodiments of the present invention, the drift region 111 is an N-type doped region, that is, the drift region 111 contains N-type impurities. For example, the impurity in the drift region 111 is P, and the doping concentration is 1E12 atom / cm³. 3 Up to 1E18atom / cm 3 Within the range.

[0040] It should be noted that, as Figure 1 In some embodiments shown, the substrate 110 has an isolation structure 112, and the drift region 111 is located between two adjacent isolation structures 112.

[0041] Continue to refer to Figure 1 After providing the substrate 110, a gate structure 120 is formed on the drift region 111.

[0042] The gate structure 120 is used to control the on and off states of the formed LDMOS channel.

[0043] Specifically, the gate structure 120 is a polysilicon gate structure. For example, the gate structure 120 includes a gate electrode, a gate dielectric located between the gate electrode and the substrate 110, and a sidewall located on the sidewall of the gate electrode, wherein the gate electrode is polysilicon. In other embodiments of the present invention, the gate structure may also be a metal gate structure; the gate electrode of the gate structure is a metal material.

[0044] In some embodiments, at least two discrete gate structures 120 are formed on the drift region 111, with the surface of the drift region 111 exposed between adjacent gate structures 120. For example, ... Figure 2 As shown, two gate structures 120 are formed on the drift region 111; the two gate structures 120 are spaced apart to expose the drift region 111.

[0045] refer to Figures 2 to 5 Ion implantation is performed on the drift region 111 between adjacent gate structures 120 at a preset implantation angle to form a body region 130.

[0046] Body region 130 is used to form the source region of the formed LDMOS.

[0047] Ion implantation is performed at a preset implantation angle to form a body region 130, which enables the formed body region 130 (such as...) Figure 5 As shown, the doping concentration distribution gradient in the formed LDMOS channel region is appropriately diffused downwards from the gate structure 120, thereby effectively reducing the doping uniformity and improving the stability of the formed LDMOS channel, and effectively reducing the variation of the threshold voltage of the formed LDMOS. Here, ion implantation at a preset implantation angle means that the angle between the beam injection direction and the normal to the surface of the substrate 110 is the preset implantation angle during the ion implantation process.

[0048] In some embodiments of the present invention, the injection angle is greater than 0° and less than 15°. By obliquely incident the doped ions to achieve ion implantation, the doping concentration distribution gradient in the LDMOS channel region can be effectively reduced. Furthermore, with an appropriate injection angle, the diffusion degree of the formed body region 130 downwards towards the gate structure 120 is suitable, effectively controlling and ensuring the maintenance of the diffusion bandgap between the formed body region 130 and the drift region 111, thus effectively ensuring the formation of the LDMOS channel. For example, the injection angle can be 5°, 8°, 10°, or 12°.

[0049] In some embodiments of the present invention, in the step of performing ion implantation on the drift region 111 on one side of the gate structure 120 at a preset implantation angle to form the body region 130, the body region 130 is a P-type doped region, that is, the body region 130 contains P-type impurities. For example, the impurity in the body region 130 is B, and the doping concentration is 1E15 atom / cm³. 3 Within the range.

[0050] In some embodiments of the present invention, the step of performing ion implantation on the drift region 111 on one side of the gate structure 120 at a preset implantation angle to form the body region 130 includes: as follows Figure 2 and Figure 3 A first ion implantation is performed using a first energy to form a first doped region 131 (e.g., ...) within the drift region 11 on one side of the gate structure 120. Figure 3 (as shown); as Figure 4 and Figure 5 As shown, a second ion implantation is performed with a second energy to form a second doped region 132 in the drift region 111 on one side of the gate structure 120. The second energy is less than the first energy. In at least one of the steps of performing the first ion implantation with the first energy and performing the second ion implantation with the second energy, ion implantation is performed at a preset implantation angle.

[0051] The first doped region 131 and the second doped region 132 cooperate to form the bulk region 130. The second energy is lower than the first energy, therefore the depth of the first doped region 131 is greater than that of the second doped region 132.

[0052] In some embodiments, the step of performing the first ion implantation at a first energy includes: as follows Figure 2 As shown, a first mask 131p is formed, and the first mask 131p exposes the source region position D on one side of the gate structure 120; a first ion implantation is performed on the source region position exposed by the first mask with a first energy.

[0053] The first mask layer 131p is suitable for defining the scope of the first ion implantation.

[0054] In some specific embodiments, during the step of forming the first mask 131p, the thickness of the first mask 131p is within... to Within the range. Since the first ion implantation has an implantation angle greater than 0°, that is, during the first ion implantation process, the beam is incident obliquely onto the surface of the substrate 110; therefore, reducing the thickness of the first mask 131p can reduce the aspect ratio of the opening 131O exposed at the source region position D, which can effectively ensure that impurities are implanted into the substrate 110, so as to ensure the doping concentration of the formed first doped region 131.

[0055] In some specific embodiments, the material of the first mask 131p is photoresist. Specifically, the steps of forming the first mask 131p include: forming a photoresist layer (not shown in the figure) on the substrate 110; and exposing and developing the photoresist layer to expose the source region location D.

[0056] In some exemplary embodiments, during the step of forming the first mask 131p, the first mask 131p at least covers the top surface of the gate structure 120. A first doped region 131 is located on one side of the gate structure 120, and in a direction parallel to the surface of the substrate 110, the first doped region 131 is separated from the gate structure 120. During the step of forming the first mask 131p, the first mask 131p also covers the sidewall surface of the gate structure 120.

[0057] In some examples, the process parameters for the first ion implantation include: an implantation energy in the range of 200 keV to 500 keV, and an implantation dose in the range of 1E12 atom / cm². 3 Up to 1E18 atom / cm 3 Within the range.

[0058] like Figure 2 and Figure 3 In some embodiments shown, at least two gate structures 120 are formed on the drift region 111; in the step of performing the first ion implantation with the first energy, the drift region 111 between adjacent gate structures 120 is subjected to the first ion implantation to form a first doped region 131 (e.g., Figure 3 As shown); in the step of forming the first mask 131p, an opening 131O is formed in the first mask 131p, and the bottom of the opening 131O exposes the source region position D.

[0059] Furthermore, in the direction of the connection between the two gate structures 120, the first doped region 131 is separated from both gate structures 120 on both sides. Therefore, in the direction of the connection between the two gate structures 120, the size of the opening 131O is smaller than the size between two adjacent gate structures 120. For example, in the step of forming the first mask 131p, the first mask 131p also covers the opposing sidewall surfaces of the two adjacent gate structures 120.

[0060] Furthermore, in some embodiments, at least two gate structures 120 are formed on the drift region 111, and the first mask 131p exposes the drift region between two adjacent gate structures 120, thus... Figure 2 and Figure 3 As shown, in the step of forming a first doped region 131 in the drift region 11 on one side of the gate structure 120 by performing a first ion implantation with a first energy, two implantations are performed on the two adjacent gate structures 120 respectively with the first energy, and both implantations are performed at an implantation angle θ1, but the tilting directions of the two implantation operations are opposite.

[0061] For example, the step of performing a first ion implantation with a first energy to form a first doped region 131 in a drift region 11 on one side of the gate structure 120 includes: Figure 2 As shown, a first implantation is performed, with the first implantation directed towards the area below the gate structure 120 on one side. The first implantation is performed at an implantation angle θ1. During the first implantation, the angle between the beam and the normal to the surface of the substrate 110 is θ1, thereby forming a doped region 131a near the gate structure 120 on one side; as Figure 3 As shown, a second implantation is performed, which is directed towards the lower side of the gate structure 120 on the other side. The second implantation is also performed at an implantation angle θ1. During the second implantation, the angle between the beam and the normal of the substrate 110 surface is also θ1, thereby forming a first doped region 131 located between adjacent gate structures 120.

[0062] In some embodiments, the step of performing a second ion implantation at a second energy includes: as Figure 4 As shown, a second mask 132p is formed, and the second mask 132p exposes at least one drift region 111 on one side of the gate structure 120; as Figure 5 As shown, a second ion implantation is performed on the drift region 111 exposed by the second mask 132p using a second energy.

[0063] It should be noted that in some embodiments, ion implantation is performed on the drift region 111 on one side of the gate structure 120 at a preset implantation angle to form the body region 130 (e.g., Figure 5 The steps (shown) further include: removing the first mask 131p after performing the first ion implantation with the first energy and before performing the second ion implantation with the second energy.

[0064] The second mask layer 132p is suitable for defining the range of the second ion implantation.

[0065] In some specific embodiments, during the step of forming the second mask 132p, the thickness of the second mask 132p is within... to Within the range. Since the second ion implantation has an implantation angle greater than 0°, that is, during the second ion implantation process, the beam is incident obliquely onto the surface of the substrate 110; therefore, reducing the thickness of the second mask 132p can effectively ensure that impurities are implanted into the substrate 110, so as to ensure the doping concentration of the formed second doped region 132.

[0066] In some specific embodiments, the material of the second mask is photoresist. Specifically, the step of forming the second mask 132p includes: forming a photoresist layer (not shown in the figure) on the substrate 110; and exposing and developing the photoresist layer to expose the drift region 111 on one side of the gate structure 120.

[0067] In some examples, in the step of forming the second mask 132p, the second mask 132p covers the gate structure 120, the second doped region 132 is located on one side of the gate structure 120, and in the direction parallel to the surface of the substrate 110, the second doped region 132 is adjacent to the gate structure 120. In the step of forming the second mask 132p, the second mask 132p covers a portion of the gate structure 120 and also exposes a portion of the gate structure 120.

[0068] The second energy is less than the first energy, therefore, as Figure 4 and Figure 5 As shown, the depth of the second doped region 132 formed by the second ion implantation is less than the depth of the first doped region 132 formed by the first ion implantation.

[0069] In some examples, the process parameters for the second ion implantation include: implantation energy below 100 keV and implantation dose of 1E18 atom / cm². 3 the following.

[0070] like Figure 4 and Figure 5 In some embodiments shown, at least two gate structures 120 are formed on the drift region 111; in the step of performing a second ion implantation with a second energy, a second ion implantation is performed on the drift region 111 between adjacent gate structures 120 to form a second doped region 132 (e.g., Figure 5 (As shown); In the step of forming the second mask 132p, an opening 132O is formed in the formed second mask 132p, and the bottom of the opening 132O exposes the drift region 111 between adjacent gate structures 120.

[0071] Furthermore, in the direction of the connection between the two gate structures 120, the second doped region 132 is adjacent to both gate structures 120 on both sides. Therefore, in the direction of the connection between the two gate structures 120, the size of the opening 132O is not less than the size between the two adjacent gate structures 120. For example, in the step of forming the second mask 132p, the second mask 132p also exposes part of the gate structure 120, and in the direction of the connection between the two gate structures 120, the size of the opening 132O is larger than the size between the two adjacent gate structures 120.

[0072] Furthermore, in some embodiments, at least two gate structures 120 are formed on the drift region 111, and the second mask 132p exposes the drift region 111 between two adjacent gate structures 120, thus... Figure 4 and Figure 5 As shown, in the step of forming a second doped region 132 in the drift region 11 on one side of the gate structure 120 by performing a second ion implantation with a second energy, two implantations are performed on the two adjacent gate structures 120 respectively with the second energy, and both implantations are performed at an implantation angle θ2, but the tilting directions of the two implantation operations are opposite.

[0073] For example, the step of forming a second doped region 132 in the drift region 11 on one side of the gate structure 120 by performing a second ion implantation with a second energy includes: Figure 4 As shown, a first implantation is performed, with the first implantation directed towards the area below the gate structure 120 on one side. The first implantation is performed at an implantation angle θ2. During the first implantation, the angle between the beam and the normal to the surface of the substrate 110 is θ2, thereby forming a doped region 132a near the gate structure 120 on one side; as Figure 5 As shown, a second implantation is performed, which is directed towards the lower side of the gate structure 120 on the other side. The second implantation is also performed at an implantation angle θ2. During the second implantation, the angle between the beam and the normal of the substrate 110 surface is also θ2, thereby forming a second doped region 132 located between adjacent gate structures 120.

[0074] Continue to refer to Figure 6 The formation method further includes: after forming the body region 130, forming a drain region 141 in the drift region on the other side of the gate structure, wherein the drain region 141 is separated from the gate structure 120; forming a source region 142 in the body region 130; forming a body contact region 143 in the source region 142; wherein the doping type of the body contact region 143 is the same as that of the body region 130, and the doping type of the source region 142 and the drain region 141 is the same; for example, the body region 130 and the body contact region 143 can be P-type doped, and the source region 142 and the drain region 141 can be N-type doped.

[0075] like Figure 6As shown, at least two gate structures 120 are formed on the drift region 111, and the body region 130 is located between two adjacent gate structures 120; therefore, in the step of forming the drain region 141, the drain region 141 is located in the drift region 111 on the side of a gate structure 120 away from the body region 130, and in the direction parallel to the surface of the substrate 111, the two gate structures 120 are located between the two drain regions 141.

[0076] It should be noted that the formation method further includes: forming a contact layer 144 in contact with the gate structure 120. Specifically, the contact layer 144 at least covers a portion of the top surface of the gate structure 120; for example, the contact layer 144 also extends to the surface of the drift region 111; as... Figure 6 As shown, the contact layer 144 also covers the drift region 111 between the gate structure 120 and the drain region 141.

[0077] In addition, the forming method also includes forming a plurality of contact plugs 145, wherein the contact plugs 145 are electrically connected to the drain area 141, the contact layer 144 and the body contact area 143 respectively.

[0078] refer to Figure 7 The diagram illustrates the threshold voltage deviation of the LDMOS formed in an embodiment of the LDMOS formation method of the present invention.

[0079] Wherein, the vertical axis represents the threshold voltage, the horizontal axis represents the standard deviation of the threshold voltage, the yellow distribution 701 shows the threshold voltage distribution of the LDMOS formed by the LDMOS formation method of the present invention, and the blue distribution 702 shows the threshold voltage distribution of the LDMOS formed by the conventional LDMOS formation method.

[0080] like Figure 7 As shown, the LDMOS formed by this invention has higher threshold voltage stability, and the standard deviation of the threshold voltage is reduced from 0.346 to 0.0077, a reduction of 78%.

[0081] Accordingly, the present invention also provides an LDMOS. The LDMOS is formed by the method of the present invention.

[0082] The LDMOS is formed by the method of the present invention. For the specific technical solution of LDMOS, please refer to the embodiments of the aforementioned LDMOS formation method. The present invention will not be repeated here.

[0083] In summary, after forming the gate structure on the drift region in the substrate, performing ion implantation on the drift region on one side of the gate structure to form the body region, and performing ion implantation at a preset implantation angle can effectively improve the stability of the formed LDMOS channel and effectively reduce the variation of the threshold voltage of the formed LDMOS.

[0084] Furthermore, in the step of performing the first ion implantation with the first energy, the thickness of the first mask formed is... to Within the range; in the step of performing the second ion implantation with the second energy, the thickness of the second mask formed is within to Within the range. The thickness of the first mask and the second mask are relatively small, and the depth-to-width ratio is small, which can effectively increase the doping concentration of the bulk region formed by ion implantation, and is beneficial to further improve the stability of the threshold voltage of the formed LDMOS.

[0085] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. A method for forming an LDMOS, characterized in that, include: A substrate is provided, wherein the substrate has a drift region; A gate structure is formed on the drift region; Ion implantation is performed on the drift region on one side of the gate structure at a preset implantation angle to form a bulk region.

2. The forming method as described in claim 1, characterized in that, The injection angle is greater than 0° and less than 15°.

3. The forming method as described in claim 1, characterized in that, The step of performing ion implantation on the drift region on one side of the gate structure at a preset implantation angle to form a bulk region includes: A first ion implantation is performed with a first energy to form a first doped region in the drift region on one side of the gate structure; A second ion implantation is performed using a second energy to form a second doped region in the drift region on one side of the gate structure, wherein the second energy is less than the first energy; In at least one of the steps of performing first ion implantation with a first energy and performing second ion implantation with a second energy, ion implantation is performed at a preset implantation angle.

4. The forming method as described in claim 3, characterized in that, The steps of performing the first ion implantation with the first energy include: A first mask is formed, which exposes the source region locations between adjacent gate structures; A first ion implantation is performed on the source region exposed by the first mask using a first energy.

5. The forming method as described in claim 4, characterized in that, In the step of forming the first mask, the thickness of the first mask is... to Within the range.

6. The forming method as described in claim 4, characterized in that, In the step of forming the first mask, the first mask at least covers the top surface of the gate structure.

7. The forming method as described in claim 6, characterized in that, In the step of forming the first mask, the first mask also covers the sidewall surface of the gate structure.

8. The forming method as described in claim 4, characterized in that, The step of performing ion implantation on the drift region on one side of the gate structure at a preset implantation angle to form a body region further includes: after performing a first ion implantation on the source region exposed by the first mask with a first energy and before performing a second ion implantation with a second energy, removing the first mask.

9. The forming method as described in claim 3, characterized in that, The steps of performing a second ion implantation with a second energy include: A second mask is formed, the second mask exposing at least one drift region on one side of the gate structure; A second ion implantation is performed on the drift region exposed by the second mask using a second energy.

10. The forming method as described in claim 9, characterized in that, In the step of forming the second mask, the thickness of the second mask is... to Within the range.

11. The forming method as described in claim 9, characterized in that, In the step of forming the second mask, the second mask also exposes at least a portion of the gate structure.

12. The forming method as described in claim 4 or 9, characterized in that, At least one of the first and second masks is made of photoresist.

13. The forming method as described in claim 1, characterized in that, In the step of forming a gate structure on the drift region, at least two discrete gate structures are formed on the drift region; In the step of performing ion implantation on the drift region on one side of the gate structure at a preset implantation angle to form a body region, ion implantation is performed on the drift region between two adjacent gate structures at a preset implantation angle to form a body region.

14. The forming method as described in claim 1, characterized in that, In the step of providing a substrate, the drift region is an N-type doped region; in the step of performing ion implantation on the drift region on one side of the gate structure at a preset implantation angle to form a body region, the body region is a P-type doped region.

15. An LDMOS, characterized in that, The LDMOS is formed by the formation method according to any one of claims 1 to 14.

Images