Bipolar ohmic contact method based on interface regulation and control, two-dimensional semiconductor transistor and reconfigurable driving circuit

Abstract

The invention discloses a bipolar ohmic contact method based on interface regulation and control, a two-dimensional semiconductor transistor and a reconfigurable driving circuit, and relates to the technical field of two-dimensional semiconductor electronic devices and integrated circuits. The method comprises the following steps of: arranging two discrete and non-contact floating gate layers between a substrate and a two-dimensional semiconductor, introducing an interface regulation and control layer between a channel layer of the two-dimensional semiconductor and a metal electrode, and obtaining corresponding ohmic contact by controlling the types of carriers injected into the channel layer of the two-dimensional semiconductor by the floating gate layers. The invention further discloses a reconfigurable driving circuit, and multifunctional logic operation and reconfigurable driving control are achieved. The method has the advantages of being high in universality, high in process compatibility, large in integration potential and the like, and is suitable for a low-power-consumption CMOS integrated circuit, a reconfigurable logic device, a neuromorphic computing system and a Micro-LED micro-display driving chip.

Description

Technical Field

[0001] This invention belongs to the field of two-dimensional semiconductor devices and integrated circuit technology, and relates to a bipolar ohmic contact method based on interface control, two-dimensional semiconductor transistors and reconfigurable driving circuits. Background Technology

[0002] As one of the core components of integrated circuits, silicon-based field-effect transistors (FETs) have seen continuous increases in integration density and feature sizes shrinking to sub-10 nm. Consequently, problems such as heat generation, power consumption, and short-channel effects have become increasingly prominent, making further scaling up increasingly challenging. Although transistors are shifting towards new advanced architectures such as FinFETs and Gate-Around FETs (GAAFETs), as device sizes approach the physical limits of materials, the carrier mobility of silicon decreases significantly. The limitations of lattice and quantum tunneling also mean that silicon scaling is nearing its end, and the growth of integrated circuit computing power is encountering a bottleneck.

[0003] Two-dimensional field-effect transistors (2D-FETs) provide a novel research platform for the sustainable development of the integrated circuit industry. Firstly, 2D-FET channel materials (such as MoS2, WSe2, InSe, and black phosphorus) are only atomically thin and can be strongly modulated by an electrostatic field, enabling 2D FETs with gate lengths less than 1 nm. Secondly, even when the device channel thickness and length are drastically reduced to below 1 nm, excellent carrier mobility can still be maintained. More importantly, it can be van der Waals integrated with different types of materials, substrates, and devices, and is compatible with traditional silicon-based technologies. Therefore, FETs based on 2D materials are considered important candidate devices for next-generation low-power integrated circuits and neuromorphic computing chips, and have the potential for use in very large-scale integrated circuit (VLSI) technology.

[0004] However, due to issues with the gold-semiconductor contact caused by fabrication processes, the carrier injection and transport efficiency of 2D-FETs is limited, and two-dimensional FETs have not exhibited the expected superior electrical performance. Under ideal gold-semiconductor contact conditions, the device polarity can be modulated by the magnitude of the metal work function, achieving bipolar behavior within the same material. However, because the channel material of 2D-FETs is only atomically thin, there are often unsatisfactory contact problems when it comes into contact with the metal electrode, leading to Fermi level pinning. This not only limits the performance of two-dimensional transistors but also restricts the realization of bipolar contacts. Secondly, while there are many realizations of high-performance n-type contacts in 2D materials, and high-quality two-dimensional n-type FETs have been successively constructed, research on high-performance p-type contacts is relatively limited. Achieving high-performance bipolar contacts has always been a challenge, limiting the application of two-dimensional semiconductors in CMOS circuits and bipolar devices. In addition, the existing two-dimensional semiconductor driving circuit structure is fixed, making it difficult to meet the needs of multifunctional computing and reconfigurable logic, thus limiting its promotion in fields such as new displays and intelligent computing.

[0005] Therefore, there is a need to develop a method and related devices that can accommodate both n-type and p-type ohmic contacts. Summary of the Invention

[0006] To address the challenge of simultaneously achieving n-type and p-type ohmic contacts in existing technologies, this invention aims to provide a two-dimensional semiconductor bipolar transistor based on interface modulation, an ohmic contact method, and a reconfigurable circuit. By introducing a discrete floating gate layer beneath the contact region to control the channel carrier injection type, and by introducing an interface modulation layer between the electrode and the two-dimensional semiconductor, the interface state density is effectively reduced, weakening the Fermi level pinning effect and achieving a bipolar ohmic contact transistor with low contact resistance. Furthermore, based on the reconfigurable characteristics of bipolar ohmic contact devices, a novel reconfigurable driving circuit is constructed to achieve reconfigurable switching between different functional circuit units. Utilizing the reconfigurable characteristics of bipolar ohmic contacts and a threshold modulation mechanism, dynamic reconfiguration of circuit functions and multi-mode driving capabilities are achieved.

[0007] The technical solution of the present invention is as follows: The bipolar ohmic contact method based on interface control involves setting two discrete and non-contact floating gate layers between the substrate and the two-dimensional semiconductor, and introducing an interface control layer between the two-dimensional semiconductor channel layer and the metal electrode. By controlling the type of charge carriers injected into the two-dimensional semiconductor channel layer by the floating gate layer, the corresponding ohmic contact can be obtained.

[0008] Preferably, when two discrete floating gate layers control the simultaneous injection of both hole and electron carriers into the channel layer, a p-type and n-type bipolar ohmic contact is obtained in the two-dimensional semiconductor; when two discrete floating gate layers control the injection of holes into the two-dimensional semiconductor channel layer alone, a unipolar p-type ohmic contact is obtained; when two discrete floating gate layers control the injection of electrons into the channel layer alone, a unipolar n-type ohmic contact is formed.

[0009] A bipolar ohmic contact two-dimensional semiconductor transistor based on interface modulation includes a substrate. The substrate has two discrete, non-contact floating gate layers, an insulating layer, a two-dimensional semiconductor channel layer, an interface modulation layer, a top gate insulating layer, and positive and negative metal electrodes. Specifically: the discrete floating gate layers are located on the substrate; the insulating layer is located on the discrete floating gate layers; the two-dimensional semiconductor channel layer is located on the insulating layer; the interface modulation layer is located on the contact region of the two-dimensional semiconductor channel layer; the top gate insulating layer is located on the two-dimensional semiconductor channel region; and the metal electrodes are located on the interface modulation layer, the insulating layer, and the top gate insulating layer. In a single device, the two discrete floating gate layers are aligned with the two-dimensional semiconductor, and the two interface modulation layers are spaced apart on the two-dimensional semiconductor and aligned with the discrete floating gate layers. The source electrode (S) and drain electrode (D) are located on the two interface modulation layers, respectively. The control gate (CG) electrode is located on the insulating layer, and the top gate (TG) electrode is located on the top gate insulating layer.

[0010] Preferably, the floating gate layer is made of graphene or a thin metal layer; the interface control layer is at least one of fluoride, oxide, two-dimensional intercalated atomic layer or organic molecular layer.

[0011] Preferably, the material of the two-dimensional semiconductor channel layer is at least one of MoS2, WS2, WSe2, InSe or black phosphorus.

[0012] Preferably, the contact resistance of the transistor is less than 10 Ω. -6 Ω·cm 2 The subthreshold swing value approaches the limit of 60mV / dec.

[0013] This invention discloses a two-dimensional semiconductor transistor with bipolar ohmic contacts. To ensure compatibility with silicon-based processes, the substrate is a conventional SiO2 / Si substrate. The discrete floating gate layer is made of graphene or a thin metal layer. Graphene is preferably a single or multiple layer with a thickness of 0.4-5 nm, and the thin metal layer is preferably 15-20 nm thick. The insulating layer is made of h-BN, Al2O3, or HfO2, typically obtained using dry transfer or atomic layer deposition, with a thickness of 5-10 nm, preferably 10 nm. The two-dimensional semiconductor channel layer is made of MoS2, WS2, WSe2, or I2. At least one of nSe or black phosphorus can be selected, and it can be a single-layer, double-layer, or multi-layer material with a thickness of approximately 1 nm-20 nm; the interface control layer is at least one of fluoride, oxide, two-dimensional intercalated atomic layer, or organic molecular layer, and its main function is to effectively reduce the interface state density and weaken the Fermi level pinning effect generated when the metal electrode contacts the two-dimensional semiconductor. Its thickness matches (approximately equals) the thickness of the two-dimensional semiconductor channel layer; the top gate insulating layer is selected from h-BN with a thickness of 5-10 nm, preferably 10 nm; the source and drain metal electrodes are selected from Pd, Pt, Au, or MoO. x Low work function metals such as Ti, Al, and Mg are used to realize p-type and n-type bipolar contact transistors with low contact resistance, with a thickness of 50-70 nm. The control gate and top gate metal electrodes do not contact the semiconductor material; they only serve to regulate the gate voltage electrostatics and can be made of common metals such as Au, Pd, Al, or composite electrode materials. Based on bipolar ohmic contact devices, on-chip logic units, amplification units, and driving units are constructed using electrode arrangement and wiring. Functional reconfiguration and switching between units are achieved through p-type / n-type polarity selection and threshold voltage regulation.

[0014] This invention innovatively proposes for the first time the concepts of bipolar ohmic contacts and multifunctional cell switching. By introducing a discrete floating gate layer to control the carrier type of the injection channel and utilizing an interface modulation layer to reduce the interface state density and weaken the Fermi level pinning effect, bipolar ohmic contacts are achieved, ultimately resulting in low contact resistance and high stability. Furthermore, a novel reconfigurable driving circuit built based on this bipolar device can achieve multifunctional switching from logic cells and amplification cells to driving cells through the selection of device polarity and threshold modulation by the discrete floating gate layer, exhibiting high flexibility and broad application potential. This invention has advantages such as strong universality, high process compatibility, and great integration potential, and is suitable for low-power CMOS integrated circuits, reconfigurable logic devices, neuromorphic computing systems, and Micro-LED microdisplay driving chips.

[0015] A method for fabricating the above-mentioned interface-controlled bipolar ohmic contact two-dimensional semiconductor transistor includes the following steps: 1) Fabricate discrete floating gate layers on a substrate; 2) An insulating layer is prepared on the floating gate layer; 3) Two-dimensional materials are transferred onto the insulating layer and the material used as the contact portion is aligned with the discrete floating gate layer; 4) Two interface control layers were synthesized at specific points on the material at the contact part of the two-dimensional material, and then annealed. 5) A top-gate insulating layer is transferred and prepared on the material of the two-dimensional material channel portion; 6) Source and drain electrodes, control gate electrode, and top gate electrode are fabricated on the interface control layer, insulating layer, and top gate insulating layer, respectively, and then annealed to obtain the two-dimensional semiconductor transistor.

[0016] By connecting the source and drain electrodes of the fabricated two-dimensional semiconductor transistor to external testing equipment, current and polarity measurements can be achieved. Contact resistance can be extracted using the common four-electrode method or the transmission length method. Based on the fabricated two-dimensional transistor with bipolar ohmic contacts, circuit design and interconnection are performed to construct logic units, amplification units, and driving units. Flexible and reconfigurable switching between various functional units is achieved by utilizing device polarity selection and threshold voltage regulation.

[0017] Step 1) above directly uses a SiO2 / Si substrate as the base. Discrete floating gate layers can be prepared on this substrate using dry transfer of graphene followed by Plasma etching, or by metal evaporation deposition. Specifically, using graphene to create discrete floating gates involves: spin-coating PMMA electron beam lithography adhesive onto the surface of the obtained graphene sample, drying it, and then sequentially performing electron beam exposure, development, and fixing to mark the graphene sample; then designing a discrete floating gate pattern based on the marked pattern, and again performing electron beam exposure, development, and fixing to expose excess graphene material; then placing the entire sample in a Plasma chamber to etch away the excess graphene material; finally, placing the sample in an acetone solution to remove the PMMA adhesive and cleaning it, ultimately obtaining a discrete graphene floating gate layer. The specific method for preparing discrete floating gates using metal evaporation deposition is as follows: PMMA electron beam exposure adhesive is directly spin-coated onto the substrate surface and dried. The designed discrete floating gate pattern is then directly exposed to electron beam. After development and fixing, the discrete floating gate pattern can be displayed on the substrate. Subsequently, metal evaporation deposition is performed, and finally, acetone is used for stripping to remove the PMMA adhesive and excess metal, thus forming a discrete floating gate layer with a specific pattern on the substrate.

[0018] Step 2) above can be used to prepare an insulating layer on a discrete floating gate layer using dry transfer or atomic layer deposition (ALD) methods.

[0019] In step 3) above, a two-dimensional semiconductor channel layer is prepared by dry transfer technology on the insulating layer, and the material used as the contact part is aligned with the discrete floating gate layer using a three-dimensional transfer stage and microscope.

[0020] The point-to-point synthesis and preparation of the two interface control layers in step 4) above can be achieved by dry transfer with the assistance of a three-dimensional transfer stage, or by patterning the two-dimensional semiconductor channel layer using electron beam lithography (EBL), followed by the subsequent preparation of the buffer layer using thermal evaporation or electron beam evaporation deposition processes. Specifically, it can be as follows: spin-coating PMMA electron beam lithography adhesive onto the sample surface obtained in step 3), drying it, and then performing electron beam lithography, development, and fixing sequentially to complete the point marking of the sample; then, using the point marking as a reference for designing the buffer layer position pattern on the sample, performing electron beam lithography, development, and fixing again to expose the buffer layer position; then, using PMMA adhesive as a mask, further processing or thermal evaporation or electron beam evaporation deposition processes are used to deposit interface control layers such as fluorides, oxides, two-dimensional intercalated atomic layers, or organic molecular layers; finally, acetone is used for stripping to remove excess PMMA adhesive, thus forming an interface control layer with a specific size, thickness, and position on the channel layer material. Finally, the transferred sample is annealed to eliminate stress, residual adhesive, and other contaminants.

[0021] In step 5) above, the top gate insulating layer can be prepared by dry transfer technology.

[0022] In step 6) above, the source and drain positive and negative electrodes, control gate electrode, and top gate electrode are formed on the interface control layer, insulating layer, and top gate insulating layer according to a designed pattern using electron beam lithography (EBL). Specifically, the following method can be used: Observe the specific position of the sample obtained in step 5) using an optical microscope; spin-coat PMMA electron beam lithography adhesive onto the surface of the obtained two-dimensional heterojunction material and dry it; perform electron beam lithography, development, and fixing in sequence to complete the point marking of the sample; then design the electrode pattern based on the point marking of the sample, perform electron beam lithography, development, and fixing, and expose the electrode pattern on the interface control layer, insulating layer, and top gate insulating layer material; then deposit the metal electrodes by thermal evaporation or electron beam evaporation coating process; finally, perform stripping, thus forming the source, drain, control gate, and top gate metal electrodes on the heterojunction material. Anneal the sample again to eliminate stress, residual adhesive, and other contaminants, and improve the contact quality of the metal electrodes.

[0023] Furthermore, the thickness of the discrete floating gate layer affects the carrier storage effect, and an excessively thick floating gate also increases stress introduction, thereby increasing the difficulty of subsequent material transfer and device fabrication. To select the optimal thickness of the discrete floating gate layer, in one embodiment of this invention, graphene material of about 5 nm is selected to prepare the floating gate layer.

[0024] Furthermore, the thickness of the insulating layer affects the modulation effect of the separated floating gate layer on the two-dimensional semiconductor channel layer. The thickness of the two-dimensional semiconductor channel layer and the thickness of the buffer layer also affect the interface coupling effect, thereby affecting the reduction of contact resistance. To select the optimal material thickness, in one embodiment of the present invention, the thickness of the insulating layer is selected as 10 nm, the thickness of the two-dimensional semiconductor channel layer is selected as approximately 10 nm, and the interface modulation layer is selected as 3-10 nm, preferably 5 nm.

[0025] Furthermore, high-vacuum annealing can eliminate stress, defects, and contaminants such as accidentally introduced residues between materials to a certain extent, increase the interface coupling effect, thereby effectively improving contact and achieving the purpose of bipolar ohmic contact.

[0026] The two-dimensional semiconductor transistor with bipolar ohmic contact, which is achieved through interface control, can be used to construct a novel reconfigurable driving circuit. By controlling and selecting the p-type / n-type polarity and adjusting the threshold voltages of the p-type and n-type output behavior, the functional reconfiguration between the logic unit, the amplification unit, and the driving unit can be realized.

[0027] A reconfigurable driving circuit is constructed based on the above-mentioned bipolar ohmic contact two-dimensional semiconductor transistor. By selecting the p-type / n-type polarity and regulating the threshold voltage of the p-type and n-type input behavior, the functional reconfiguration between the logic unit, the amplification unit and the driving unit can be realized.

[0028] Preferably, the driving circuit is a reconfigurable logic circuit or a neuromorphic computing circuit.

[0029] Compared with the prior art, the beneficial effects of the present invention are: The interface control layer of this invention adopts fluoride, oxide, two-dimensional intercalated atomic layer or organic molecular layer, which has the advantages of high carrier concentration, strong structural stability and easy preparation.

[0030] This invention can realize a two-dimensional semiconductor transistor with bipolar ohmic contact, exhibiting bipolar transport behavior and good electrical transport characteristics.

[0031] This invention utilizes discrete floating gate layers to control the carrier type of the injection channel, and in conjunction with the interface control layer, achieves high-performance p-type and n-type transport behavior of ohmic contacts. Furthermore, through polarity selection and threshold voltage control, it realizes functional reconfiguration between logic units, amplification units, and driving units. Attached Figure Description

[0032] Figures 1-7 This is a schematic diagram of the structural steps involved in preparing the two-dimensional semiconductor transistor with bipolar ohmic contact based on interface modulation, as described in Embodiment 1 of the present invention.

[0033] Figure 1 This is a schematic diagram of the selected SiO2 / Si substrate; Figure 2 To prepare discrete floating gate layers on a substrate using dry transfer or metal evaporation deposition methods; Figure 3 To fabricate an insulating layer onto a discrete floating gate layer using a dry transfer or atomic layer deposition (ALD) method; Figure 4 To utilize dry transfer technology to transfer two-dimensional materials onto an insulating layer; Figure 5 To utilize dry point transfer or evaporation coating processes to prepare an interface control layer onto the material layer at the contact portion of two-dimensional materials; Figure 6 To utilize dry transfer technology to precisely transfer the top grid insulation layer onto a two-dimensional material channel layer; Figure 7 To utilize metal deposition technology, source and drain, control gate, and top gate metal electrodes are deposited onto the interface control layer, insulating layer, and top gate insulating layer to obtain a two-dimensional semiconductor transistor with bipolar ohmic contacts. Figure 8 An optical microscope image of the bipolar ohmic contact two-dimensional semiconductor transistor with an interface control layer that has been prepared. Figure 9 The transfer characteristic curves of a two-dimensional semiconductor transistor with bipolar contacts; Figure 10 To utilize the control of discrete floating gate layers and interface control layers to form a high-performance p-type ohmic contact with the channel, the transfer characteristic curve is obtained. Figure 11 To utilize the control of discrete floating gate layers and interface control layers to form a high-performance n-type ohmic contact with the channel, the transfer characteristic curve is obtained. Figure 12 The output characteristics of a CMOS inverter circuit built based on p-type ohmic contact and n-type ohmic contact transistors are shown. Figure 13 Power consumption diagram and noise margin extraction diagram for CMOS inverter circuit; Figure 14 The output characteristic diagrams of reconfigurable logic gates implemented through polarity selection and threshold voltage regulation are shown, including AND gates, NOR gates, XOR gates, NIMP, and RNIMP.

[0034] The meanings of the labels in the figures are as follows: 1. Si substrate, 2. SiO2 layer, 3. Discrete floating gate layer (graphene or thin metal layer), 4. Insulating layer, 5. Two-dimensional semiconductor channel layer (channel layer), 6. Interface control layer, 7. Top gate insulating layer, 8. Source (S), drain (D), control gate (CG), top gate (TG) metal electrodes. Detailed Implementation

[0035] The present invention will now be described in further detail with reference to the accompanying drawings and specific embodiments, so that those skilled in the art can more clearly understand the present invention.

[0036] This invention provides a bipolar ohmic contact method based on interface control, which includes: setting two discrete and non-contact floating gate layers between a substrate and a two-dimensional semiconductor, and introducing an interface control layer between the two-dimensional semiconductor channel layer and a metal electrode; and obtaining the corresponding ohmic contact by controlling the type of charge carriers injected into the two-dimensional semiconductor channel layer by the floating gate layer.

[0037] Furthermore, when two discrete floating gate layers control the simultaneous injection of both hole and electron carriers into the channel layer, a bipolar ohmic contact of p-type and n-type is obtained in the two-dimensional semiconductor; when two discrete floating gate layers control the injection of holes into the two-dimensional semiconductor channel layer alone, a unipolar p-type ohmic contact is obtained; when two discrete floating gate layers control the injection of electrons into the channel layer alone, a unipolar n-type ohmic contact is formed.

[0038] The following explanation uses a two-dimensional semiconductor transistor with bipolar ohmic contact based on interface modulation as an example. This is a device that uses a discrete floating gate and interface modulation layer to control the contact between the metal electrode and the semiconductor, avoiding Fermi level pinning, thereby achieving a bipolar ohmic contact. Its basic structure is as follows: Figure 7 As shown, the device unit includes a Si substrate 1, a SiO2 layer 2, a discrete floating gate layer 3, an h-BN / Al2O3 / HfO2 insulating layer 4, a two-dimensional semiconductor channel layer (WSe2) 5, an interface control layer 6, a top gate insulating layer (h-BN) 7, and source (S), drain (D), control gate (CG), and top gate (TG) metal electrodes 8. The discrete floating gate layer between the substrate and the insulating layer is used to control the type of carriers injected into the two-dimensional semiconductor channel layer by the electrodes; the interface control layer between the metal electrodes and the channel layer material WSe2 serves as a contact layer to improve the device contact quality and ultimately achieve a high-performance bipolar ohmic contact.

[0039] The working principle of the bipolar ohmic contact device unit is as follows: By introducing a contact floating gate layer through dry transfer or coating processes, the channel carrier injection type can be controlled. When opposite pulse voltages are applied to the two control gates (CG), different types of carriers—electrons and holes—are stored simultaneously in the discrete control gates. Based on the capacitor principle, holes and electrons can be injected into the channel from the electrodes at the same time, and the device exhibits p-type and n-type bipolar transport behavior. When the same positive or negative pulse voltage is applied to the two control gates, the same type of carrier—only holes or only electrons—is stored in the discrete floating gate layer. Based on the capacitor principle, only electrons or holes of a single type are allowed to be injected into the channel from the electrodes, and the device exhibits p-type or n-type unipolar transport behavior. Meanwhile, the interface control layer with high carrier mobility can effectively control the contact barrier generated when the metal electrode is in contact with the two-dimensional semiconductor channel layer WSe2, and avoid the introduction of defects when the metal electrode is in direct contact with the two-dimensional semiconductor channel layer WSe2, so that the device can achieve bipolar contact with ohmic contact and exhibit good electrical performance.

[0040] The device fabrication method of the present invention is applicable to most two-dimensional semiconductor materials, and the fabrication is highly controllable and efficient. While realizing p-type and n-type bipolar contacts, it improves the electrical performance of the device, providing a new approach for building high-performance bipolar contact devices and reconfigurable logic circuits in the future.

[0041] The following describes a controllable fabrication method for bipolar ohmic contact two-dimensional semiconductor transistor devices based on interface modulation, including the following steps: Step 1: Use p-type doped SiO2 / Si as the substrate. First, before material preparation, ultrasonically clean SiO2 / Si substrates 1 and 2 using an organic solvent, following the sequence of acetone (5-10 min) → isopropanol (10-15 min) → deionized water (10-20 min). Finally, use a nitrogen gun to dry any remaining deionized water on the substrate, obtaining a clean Si / SiO2 substrate, as shown below. Figure 1 As shown.

[0042] Step 2: Taking the preparation of discrete graphene floating grating layers as an example, the graphene is transferred and prepared on the clean substrate obtained in the previous step. Two-dimensional materials are obtained using a mechanical exfoliation method and then prepared on the substrate using a dry transfer technique. The specific method is described in detail below. First, sheet-like graphene crystals are uniformly dispersed on a pre-prepared Scotch tape. This tape is then applied to a silicone-like transparent polydimethylsiloxane (PDMS) substrate and peeled off, leaving many graphene samples of different sizes and thicknesses on the PDMS substrate. Samples with uniform thickness and suitable size are selected and marked for positioning. Then, the PDMS containing the target two-dimensional material is placed on a glass slide, and the graphene is transferred onto the substrate using a three-dimensional transfer stage. The obtained graphene samples undergo spin coating, exposure, marking, re-exposure, and development steps to expose and remove excess material. Finally, the sample is placed in a Plasma etching system to etch away excess graphene material, resulting in the structure shown below. Figure 2 As shown.

[0043] Step 3: Continue to fabricate an insulating layer on the discrete graphene floating gate layer obtained in Step 2. Method 1: A dry transfer method can be used to transfer and fabricate the insulating layer h-BN on the discrete graphene floating gate layer. First, the insulating layer h-BN is peeled off onto PDMS using Scotch tape. Then, using an optical microscope and a three-dimensional transfer platform, the insulating layer h-BN on the PDMS is aligned and transferred with the discrete graphene floating gate layer on the substrate, ultimately forming a heterojunction material, such as... Figure 3As shown. Method 2: The insulating layer HfO2 can be prepared using the ALD method. First, the substrate is cleaned for 10 minutes with a mixed solution of strong ammonium oxide / hydrogen peroxide / deionized water, then cleaned with deionized water, and then immersed in hydrofluoric acid / deionized water for half a minute to remove the natural oxide layer on the surface. Then, after ultrasonic cleaning with deionized water for 10 minutes, it is immediately dried with nitrogen and placed in the ALD vacuum chamber to deposit HfO2. Tetradiaminemethylhafnium is used as the hafnium source precursor and ultrapure water as the oxygen source precursor. The sample is deposited in a high vacuum environment to reduce impurity contamination. At the same time, tetradiaminemethylhafnium is usually heated to 75 °C to ensure that the vapor pressure meets the process requirements to meet the chemical activity of the precursor molecules during the film formation reaction. During the deposition process, an inert gas is first used as a carrier gas to pulse the precursor A (oxygen source) into the reaction chamber. Due to the large number of surface dangling bonds on the substrate, the precursor molecules will be adsorbed on the substrate surface. Once adsorption saturation is achieved, inert gas is continuously purged to remove excess precursor source from the chamber. Subsequently, precursor B (hafnium source) is introduced into the reaction chamber via a carrier gas pulse. It reacts with precursor A adsorbed on the substrate surface and reaches saturation. Inert gas is then continuously purged to remove reaction byproducts and excess precursor source from the chamber, thus completing one cycle of molecular thin film growth. By repeating different growth cycles, HfO2 films of varying thicknesses can be obtained.

[0044] Step 4: Two-dimensional material WSe2 is prepared by dry transfer onto the sample obtained in Step 3. Similarly, the two-dimensional material is obtained using mechanical exfoliation and then prepared on a discrete graphene floating gate layer with an insulating layer using dry transfer technology. First, WSe2 crystals are relatively uniformly dispersed on a (PDMS) substrate. WSe2 crystals of uniform thickness and suitable size that meet the usage requirements are marked and positioned. Then, using a microscope and a three-dimensional transfer stage, the WSe2 material is aligned with and transferred to the discrete graphene floating gate layer to obtain a heterojunction material. Its structure is as follows... Figure 4 As shown.

[0045] Step 5: Transfer and prepare a two-dimensional interface control layer on the two-dimensional semiconductor channel layer obtained in Step 4. Method 1: A dry transfer technique can be used to prepare the two-dimensional interface control layer on the two-dimensional semiconductor channel layer. First, the interface control layer is peeled off onto PDMS using Scotch tape. Then, an optical microscope and a 3D transfer platform are used to align the interface control layer on the PDMS with the two-dimensional material WSe2 on the substrate and transfer it at specific points to form a heterojunction material. Method 2: A fluoride, oxide, or organic molecular layer can be prepared on the two-dimensional semiconductor channel layer using evaporation deposition. First, a spin coating process is performed on the sample obtained in Step 4. Then, the designed interface control layer pattern is exposed on the sample using a maskless photolithography system. The pattern is then developed in a photoresist developer and cleaned with deionized water. Finally, a thermal evaporation / electron beam deposition system is used, maintaining a 5*10... -5 Fluoride, oxide, or organic molecular layers are prepared by vapor deposition at a pressure of Pa and an evaporation rate of 0.1-0.3 Å / s. Finally, the photoresist is removed by stripping, resulting in a heterojunction material. The transferred sample is then annealed in a high-vacuum annealing furnace to eliminate stress, residual photoresist, and other contaminants. The annealing temperature is typically 200 °C for 6 hours, with a vacuum level of ~2.5 × 10⁻⁶. -7 mbar. Its structure is as follows: Figure 5 As shown.

[0046] Step Six: Using the same dry transfer technique, the top gate insulating layer h-BN is transferred and prepared onto the channel WSe2 layer. First, Scotch tape is used to peel the insulating layer h-BN onto PDMS. Then, using an optical microscope and a 3D transfer platform, the appropriately thick and sized insulating layer h-BN on the PDMS is aligned with the channel WSe2, and their heights are adjusted to ensure they adhere together. The heterojunction structure is as follows: Figure 6 As shown.

[0047] Step 7: Perform homogenization, exposure, marking, re-exposure, and development processes on the sample obtained in Step 6. This will expose the designed electrode shape on the specific sample. Then, using a thermal evaporation / electron beam coating system, maintain a 5*10... -5 The coating is completed at a pressure of Pa and an evaporation rate of 0.1-0.3 Å / s; finally, a stripping process is performed to obtain the source (S), drain (D), control gate (CG), and top gate (TG) metal electrodes 8, as shown. Figure 7 As shown. Finally, the prepared sample is placed in a high-vacuum annealing furnace for annealing to eliminate stress, residual adhesive, and other contaminants, further improving the contact quality between the electrode and the semiconductor material. The annealing temperature is generally selected as 200 ℃, the time is 6 hours, and the vacuum degree is ~2.5×10⁻⁶. -7 mbar.

[0048] The following are specific embodiments of the array device based on a metal-semiconductor heterojunction prepared according to the present invention.

[0049] Example 1 An optical microscope image of a bipolar contact two-dimensional transistor based on an interface modulation layer is shown below. Figure 8 As shown, from bottom to top, it includes a Si substrate 1, a SiO2 layer 2, a discrete graphene floating gate layer 3, an h-BN insulating layer 4, a two-dimensional semiconductor channel layer (WSe2) 5, an interface control layer 6, a top gate insulating layer (h-BN) 7, and source (S), drain (D), control gate (CG), and top gate (TG) metal electrodes 8. Among them, the discrete graphene floating gate layer 3 is prepared on the SiO2 / Si substrate by dry transfer and Plasma etching. The h-BN insulating layer 4 prepared by dry transfer is on the discrete floating gate layer 3. The WSe2 two-dimensional semiconductor channel layer 5 prepared by dry transfer is on the insulating layer 4. The interface control layer 6 prepared by dry transfer is on the two-dimensional semiconductor channel layer 5. Similarly, the top gate insulating layer (h-BN) 7 prepared by dry transfer is on the two-dimensional semiconductor channel layer 5. The source (S) and drain (D), control gate (CG), and top gate (TG) metal electrodes 8, obtained by electron beam exposure and electron beam evaporation of 50 nm Au, are located on the interface control layer 6, the h-BN insulating layer 4, and the top gate insulating layer (h-BN) 7. The contact point source (S) and drain (D) metal electrodes have a width of 2 μm and a length of 15 μm; the control gate (CG) metal electrode has a width of 3 μm and a length of 4 μm; and the top gate (TG) metal electrode has a width of 4 μm and a length of 15 μm.

[0050] like Figure 9 As shown, when opposite pulse voltages are applied to control gates CG1 and CG2 ( V CG1 = +10V, V CG2 = -10V; or V CG1 = -10V, V CG2 = +10V), electrons and holes are stored simultaneously in the discrete floating gate, allowing holes and electrons to be injected into the channel at the same time. In this case, the transfer characteristic curve of the two-dimensional transistor with bipolar ohmic contact exhibits typical bipolar electrical transport behavior. Under bias voltage... V D At 0.2 V, the subthreshold swing SS of the left-side p-type input behavior is 66 mV / dec, approaching the theoretical optimal limit of 60 mV / dec, and the on / off ratio is 10. 6The subthreshold swing SS of the right-hand n-type input behavior is 70 mV / dec, and the on / off ratio is 10. 6 The bipolar ohmic contact two-dimensional transistor realized using discrete floating gate layers and interface modulation layers exhibits excellent and highly symmetrical bipolar behavior.

[0051] like Figure 10 As shown, when the same negative pulse voltage is applied to control gates CG1 and CG2 ( V CG1 = V CG2 = -10V), the discrete floating gate stores only electrons and allows only hole injection into the channel, forming a high-performance p-type ohmic contact. The transfer characteristic curve exhibits typical p-type unipolar transport behavior under bias voltage. V D At 0.2 V, the subthreshold swing SS of the p-type ohmic contact device's output behavior is 64 mV / dec, approaching the theoretical optimal limit of 60 mV / dec, and the on / off ratio is 10. 6 .

[0052] like Figure 11 As shown, when the same positive pulse voltage is applied to control gates CG1 and CG2 ( V CG1 = V CG2 = +10V), the discrete floating gate stores only holes and allows only electron injection into the channel, forming a high-performance n-type ohmic contact. The transfer characteristic curve exhibits typical n-type unipolar transport behavior under bias voltage. V D At 0.2 V, the subthreshold swing SS of the n-type ohmic contact device's output behavior is 69 mV / dec, approaching the theoretical optimal limit of 60 mV / dec, and the on / off ratio is 10. 6 .

[0053] like Figure 12 As shown, the polarity of a two-dimensional transistor is selected using discrete floating gate layers and interface modulation layers. A CMOS inverter circuit is constructed using unipolar p-type ohmic contacts and unipolar n-type ohmic contacts. Its operating characteristic curves show typical inverter output characteristics, i.e., at the input... V IN When it is low level 0, the output is... V OUT High level 1; at input V IN When it is high level 1, the output is... V OUT The voltage level is low (0). Simultaneously, the inverter has a high gain of Gain = 134 (...).V D = 1 V).

[0054] like Figure 13 As shown, the CMOS circuit exhibits high noise margin, with a total noise margin exceeding 91% (low level NML = 0.44 V, high level NMH = 0.47 V, VDD = 1 V), outperforming most similar devices. Simultaneously, by calculating power consumption (P = V... DD ×I D It was discovered that V DD At 1 V, the peak power consumption is 1.2 nW, which can be further suppressed to 37 pW when the supply voltage drops to 0.8 V, far lower than the dynamic power consumption of traditional CMOS circuits (approximately μW to mW). The static power consumption in both the "1" and "0" states at all voltages is in the sub-picowatt range, also far lower than the static power consumption of traditional CMOS circuits (approximately nW to μW). This ultra-low power consumption characteristic stems from the excellent turn-off performance in both p-type and n-type states.

[0055] like Figure 14 As shown, by controlling the polarity of bipolar ohmic contact two-dimensional transistors through discrete floating gate layers and interface control layers, and by utilizing threshold voltage control and device interconnection, a variety of reconfigurable logic gates can be implemented, including AND gates, NOR gates, XOR gates, NIMP, and RNIMP.

[0056] This invention presents a method for bipolar ohmic contacts in two-dimensional semiconductor transistors based on interface modulation. This method achieves high-performance and highly symmetrical p-type and n-type bipolar contacts, exhibiting excellent turn-on and turn-off performance, a high on / off ratio, and steep switching characteristics. Furthermore, by controlling the contact barrier, transport polarity, and threshold voltage through discrete floating gate layers and interface modulation layers, p-type / n-type unipolar ohmic contacts with the same high on / off ratio and steep switching characteristics can be achieved. This provides greater flexibility for constructing CMOS circuits and reconfigurable logic gates, showing broad application prospects in the future fields of low-power CMOS integrated circuits, security circuits, neuromorphic computing systems, and Micro-LED microdisplay driver chips.

[0057] Finally, it should be noted that the purpose of disclosing the embodiments is to help further understand the present invention. Those skilled in the art should understand that various substitutions and modifications are possible without departing from the spirit and scope of the present invention and the appended claims. Therefore, the present invention should not be limited to the content disclosed in the embodiments, and the scope of protection of the present invention is defined by the claims.

Claims

1. A bipolar ohmic contact method based on interface control, characterized in that: Two discrete, non-contact floating gate layers are set between the substrate and the two-dimensional semiconductor. At the same time, an interface control layer is introduced between the two-dimensional semiconductor channel layer and the metal electrode. By controlling the type of charge carriers injected into the two-dimensional semiconductor channel layer by the floating gate layer, the corresponding ohmic contact is obtained.

2. The bipolar ohmic contact method based on interface control according to claim 1, characterized in that: When two discrete floating gate layers control both holes and electrons to be injected into the channel layer simultaneously, a bipolar p-type and n-type ohmic contact is obtained in the two-dimensional semiconductor; when two discrete floating gate layers control holes to be injected into the channel layer of the two-dimensional semiconductor individually, a unipolar p-type ohmic contact is obtained; when two discrete floating gate layers control electrons to be injected into the channel layer individually, a unipolar n-type ohmic contact is formed.

3. A bipolar ohmic contact two-dimensional semiconductor transistor based on interface modulation, characterized in that, The device includes a substrate on which two discrete, non-contact floating gate layers, an insulating layer, a two-dimensional semiconductor channel layer, an interface control layer, a top gate insulating layer, and positive and negative metal electrodes are disposed. Specifically: the discrete floating gate layers are located on the substrate; the insulating layer is located on the discrete floating gate layers; the two-dimensional semiconductor channel layer is located on the insulating layer; the interface control layer is located on the contact area of ​​the two-dimensional semiconductor channel layer; the top gate insulating layer is located on the two-dimensional semiconductor channel region; and the metal electrodes are located on the interface control layer, the insulating layer, and the top gate insulating layer. In a single device, the two discrete floating gate layers are aligned with the two-dimensional semiconductor, and the two interface control layers are spaced apart on the two-dimensional semiconductor and aligned with the discrete floating gate layers. The source electrode (S) and drain electrode (D) are located on the two interface control layers, the control gate (CG) electrode is located on the insulating layer, and the top gate (TG) electrode is located on the top gate insulating layer.

4. The interface-controlled bipolar ohmic contact two-dimensional semiconductor transistor according to claim 3, characterized in that: The floating grid layer is made of graphene or a thin layer of metal; The interface control layer is at least one of fluoride, oxide, two-dimensional intercalated atomic layer or organic molecular layer.

5. The interface-controlled bipolar ohmic contact two-dimensional semiconductor transistor according to claim 3, characterized in that: The material of the two-dimensional semiconductor is at least one of MoS2, WS2, WSe2, InSe or black phosphorus.

6. The interface-controlled bipolar ohmic contact two-dimensional semiconductor transistor according to claim 3, characterized in that: The contact resistance of the transistor is less than 10. -6 Ω·cm 2 The subthreshold swing value approaches the limit of 60 mV / dec.

7. The interface-controlled bipolar ohmic contact two-dimensional semiconductor transistor according to claim 3, characterized in that: The thickness of the floating gate layer is 0.4-20 nm; the thickness of the insulating layer is 5-10 nm; the thickness of the two-dimensional semiconductor channel layer is 1-20 nm; the thickness of the interface control layer is 3-10 nm; and the thickness of the top gate insulating layer is 5-10 nm.

8. The method for fabricating a bipolar ohmic contact two-dimensional semiconductor transistor based on interface modulation according to any one of claims 3-7, characterized in that, Includes the following steps: 1) Fabricate discrete floating gate layers on a substrate; 2) An insulating layer is prepared on the floating gate layer; 3) Two-dimensional materials are transferred onto the insulating layer and the material used as the contact portion is aligned with the discrete floating gate layer; 4) Two interface control layers were synthesized at specific points on the material at the contact part of the two-dimensional material, and then annealed. 5) A top-gate insulating layer is transferred and prepared on the material of the two-dimensional material channel portion; 6) Source and drain electrodes, control gate electrode, and top gate electrode are fabricated on the interface control layer, insulating layer, and top gate insulating layer, respectively, and then annealed to obtain the two-dimensional semiconductor transistor.

9. A reconfigurable driving circuit, characterized in that, Based on the bipolar ohmic contact two-dimensional semiconductor transistor constructed according to any one of claims 3-7, the functional reconfiguration between the logic unit, the amplification unit and the driving unit is realized by selecting the p-type / n-type polarity and regulating the threshold voltage of the p-type and n-type output behavior.

10. The reconfigurable drive circuit according to claim 9, characterized in that, The driving circuit is a reconfigurable logic circuit or a neuromorphic computing circuit.

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