A method for manufacturing a trench gate of a trench MOS device

Abstract

The application relates to the technical field of semiconductor manufacturing, and discloses a preparation method of a trench gate in a trench MOS device, which comprises the following steps: conformally depositing an amorphous metal silicide precursor film on a semiconductor substrate with a trench by adopting an atomic layer deposition process; subsequently, performing two-step continuous plasma in-situ conversion treatment on the precursor film: first, in an oxygen-containing or nitrogen-containing atmosphere, applying a radio frequency bias with dynamic time control to in-situ convert part of the precursor film close to the substrate into a gate dielectric layer; and then, in an inert atmosphere, applying a low-frequency high-power radio frequency bias to induce solid-state phase change of the remaining precursor film through high-energy ion implantation. The integrated low-temperature in-situ conversion process not only simplifies the preparation process and reduces the overall thermal budget, but also fundamentally eliminates the polysilicon depletion effect, so that a gate structure composed of a high-performance gate dielectric layer and a metal silicide conductor is obtained.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing technology, specifically to a method for fabricating a trench gate in a trench-type MOS device. Background Technology

[0002] Trench metal-oxide-semiconductor field-effect transistors (MOSFETs) are important semiconductor power devices, widely used in power management, automotive electronics, and industrial control due to their low on-resistance and high integration density. The trench gate is the core structure of this type of device, and the quality of its fabrication method directly determines the final performance and reliability of the device.

[0003] Traditional trench gate fabrication methods typically involve etching trenches in a semiconductor substrate, followed by growing a silicon dioxide layer on the inner wall of the trench as the gate dielectric layer using a high-temperature thermal oxidation process, then filling the trench with doped polysilicon as the gate conductor material using a chemical vapor deposition process, and finally forming a planarized gate structure through processes such as chemical mechanical polishing. However, this traditional process route has inherent technical limitations in practical applications.

[0004] In this process flow, the high-temperature thermal oxidation process used to form the gate dielectric layer, and the subsequent high-temperature annealing treatment to reduce the resistivity of polysilicon, together constitute a significant process thermal budget. This high thermal budget may lead to unexpected impurity redistribution in the doped regions already formed in the device, thereby affecting the final electrical performance parameters of the device. Furthermore, when thermal oxidation is performed inside trenches with high aspect ratios, the oxide layer growth rate in the trench corner regions is uneven, easily leading to physical thinning. This structural weakness will cause electric field concentration during device operation, reducing the long-term reliability and breakdown voltage of the gate dielectric layer. Simultaneously, using doped polysilicon as the gate conductor material also introduces a performance bottleneck. Under the action of the gate voltage, a depletion layer will form at the interface between the polysilicon and the gate dielectric, i.e., the polysilicon depletion effect. This effectively increases the total thickness of the gate dielectric, weakens the gate's control capability, and reduces the device's drive current.

[0005] Therefore, developing a novel trench gate fabrication method that can reduce process thermal budget, improve trench gate dielectric reliability, and eliminate the performance bottleneck of polysilicon gates is a technical problem that urgently needs to be solved in the current semiconductor technology field. Summary of the Invention

[0006] To address the shortcomings of existing technologies, this invention provides a method for fabricating trench gates in trench-type MOS devices, which solves the problems of high process thermal budget, reduced gate dielectric reliability, and limited device performance caused by the use of high-temperature processes and polycrystalline silicon materials in existing trench gate fabrication methods.

[0007] To achieve the above objectives, the present invention provides the following technical solution: a method for fabricating a trench gate in a trench-type MOS device, comprising:

[0008] The first aspect of this invention provides a method for fabricating a trench gate in a trench-type MOS device, comprising the following steps:

[0009] S1: Trench is formed by etching in a semiconductor substrate;

[0010] S2: An amorphous metal silicide precursor film is conformally deposited within the trench using atomic layer deposition (ALD). Specifically, the atomic ratio of metal to silicon in the amorphous metal silicide precursor film is controlled to be between 1:2 and 1:4 by adjusting the cycle ratio of the metal source to the silicon source during ALD. The purpose of this step is to form a reaction material layer with uniform composition and controllable thickness.

[0011] In one specific embodiment, the deposition temperature of the atomic layer deposition process is 250-350°C. The material of the amorphous metal silicide precursor film is selected from one of amorphous hafnium silicon film, amorphous titanium silicon film, or amorphous zirconium silicon film.

[0012] S3: Perform a two-step continuous in-situ plasma conversion process on the amorphous metal silicide precursor film. This step utilizes precisely controlled plasma energy to differentiate the single-component raw material layer into functional layers with different electrical properties in situ.

[0013] This process specifically includes the following two consecutive sub-steps:

[0014] Programmable conversion of the interface dielectric layer: Under an environment containing oxygen or nitrogen reaction gas, a dynamically adjustable radio frequency bias voltage is applied to the semiconductor substrate, converting the amorphous metal silicide precursor film adjacent to the semiconductor substrate in situ into a gate dielectric layer. The mechanism of this step lies in the fact that by precisely controlling the injected plasma energy, the precursor film undergoes a selective chemical reaction with the reaction gas to form a dielectric.

[0015] The specific application method of the time-dynamically controlled radio frequency bias voltage is as follows: In the initial stage of the process, a radio frequency bias voltage with a frequency of 60-100MHz and a power of 10-40W is applied. The energy penetration depth of this high-frequency, low-power plasma is shallow, which is used to form a high-quality initial interface layer between the precursor film and the semiconductor substrate. Subsequently, the frequency of the radio frequency bias voltage is linearly or stepwise reduced from the initial value of 60-100MHz to 13.56MHz, while the power is linearly or stepwise increased from the initial value of 10-40W to 80-150W. This plasma with increasing energy is used to controllably advance the chemical reaction interface into the precursor film to form the main body of the gate dielectric layer with a predetermined thickness.

[0016] In one specific embodiment, the plasma used in this step is inductively coupled plasma, with a radio frequency source power of 300-800W and a reaction pressure of 5-20mTorr. The reaction gas is a mixture of oxygen, nitrogen, and argon, and the gate dielectric layer formed therefrom is metal oxynitride.

[0017] Bulk conductor phase transition: After completing step S3, within the same reaction chamber, the flow of oxygen- or nitrogen-containing reaction gas is stopped, and an inert gas environment is introduced. A low-frequency, high-power radio frequency bias is applied to the semiconductor substrate, converting the remaining amorphous metal silicide precursor film into a gate conductor in situ. The mechanism of this step is that by injecting high-energy inert gas ions, the energy required for crystallization of the amorphous precursor film is provided, inducing a solid-state phase transition, transforming it into a low-resistivity crystalline metal silicide without undergoing a chemical reaction.

[0018] The low-frequency, high-power radio frequency bias voltage has a frequency of 2-13.56MHz and a power of 200-600W. In one specific embodiment, when the amorphous metal silicide precursor film is an amorphous hafnium silicon film, the formed gate conductor is hafnium disilicide.

[0019] In one specific implementation, the plasma used in this step is inductively coupled plasma, with a radio frequency source power of 500-1000W and a reaction pressure of 5-20mTorr.

[0020] S4: Remove the gate dielectric layer and the gate conductor outside the trench to form a trench gate.

[0021] To precisely control the removal process, prior to S1, a silicon nitride hard mask layer is deposited on the surface of the semiconductor substrate, and an opening for defining the trench is formed by patterning. Accordingly, S4 is specifically performed by using a chemical mechanical polishing process, with the silicon nitride hard mask layer as the polishing stop layer, to remove the material.

[0022] This invention provides a method for fabricating a trench gate in a trench-type MOS device. It has the following advantages:

[0023] 1. This method employs a two-step continuous in-situ plasma conversion process to form the gate dielectric layer and gate conductor, with all core fabrication steps completed at low temperatures. This method replaces the high-temperature thermal oxidation and high-temperature annealing steps in traditional processes, significantly reducing the overall thermal budget for device manufacturing. This suppresses the redistribution of impurities in the already formed doped regions of the device, which is beneficial for the precise control of the final electrical parameters of the device.

[0024] 2. This method integrates the formation of the gate dielectric layer and the gate conductor into an in-situ processing of a single amorphous metal silicide precursor film. Compared to the multiple independent steps required by traditional methods for dielectric layer growth and conductor material deposition, this method simplifies the process flow, reduces wafer transfer between different devices, and lowers the possibility of contamination or defects at the interlayer interface.

[0025] 3. The gate conductor prepared by this method is a crystalline metal silicide. As a metallic conductor, this material does not exhibit the polycrystalline silicon depletion effect in its conductivity mechanism, thus avoiding the increase in the equivalent gate dielectric thickness and enhancing the gate's control over the channel. Simultaneously, the formed metal silicide has a lower resistivity compared to heavily doped polycrystalline silicon, reducing gate resistance and contributing to increased device operating frequency and reduced gate power consumption. Detailed Implementation

[0026] The technical solutions in the embodiments of the present invention will be clearly and completely described below. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0027] Example:

[0028] Example 1

[0029] This embodiment provides a method for fabricating a trench gate in a trench-type MOS device, and the specific steps are as follows:

[0030] Substrate preparation and trench etching:

[0031] In a P-shaped <100> A 200nm thick silicon nitride hard mask is deposited on a crystal-oriented silicon substrate using LPCVD at 780℃ and 350mTorr.

[0032] The silicon nitride hard mask was patterned using photolithography and etching, followed by trench etching using a Bosch process. The etching parameters were: ICP source power 2000W, substrate bias power 100W, and reaction pressure 25mTorr. This resulted in trenches with a depth of 5µm and a width of 1µm.

[0033] Amorphous metal silicide precursor thin film deposition:

[0034] The trenched wafer is fed into the ALD reaction chamber, and an amorphous hafnium silicon precursor film is conformally deposited at a deposition temperature of 300°C.

[0035] By controlling the ALD cycle ratio of the TDMAH source to the Si2H6 source to be 1:3, the atomic ratio of Hf to Si in the thin film is made to be 1:3. The total deposition thickness is 60 nm.

[0036] Dynamic energy injection in-situ conversion:

[0037] Programmable switching of the interface dielectric layer: The wafer is placed in an ICP reaction system, and a mixed gas of O2, N2, and Ar is introduced at a reaction pressure of 12 mTorr. The ICP source power is set to 550 W. A dynamically controlled RF bias is applied to the substrate: In the initial stage (0-30s), the frequency is 80MHz and the power is 25W; subsequently (30-150s), the frequency linearly decreases from 80MHz to 13.56MHz, while the power linearly increases from 25W to 115W. After this step, a 10nm thick HfSiON gate dielectric layer is formed.

[0038] Bulk conductor phase transition: Within the same reaction chamber, the flow of O2 and N2 is stopped, and only Ar gas is introduced. The ICP source power is increased to 750W. An RF bias voltage is applied to the substrate, with the frequency set to 7MHz and the power set to 400W, for a processing time of 120s. After this step, the remaining a-HfSix thin film is converted into a hafnium disilicide gate conductor.

[0039] Gate structure planarization:

[0040] Chemical mechanical polishing (CMP) was employed, using a silicon nitride hard mask layer as the polishing stop layer to remove HfSiON and HfSi2 outside the trenches. The polishing head pressure was 2.5 psi, and the rotation speed was 60 rpm.

[0041] Finally, the silicon nitride hard mask is removed by wet etching to complete the fabrication of the trench gate.

[0042] Example 2

[0043] This embodiment provides a method for fabricating a trench gate in a trench-type MOS device, and the specific steps are as follows:

[0044] Substrate preparation and trench etching:

[0045] In a P-shaped <100> A 150nm thick silicon nitride hard mask is deposited on a crystal-oriented silicon substrate using LPCVD at 700℃ and 200mTorr.

[0046] The silicon nitride hard mask was patterned using photolithography and etching, followed by trench etching using a Bosch process. The etching parameters were: ICP source power 1500W, substrate bias power 50W, and reaction pressure 10mTorr. This resulted in trenches with a depth of 2µm and a width of 0.5µm.

[0047] Amorphous metal silicide precursor thin film deposition:

[0048] The grooved wafer is fed into the ALD reaction chamber, and an amorphous titanium silicon precursor film is conformally deposited at a deposition temperature of 250°C.

[0049] By controlling the ALD cycle ratio of titanium source to silicon source to be 1:2, the atomic ratio of Ti to Si in the thin film is made to be 1:2. The total deposition thickness is 40 nm.

[0050] Dynamic energy injection in-situ conversion:

[0051] Programmable switching of the interface dielectric layer: The wafer is placed in an ICP reaction system, and a mixture of O2 and Ar gas is introduced at a reaction pressure of 5 mTorr. The ICP source power is set to 300 W. Dynamically controlled RF bias is applied to the substrate: In the initial stage (0-30s), the frequency is 60MHz and the power is 10W; subsequently (30-150s), the frequency decreases from 60MHz to 13.56MHz in steps, while the power increases from 10W to 80W in steps. After this step, a 5nm thick TiSiO gate dielectric layer is formed.

[0052] Bulk conductor phase transition: Within the same reaction chamber, O2 supply is stopped, and only Ar gas is introduced. The ICP source power is set to 500W. An RF bias voltage is applied to the substrate, with a frequency set to 2MHz and a power set to 200W, for a processing time of 180s. After this step, the remaining a-TiSix thin film is converted into a titanium disilicide gate conductor.

[0053] Gate structure planarization:

[0054] Chemical mechanical polishing (CMP) was employed, using a silicon nitride hard mask layer as the polishing stop layer to remove TiSiO and TiSi2 outside the trenches. The polishing head pressure was 1 psi, and the rotation speed was 30 rpm.

[0055] Finally, the silicon nitride hard mask is removed by wet etching to complete the fabrication of the trench gate.

[0056] Example 3

[0057] This embodiment provides a method for fabricating a trench gate in a trench-type MOS device, and the specific steps are as follows:

[0058] Substrate preparation and trench etching:

[0059] In a P-shaped <100> A 250nm thick silicon nitride hard mask is deposited on a crystal-oriented silicon substrate using LPCVD at 850℃ and 500mTorr.

[0060] The silicon nitride hard mask was patterned using photolithography and etching, followed by trench etching using a Bosch process. The etching parameters were: ICP source power 2500W, substrate bias power 150W, and reaction pressure 40mTorr. This resulted in trenches with a depth of 10µm and a width of 2µm.

[0061] Amorphous metal silicide precursor thin film deposition:

[0062] The grooved wafer is fed into the ALD reaction chamber, and an amorphous zirconium silicon precursor film is conformally deposited at a deposition temperature of 350°C.

[0063] By controlling the ALD cycle ratio of zirconium source to silicon source to be 1:4, the atomic ratio of Zr to Si in the thin film is made to be 1:4. The total deposition thickness is 80 nm.

[0064] Dynamic energy injection in-situ conversion:

[0065] Programmable switching of the interface dielectric layer: The wafer is placed in an ICP reaction system, and a mixture of N2 and Ar gases is introduced at a reaction pressure of 20 mTorr. The ICP source power is set to 800 W. A dynamically controlled RF bias is applied to the substrate: In the initial stage (0-30s), the frequency is 100MHz and the power is 40W; subsequently (30-150s), the frequency linearly decreases from 100MHz to 13.56MHz, while the power linearly increases from 40W to 150W. After this step, a 15nm thick ZrSiN gate dielectric layer is formed.

[0066] Bulk conductor phase transition: Within the same reaction chamber, N2 supply is stopped, and only Ar gas is introduced. The ICP source power is increased to 1000W. An RF bias voltage is applied to the substrate, with a frequency set to 13.56MHz and a power set to 600W, for a processing time of 60s. After this step, the remaining a-ZrSix thin film is converted into a zirconium disilicide gate conductor.

[0067] Gate structure planarization:

[0068] Chemical mechanical polishing (CMP) was employed, using a silicon nitride hard mask layer as the polishing stop layer to remove ZrSiN and ZrSi2 outside the trenches. The polishing head pressure was 4 psi, and the rotation speed was 90 rpm.

[0069] Finally, the silicon nitride hard mask is removed by wet etching to complete the fabrication of the trench gate.

[0070] Comparative Example

[0071] Compared with Example 1, Comparative Example 1 differs in that the dynamic control of the RF bias voltage is removed in the "programmable conversion of the interface dielectric layer" sub-step in step 3. Instead, a constant RF bias voltage parameter is used for processing. Specifically, the RF bias voltage frequency is constant at 13.56MHz and the power is constant at 50W throughout the entire processing time. The remaining steps and parameters are the same as in Example 1.

[0072] Compared with Example 1, Comparative Example 2 differs in that, in step 3, after completing the interface dielectric layer programmable conversion sub-step, the bulk conductor phase transition conversion sub-step is omitted, and the process directly proceeds to step 4, gate structure planarization. All other steps and parameters are the same as in Example 1.

[0073] Comparative Example 3 differs from Example 2 in that, in step 2, the deposited thin film material is not an amorphous titanium-silicon precursor film, but an amorphous silicon thin film of the same thickness deposited using the same atomic layer deposition process. The subsequent dynamic energy injection in-situ conversion treatment in step 3 is still applied to this amorphous silicon thin film according to the parameters of Example 2. All other steps and parameters are the same as in Example 2.

[0074] Comparative Example 4 differs from Example 2 in that the dynamic energy injection in-situ conversion process in step 3 is omitted and replaced with a rapid thermal annealing process. This rapid thermal annealing process is carried out in a nitrogen atmosphere at an annealing temperature of 500°C for 60 seconds. All other steps and parameters are the same as in Example 2.

[0075] Comparative Example 5 differs from Example 3 in that the two consecutive plasma in-situ conversion processes in step 3 are combined into a single plasma process. This single process is carried out in a mixed gas environment of nitrogen and argon, directly using the plasma parameters of the bulk conductor phase transition sub-step, with a total processing time of 150 seconds. The remaining steps and parameters are the same as in Example 3.

[0076] Comparative Example 6 differs from Example 3 in that the execution order of the two sub-steps in step 3 is reversed. That is, the bulk conductor phase transition sub-step is performed on the amorphous zirconium silicon precursor film first, and then the interface dielectric layer programmable transition sub-step is performed on it. The remaining steps and parameters are the same as in Example 3.

[0077] Test Example 1: Comparative Test of Insulation Performance of Gate Dielectric Layer

[0078] Experimental instructions

[0079] To evaluate the electrical insulation properties of the gate dielectric layer in trench gate structures prepared by different methods, gate leakage current and breakdown voltage were tested on samples prepared in Examples 1-3 and Comparative Examples 1, 5, and 6. The tests were performed on a wafer-level probe station using a semiconductor parameter analyzer. Twenty test structures were randomly selected from each wafer for measurement to obtain statistical data.

[0080] Experimental steps:

[0081] Sample preparation: Place the prepared wafer on the sample tray of the probe station and fix it under vacuum adsorption.

[0082] Probe contact: With the aid of a microscope, the probe is precisely contacted with the gate test pad and the substrate ground terminal of the trench gate structure under test, respectively.

[0083] Gate leakage current test:

[0084] Test parameters were set as follows: A constant DC voltage was applied between the gate and the substrate. For the samples of Examples 1, 2, 3 and Comparative Examples 1, 5, 6, the applied test voltage was 5V.

[0085] Measurement: After applying voltage, allow 3 seconds for stabilization and record the current flowing through the gate. Divide this current value by the gate area to calculate the gate leakage current density.

[0086] Breakdown voltage test:

[0087] Set the test parameters: Apply a positive ramp scan voltage to the gate starting from 0V at a rate of 0.1V / s. Set the current compliance value to 1mA / cm², and stop the scan when the measured gate leakage current density reaches this value.

[0088] Perform the measurement: Record the voltage value when the scan stops; this value is defined as the breakdown voltage of the gate dielectric layer.

[0089] Data logging: Repeat steps 3 and 4 for 20 test points on each wafer and record all data for subsequent analysis.

[0090] The experimental data are shown in Table 1.

[0091] Table 1 Test data of gate dielectric layer insulation performance

[0092]

[0093] Test Example 2: Comparative Test of Gate Conductor Conductivity

[0094] Experimental instructions

[0095] To evaluate the electrical conduction characteristics of gate conductors prepared by different methods, sheet resistance tests were performed on samples from Examples 1-3 and Comparative Examples 2, 3, and 4. The tests were conducted on specially designed van der Burg test structures after the gate structure planarization step during wafer fabrication. A four-probe tester was used. Twenty test structures were randomly selected from each wafer for measurement to obtain statistical data.

[0096] Experimental steps:

[0097] Sample preparation: Place the wafer that has completed the chemical mechanical polishing step on the sample stage of the four-probe tester.

[0098] Probe positioning: The four-probe test head is precisely positioned in the central area of ​​the van der Burg test structure using an optical system.

[0099] Parameter settings: Set the test current to 1mA. The instrument will automatically perform a current-voltage scan to determine the film resistance.

[0100] Execute the measurement: Start the measurement program. The instrument applies a set current through the two outer probes, while simultaneously measuring the voltage difference between the two inner probes, and automatically calculates the thin-film resistance value according to the van der Berg equation.

[0101] Data logging: Repeat step 4 for each of the 20 test points on each wafer and record all measurement data for subsequent analysis.

[0102] The experimental data are shown in Table 2.

[0103] Table 2 Test data of gate conductor conductivity

[0104]

[0105] The test data in Table 2 show that the samples prepared by the methods of Examples 1, 2, and 3 have a sheet resistance of gate conductors ranging from 13 Ω / sq to 23 Ω / sq. In contrast, the samples prepared by the methods of Comparative Examples 2, 3, and 4 have sheet resistances of 10 Ω / sq and 13 Ω / sq, respectively. 5 Ω / sq, 10 4 Ω / sq and 10 2 The order of magnitude is Ω / sq.

[0106] The above data demonstrate that the bulk conductor phase transition step is the decisive step in forming a low-resistivity gate conductor. In this step, a low-frequency, high-power radio frequency bias applied in an inert gas environment provides the atoms in the amorphous metal silicide precursor film with the energy required for a solid-state phase transition through the physical implantation of high-energy ions. This promotes in-situ crystallization at low temperatures, forming a crystalline metal silicide with low resistivity. The low sheet resistance values ​​measured in Examples 1, 2, and 3 directly reflect the effectiveness of this physical mechanism.

[0107] The test results of Comparative Examples 2, 3, and 4 corroborate the technical configuration of the method of the present invention from different perspectives. Comparative Example 2, which omits the bulk conductor phase transition step, exhibits extremely high sheet resistance values, indicating that the remaining precursor film, untreated by this step, remains in a highly resistive amorphous state. Comparative Example 3, using amorphous silicon as the precursor, shows a significantly higher sheet resistance than the examples even with the same plasma treatment, demonstrating that using metal silicide precursors is the material basis for forming low-resistivity conductors. Comparative Example 4, employing rapid thermal annealing instead of plasma treatment, yields sheet resistances two orders of magnitude higher than the examples. This indicates that at low temperatures, the energy provided by bulk heating is insufficient to drive complete crystallization of the precursor film, further confirming the specific role of high-energy plasma injection in the induced phase transition process.

[0108] Test Example 3: Comparative Test of Basic Electrical Characteristics of Trench MOS Devices

[0109] Experimental instructions

[0110] To evaluate the overall electrical performance of trench MOS devices fabricated using different gate fabrication methods, electrical characteristics were tested on the complete devices fabricated in Examples 1-3 and Comparative Examples 1-6. The tests were performed on a wafer-level probe station using a semiconductor parameter analyzer. Twenty devices were randomly selected from each wafer for measurement to obtain statistical data.

[0111] Experimental steps:

[0112] Sample preparation: Place the wafer that has completed all preparation steps on the sample tray of the probe station and fix it by vacuum adsorption.

[0113] Probe contact: With the aid of a microscope, the probes are precisely contacted onto the test pads of the source, drain, gate, and substrate electrodes of the trench MOS device under test.

[0114] Threshold voltage test:

[0115] Set the test parameters: Set the drain voltage to 0.1V. Scan the gate voltage from 0V to 5V in steps of 0.05V.

[0116] Measurements were performed: The drain current corresponding to each gate voltage step was recorded to form the Id-Vg transfer characteristic curve. A linear extrapolation method was used to extrapolate from the linear region of the curve to the intercept on the horizontal axis where the current is zero. This intercept value was defined as the threshold voltage of the device.

[0117] Device functional verification:

[0118] Set the test parameters: Increase the gate voltage in 1V increments, from 1V to 5V. For each fixed gate voltage, scan the drain voltage from 0V to 5V.

[0119] Measurement: Record the drain current as a function of drain voltage under different gate voltages to form a family of Id-Vd output characteristic curves. Observe whether the family of curves has a clear linear region and saturation region to determine whether the device has normal gate control capability.

[0120] The experimental data are shown in Table 3.

[0121] Table 3 Test data of basic electrical characteristics of trench MOS devices

[0122]

[0123] The test data in Table 3 show that the devices prepared by the methods in Examples 1, 2, and 3 all exhibited normal device functionality, and their threshold voltages were distributed within the range of 2.4V to 2.8V. In contrast, the samples in Comparative Examples 2, 3, 5, and 6 could not extract threshold voltages and did not possess effective device functionality; the sample in Comparative Example 4 had weak gate control capability; and although the sample in Comparative Example 1 functioned normally, its threshold voltage shifted compared to the examples.

[0124] The above data indicates that the two-step continuous plasma in-situ conversion process provided by this invention is the direct reason for constructing a functional trench gate structure. This method first forms a gate dielectric layer with specific insulating properties on the surface of a semiconductor substrate through a programmable interface dielectric layer conversion step; then, through a bulk conductor phase transition conversion step, the remaining precursor film is transformed into a low-resistivity gate conductor. These two steps together constitute a complete gate stack, enabling the gate voltage to effectively control the carrier concentration in the channel region, thereby achieving normal transistor switching function.

[0125] The test results of the comparative samples confirmed the specific effects of each technical feature in the method of the present invention. Comparative Examples 2, 3, and 4, due to the failure to form a low-resistivity gate conductor, resulted in the gate voltage not being effectively applied across the entire channel, exhibiting no gate control capability or weak gate control capability. Comparative Examples 5 and 6, due to the failure to form an effective gate dielectric layer or the disruption of the dielectric layer's integrity, resulted in a conductive path between the gate and the substrate, causing the devices to exhibit short circuits. Comparative Example 1, because it did not utilize dynamic control of the RF bias, resulted in a high interface state density between the formed dielectric layer and the semiconductor substrate, causing a shift in the device's threshold voltage.

Claims

1. A method for fabricating a trench gate in a trench-type MOS device, characterized in that, Includes the following steps: S1: Trench is formed by etching in a semiconductor substrate; S2: An amorphous metal silicide precursor film is conformally deposited in the trench using an atomic layer deposition process, wherein the atomic ratio of metal to silicon in the amorphous metal silicide precursor film is controlled to be 1:2 to 1:4 by adjusting the cycle ratio of metal source to silicon source in the atomic layer deposition process. S3: Perform a two-step continuous in-situ plasma conversion process on the amorphous metal silicide precursor film: Programmable conversion of the interface dielectric layer: In an environment containing oxygen or nitrogen reaction gas, a radio frequency bias voltage that is dynamically controlled over time is applied to the semiconductor substrate to convert the amorphous metal silicide precursor film adjacent to the semiconductor substrate into a gate dielectric layer in situ; wherein, the dynamic control includes: applying a radio frequency bias voltage with a frequency of 60-100MHz and a power of 10-40W in the initial stage, and then reducing the frequency and increasing the power; Bulk conductor phase transition: In an inert gas environment, a low-frequency, high-power radio frequency bias is applied to the semiconductor substrate to convert the remaining amorphous metal silicide precursor film into a gate conductor in situ; wherein the frequency of the low-frequency, high-power radio frequency bias is 2-13.56MHz and the power is 200-600W. S4: Remove the gate dielectric layer and the gate conductor outside the trench to form a trench gate.

2. The method according to claim 1, characterized in that, In step S2, the material of the amorphous metal silicide precursor film is selected from one of amorphous hafnium silicon film, amorphous titanium silicon film, or amorphous zirconium silicon film.

3. The method according to claim 1, characterized in that, In S2, the deposition temperature of the atomic layer deposition process is 250-350℃.

4. The method according to claim 1, characterized in that, In S3, the specific method of dynamically adjusting the radio frequency bias voltage over time is as follows: the frequency of the radio frequency bias voltage is linearly or stepwise reduced from an initial value of 60-100MHz to 13.56MHz, while the power is linearly or stepwise increased from an initial value of 10-40W to 80-150W.

5. The method according to claim 1 or 4, characterized in that, In step S3, the reaction gas is a mixture of oxygen, nitrogen, and argon, and the gate dielectric layer is metal oxynitride.

6. The method according to claim 1, characterized in that, In S3, the plasma used for the programmable conversion processing of the interface dielectric layer is inductively coupled plasma, with a radio frequency source power of 300-800W and a reaction pressure of 5-20mTorr.

7. The method according to claim 2, characterized in that, In step S3, when the amorphous metal silicide precursor film is an amorphous hafnium silicon film, the gate conductor is hafnium disilicide.

8. The method according to claim 1, characterized in that, In S3, the plasma used for the bulk conductor phase transition conversion process is inductively coupled plasma, with a radio frequency source power of 500-1000W and a reaction pressure of 5-20mTorr.

9. The method according to claim 1, characterized in that, Before step S1, the method further includes: depositing a silicon nitride hard mask layer on the surface of the semiconductor substrate and forming an opening for defining the trench by patterning.

10. The method according to claim 9, characterized in that, The specific method of S4 is as follows: using a chemical mechanical polishing process, with the silicon nitride hard mask layer as the polishing stop layer, to remove the gate dielectric layer and the gate conductor outside the trench.

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