Semiconductor module

Abstract

A semiconductor module includes: an insulator substrate; a first metallization layer disposed at the insulator substrate; two or more controllable semiconductor elements disposed on a surface of the first metallization layer, each controllable semiconductor element including a gate electrode, a first load electrode, and a second load electrode; a control current path between the gate electrode and the first load electrode; a controllable load current path between the first load electrode and the second load electrode; and a first circuit element arranged between the control current path and the load current path.

Description

Technical Field

[0001] This disclosure relates to a semiconductor module. Background Technology

[0002] Power semiconductor modules typically include at least one semiconductor substrate disposed within a housing. A semiconductor device comprising multiple controllable semiconductor elements (e.g., IGBTs, MOSFETs, HEMTs, etc.) is disposed on each of the at least one substrate. Each substrate typically includes a substrate layer (e.g., a ceramic layer) serving as an insulating layer and a first metallization layer deposited on a first side of the substrate layer. The substrate and insulating layer may be referred to as an insulating substrate. The controllable semiconductor elements are mounted, for example, on the first metallization layer. In many applications, two or more individual controllable semiconductor elements are electrically coupled in parallel to each other to meet requirements regarding the current capability of the device. However, oscillations can occur when the parallel-coupled controllable semiconductor elements are turned on and off. One type of oscillation that can occur is so-called inter-chip oscillation, where oscillations are caused by the interaction of the parasitic capacitance of a controllable semiconductor element with the parasitic inductance present between the respective controllable semiconductor elements. Another type of oscillation is the oscillation between the output capacitance of a switch and the parasitic inductance in the commutation unit (typically the sum of chip interconnect inductance, package lead inductance, busbar inductance, and DC link capacitor inductance). Such oscillations can lead to EMI (electromagnetic interference) problems.

[0003] Therefore, a semiconductor module is typically required in which oscillations are significantly reduced, and in particular, inter-chip oscillations are significantly reduced. Summary of the Invention

[0004] According to a first aspect of this disclosure, a semiconductor module includes: an insulating substrate; a first metallization layer disposed on the insulating substrate; two or more controllable semiconductor elements disposed on the surface of the first metallization layer, each controllable semiconductor element including a gate electrode, a first load electrode and a second load electrode; a controllable current path between the gate electrode and the first load electrode; a controllable load current path between the first load electrode and the second load electrode; and a first circuit element disposed between the control current path and the load current path.

[0005] This disclosure provides one or more centrally located or non-centrally located first circuit elements arranged between the gate and source, all within the gate-source current path within the semiconductor module, to avoid or mitigate undesirable oscillations caused by geometric and / or electrical asymmetries within the semiconductor module. This disclosure reduces electrical asymmetries or the geometric asymmetries that cause them. This can be achieved by using appropriately designed first circuit elements configured to balance electrical asymmetries in the layout. Consequently, controllable groups of semiconductor elements within the semiconductor module can be decoupled, and dynamic current misdistribution effects can be reduced.

[0006] According to a first aspect, the semiconductor module includes an insulating substrate, wherein the insulating substrate may consist of a substrate and an insulating layer. The insulating layer may be disposed on the substrate or on top of the substrate. A first metallization layer may be disposed on the top side plane of the insulating substrate to form a conductive structure. The conductive structure may form a current path that can be connected to a controllable semiconductor element. The controllable semiconductor element may be a switch including a load current path and a control current path for controlling the load current path. A first circuit element may be disposed on the substrate, or different portions or structures on the substrate may be connected to each other. The first circuit element may be coupled between a gate electrode and a first load electrode, the first load electrode being a source / emitter electrode on the substrate level. By implementing the first circuit element on the substrate level, parasitic effects caused by contact pins and / or bonding wires can be reduced. The term "substrate level" may be used to describe the interior of a semiconductor module in relation to this disclosure.

[0007] In one embodiment, the first metallization layer includes a gate segment, a second segment, and at least a third segment, and the semiconductor module further includes a plurality of first electrical connection elements, wherein the gate electrode of each of two or more controllable semiconductor elements is electrically coupled to the gate segment through one or more of the first electrical connection elements, wherein the first load electrode of each of the two or more controllable semiconductor elements is electrically coupled to the second segment through one or more of the first electrical connection elements, and wherein the second load electrodes of the two or more controllable semiconductor elements are electrically coupled to the third segment through a conductive connection layer.

[0008] The first metallization layer can be disposed on an insulating substrate and can include segments at various potentials. Specifically, the metallization layer includes a gate segment, a second segment (the second segment can be a source / emitter segment), and a third segment (the third segment can be a drain or collector segment). A controllable semiconductor element is coupled to and can be controlled by the gate segment. Therefore, the gate electrode of each controllable semiconductor element is coupled (i.e., electrically bonded) to the gate segment. The first electrical connection element can be, for example, a bonding wire, a clamp, a layered structure, etc.

[0009] In one embodiment, the first circuit element may be arranged between the gate segment and the second segment.

[0010] Specifically, the first circuit element can be electrically coupled between the gate segment and the second segment of the metallization layer, where the second segment can be the source / emitter segment of the metallization layer. Therefore, electrical coupling can be achieved between the two segments.

[0011] Specifically, the gate segment can be at the gate potential, and the second segment can be at a source / emitter potential different from the gate potential.

[0012] In one embodiment, the load current path is formed between the second segment and the third segment.

[0013] In one embodiment, a first circuit element is disposed on top of a first metallization layer. The first circuit element may be disposed on a substrate layer as part of the metallization layer or as a separate portion on top of the metallization layer. The first circuit element may be part of the substrate and / or may be part of the layer structure of a multilayer substrate.

[0014] In one embodiment, the first circuit element is a passive element. The term "passive element" refers to a type of electronic component that does not require an external power source to operate and / or does not require an external control path to operate. Instead, it can respond to or transmit electrical signals without adding energy to the circuit. Passive elements are fundamental building blocks in electronic circuits and contrast with active elements, which can introduce power gains. Some common examples of passive elements include resistors, capacitors, inductors, and transformers. However, active snubber circuits are also possible.

[0015] In one embodiment, the passive component is impedance. Impedance is a measure of the barrier a circuit provides to the flow of alternating current (AC). It is a complex number that includes both resistance and reactance. Resistance, measured in ohms, represents the barrier to the flow of current in a direct current (DC) circuit, while reactance, arising from the effects of capacitance and inductance, is also measured in ohms.

[0016] Impedance can be at least one of a capacitor, resistor, or inductor. As an alternative to a capacitor, an impedance can also typically be inserted into the gate-source path. These impedances (e.g., additional gate resistors) are used asymmetrically, as in the example of a capacitor, to suit the switching characteristics of the subsystem or secondary subsystem and to avoid or reduce oscillations.

[0017] Typically, asymmetric compensation can be performed for both capacitors and impedances. That is, the additional passive components are not symmetrically distributed across all the chips in the parallel circuit, but are specifically (asymmetrically) used for a particular subsystem (secondary subsystem), which itself is a parallel circuit or a single chip.

[0018] If the passive component is a capacitor, the additional capacitance introduced can be on the order of 10% of the (total) capacitance to avoid an excessive increase in total losses.

[0019] If the passive component is an additional gate resistor, the additional ohmic resistance can be on the order of 10% of the (total) resistance to avoid an excessive increase in total losses. In this case, both the external and internal gate resistors are considered as references.

[0020] While the additional capacitance primarily affects the turn-on behavior and thus di / dt, the turn-off behavior (in the case of a MOSFET) and dv / dt can also be controlled by the additional gate resistor. Regardless of the prescribed guidelines for the selection of capacitor and resistor values, much larger or even smaller values ​​can be implemented if a corresponding reduction in oscillation can be achieved as a result.

[0021] In one embodiment, the gate segment includes at least a first sub-segment and a second sub-segment, wherein the first sub-segment and the second sub-segment are electrically isolated from each other, and wherein the sub-segments are connected by a second circuit element.

[0022] The gate segment can be subdivided into several sub-segments, for example, subdivided into gate islands. The sub-segments can be electrically connected to each other again via a second circuit element. The second circuit element can also be a passive element.

[0023] Specifically, the second circuit element can be an inductor, particularly a wire or coil. The gate islands (i.e., sub-segments) can be connected by wires. These wires have resistance, but also unavoidable inductance. The wires and the sub-segments of the gate islands are at the same potential and form a gate current path. The first circuit element can be applied as needed to counteract the undesirable effects of the unavoidable second circuit element.

[0024] In one embodiment, the first segment includes a third sub-segment connected to the second sub-segment via a second circuit element, and wherein the control current path is formed to start at the first sub-segment of the gate segment, pass through the second and third sub-segments, and then through the second circuit element to the gate electrode.

[0025] In one embodiment, each sub-segment controls at least two controllable semiconductor elements, wherein the semiconductor elements are connected in parallel with each other via the respective sub-segments. This provides a high-inductance gate connection between the oscillating pairs of controllable semiconductor elements, thereby ensuring additional damping between the oscillating elements. This drives the effective gate inductance between the chips to a higher value, thus stabilizing the system.

[0026] In one embodiment, a first sub-segment is connected to a second segment via a first first circuit element, particularly via a first capacitor, and / or wherein a second sub-segment is connected to a second first circuit element, and / or wherein a third sub-segment is coupled to a second segment via a third first circuit element. Various “gate intersections” can be formed along the gate current path by sequentially connecting the gate sub-segments with wires. Each “intersection” can be electrically connected to a subset of controllable semiconductor elements to connect them in parallel. Thus, a subsystem is formed within a set of semiconductor elements, and each subsystem receives a separate gate-source capacitor or gate-source impedance. This type of transition allows switching asymmetry (caused by a magnetic field) within a subsystem to be avoided by reducing the switching speed of the individual subsystems. If multiple components are connected in parallel and these components are in contact via a bonding connection (stitching), additional gate-source capacitors / impedances can be attached to each component to compensate for the accelerating effect of the gate inductance.

[0027] In one embodiment, a first subset of controllable semiconductor elements is arranged symmetrically with respect to a second subset of controllable semiconductor elements on an insulating substrate. By introducing geometric symmetry into the layout of the semiconductor module, electrical symmetry is typically enhanced. By enhancing electrical symmetry, undesirable constructive interference effects from oscillating adjacent controllable semiconductor elements are reduced.

[0028] In one embodiment, the first circuit element is a capacitor that is welded, sintered, clamped, glued, or conductively coupled between the gate potential and the source potential.

[0029] In one embodiment, the capacitor is integrated on and in contact with the surface of the additional substrate, or the capacitor is formed of the additional substrate (metal-insulator-metal) and integrated into the semiconductor module.

[0030] In one embodiment, the surface of the additional substrate is an additional welded substrate or a sintered substrate.

[0031] In one embodiment, the controllable semiconductor element is at least one of GaN HEMT, SiC MOSFET, Si IGBT, and Si MOSFET.

[0032] The invention can be better understood by referring to the following figures and description. The components in the figures are not necessarily drawn to scale, but rather the focus is on illustrating the principles of the invention. In the figures, the same reference numerals denote corresponding parts in different views. Attached Figure Description

[0033] In the accompanying figures, this disclosure is shown by way of example and not limitation, wherein the same reference numerals refer to similar or identical elements. Elements in the figures are not necessarily drawn to scale relative to each other. Features of the various illustrated examples can be combined unless they are mutually exclusive.

[0034] Figure 1 This is a schematic circuit diagram of one embodiment of the present disclosure.

[0035] Figure 2 This is a schematic side view of one embodiment.

[0036] Figure 3 This is an illustrative exemplary embodiment of the present disclosure.

[0037] Figure 4 yes Figure 3 Another illustrative exemplary embodiment of the disclosed embodiments.

[0038] Figure 5A This is an exemplary high-side implementation.

[0039] Figure 5B This is an exemplary low-side embodiment.

[0040] Figure 6 This is another lower-side embodiment with two subsystems.

[0041] Figure 7 This is another lower-side embodiment illustrating two secondary subsystems.

[0042] Figure 8 is another embodiment of this disclosure. Detailed Implementation

[0043] In the following detailed description, reference is made to the accompanying drawings. The drawings illustrate specific examples in which the invention can be practiced. It should be understood that, unless otherwise specifically stated, the features and principles described with respect to the various examples can be combined with each other. Similarly, the use of terms such as “first element,” “second element,” “third element,” etc., in the claims should not be construed as an enumeration. Rather, such names are used only to refer to different “elements.” That is, for example, the presence of a “third element” does not require the presence of a “first element” and a “second element.” The electrical circuit described herein may be a single conductive element or may comprise at least two separate conductive elements connected in series and / or in parallel. The electrical circuit may comprise metallic and / or semiconductor materials and may be permanently conductive (i.e., non-switchable). The electrical circuit may have a resistivity independent of the direction of the current flowing through it. The semiconductor body described herein may be made of (doped) semiconductor material and may be a semiconductor chip or included in a semiconductor chip. The semiconductor body has electrically connected pads and includes at least one semiconductor element having electrodes. The pads are electrically connected to the electrodes, which includes the pads being electrodes and vice versa.

[0044] Although specific examples have been shown and described herein, those skilled in the art will understand that various alternatives and / or equivalent embodiments may be implemented in place of the specific examples shown and described without departing from the scope of the invention. This application is intended to cover any modifications or variations of the specific examples discussed herein. Therefore, the invention is intended to be limited only by the claims and their equivalents.

[0045] It should be noted that the methods and apparatus outlined in this document (including preferred embodiments of the methods and apparatus) can be used independently or in combination with other methods and apparatus disclosed in this document. Furthermore, features outlined in the context of the apparatus can also be applied to the corresponding methods, and vice versa. Moreover, all aspects of the methods and apparatus outlined in this document can be combined arbitrarily. In particular, the features of the claims can be combined with each other in any manner.

[0046] It should be noted that the specification and accompanying drawings only illustrate the principles of the proposed methods and systems. Those skilled in the art will be able to implement various arrangements, which, although not explicitly described or shown herein, embody the principles of the invention and are included within its spirit and scope. Furthermore, all examples and embodiments outlined in this document are primarily and explicitly intended for illustrative purposes only to aid the reader in understanding the principles of the proposed methods and systems. Moreover, all statements herein used to provide the principles, aspects, and embodiments of the invention, as well as specific examples thereof, are intended to cover their equivalents.

[0047] refer to Figure 1The circuit diagram illustrating the principles of this disclosure is shown. The semiconductor (power) module 1 includes a controllable semiconductor element 2. The semiconductor element 2 has a gate connector 3, a source connector 4, and a drain connector 5. A gate series resistor 6 or an additional gate resistor (R) is provided. GVOR Impedance 7 is arranged in the gate current path. Impedance 7 is arranged between the gate potential and the source potential. That is, impedance 7 is coupled to the gate path between the gate connector 3 and the gate series resistor 6 of the controllable semiconductor element 2 on one side, and coupled to the source potential on the other side, i.e., the source connector 4. Impedance 7 can be one of a resistor, coil, inductor, or capacitor. At the substrate level, impedance 7 is typically arranged within module 1.

[0048] Figure 2 yes Figure 1 The schematic side view of the embodiment illustrates an exemplary implementation of one aspect of this disclosure at the substrate level.

[0049] Semiconductor module 1 includes an insulating substrate 8. The insulating substrate consists of an insulating layer 9 and a substrate 10. Alternatively, the substrate may be an insulator. In embodiments of this disclosure, the substrate may consist of a back metallization layer, a ceramic insulator, and a front metallization layer. The insulating layer 9 covers the substrate 10. A first metallization layer 11 (which may correspond to the front metallization layer) is disposed at the insulating layer 9. The metallization layer 11 may form a lead frame and includes a gate segment 12, a second segment 13 which may be a source or emitter segment, and a third segment 14. The third segment 14 acts as a die pad for attaching a controllable semiconductor element 2. The third segment 14 may be a DC- / + segment or an AC segment. The segments are isolated from each other. Trench 15 is formed between the segments, wherein the bottom of each trench is the top side surface of the insulating layer 9. The controllable semiconductor element 2 is arranged and electrically bonded to the third segment 14 via a layer structure 16 with its lower surface. Layer structure 16 can be a die-attach adhesive, such as epoxy resin, including additives such as silver foil, reactive epoxy resin diluents or solvents, and catalysts. Alternatively, layer structure 16 can be metal solder, sintering paste or film, or a preform. The lower surface of the controllable semiconductor element 2 is a drain / collector connector / electrode.

[0050] The controllable semiconductor element 2 also includes a gate electrode 17 and a source electrode 18. The gate electrode 17 is coupled to the gate segment 12 via a second circuit element 23. The source electrode 18 is coupled to the second segment 13 via one or more first electrical connection elements 19. Thus, a gate current path is formed that starts at the gate segment 12 and extends via the second circuit element 23 to the gate electrode 17 of the corresponding controllable semiconductor element 2. A load current path is formed that starts at the second segment 13 and extends via the first electrical connection element 19 toward the source electrode 18 of the controllable semiconductor element 2, thereby enabling load current to flow between the second segment and a third segment, which can be DC+ or AC, depending on whether the controllable semiconductor element 2 is arranged on the high side or the low side.

[0051] Impedance 7 is arranged between gate segment 12 and second segment 13. In the present case, impedance is the capacitor between the load current path and the gate current path.

[0052] The capacitor 7 is disposed on top of the first metallization layer 11 in the gate-source current path. Top means that the capacitor is not part of the metallization layer, but a separate element connecting different sections of the metallization layer. Alternatively, the capacitor 7 may be disposed in the trench 15, or as an additional bonding substrate disposed on one of the gate section 12 or the second section 13.

[0053] Figure 3 This is another illustrative exemplary embodiment of the semiconductor module 1 according to the present disclosure. The semiconductor module 1 includes a plurality of controllable semiconductor elements 2. The controllable semiconductor elements 2 are subdivided into a first group 20 and a second group 21. The arrangement of the semiconductor elements 2 in the first group 20 is generally symmetrical to the arrangement of the semiconductor elements 2 in the second group 21.

[0054] Both groups are connected to the central gate segment 12, which may be a central gate island formed within the first metallization layer 11 (not shown).

[0055] Typically, the gate segment 12 at the metallization layer 11 is subdivided into several sub-segments. Figure 3 In this configuration, the central gate segment 12 is the first sub-segment G1 of the gate segment. Following the first sub-segment G1 are the second sub-segment G2 and the third sub-segment G3. Sub-segments G2 and G3 are sequentially connected to the central gate segments G1 and G2, forming part of the control current path. The second and third sub-segments G2 and G3 are each connected to at least one pair of controllable semiconductor elements 2. Each sub-segment is electrically connected to the gate electrode 17 of the corresponding semiconductor element 2 in the corresponding pair via a second circuit element 23.

[0056] Both groups 20 and 21 are connected to the central source pole segment 13, which serves as the central source pole island. Source pole segment 13 corresponds to... Figure 2 The second segment 13. Source segment 13 is electrically connected via a first electrical connection element 19 to the source island surrounding both the second sub-segment G2 and the third sub-segment G3 of the gate island 12. The source island is electrically insulated from the gate segments G1-G3 and is at the source potential. The source island is about Figure 2 Part of the second section 13 described.

[0057] The source island is connected to the source electrode 18 of the controllable semiconductor element 2 via a first electrical connection element 19 (e.g., via a bonding wire). The source electrode 18 is the first load electrode and forms part of the load current path.

[0058] A first circuit element (which can be any type of impedance 7) is arranged between the central gate section 12 and the central source section 13. Figure 3 In the diagram, the impedance is capacitor 22. Capacitor 22 is coupled between the control current path and the load current path.

[0059] When capacitor 22 is coupled between the central gate island and the central source island, the capacitor constitutes a delay, damping, and stabilizing element between the control current path and the load current path. This reduces electrical asymmetry that could cause undesirable oscillations, which might be at least partially caused by geometric asymmetry.

[0060] If the switch is a GaN HEMT, the capacitor is located in the gate RC link. GaN HEMTs may also include additional buffer circuitry between the gate electrode and the source electrode.

[0061] Figure 4 It shows Figure 3 It is part of the control current path. The central gate sections G1 and G2 are connected in series to the gate sub-sections G2 and G3 via the second circuit element 23. Each of the gate sub-sections G2 and G3 provides a control current to the gate electrode 17 of at least one pair of substantially symmetrically arranged controllable semiconductor elements 2. Each of the gate sub-sections G2 and G3 can be coupled to the surrounding source potential via the first circuit element 22.

[0062] The subsystem of semiconductor element 2 is defined by the location of impedance 7 in the control current path. Thus, the subsystem of multiple semiconductor elements 2 is defined by any subgroup of controllable semiconductor elements 2, which, from the perspective of impedance 7, is located further downstream in the control current path.

[0063] As an example, in Figure 3In this configuration, impedance 7 is arranged such that the central gate island 12 is connected to the source potential, i.e., the source island 13. Subsequently, all controllable semiconductor elements 2 located further "downstream" (i.e., closer to the gate electrode 17 of the corresponding controllable element 2) are affected by the impedance, thus forming the electrical subsystem of the semiconductor module 1. The electrical characteristics and location of impedance 7 can be selected depending on the need to eliminate undesirable effects caused by electrical asymmetry.

[0064] As another example, in Figure 4 In this configuration, an impedance 7 (which may be a capacitor 22) can be arranged such that the first sub-segment G1 is coupled to the source potential. Thus, all the semiconductor elements 2 shown form a common subsystem corresponding to the first and second groups 20, 21. If an additional impedance, i.e., another capacitor 22, is arranged between the second gate sub-segment G3 and the source potential, the semiconductor elements are divided into a first subsystem 24 and a second subsystem 25. The first subsystem 24 includes two symmetrically arranged downstream semiconductor elements 2 as seen from the second sub-segment G2. The second subsystem 25 includes four symmetrically arranged downstream semiconductor elements 2 as seen from the third sub-segment G3.

[0065] Figure 5A This is an exemplary high-side embodiment according to a first aspect of this disclosure. Semiconductor element 2 is coupled to a third segment 14 of metallization layer 11 via a first load electrode 5, which is at a DC+ potential in the high-side arrangement. Source electrode 18 is coupled to a source potential, such as AC, via a first electrical connection element 19, i.e., coupled to a second segment 13. A load current path is formed between the source electrode 18 and the first load electrode 5. The load current path can be controlled by a gate current path. Metallization layer 11 has a gate segment 12. The gate segment at the gate potential is subdivided into a first sub-segment G1 and two second sub-segments G2. Each sub-segment G2 is connected to sub-segment G1 via a second circuit element 23, which is a wire in this case. Sub-segment G1 forms a central gate island. Sub-segment G1 is connected to the second segment 13 at the source potential via a capacitor 22. The capacitor 22 thereby links the gate current path to the load current path. Because capacitor 22 is positioned centrally, i.e., at the beginning of the gate current path, it affects the behavior of all electrical components further downstream in the gate current path (particularly the second circuit element 23). Therefore, the switching behavior of all the plurality of controllable semiconductor elements 2 (i.e., the first group 20 and the second group 21 of controllable semiconductor elements 2) is influenced by a central impedance / capacitor 22.

[0066] Figure 5B It corresponds to Figure 5AAn exemplary low-side embodiment of the high-side embodiment. Semiconductor element 2 is coupled to a third segment 14 of metallization layer 11 via a first load electrode 5, which is at an AC potential in the low-side arrangement. The source electrode 18 of the controllable semiconductor element 2 is coupled to a source potential, i.e., coupled to a second segment 13, via a first electrical connection element 19, which is at a DC potential in the low-side arrangement. Gate segment 12 is subdivided into a first sub-segment G1, a second sub-segment G2, and a third sub-segment G3, which are arranged in parallel on each side. Sub-segments G1-G3 are connected in series with each other via wires 23, thereby forming a gate current path. A capacitor 22 is arranged between the central gate island 12, G1, and the central second segment 13. The central second segment 13 forms a source island.

[0067] Figure 6 This is another low-side embodiment with two subsystems. A first subsystem 24 is formed by arranging a first-stage capacitor 22a within a first group 20 of controllable semiconductor elements 2 between a gate sub-section G2 and a source sub-section 13. The first subsystem 24 includes the controllable semiconductor elements 2 of the first group 20. A second subsystem 25 is formed by arranging a first-stage capacitor 22a within a second group 21 of controllable semiconductor elements 2 between a second gate sub-section G2 and a source sub-section. Therefore, the second subsystem 25 includes the controllable semiconductor elements 2 of the second group 21.

[0068] Figure 7 This is another embodiment with two secondary subsystems. The first subsystem 24, comprising the controllable semiconductor element 2 of the first group 20, is further subdivided into a first-stage subsystem 26 and a second-stage subsystem 27. The first-stage subsystem 26 is formed by arranging a first-stage capacitor 22a between the second gate sub-section G2 and the source sub-section 13. The second-stage subsystem 27 is formed by arranging a second-stage capacitor 22b between the third gate sub-section G3 and the source sub-section 13.

[0069] Figure 8A and Figure 8B An embodiment of gate segment 12 having sub-segments G1, G2 and G3 is shown. Figure 8B yes Figure 8A Detailed view of gate section 12.

[0070] Gate segment 12 is formed from a segment of metallization layer 11 on insulating substrate 8. Gate segment 12 is further subdivided into sub-segments G1-G3 of metallization layer 11, thereby forming islands on insulating substrate 8. The islands are interconnected by second circuit element 23. Figure 8AThe second circuit element 23 is a portal-shaped conductor structure that exhibits at least some of the electrical characteristics of a coil. Therefore, the second circuit element forms an inductor. Thus, the gate island is coupled through the inductor element. Therefore, the inductor element is arranged within the gate current path, thereby driving the gate current and thus affecting the switching speed of the other downstream controllable semiconductor element 2.

Claims

1. A semiconductor module, comprising: Insulating substrate; A first metallization layer is disposed on the insulating substrate; Two or more controllable semiconductor elements are disposed on the surface of the first metallization layer, each controllable semiconductor element including a gate electrode, a first load electrode and a second load electrode; The control current path between the gate electrode and the first load electrode; A controllable load current path between the first load electrode and the second load electrode; as well as A first circuit element disposed between the control current path and the load current path.

2. The semiconductor module according to claim 1, in, The first metallization layer includes a gate segment (G), a second segment (S), and at least a third segment (DC+ / DC- / AC); and The semiconductor module further includes a plurality of first electrical connection elements; wherein The gate electrode of each of the two or more controllable semiconductor elements is electrically coupled to the gate segment (G) through one or more of the first electrical connection elements, wherein The first load electrode of each of the two or more controllable semiconductor elements is electrically coupled to the second segment (S) through one or more of the first electrical connection elements, and wherein The second load electrode of the two or more controllable semiconductor elements is electrically coupled to the third segment through a conductive connection layer.

3. The semiconductor module according to any of the preceding claims, wherein, The first circuit element is arranged between the gate segment and the second segment.

4. The semiconductor module according to claim 2 or 3, wherein, The gate segment is at the gate potential, and the second segment is at the source potential, which is different from the gate potential.

5. The semiconductor module according to claim 2, wherein, The load current path is formed between the second segment and the third segment.

6. The semiconductor module according to any of the preceding claims, wherein, The first circuit element is arranged on top of the first metallization layer.

7. The semiconductor module according to any of the preceding claims, wherein, The first circuit element is a passive element.

8. The semiconductor module according to claim 7, wherein, The passive component is an impedance.

9. The semiconductor module according to claim 8, wherein, The impedance is at least one of a capacitor, a resistor, or an inductor.

10. The semiconductor module according to any of the preceding claims, wherein, The gate segment includes at least a first sub-segment (G1) and a second sub-segment (G2), wherein the first sub-segment and the second sub-segment (G1, G2) are electrically isolated from each other, and wherein the first sub-segment and the second sub-segment (G1, G2) are connected by a second circuit element.

11. The semiconductor module according to claim 10, wherein, The second circuit element is an inductor, particularly a wire or coil.

12. The semiconductor module according to claim 10 or 11, wherein, The first segment includes a third sub-segment (G3) connected to the second sub-segment via the second circuit element, and wherein the control current path is formed to start at the first sub-segment (G1) of the gate segment (G), via the second sub-segment and the third sub-segment, via the second circuit element to the gate electrode.

13. The semiconductor module according to claim 12, wherein, Each of the second and third sub-segments controls at least two of the controllable semiconductor elements, wherein the semiconductor elements are connected in parallel to each other via corresponding sub-segments of the second and third sub-segments.

14. The semiconductor module according to claim 12 or 13, wherein, The first sub-segment is connected to the second segment via a first first circuit element, particularly via a first capacitor, and / or wherein the second sub-segment is connected to the second segment via a second first circuit element, and / or wherein the third sub-segment is coupled to the second segment via a third first circuit element.

15. The semiconductor module according to any of the preceding claims, wherein, The first subset of the controllable semiconductor elements is arranged symmetrically with respect to the second subset of the controllable semiconductor elements on the insulating substrate.

16. The semiconductor module according to any of the preceding claims, wherein, The first circuit element is a capacitor that is welded, sintered, clamped, glued, or electrically coupled between the gate potential and the source potential.

17. The semiconductor module according to claim 16, wherein, The capacitor is integrated on and in contact with the surface of the additional substrate, or the capacitor is formed from the additional substrate and integrated into the semiconductor module.

18. The semiconductor module according to claim 17, wherein, The additional substrate is a metal-insulator-metal substrate.

19. The semiconductor module according to claim 17 or 18, wherein, The surface of the additional substrate is an additional welding substrate.

20. The semiconductor module according to any of the preceding claims, wherein, The controllable semiconductor element is at least one of GaNHEMT, SiC MOSFET, Si IGBT, and Si MOSFET.

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