Integrated device and preparation method thereof

Abstract

The invention relates to an integrated device and a preparation method thereof. The integrated device comprises a P-type substrate; the LDMOS is formed in a first region of the P-type substrate, the first region comprises a deep N well and a first deep P well, the LDMOS comprises a first source region, a grid electrode, a drain region and a first body region, and the first source region is composed of an N + region formed in the first deep P well; the drain region consists of an N + region formed in the deep N well region; a region between the drain region and the first source region is a drift region; the grid electrode is of a closed surrounding structure formed by end-to-end connection; the first body region is composed of a P + region formed in the first deep P well; the JFET is formed in a second region, close to the drain region, of the P-type substrate; the JFET comprises a second source region, a second deep P well and a pinch-off region, the second deep P well is comb-shaped, comb teeth in the comb shape and the deep N wells in the second region are distributed in a crossed manner, and the second source region is composed of a plurality of N + regions in the deep N wells formed among the comb teeth; and the pinch-off region consists of a plurality of arc-shaped deep P traps which are formed in the deep N traps, close to the drain region, at the tip end of each comb-tooth active region.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, specifically to an integrated device and its fabrication method. Background Technology

[0002] In Ultra-HVBCD (Ultra-High Voltage Bipolar-Complementary Metal-Oxide-Semiconductor-Double-Diffused Metal-Oxide-Semiconductor Integrated Process) devices, LDMOS (Laterally Diffused Metal-Oxide-Semiconductor) is typically used for LED (Light Emitting Diode) driving, while JFET (Junction Field-Effect Transistor) is used for analog switching. To combine the characteristics of both structures, LDMOS integrated with JFET has become a widely used solution in the Ultra-HVBCD field. In this design, JFET can provide initial current for the high-voltage startup system, while LDMOS takes over the high-power switching task after the system stabilizes. The JFET pinch-off voltage is a critical evaluation item in chip circuit design, and its magnitude is key to device performance. Current pinch-off can be controlled by forming a depletion region through N / P-type well injection.

[0003] However, when no voltage is applied to the source of the JFET, current flows through the DNW (Deep N Well) and exits through the source. When voltage is applied to the source of the JFET, current is depleted through P-type IMP (Implantation) in the P-top (Top P-type Region) combined with the DPW (Deep P Well), thus pinching off the current. The size and spacing of the square DPW blocks are limited, restricting the pinch-off voltage to 20V-30V, which cannot meet a wider range of pinch-off voltage requirements.

[0004] Therefore, how to meet the pinch-off voltage requirements over a wider range is an urgent problem to be solved. Summary of the Invention

[0005] This application provides an integrated device and its fabrication method to address the issue of a wider range of pinch-off voltage requirements.

[0006] To address the aforementioned problems, this application provides an integrated device comprising: a P-type substrate; an LDMOS formed in a first region of the P-type substrate, the first region including a deep N-well and a first deep P-well, the LDMOS including a first source region, a gate, a drain region, and a first body region, the first source region being composed of an N+ region formed in the first deep P-well; the drain region being composed of an N+ region formed in the deep N-well region; the region between the drain region and the first source region being a drift region; the gate being a closed surrounding structure formed end-to-end, the surrounding structure enclosing the drift region and the drain region, the surrounding structure being located within the deep N-well region; and the first body region being composed of an N+ region formed in the first deep P-well region. The first body region is formed by the P+ region in the well and the first body region surrounds the outside of the gate to form a first body region surrounding structure with an opening; the JFET is formed in a second region of the P-type substrate near the drain region, the second region includes a partial deep N-well; the JFET includes a second source region, a second deep P-well and a pinch-off region, the second deep P-well is comb-shaped, the comb teeth in the comb shape are interspersed with the deep N-wells of the second region, the second source region is composed of several N+ regions in the deep N-wells formed between the comb teeth; the pinch-off region is composed of multiple arc-shaped deep P-wells formed in the deep N-wells near the drain region at the active region tip of each comb tooth, wherein the JFET and LDMOS share the gate and drain regions.

[0007] To address the aforementioned problems, this application also provides a method for fabricating an integrated device. The method includes: providing a P-type substrate; forming an LDMOS in a first region of the P-type substrate, the first region including a deep N-well and a first deep P-well, the LDMOS including a first source region, a gate, a drain region, and a first body region; the first source region being composed of an N+ region formed in the first deep P-well; the drain region being composed of an N+ region formed in the deep N-well region; the region between the drain region and the first source region being a drift region; the gate being a closed, interconnected surrounding structure that surrounds the drift region and the drain region, the surrounding structure being located within the deep N-well region; the first body region being formed by... The first body region is formed in the P+ region within the first deep P-well, and a first body region surrounds the gate to form an open structure. A JFET is formed in a second region of the P-type substrate near the drain region. The second region includes a portion of the deep N-well. The JFET includes a second source region, a second deep P-well, and a pinch-off region. The second deep P-well is comb-shaped, with the comb teeth interspersed with the deep N-wells in the second region. The second source region is composed of several N+ regions formed in the deep N-wells between the comb teeth. The pinch-off region is composed of multiple arc-shaped deep P-wells formed in the deep N-wells near the drain region at the active region tip of each comb tooth. The JFET shares the gate and drain regions with the LDMOS.

[0008] The beneficial effects of this application are as follows: The integrated device and its fabrication method provided in this application form a first region on a P-type substrate including a deep N-well and a first deep P-well. The deep N-well and the first deep P-well constitute the basic structure of LDMOS. The distribution and interaction of different types of wells affect the electrical performance of LDMOS, such as current conduction. Since LDMOS shares part of the structure with JFET, it indirectly affects the pinch-off voltage range of JFET. The depth and concentration of the deep N-well and the first deep P-well affect the on-resistance and other performance of LDMOS. These performances are related to the electrical performance of the entire integrated device under different operating states, thereby affecting the pinch-off voltage range. Attached Figure Description

[0009] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0010] Figure 1 and Figure 2 These are schematic diagrams of different structures of integrated devices in existing technologies; Figure 3 This is a schematic diagram showing how the pinch-off voltage changes as the DPW width increases when the spacing between the DPWs of the integrated device is 7 micrometers in the prior art. Figure 4 This is a schematic diagram showing how the pinch-off voltage changes as the DPW spacing increases when the width of the DPW in an integrated device is 1.5 micrometers in the prior art. Figure 5 This is a top view of the integrated device provided in the embodiments of this application; Figure 6 This is a top view schematic diagram of the integrated device provided in the embodiments of this application, showing the area below the field oxide layer; Figure 7 This application provides an embodiment of the method for... Figure 5 A schematic diagram of the structure of an integrated device after it has been cut and observed along the X-axis in the XYZ coordinate system; Figure 8 This is a top view of the JFET structure provided in the embodiments of this application; Figure 9 This application provides an embodiment of the method for... Figure 8 The diagram shows the structure of the JFET after the second source region has been cut and observed along the Y-axis in the XYZ coordinate system. Figure 10 This is a top view schematic diagram of another JFET structure provided in an embodiment of this application; Figure 11This is a top view schematic diagram of another JFET structure provided in an embodiment of this application; Figure 12 This application provides an embodiment of the method for... Figure 8 , Figure 10 A schematic diagram of the structure observed along the Y-axis in the XYZ coordinate system after the JFET has been cut. Figure 13 A schematic diagram illustrating how the pinch-off voltage varies with the spacing of the toothed active region in the integrated device provided in this application embodiment; Figure 14 A schematic diagram illustrating how the pinch-off voltage varies with the width of the arc-shaped deep P-well in the integrated device provided in this application embodiment; Figure 15 A schematic diagram illustrating how the pinch-off voltage varies with the spacing between the arc-shaped deep P-wells in the integrated device provided in this application embodiment; Figure 16 This is a schematic flowchart of the fabrication method of the integrated device provided in the embodiments of this application. Detailed Implementation

[0011] The embodiments of this application will be further described in detail below with reference to the accompanying drawings and examples. It should be particularly noted that the following embodiments are only used to illustrate the embodiments of this application and do not limit the scope of the embodiments of this application. Similarly, the following embodiments are only some embodiments of the embodiments of this application, and not all embodiments. All other embodiments obtained by those skilled in the art without creative effort are within the protection scope of the embodiments of this application.

[0012] The following detailed description is based on specific embodiments. It should be noted that the embodiments of this application can be presented in various forms, and some examples will be described below.

[0013] Figure 1 and Figure 2 These are schematic diagrams illustrating different structures of integrated devices in existing technologies. For example... Figure 1 and Figure 2As shown, an LDMOS integrated JFET device consists of a JFET on top and an LDMOS on the bottom, with a P-type substrate. The LDMOS and JFET share a drain and a gate. Each has a source terminal; the LDMOS source is called the Source, and the JFET source is called the Sense. For the LDMOS, the region between the drain and the source is the drift region, and the channel is defined as the area between the polycrystalline (POLY) and the polycrystalline (PW) P-well. The region between the polycrystalline and the P-well is the active region (AA in the diagram). For the JFET, the gate shared with the LDMOS does not control pinch-off; instead, pinch-off is achieved through the depletion of the DNW and DPW. The drain terminal consists of an N+ region formed in the deep N-well. The LDMOS source terminal consists of an N+ region formed in the channel region. The JFET sense terminal consists of an N+ region formed in the DNW.

[0014] Figure 2 In the diagram, the yellow area represents DNW, and the green area represents DPW blocks. When no voltage is applied to the JFET Sense terminal, the current flows along DNW through the Sense terminal. When voltage is applied to the JFET Sense terminal, the current is depleted by the P-type IMP of the Ptop in conjunction with DPW, thus pinching off the current.

[0015] Figure 3 This is a schematic diagram illustrating how the pinch-off voltage changes as the DPW (Distributed Power Width) of an integrated device increases when the DPW spacing is 7 micrometers, as seen in existing technologies. Figure 3 As shown, the horizontal axis represents the width of the DPW block, ranging from 1.4 to 2.9 μm; the vertical axis represents the pinch-off voltage (VOFF) of the JFET, ranging from 25.6 to 31.6 V. Figure 3 It can be seen that when the spacing of the DPW is fixed at 7μm, as the width of the DPW increases from 1.4μm to 2.5μm, the pinch-off voltage gradually decreases from about 30.6V to about 26.6V. The two are negatively correlated, that is, the larger the width, the lower the pinch-off voltage.

[0016] Figure 4 This is a schematic diagram illustrating how the pinch-off voltage changes as the DPW spacing increases when the width of the DPW in an integrated device is 1.5 micrometers in the prior art. For example... Figure 4 As shown, the horizontal axis represents the DPW spacing, ranging from 5.0 to 11.0 μm; the vertical axis represents the pinch-off voltage (VOFF), ranging from 29.10 to 31.60 V. Figure 4It can be seen that when the width of the DPW is fixed at 1.5μm, as the spacing of the DPW increases from about 6.0μm to about 10.0μm, the pinch-off voltage gradually increases from about 29.6V to about 31.10V. The two are positively correlated, that is, the larger the spacing of the DPW, the higher the pinch-off voltage.

[0017] from Figure 3 and Figure 4 The data shows that changes in Width and Space have limitations on the control of the pinch-off voltage. Therefore, the size and distance of the square DPW blocks are limited, resulting in a pinch-off voltage limited to 20V-30V, making it difficult to meet smaller pinch-off voltage requirements.

[0018] To address the aforementioned issues, this application provides an integrated device and its fabrication method. The first region formed on a P-type substrate includes a deep N-well and a first deep P-well. The deep N-well and the first deep P-well constitute the basic structure of an LDMOS. The distribution and interaction of different types of wells affect the electrical performance of the LDMOS, such as current conduction. Since the LDMOS shares some structures with a JFET, it indirectly affects the pinch-off voltage range of the JFET. The depth and concentration of the deep N-well and the first deep P-well affect the on-resistance and other properties of the LDMOS. These properties are related to the electrical performance of the entire integrated device under different operating conditions, thereby affecting the pinch-off voltage range.

[0019] Furthermore, for LDMOS, the first source region consists of the N+ region within the first deep P-well. As one endpoint of the LDMOS current output, it determines the path and characteristics of current flow from the LDMOS, which is related to the current transport of the entire integrated device and affects the JFET's pinch-off voltage range. The gate is a closed loop structure formed end-to-end, surrounding the drift region and drain region and located within the deep N-well region. This allows for more effective control of the electric field of the drift and drain regions by the gate, enabling precise adjustment of the LDMOS's on / off state. This, in turn, affects the current distribution of the entire integrated device under different operating modes, ultimately influencing the achievable pinch-off voltage range of the JFET. The drain region consists of the N+ region within the deep N-well region and is one endpoint of the LDMOS current input. Its collaborative work with the source, drift region, and gate determines the electrical performance of the LDMOS. The shared structural characteristics of LDMOS and JFET mean that the drain-related performance affects the JFET's pinch-off voltage range. The first body region is composed of the P+ region in the first deep P-well and forms an open surrounding structure around the outside of the gate. The first body region can adjust the electrical performance of the LDMOS, such as the threshold voltage. Changes in the performance of the LDMOS will affect the JFET that shares part of the structure with it, thereby affecting the range of the JFET's pinch-off voltage.

[0020] For a JFET, the second region of the P-type substrate near the drain region includes a portion of deep N-wells, providing a specific area for JFET formation. The association of this region with the LDMOS region and the distribution of the deep N-wells affect the pinch-off voltage range. The second source region consists of the N+ regions in the deep N-wells between the comb teeth. As the current output terminal of the JFET, it determines the current output characteristics of the JFET. Different numbers and distributions of the source N+ regions will change the magnitude and distribution of the JFET current, thus affecting the pinch-off voltage range. The second deep P-well is comb-shaped with the comb teeth interspersed with the deep N-wells in the second region. The comb-shaped structure increases the contact area and interaction region between the deep P-wells and deep N-wells, making the formation and adjustment of the depletion region more flexible, thereby enabling more effective control of the pinch-off voltage and expanding the achievable range of the pinch-off voltage. The pinch-off region consists of arc-shaped deep P-wells in the deep N-wells near the drain region at the tip of the active region of the comb teeth. The arc-shaped deep P-wells allow for a more specific shape and distribution of the depletion region. Compared with traditional structures, the electric field of the depletion region can be adjusted more precisely, thereby achieving a wider pinch-off voltage range. Finally, multiple parallel comb active areas replace the existing single active area. By adjusting the number and size of the comb active areas, the DPW storage space between adjacent comb active areas can be changed. When more DPW cooperates with the P-type injection of Ptop, it can more fully exhaust DNW, thus reducing the required pinch-off voltage. Conversely, reducing the number of comb active areas reduces the total amount of DPW, retains more DNW, increases the pinch-off voltage, and directly widens the adjustment range of the pinch-off voltage. In photolithography, the arc-shaped deep P-well can avoid the right-angle diffraction interference problem of square DPWs. Without violating the design rule, the width and adjacent spacing of the arc-shaped deep P-well can be flexibly adjusted. In addition, the arc-shaped deep P-well, in conjunction with the comb-tooth active region, enables the depletion region of the DNW to achieve segmented and controllable characteristics. When the width of the arc-shaped deep P-well increases, the depletion capability of a single DPW segment is enhanced, the overall depletion region is more likely to cover the DNW, and the pinch-off voltage is reduced. When the spacing of the arc-shaped deep P-well increases, the undepleted DNW area between the depletion regions becomes wider, requiring a higher voltage to achieve complete depletion, and the pinch-off voltage increases.

[0021] The following detailed description is based on specific embodiments. It should be noted that the embodiments of this application can be presented in various forms, and some examples will be described below.

[0022] In one embodiment of this application, an integrated device is provided, comprising: a P-type substrate; an LDMOS formed in a first region of the P-type substrate, the first region including a deep N-well and a first deep P-well, the LDMOS including a first source region, a gate, a drain region, and a first body region, the first source region being composed of an N+ region formed in the first deep P-well; the drain region being composed of an N+ region formed in the deep N-well region; the region between the drain region and the first source region being a drift region; the gate being a closed surrounding structure formed end-to-end, the surrounding structure surrounding the drift region and the drain region, the surrounding structure being located within the deep N-well region; the first body region being composed of an N+ region formed in the first deep P-well region. The first body region is composed of a P+ region, and a first body region surrounds the outside of the gate to form a first body region surround structure with an opening; the JFET is formed in a second region on a P-type substrate near the drain region, the second region including a partial deep N-well; the JFET includes a second source region, a second deep P-well and a pinch-off region, the second deep P-well is comb-shaped, the comb teeth in the comb shape are interspersed with the deep N-wells of the second region, the second source region is composed of several N+ regions formed in the deep N-wells between the comb teeth; the pinch-off region is composed of multiple arc-shaped deep P-wells formed in the deep N-wells near the drain region at the tip of the active region of each comb tooth, wherein the JFET and LDMOS share the gate and drain regions.

[0023] In the semiconductor field, an integrated device refers to a device structure that integrates two or more semiconductor devices with different functions on the same substrate through semiconductor manufacturing processes, achieving functional reuse and performance synergy. In this embodiment, the integrated device specifically refers to a structure that integrates an LDMOS and a JFET on the same P-type substrate. The two share the gate and drain regions, enabling the JFET to provide high-voltage startup initial current and the LDMOS to take over high-power switching after stabilization. The P-type substrate is the basic supporting structure of semiconductor devices. It is made of single-crystal silicon and doped with P-type impurities, providing a carrier for the growth and formation of various functional regions of the device, while also achieving isolation between devices through its own doping characteristics.

[0024] The first deep P-well is a highly concentrated P-type doped region formed by ion implantation within the first region of the P-type substrate. Its depth matches that of the deep N-well, and it primarily defines the positions of the LDMOS source and body regions, working in conjunction with the deep N-well to achieve source-drain isolation. The first source region is the region in the LDMOS that provides charge carriers, typically heavily doped N-type (N+). It forms a conductive channel with the gate, through which charge carriers flow to the drain region. The gate is the structure in the LDMOS that controls the channel's on / off state. It is typically made of polysilicon, and the electric field of the oxide layer beneath the gate is changed by applying a voltage, thereby controlling the conduction path of the charge carriers. The drain region is the region in the LDMOS that collects charge carriers (electrons), typically heavily doped N-type (N+). It needs to withstand a relatively high voltage and is isolated from the source region by the drift region. The first body region is the same type as the source region in the LDMOS, typically heavily doped P-type, used to electrically connect the source region and the substrate, suppressing latch-up effects.

[0025] Figure 5 This is a top view of the integrated device provided in the embodiments of this application. Figure 5 In the diagram, the top view of the structure is obtained by observing along the Z-axis of the XYZ coordinate system, as shown below. Figure 5 As shown, the substrate of integrated device 1 is divided into a first region 110 and a second region 120. Figure 5 The white area in the image is the field oxide layer. The first region is a specific area pre-defined on the P-type substrate, in which a deep N-well and a first deep P-well are formed, providing space for the formation of the first source region 210, gate 220, drain region 230, first body region 240, and drift region 250 of the LDMOS, ultimately enabling the LDMOS to have high-voltage, high-power switching capability.

[0026] The region between the drain region and the first source region is called the drift region. In this embodiment, the drift region is located inside the gate's surrounding structure. The gate can control the carrier concentration in the drift region through an electric field. When a positive voltage is applied to the gate, the portion of the drift region near the gate forms a channel, through which electrons can flow from the source region to the drain region. When no voltage is applied to the gate, the drift region remains in a high-resistance state, achieving the cutoff of the LDMOS, which conforms to the working logic of a high-voltage switch.

[0027] Figure 6 This is a top view of the integrated device provided in the embodiments of this application, showing the area below the field oxide layer. Figure 6 In the diagram, the top-down view is obtained by observing along the Z-axis of the XYZ coordinate system. For example... Figure 6 As shown, the outer region is the body region, and the central region is the drain electrode 230.

[0028] Figure 7 This application provides an embodiment of the method for... Figure 5 A schematic diagram of the structure of an integrated device after it has been cut and observed along the X-axis in the XYZ coordinate system. (See diagram below.) Figure 5 As shown, the dashed line 410 in the first cutting diagram indicates the cutting direction, which is the Y-axis direction in the XYZ coordinate system. Figure 7 As shown, the deep N-well 111 is divided into two parts: one part is located in the first region 110, serving as the carrier of the drain region of the LDMOS and the background of the drift region; the other part is located in the second region 120, serving as the conductive channel of the JFET, realizing the structural reuse of LDMOS and JFET.

[0029] like Figure 7 As shown, the first deep P-well 112 is located above the P-type substrate 100 and is located outside the deep N-well 111. The first source region and the first body region 240 of the LDMOS are formed inside. The parasitic NPN transistor effect of the LDMOS is suppressed by the P-type doping characteristics, thereby improving the reliability of the device.

[0030] like Figure 7 As shown, the first source region consists of an N+ region 211 formed in the first deep P-well 112. Serving as the source terminal of the LDMOS, it provides electrons to the drift region when a forward voltage is applied to the gate, supporting high-power current output. By embedding the N+ source region into the P-type deep well, the hole characteristics of the P-type deep well are utilized to suppress parasitic current between the source region and the substrate. This ensures that electrons in the first source region can only flow to the drain region through the gate-controlled channel, preventing direct electron flow into the P-type substrate. Simultaneously, the P-type doping of the first deep P-well can form a PN junction with the N-type doping of the deep N-well, improving the breakdown voltage of the LDMOS.

[0031] like Figure 7 As shown, the drain region consists of an N+ region 231 formed in a deep N-well 111. The deep N-well 111 provides an N-type conductive background for the drain region, which can disperse the high voltage electric field borne by the drain region. The heavy N+ doping improves the carrier collection efficiency of the drain region, which not only meets the high voltage requirements of LDMOS, but also allows the deep N-well where the drain region is located to extend to the second region of the JFET, providing a conductive channel for the JFET and supporting the integrated structure of the shared drain region.

[0032] The gate is a closed loop structure formed by connecting the ends of the gate. The closed loop structure makes the electric field control of the drift region more uniform and avoids the problem of local electric field concentration caused by traditional strip gates.

[0033] like Figure 5 As shown, gate 220 has a closed, surrounding structure formed by connecting the ends of the gate. (As...) Figure 7 As shown, the gate is located in the region of the deep N-well 111, surrounding the drift region and the drain region. This allows for uniform control of the electric field distribution in the drift region, preventing excessive local electric field from causing device breakdown, while also meeting the requirements for sharing with JFETs.

[0034] like Figure 5 As shown, the drift region 230 is located within the deep N-well of the first region 110 and is surrounded by the surrounding structure of the gate 220. Its length needs to be designed according to the device's voltage withstand requirements to ensure that the LDMOS does not experience avalanche breakdown during high-power operation. The surrounding structure surrounds the drift region and the drain region, ensuring that the gate can fully control the conductivity state of the drift region and the electric field distribution of the drain region, so that the drain region is completely within the electric field control range of the gate, avoiding parasitic conduction between the drain region and the substrate. At the same time, after the drift region is surrounded, its carriers can only flow along the path defined by the gate, reducing power loss caused by current dispersion and improving the switching efficiency of the LDMOS.

[0035] like Figure 7As shown, the surrounding structure is located in the deep N-well region. The N-type doping of the deep N-well can form a good electric field coupling with the gate, which enhances the gate's control over the drift region and avoids the gate from directly contacting the P-type substrate. At the same time, the deep N-well provides a stable conductive background for the gate, ensuring that the gate voltage can be effectively transferred to the drift region, thereby realizing precise switching control of LDMOS.

[0036] like Figure 5 As shown, the first body region 240 surrounds the outer side of the gate 220 to form a first body region surrounding structure with an opening. The opening position of the surrounding structure corresponds to the first source region, which facilitates the simultaneous connection of the metal layer to the first source region and the first body region, simplifying the wiring. At the same time, the design surrounding the outer side of the gate enables the body region to cooperate with the gate, stabilize the threshold voltage of the LDMOS, and avoid threshold drift caused by temperature or voltage changes.

[0037] like Figure 7 As shown, the first body region is composed of a P+ region 241 formed in the first deep P-well 112. By embedding the P+ body region into the first deep P-well 112, the high conductivity of P+ is used to achieve electrical connection between the body region and the source region, suppressing the latch-up effect. The P-type doping of the first deep P-well and the heavy doping of the P+ body region form a gradient doping, which ensures the conductivity of the body region and avoids the PN junction between the body region and the deep N-well from conducting. At the same time, the depth of the first deep P-well matches the depth of the deep N-well, ensuring that the body region can effectively isolate the source and drain regions of the LDMOS.

[0038] like Figure 5 As shown, the second region 120 is the region on the P-type substrate near the drain region 230. Part of the deep N-well in this region is connected to the deep N-well in the first region, so that the current of the JFET can flow directly to the common drain region, realizing the function of the JFET to provide initial current.

[0039] In this embodiment, the JFET is formed in a second region of the P-type substrate near the drain region, which shortens the distance between the JFET and the drain region and reduces path losses for current flowing from the JFET to the drain region. Specifically, the distance between the boundary of the second region and the drain region can be designed according to actual needs to ensure that the current output from the second source region of the JFET can quickly flow to the drain region through the deep N-well of the second region, avoiding increased parasitic resistance due to excessively long paths and improving the overall efficiency of the integrated device.

[0040] The second region includes a partial deep N-well, enabling structural reuse between JFET and LDMOS. By sharing a partial deep N-well, it avoids fabricating a separate deep N-well for the JFET, reducing the number of ion implantation steps. In this embodiment, the partial deep N-well in the second region is an extension of the deep N-well in the first region, with the same doping concentration and depth. It serves both as a conductive channel for the JFET and as a carrier for the second source region, achieving dual functionality and reducing process costs.

[0041] Specifically, the second source region is the area in the JFET that provides charge carriers. It can be heavily doped with N-type and serves as the current output terminal of the JFET. The second deep P-well is the structure in the JFET used to form the depletion region. It is a highly concentrated P-type doped region. By forming a PN junction with the deep N-well, its depletion region can control the current conduction and pinch-off within the deep N-well. The pinch-off region is the key region in the JFET for achieving current pinch-off. It consists of the well structure that controls the depletion region. When the depletion region completely covers the conductive channel of the deep N-well, the current is pinched off.

[0042] Figure 8 This is a top view schematic diagram of the JFET structure provided in an embodiment of this application. Figure 8 As shown, the pinch-off region 330 consists of multiple arc-shaped deep P-wells 331, located in the deep N-well near the drain region at the tip of the active region 321 of each comb tooth. The arc-shaped structure optimizes the distribution of the depletion region, and multiple arc-shaped deep P-wells can form multi-point pinch-off, improving the accuracy of pinch-off. The width and spacing of the arc-shaped deep P-wells at the tip of the active region of each comb tooth can be adjusted independently: when the width increases, the depletion region becomes narrower and the pinch-off voltage decreases; when the spacing increases, the coverage area of ​​the depletion region decreases and the pinch-off voltage increases, ultimately breaking through the limitation of 20-30V and achieving a wide-range pinch-off of 5-30V.

[0043] like Figure 5 As shown, the second source region 310 consists of several N+ regions formed in the deep N-wells between the comb teeth. Multiple segmented source regions can cooperate with the comb-shaped second deep P-wells, and the pinch-off voltage can be controlled by adjusting the number and size of the source regions. The comb-shaped structure divides the traditional single-segment deep P-well into multiple independent comb teeth. The width and spacing of each comb tooth can be adjusted independently. When the comb tooth width increases, more P-type regions participate in depletion, and the pinch-off voltage decreases. When the comb tooth spacing increases, more conductive areas in the deep N-wells increase, and the pinch-off voltage increases, providing a basis for a wide range of pinch-off voltage adjustments.

[0044] like Figure 5 As shown, the second deep P-well is a comb-shaped structure located within the deep N-well in the second region, interspersed with the deep N-wells. Each comb tooth can serve as an independent depletion unit. By adjusting the size and spacing of the comb teeth, the area of ​​the P-type region participating in depletion can be changed, thereby adjusting the pinch-off voltage. The interspersed distribution of the comb teeth with the deep N-wells in the second region ensures that the comb teeth can uniformly divide the conductive channels of the deep N-wells, allowing the depletion region to fully cover the conductive area. For example, the interspersed distribution is such that the comb teeth extend along the Y-axis, and the deep N-wells extend along the X-axis. Each comb tooth passes through the deep N-well, forming an alternating structure of P-type comb teeth, N-type deep N-wells, and P-type comb teeth. When the current flows along the X-axis to the drain region within the deep N-well, it must pass through the depletion regions corresponding to multiple comb teeth, ensuring that the current can be fully controlled and avoiding leakage current caused by local unpinched areas.

[0045] Specifically, JFET and LDMOS share the gate and drain regions. By reusing the structure, the number of process steps and parasitic parameters are reduced. The shared drain region allows the current of both to be collected in the same drain region, eliminating the need to make additional metal connections for the JFET drain region and reducing parasitic capacitance. When sharing the gate, the gate of the JFET only serves as a field plate, eliminating the need to deposit a separate polysilicon gate for the JFET, reducing photolithography and etching steps, simplifying the device structure, and improving integration.

[0046] In one embodiment, the number and size of the active regions of the comb teeth are determined according to a preset pinch-off voltage.

[0047] Continue to refer to Figure 8 Multiple comb-tooth active regions 321 are arranged side by side along a preset direction. The gap between two adjacent comb-tooth active regions 321 completely fills the arc-shaped deep P-well 331. All comb-tooth active regions 321 are embedded inside the DNW and are in direct contact with the DNW. This means that changes in the number and size of the comb-tooth active regions 321 will directly change the total number and distribution density of the arc-shaped deep P-well 321.

[0048] The pinch-off voltage is the voltage required to completely deplete the DNW current channel. The degree of DNW depletion is determined by the total number of arc-shaped deep P-wells involved in the depletion. The more active regions of the comb teeth, the more arc-shaped deep P-wells there are. The larger the size of the active regions of the comb teeth, the wider the DNW area that a single arc-shaped deep P-well can cover.

[0049] Specifically, if the system's preset pinch-off voltage is low, the number of active regions on the comb teeth is increased according to design requirements, and the width of each active region on the comb teeth is appropriately increased. The increased number of active regions increases the total number of arc-shaped deep P-wells, and the increased width allows each arc-shaped deep P-well to cooperate with the P-type injection of the Ptop to cover a wider DNW region. Both factors together improve the overall depletion capability of the arc-shaped deep P-wells, ensuring that the DNW current path can be depleted at a lower voltage. If the system's preset pinch-off voltage is high, the number of active regions on the comb teeth is reduced, and the width of each active region on the comb teeth is decreased. The reduced number of active regions reduces the total number of arc-shaped deep P-wells, and the decreased width reduces the coverage area of ​​each arc-shaped deep P-well, lowering the overall depletion capability. A higher voltage is required to completely deplete the DNW current path.

[0050] Specifically, when the device is operating, after a voltage is applied to the second source terminal of the JFET, the arc-shaped deep P-well between the comb-shaped active regions works synergistically with the P-type injection from the Ptop. The P-type carriers released from the arc-shaped deep P-well diffuse into the DNW and recombine with the N-type carriers in the DNW, gradually shrinking the current path of the DNW. Since the parameters of the comb-shaped active regions have been optimized according to the preset pinch-off voltage, when the applied voltage reaches the preset value, the total depletion capability of the arc-shaped deep P-well precisely closes the current path of the DNW, achieving precise current pinch-off without affecting the normal operation of the LDMOS.

[0051] In this embodiment, by adjusting the number and size of the active areas of the comb teeth according to the preset pinch-off voltage, the pinch-off voltage can be precisely controlled to any target value within the 5V-30V range, perfectly matching the working requirements of different ultra-high voltage BCD systems. Adjusting the number and size of the active areas of the comb teeth according to the preset pinch-off voltage does not require changing process conditions or replacing the main structure of the mask, significantly reducing design and production costs.

[0052] In some embodiments, the depth of the arc-shaped deep P-well is the same as the depth of the deep N-well.

[0053] Among them, the N-type heavily doped region formed in the P-type substrate through low-energy ion implantation and high-temperature push-well process, the depth refers to the vertical distance from the substrate surface to the point where the doping concentration in the well region decreases to the intrinsic doping concentration of the substrate. It can serve as the conductive channel of JFET and at the same time provide a high-voltage isolation basis for the drain region of LDMOS.

[0054] Continue to refer to Figure 7 The arc-shaped deep P-well 331 is located inside the deep N-well 111. It is a heavily doped P-type region formed by the same low-energy injection and push-well process as the deep N-well 111. Its depth is defined in the same way as the deep N-well 111. It can form a PN junction with the deep N-well 111. By expanding the depletion region, the conductive channel of the deep N-well 111 is controlled, and the JFET current pinch-off is achieved.

[0055] Specifically, the curved DPW is located inside the DNW. In the Z-axis direction, if the depth of the curved DPW is shallower than the DNW, an uncovered conductive channel segment will remain at the bottom of the DNW. Even if the depletion region of the DPW expands, this segment can still conduct current, resulting in incomplete pinch-off of the JFET. If the depth of the curved DPW is deeper than the DNW, the DPW will penetrate the DNW and contact the P-type substrate below, forming a DPW-Psub parasitic PN junction. This junction is prone to conduction under high voltage, destroying the pinch-off function of the JFET. When both are the same depth, the curved DPW completely covers the conductive area of ​​the DNW in the Z-axis direction. Its depletion region can extend from the surface of the DNW to the bottom, with no residual conductive channel and no risk of parasitic junction conduction, ensuring that the JFET can completely pinch off the current.

[0056] In this embodiment, the arc-shaped deep P-well and the deep N-well have the same depth, ensuring the complete pinch-off of the JFET and avoiding the residual conductive channel at the bottom of the DNW caused by the DPW being shallower than the DNW. When the second source region is pressurized, the depletion region of the arc-shaped DPW can extend from the surface of the DNW to the bottom, completely blocking the current path. The arc-shaped DPW and the DNW share the same low-energy injection and push-well steps, eliminating the need to design push-well temperature or time separately for adjusting the depth, reducing process control steps, and lowering manufacturing costs and process complexity.

[0057] In some embodiments, a second P-well and a second body region formed within the second deep P-well are further formed therein. Near the first region, the first body region surrounds the first body region at the structural opening and connects with the second body region within the second region.

[0058] Among them, the P-well ion doping concentration is lower than that of the deep P-well, and the depth is also shallower than that of the deep P-well. It can be used as a carrier for the bulk region, to isolate adjacent functional regions, or to adjust the threshold voltage of the device.

[0059] Figure 9 This application provides an embodiment of the method for... Figure 8 The diagram shows the structure of the JFET after the second source region has been cut, observed along the Y-axis in the XYZ coordinate system. Figure 8 As shown, the dashed line 420 in the second cutting diagram indicates the cutting direction, which is the X-axis direction in the XYZ coordinate system. Figure 7 and Figure 9 As shown, the second P-well 340 is located inside the second deep P-well 320, which can meet the formation requirements of the second body region. The second deep P-well 320 is relatively deep, and forming a heavily doped body region directly inside it can easily lead to an excessively large impurity diffusion range. However, the second P-well 340, as an intermediate transition layer, can precisely define the position of the second body region, and at the same time enhance the electrical connection between the second deep P-well and the second body region through its P-type doping characteristics.

[0060] The second body region is a heavily doped P-type region that can electrically connect the body potential of the device, suppress parasitic transistor effects, or stabilize the electrical performance of the device. It needs to form an equipotential connection with the source region or the substrate.

[0061] like Figure 7 and Figure 9 As shown, the second body region 350 is formed inside the second P-well 340. The heavily doped characteristics of the second body region can reduce the body resistance and ensure the stability of the body potential when the JFET is operating. The second body region 350, together with the second P-well and the second deep P-well, constitutes a doping gradient structure, which can buffer the potential difference between the JFET and the LDMOS and avoid local electric field concentration under high voltage. Figure 7 As shown, viewed along the Z-axis, the outermost layer is the second deep P-well, the middle layer is the second P-well, and the innermost layer is the second body region. This nested structure prevents heavily doped impurities in the second body region from directly diffusing into the deep N-well. Simultaneously, the transition through the second P-well ensures a good ohmic contact between the second body region and the second deep P-well. The second deep P-well participates in the depletion of the DNW (Dual N-well), defines the location of the second body region, enhances the connection with the second deep P-well, and the stable JFET body potential of the second body region ensures that the JFET achieves pinch-off functionality while avoiding parasitic effects.

[0062] Continue to refer to Figure 5The first body region of the first region 110 has an opening in its surrounding structure, which faces the second region 120. The second body region 350 is located at both ends of the second deep P-well along the X-axis near the sides of the first region, and the positions of the second body region 350 correspond one-to-one with the two ends of the opening of the first body region. If the potentials of the first body region of the LDMOS and the second body region of the JFET are not uniform, a parasitic electric field will be formed between them, leading to increased leakage current or device latch-up. Connecting the second body regions at both ends of the first region to the first body regions at the openings of the surrounding structure of the first body region can eliminate the parasitic electric field by unifying the potentials, and at the same time, form a surrounding protective structure for the entire integrated device, enhancing stability under high voltage.

[0063] In some embodiments, the JFET further includes a first field oxide layer, which includes a second field oxide layer formed between the second body region and the second source region and a third field oxide layer formed between two adjacent second body regions.

[0064] Figure 10 This is a top view schematic diagram of another JFET structure provided in an embodiment of this application. (See attached diagram.) Figure 10 As shown, the first field oxide layer 360 is distributed inside and around the second deep P-well of the JFET, and does not extend into the first region of the LDMOS. The first field oxide layer 360 is further subdivided into a second field oxide layer 361 and a third field oxide layer 362 to ensure that each functional region of the JFET achieves the pinch-off function without parasitic leakage.

[0065] Specifically, the second body region 350 is located at both ends of the comb-shaped second deep P-well, and the second source region 310 is located in the deep N-well between the comb teeth. The two have an adjacent boundary in the XY plane, and the second field oxide layer 361 fills the gap to form a silicon dioxide isolation band. The second body region is heavily P+ doped, and the second source region is heavily N+ doped. If the two are directly adjacent, a P+-N+ contact junction will be formed. This junction is easy to conduct under forward bias and easy to break down under reverse bias. The second field oxide layer blocks this contact through physical isolation, while avoiding the formation of parasitic capacitance between the two, ensuring that the pinch-off voltage of the JFET is not affected by the body-source coupling.

[0066] Figure 11 This is a top view schematic diagram of another JFET structure provided in an embodiment of this application. (See attached diagram.) Figure 11 As shown, two adjacent second body regions 350 are spaced apart in the XY plane, and the third field oxide layer 362 fills the gap to form an isolation band. Although the second body regions are all heavily P+ doped and have a uniform potential, if adjacent second body regions are directly connected through the substrate or deep P-well, a current path will be formed between the body regions, resulting in local current concentration and affecting the uniformity of JFET pinch-off. The third field oxide layer isolates multiple second body regions to ensure that each second body region transfers potential only through a preset metal layer connection, avoiding current crosstalk.

[0067] In some embodiments, the JFET further includes a first polysilicon layer located above the third field oxide layer.

[0068] The first polysilicon layer is a dedicated polysilicon layer within the JFET region. It serves as a field plate above the third field oxide layer, rather than being the control gate of the JFET. This first polysilicon layer is distributed only above the third field oxide layer of the JFET and does not extend into the LDMOS region or other parts of the JFET. It is typically lightly doped with N-type silicon, providing some conductivity while avoiding excessive parasitic capacitance with the underlying field oxide layer. The first polysilicon layer and the third field oxide layer form a polysilicon-oxide stack structure, utilizing the field plate effect of the polysilicon to improve the electric field distribution below and around the third field oxide layer.

[0069] Continue to refer to Figure 10 In the Z-axis direction, the first polysilicon layer 370 is directly deposited on the upper surface of the third field oxide layer 362 via CVD, without any other dielectric layer separating them. In the plane formed by the X and Y axes, the projection range of the first polysilicon layer 370 can completely overlap with the projection range of the third field oxide layer 362, ensuring coverage of the entire area of ​​the third field oxide layer 362. The third field oxide layer 362 is located between two adjacent second body regions 350, and its lower part and surrounding area are the deep N-well conductive channels of the JFET. Under high voltage, this region is prone to forming a concentrated electric field at the tip. The first polysilicon layer acts as a field plate. After being connected to a fixed potential, it can form a compensating electric field below the third field oxide layer through electrostatic induction to offset part of the concentrated electric field and avoid breakdown of the field oxide layer or local breakdown of the deep N-well.

[0070] In some embodiments, the LDMOS further includes a fourth field oxide layer, which isolates an active region, including a first source region, a drain region, and a first body region.

[0071] The fourth field oxide layer is an insulating and isolation framework for the LDMOS region. It is only distributed in the first region of the P-type substrate and does not extend to the second region of the JFET. It physically isolates the active and non-active regions of the LDMOS to avoid parasitic leakage and current crosstalk.

[0072] The active area (AA) of LDMOS includes the region within the first region that is surrounded / separated by the fourth field oxide layer and is used to form the key functional region of LDMOS.

[0073] Figure 12 This application provides an embodiment of the method for... Figure 8 , Figure 10 A schematic diagram of the structure observed along the Y-axis in the XYZ coordinate system after the JFET has been cut. (See diagram below.) Figure 8As shown, the dashed line 430 in the third cutting diagram indicates the cutting direction, which is the X-axis direction in the XYZ coordinate system; as Figure 10 As shown, the dashed line 440 in the fourth cutting diagram indicates the cutting direction, which is the X-axis direction in the XYZ coordinate system. Figure 5 , Figure 7 and Figure 12 As shown, when viewed along the Z-axis, the fourth field oxide layer 380 is distributed in a frame or mesh pattern: it forms closed or semi-closed insulating bands around the first source region 210, drain region 230, and first body region 240, surrounding and separating the three sub-regions: the fourth field oxide layer 380 surrounding the first source region 210 isolates the first source region 210 from the substrate outside the first deep P-well 112; the fourth field oxide layer 380 surrounding the drain region 230 isolates the drain region 230 from the non-functional segment of the drift region 250; and the fourth field oxide layer 380 separating the first body region 240 from the gate 220 isolates the first body region 240 from the gate 220. The silicon dioxide material of the fourth field oxide layer 380 has extremely high insulation resistance and breakdown voltage, which physically blocks the carrier flow between the active and non-active regions, prevents electrons from the first source region from directly flowing into the P-type substrate 100, and prevents the high voltage of the drain region from diffusing into the substrate.

[0074] In some embodiments, the gate includes a second polysilicon layer and a third polysilicon layer formed on a fourth field oxide layer, the outer sides of the first source region and the second polysilicon layer are self-aligned, the inner side of the second polysilicon layer extends onto a portion of the fourth field oxide layer, and the third polysilicon layer and the second polysilicon layer are connected to form a surrounding structure.

[0075] Continue to refer to Figure 7 The gate comprises a second polysilicon layer 221 and a third polysilicon layer 222 formed on the fourth field oxide layer 380. Both the second polysilicon layer 221 and the third polysilicon layer 222 are heavily N-type doped polysilicon. The heavy doping ensures that the gate has good conductivity and can efficiently transfer the gate voltage. The N-type doping forms a matching electric field coupling with the N-type drift region of the LDMOS, avoiding the accumulation of parasitic charges between the gate and the drift region. The second polysilicon layer 221 and the third polysilicon layer 222 are directly formed on the upper surface of the fourth field oxide layer 380 without any other dielectric layer spacers. The fourth field oxide layer 380 serves as an insulating substrate, isolating the gate from the underlying active region, preventing short circuits between the gate and the active region, and providing a stable support structure for the polysilicon layers.

[0076] like Figure 7As shown, the first source region, composed of the N+ region 211 in the first deep P-well 112, and the outer sides of the second polysilicon layer 221 are self-aligned. During the fabrication of the second polysilicon layer 221, its pattern is first defined by photolithography, and then N+ ion implantation of the first source region is performed directly using the second polysilicon layer 221 as a mask. During implantation, the second polysilicon layer 221 blocks ions from bombarding the area below it, and only the uncovered area forms the first source region. Ultimately, the outer edge of the first source region automatically aligns with the outer edge of the second polysilicon layer 221, eliminating the need for additional photolithography calibration. The LDMOS channel is the core path for current conduction. The self-alignment of the first source region with the outer sides of the second polysilicon layer 221 ensures uniform channel length and avoids the hot electron effect caused by excessively short local channels.

[0077] like Figure 7 As shown, the inner side of the second polysilicon layer 221 extends onto a portion of the fourth field oxide layer 380. The inner side of the second polysilicon layer 221 refers to the side of the second polysilicon layer 210 facing the drift region / drain region. The portion of the fourth field oxide layer refers to the region in the fourth field oxide layer 380 located between the first source region and the drift region. The drift region of an LDMOS is a high-voltage bearing region. When the gate only covers the active region in a conventional manner, the electric field in the drift region far from the gate tends to concentrate. After the second polysilicon layer 221 extends onto the oxide layer, the gate voltage it carries can be coupled to the drift region below through the oxide layer, forming an auxiliary electric field. This flattens the electric field intensity in the drift region from a local peak to a uniform distribution, reducing the risk of breakdown.

[0078] In this structure, the third polysilicon layer and the second polysilicon layer are connected to form a surrounding structure. In a top view, the second polysilicon layer is U-shaped, covering both sides of the first source region and the side furthest from the drain region. The third polysilicon layer is linear or arc-shaped, connecting the two open ends of the U-shape, ultimately forming a rectangular or circular closed surrounding structure. Compared to the traditional strip gate, the closed surrounding structure can reduce the maximum electric field strength in the drift region, significantly improving the drain-source breakdown voltage of the LDMOS, while avoiding localized overheating caused by current concentration.

[0079] In some embodiments, the LDMOS also includes a deep N-well PTOP layer formed beneath a fourth field oxide layer between the first source and drain regions.

[0080] The PTOP layer (top P-type doped layer) is a lightly doped P-type region formed on the surface of the deep well through a low-to-medium energy ion implantation process. It is used to adjust the electric field distribution on the surface of the deep well and suppress the conduction of parasitic devices. In high-voltage devices, the deep N-well serves as a drift region background, and the surface layer is prone to electric field concentration due to high voltage. The lightly doped P-type layer can compensate for part of the electric field through the space charge region, while blocking the parasitic PN junction formed between the deep N-well and the structure above.

[0081] Continue to refer to Figure 7In the Z-axis direction below the fourth field oxide layer 380, the PTOP layer 390 is located between the fourth field oxide layer 380 and the deep N-well 111. The fourth field oxide layer 380 is an insulating layer, and the PTOP layer 390 below it can directly act on the surface of the deep N-well 111, avoiding the oxide layer from blocking the electric field modulation effect. At the same time, the PTOP layer 390 does not directly contact the gate above it, preventing the formation of excessive parasitic capacitance.

[0082] In one embodiment, when the width of the active region of the comb teeth increases, the number of deep P-wells participating in depletion increases, and the pinch-off voltage of the integrated device decreases; when the width of the active region of the comb teeth decreases, the number of deep N-wells participating in depletion increases, and the pinch-off voltage of the integrated device increases.

[0083] The width of the comb-tooth active region and the available space of adjacent arc-shaped deep P-wells are in a fixed, inverse relationship. With the total length in the X direction remaining constant, changes in the width of a single comb-tooth active region directly alter the distribution space of the arc-shaped deep P-wells. When the width of the comb-tooth active region increases, the gap between two adjacent comb-tooth active regions widens, increasing the number of arc-shaped deep P-wells that can be accommodated. Conversely, when the width of the reverse comb-tooth active region decreases, the space for setting up the arc-shaped deep P-wells shrinks, reducing the number of arc-shaped deep P-wells that can be accommodated. Simultaneously, the arc-shaped deep P-wells are in direct contact with the DNW and form an electrical connection with the P-type injection layer of the Ptop. Their number directly determines the total amount of P-type carriers participating in the depletion of the DNW, thus becoming a core variable affecting the pinch-off voltage.

[0084] In this process, the pinch-off of the JFET depends on the recombination of P-type carriers released by the DPW with N-type carriers in the DNW. The more DPWs involved in the depletion, the larger the total number of P-type carriers, and the lower the voltage required to deplete the DNW. Conversely, the fewer DPWs involved in the depletion, the smaller the total number of P-type carriers, and the higher the voltage required to completely deplete the DNW. The relative number of DNWs will adjust inversely with the change in the number of DPWs.

[0085] Specifically, when the system requires a low pinch-off voltage, the width of the active region of a single comb tooth is increased. Since the total length in the X direction remains constant, the gap between adjacent comb tooth active regions widens, allowing for the embedding of more arc-shaped deep P-wells, thus increasing the total amount of DPWs participating in depletion. When a voltage is applied to the second source terminal of the JFET, more arc-shaped deep P-wells, in conjunction with the P-type injection at the Ptop, release P-type carriers. These carriers rapidly diffuse into the DNW, fully recombine with N-type carriers, and accelerate the closing of the DNW current path. Only a lower voltage is needed to completely deplete the DNW, ultimately reducing the pinch-off voltage.

[0086] Specifically, when the system requires a high pinch-off voltage, the width of the active region of a single comb tooth is reduced. This narrows the gap between adjacent comb tooth active regions, limiting the capacity of the arc-shaped deep P-well, reducing the number of DPWs participating in depletion, and consequently decreasing the total number of P-type carriers. When a voltage is applied, the limited number of P-type carriers can only gradually deplete a local area of ​​the DNW. The voltage must be continuously increased to allow P-type carriers to cover the entire DNW current channel until it is completely closed, ultimately increasing the pinch-off voltage.

[0087] In one embodiment, when the spacing between the active regions of the comb teeth increases, the number of deep N-wells participating in depletion increases, and the pinch-off voltage of the integrated device increases; when the spacing between the active regions of the comb teeth decreases, the number of deep P-wells participating in depletion increases, and the pinch-off voltage of the integrated device decreases.

[0088] The spacing between the active regions of the comb teeth and the space occupied by the arc-shaped deep P-well have a fixed inverse relationship. With the total length in the X direction remaining constant, increasing the spacing between the active regions of the comb teeth will correspondingly expand the space between adjacent active regions; conversely, decreasing the spacing will shrink the space occupied by the arc-shaped deep P-well. Simultaneously, the arc-shaped deep P-well and the P-type injection layer of the Ptop are electrically correlated. Their number and coverage directly determine the total number of P-type carriers participating in the depletion of the DNW, while the area of ​​the undepleted region of the DNW changes inversely with the number of DPWs, ultimately jointly affecting the magnitude of the pinch-off voltage.

[0089] Specifically, when a high pinch-off voltage is required by the system, the spacing between the active regions of the comb teeth is increased. Since the total length in the X direction remains unchanged, the increased spacing reduces the space occupied by the arc-shaped deep P-wells between adjacent active regions of the comb teeth, thus reducing the number of arc-shaped deep P-wells that can be embedded, and consequently decreasing the total amount of DPWs participating in depletion. When a voltage is applied to the second source terminal of the JFET, the limited number of P-type carriers released by the small number of arc-shaped deep P-wells and the P-type injection from the Ptop can only gradually cover a local area of ​​the DNW, and cannot quickly fill the entire DNW current channel; the voltage needs to be continuously increased to force the P-type carriers to diffuse deeper into the DNW until the current channel of the DNW is completely depleted, ultimately achieving an increase in the pinch-off voltage.

[0090] Specifically, when the system requires a low pinch-off voltage, the spacing between the active regions of the comb teeth is reduced. This expands the space occupied by the arc-shaped deep P-wells between adjacent active regions, increasing the number of arc-shaped deep P-wells that can be embedded and significantly increasing the total amount of DPWs participating in depletion. When a voltage is applied to the second source terminal, a large number of P-type carriers released from the arc-shaped deep P-wells rapidly diffuse into the DNW, efficiently recombine with N-type carriers, and quickly fill the current channels of the DNW; DNWs can be completely depleted without a high voltage, ultimately reducing the pinch-off voltage.

[0091] Figure 13This is a schematic diagram illustrating how the pinch-off voltage varies with the spacing of the toothed active region in the integrated device provided in this application embodiment. Figure 13 As shown, as the spacing of the active regions of the comb teeth increases, the pinch-off voltage also increases, thus enabling a pinch-off voltage range of 5V to 30V.

[0092] In one embodiment, when the width of the arc-shaped deep P-well increases, the number of deep P-wells participating in depletion increases, and the pinch-off voltage of the integrated device decreases; when the width of the arc-shaped deep P-well decreases, the number of deep P-wells participating in depletion decreases, and the pinch-off voltage of the integrated device increases.

[0093] Specifically, when a low pinch-off voltage is required, the width of the arc-shaped deep P-well is increased. Since the gap space between adjacent comb active regions is fixed, increasing the width increases the number of DPWs participating in depletion within that gap. When a voltage is applied to the second source terminal of the JFET, the increased arc-shaped deep P-well, together with the P-type injection at Ptop, releases more P-type carriers. These carriers rapidly diffuse into the DNW and efficiently recombine with the N-type carriers in the DNW. Only a lower voltage is needed for the P-type carriers to cover the entire DNW current path, causing the DNW to be completely depleted, ultimately reducing the pinch-off voltage.

[0094] Specifically, when a high pinch-off voltage is required by the system, the width of the arc-shaped deep P-well is reduced. This decreases the number of DPWs participating in depletion within the fixed gap, thus reducing the total number of P-type carriers. After voltage is applied, the limited number of P-type carriers can only gradually cover a local area of ​​the DNW, failing to quickly fill the current channel; the voltage needs to be continuously increased to force P-type carriers to diffuse deeper into the DNW until the current channel is completely depleted, ultimately increasing the pinch-off voltage.

[0095] Figure 14 This is a schematic diagram illustrating how the pinch-off voltage varies with the width of the arc-shaped deep P-well in the integrated device provided in this application embodiment. Figure 14 As shown, the pinch-off voltage decreases as the width of the arc-shaped deep P-well increases.

[0096] In one embodiment, when the spacing between the arc-shaped deep P-wells increases, the depletion region of the JFET widens and the pinch-off voltage of the integrated device increases; when the spacing between the arc-shaped deep P-wells decreases, the depletion region of the JFET narrows and the pinch-off voltage of the integrated device decreases.

[0097] Specifically, when a high pinch-off voltage is required by the system, the spacing between the arc-shaped deep P-wells is increased. Due to the increased spacing between adjacent arc-shaped deep P-wells, the depletion region formed by the P-type carriers released from a single arc-shaped deep P-well cannot merge with the depletion region of an adjacent DPW, forming a wider undepleted DNW region between adjacent depletion regions. This region still retains a large number of N-type carriers and can conduct current. At this point, a higher voltage needs to be applied to the second source terminal of the JFET. The higher voltage forces P-type carriers to diffuse deeper into the DNW and into the wider-spaced undepleted region, gradually filling the undepleted N-type carrier region. Only when the voltage rises to a preset high value do P-type carriers completely cover all undepleted regions, closing the DNW current path and ultimately increasing the pinch-off voltage.

[0098] Specifically, when a low pinch-off voltage is required by the system, the spacing between the arc-shaped deep P-wells is reduced. This shortens the distance between the depletion regions of adjacent arc-shaped deep P-wells, allowing P-type carriers to quickly merge and even overlap after diffusion. The undepleted DNW region between adjacent depletion regions becomes significantly narrower, leaving only a small number of N-type carriers. Applying a lower voltage to the second source terminal can drive P-type carriers to cover the narrowly spaced undepleted region. At this lower voltage, P-type carriers do not need to diffuse over long distances to quickly recombine with the remaining N-type carriers, closing the DNW current path and ultimately reducing the pinch-off voltage.

[0099] Figure 15 This is a schematic diagram illustrating how the pinch-off voltage in an integrated device varies with the spacing between the arc-shaped deep P-wells, as provided in the embodiments of this application. Figure 15 As shown, the pinch-off voltage decreases as the spacing between the arc-shaped deep P-wells increases.

[0100] Figure 16 This is a schematic flowchart of the fabrication method of the integrated device provided in this application embodiment. This embodiment takes the formation of the integrated device of any of the above embodiments as an example to illustrate the fabrication method. The specific process of the fabrication method of the integrated device can be as follows: S1601 provides a P-type substrate.

[0101] S1602. An LDMOS is formed in a first region of a P-type substrate. The first region includes a deep N-well and a first deep P-well. The LDMOS includes a first source region, a gate, a drain region, and a first body region. The first source region is composed of an N+ region formed in the first deep P-well. The drain region is composed of an N+ region formed in the deep N-well region. The region between the drain region and the first source region is a drift region. The gate is connected end to end to form a closed surrounding structure. The surrounding structure surrounds the drift region and the drain region. The surrounding structure is located within the deep N-well region. The first body region is composed of a P+ region formed in the first deep P-well. The first body region surrounds the outside of the gate to form a first body region surrounding structure with an opening.

[0102] S1603. A JFET is formed in a second region of a P-type substrate near the drain region. The second region includes a partial deep N-well. The JFET includes a second source region, a second deep P-well, and a pinch-off region. The second deep P-well is comb-shaped, and the comb teeth in the comb shape are interspersed with the deep N-wells in the second region. The second source region is composed of several N+ regions formed in the deep N-wells between the comb teeth. The pinch-off region is composed of multiple arc-shaped deep P-wells formed in the deep N-wells near the drain region at the active region tip of each comb tooth. The JFET shares the gate and drain regions with the LDMOS.

[0103] For example, in some embodiments, the fabrication method of the integrated device may include the following steps: providing a P-type substrate; fully implanting deep N-well ions onto the P-type substrate; after photolithography, implanting deep P-well ions; removing the photoresist and cleaning; forming two deep well junctions, a deep N-well and a deep P-well, using a high-temperature push-well process; depositing silicon nitride on the wafer; performing active region photolithography; etching away silicon nitride not covered by photoresist in the active region; forming a field oxide layer using a furnace tube process; where there is no silicon nitride, a field oxide layer will grow; finally, removing the remaining silicon nitride to form the active region and the field oxide layer; after forming the active region, completing the N-well, P-well, and P-top formation using a photolithography process. Ion implantation; deposition of polycrystalline silicon material on a wafer; photolithography and etching of the polycrystalline silicon material to form a polycrystalline silicon structure; defining heavily doped N-type (N+) and heavily doped P-type (P+) regions through photolithography; deposition of a self-aligned silicide barrier oxide layer, forming the self-aligned silicide barrier layer through photolithography and etching; deposition of silicides, selectively removing cobalt / titanium nitride; deposition of a dielectric layer through chemical vapor deposition, followed by planarization and photolithography and etching to form contact holes; deposition of tungsten through physical vapor deposition, followed by planarization and deposition of aluminum through physical vapor deposition; formation of a metal layer after photolithography and etching. Deposition of an oxide layer through chemical vapor deposition, followed by photolithography and etching to form a passivation layer, completing the fabrication of the integrated device.

[0104] As can be seen from the above, the fabrication method of the integrated device provided in this application forms a first region on a P-type substrate including a deep N-well and a first deep P-well. The deep N-well and the first deep P-well constitute the basic structure of LDMOS. The distribution and interaction of different types of wells affect the electrical performance of LDMOS, such as current conduction. Since LDMOS shares part of the structure with JFET, it indirectly affects the pinch-off voltage range of JFET. The depth and concentration of the deep N-well and the first deep P-well affect the on-resistance and other performance of LDMOS. These performances are related to the electrical performance of the entire integrated device under different operating states, thereby affecting the pinch-off voltage range.

[0105] Furthermore, for LDMOS, the first source region consists of the N+ region within the first deep P-well. As one endpoint of the LDMOS current output, it determines the path and characteristics of current flow from the LDMOS, which is related to the current transport of the entire integrated device and affects the JFET's pinch-off voltage range. The gate is a closed loop structure formed end-to-end, surrounding the drift region and drain region and located within the deep N-well region. This allows for more effective control of the electric field of the drift and drain regions by the gate, enabling precise adjustment of the LDMOS's on / off state. This, in turn, affects the current distribution of the entire integrated device under different operating modes, ultimately influencing the achievable pinch-off voltage range of the JFET. The drain region consists of the N+ region within the deep N-well region and is one endpoint of the LDMOS current input. Its collaborative work with the source, drift region, and gate determines the electrical performance of the LDMOS. The shared structural characteristics of LDMOS and JFET mean that the drain-related performance affects the JFET's pinch-off voltage range. The first body region is composed of the P+ region in the first deep P-well and forms an open surrounding structure around the outside of the gate. The first body region can adjust the electrical performance of the LDMOS, such as the threshold voltage. Changes in the performance of the LDMOS will affect the JFET that shares part of the structure with it, thereby affecting the range of the JFET's pinch-off voltage.

[0106] For a JFET, the second region of the P-type substrate near the drain region includes a portion of deep N-wells, providing a specific area for JFET formation. The association of this region with the LDMOS region and the distribution of the deep N-wells affect the pinch-off voltage range. The second source region consists of the N+ regions in the deep N-wells between the comb teeth. As the current output terminal of the JFET, it determines the current output characteristics of the JFET. Different numbers and distributions of the source N+ regions will change the magnitude and distribution of the JFET current, thus affecting the pinch-off voltage range. The second deep P-well is comb-shaped with the comb teeth interspersed with the deep N-wells in the second region. The comb-shaped structure increases the contact area and interaction region between the deep P-wells and deep N-wells, making the formation and adjustment of the depletion region more flexible, thereby enabling more effective control of the pinch-off voltage and expanding the achievable range of the pinch-off voltage. The pinch-off region consists of arc-shaped deep P-wells in the deep N-wells near the drain region at the tip of the active region of the comb teeth. The arc-shaped deep P-wells allow for a more specific shape and distribution of the depletion region. Compared with traditional structures, the electric field of the depletion region can be adjusted more precisely, thereby achieving a wider pinch-off voltage range. Finally, multiple parallel comb active areas replace the existing single active area. By adjusting the number and size of the comb active areas, the DPW storage space between adjacent comb active areas can be changed. When more DPW cooperates with the P-type injection of Ptop, it can more fully exhaust DNW, thus reducing the required pinch-off voltage. Conversely, reducing the number of comb active areas reduces the total amount of DPW, retains more DNW, increases the pinch-off voltage, and directly widens the adjustment range of the pinch-off voltage. In photolithography, the arc-shaped deep P-well can avoid the right-angle diffraction interference problem of square DPWs. Without violating the design rule, the width and adjacent spacing of the arc-shaped deep P-well can be flexibly adjusted. In addition, the arc-shaped deep P-well, in conjunction with the comb-tooth active region, enables the depletion region of the DNW to achieve segmented and controllable characteristics. When the width of the arc-shaped deep P-well increases, the depletion capability of a single DPW segment is enhanced, the overall depletion region is more likely to cover the DNW, and the pinch-off voltage is reduced. When the spacing of the arc-shaped deep P-well increases, the undepleted DNW area between the depletion regions becomes wider, requiring a higher voltage to achieve complete depletion, and the pinch-off voltage increases.

[0107] It should be noted that, unless otherwise specified, the embodiments and features described in this application can be combined with each other. The features, structures, or characteristics described above can be combined in any suitable manner in one or more embodiments.

[0108] The above description is merely a preferred embodiment of this application and is not intended to limit this application. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this application should be included within the protection scope of this application.

Claims

1. An integrated device, characterized in that, The integrated device includes: P-type substrate; An LDMOS is formed in a first region of the P-type substrate, the first region including a deep N-well and a first deep P-well. The LDMOS includes a first source region, a gate, a drain region, and a first body region. The first source region is composed of an N+ region formed in the first deep P-well. The drain region is composed of an N+ region formed in the deep N-well region. The region between the drain region and the first source region is a drift region. The gate is a closed surround structure formed end-to-end, the surround structure surrounding the drift region and the drain region, and the surround structure is located within the deep N-well region. The first body region is composed of a P+ region formed in the first deep P-well, and the first body region surrounds the outside of the gate to form a first body region surround structure with an opening. A JFET is formed in a second region of the P-type substrate near the drain region, the second region including a portion of the deep N-well; the JFET includes a second source region, a second deep P-well, and a pinch-off region, the second deep P-well being comb-shaped, the comb teeth of the comb being interspersed with the deep N-wells of the second region, the second source region being composed of a plurality of N+ regions formed in the deep N-wells between the comb teeth; the pinch-off region is composed of a plurality of arc-shaped deep P-wells formed in the deep N-wells near the drain region at the tip of the active region of each comb tooth, wherein the JFET and the LDMOS share the gate and the drain region.

2. The integrated device according to claim 1, characterized in that, The number and size of the active areas of the comb teeth are determined according to the preset pinch-off voltage.

3. The integrated device according to claim 1, characterized in that, The depth of the arc-shaped deep P-well is the same as the depth of the deep N-well.

4. The integrated device according to claim 1, characterized in that, The second deep P-well also contains a second P-well and a second body region formed within the second P-well. Near the first region, the first body region surrounds the first body region at the opening of the structure and connects with the second body region within the second region.

5. The integrated device according to claim 4, characterized in that, The JFET further includes a first field oxide layer, which includes a second field oxide layer formed between the second body region and the second source region and a third field oxide layer formed between two adjacent second body regions.

6. The integrated device according to claim 5, characterized in that, The JFET also includes a first polysilicon layer, which is located above the third field oxide layer.

7. The integrated device according to claim 1, characterized in that, The LDMOS also includes a fourth field oxide layer, which isolates an active region, including the first source region, the drain region, and the first body region.

8. The integrated device according to claim 7, characterized in that, The gate includes a second polysilicon layer and a third polysilicon layer formed on the fourth field oxide layer. The outer sides of the first source region and the second polysilicon layer are self-aligned. The inner side of the second polysilicon layer extends onto a portion of the fourth field oxide layer. The third polysilicon layer and the second polysilicon layer are connected to form the surrounding structure.

9. The integrated device according to claim 1, characterized in that, The LDMOS also includes a PTOP layer of the deep N-well formed beneath the fourth field oxide layer between the first source region and the drain region.

10. A method for fabricating an integrated device, characterized in that, include: P-type substrates are provided; An LDMOS is formed in a first region of the P-type substrate. The first region includes a deep N-well and a first deep P-well. The LDMOS includes a first source region, a gate, a drain region, and a first body region. The first source region is composed of an N+ region formed in the first deep P-well. The drain region is composed of an N+ region formed in the deep N-well region. The region between the drain region and the first source region is a drift region. The gate is a closed surround structure formed by connecting the ends of the gate. The surround structure surrounds the drift region and the drain region. The surround structure is located in the deep N-well region. The first body region is composed of the P+ region formed in the first deep P-well. The first body region surrounds the outside of the gate to form a first body region surround structure with an opening. A JFET is formed in a second region of the P-type substrate near the drain region. The second region includes a portion of the deep N-well. The JFET includes a second source region, a second deep P-well, and a pinch-off region. The second deep P-well is comb-shaped, with the comb teeth interspersed with the deep N-wells in the second region. The second source region consists of N+ regions formed in the deep N-wells between the comb teeth. The pinch-off region consists of multiple arc-shaped deep P-wells formed in the deep N-wells near the drain region at the active region tip of each comb tooth. The JFET shares the gate and the drain region with the LDMOS.

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