Light emitting diode structure, micro device substrate, display panel and display device

Abstract

The invention provides a light-emitting diode structure, a micro-device substrate, a display panel and a display device, and relates to the technical field of display, and the light-emitting diode structure comprises at least two light-emitting core particles, a first electrode and a second electrode which are electrically connected. The first electrode is connected with one light-emitting core particle, and the second electrode is connected with the other light-emitting core particle; an isolation groove is arranged between every two adjacent light-emitting core particles, and a flat layer is arranged in each isolation groove. According to the light emitting diode structure, the flat layer is utilized to cure and enhance the connection between the light emitting core particles, the current efficiency is successfully doubled when the same current is input, meanwhile, the mass transfer process is simplified, and the mechanical reliability of the light emitting diode structure is improved.

Description

Technical Field

[0001] This disclosure relates to the field of display technology, and in particular to a light-emitting diode structure, a microdevice substrate, a display panel, and a display device. Background Technology

[0002] With the continuous development of science and technology, more and more display products, such as mobile phones, tablets, laptops and smart wearable devices, are being widely used in people's daily lives and work, bringing great convenience to people's daily lives and work, and becoming an indispensable tool for people today.

[0003] Micro-LEDs are widely used in display products due to their advantages such as high brightness, high contrast, and high reliability. However, in practical applications, the smaller the Micro-LED size, the more severe the sidewall damage, especially at low currents, resulting in lower current efficiency. Therefore, improving the current efficiency of Micro-LED display products is one of the urgent technical problems to be solved. Summary of the Invention

[0004] To address the aforementioned technical problems, this disclosure provides a light-emitting diode structure, a microdevice substrate, a display panel, and a display device, aiming to improve the current efficiency of display products.

[0005] In a first aspect, this disclosure provides a light-emitting diode structure, including at least two light-emitting cores electrically connected to each other, a first electrode and a second electrode; the first electrode is connected to one light-emitting core, and the second electrode is connected to the other light-emitting core. Adjacent light-emitting cores are separated by isolation trenches, and a flat layer is provided in the isolation trenches.

[0006] Optionally, the planarization layer is disposed around the epitaxial layer of the light-emitting core.

[0007] Alternatively, the electrically connected light-emitting chips are fabricated using the same epitaxial wafer.

[0008] Optionally, the first electrode and the second electrode are located on the same side of the light-emitting core; the light-emitting core includes an N-type semiconductor layer, a P-type semiconductor layer and a light-emitting layer, wherein the light-emitting layer is located between the N-type semiconductor layer and the P-type semiconductor layer, and the N-type semiconductor layer is located on the side of the light-emitting layer away from the first electrode and the second electrode; the isolation trench penetrates the P-type semiconductor layer, the light-emitting layer and at least a portion of the N-type semiconductor layer.

[0009] Optionally, the refractive index of the planarization layer is n1, and the refractive index of the N-type semiconductor layer is n2, where n1 < n2.

[0010] Optionally, the light-emitting diode structure further includes a conductive layer corresponding to the light-emitting chip, the conductive layer being located on the side of the P-type semiconductor layer away from the light-emitting layer; along the thickness direction of the epitaxial layer of the light-emitting chip, the conductive layer overlaps with and is electrically connected to the P-type semiconductor layer.

[0011] Optionally, the surface of the planarization layer facing the first electrode does not extend beyond the surface of the conductive layer facing the first electrode in the thickness direction of the epitaxial layer of the light-emitting core.

[0012] Optionally, the surface of the planarization layer facing the first electrode is flush with the surface of the N-type semiconductor layer facing the first electrode.

[0013] Optionally, the isolation trench penetrates the N-type semiconductor layer along the thickness direction of the epitaxial layer of the light-emitting core.

[0014] Optionally, the surface of the planarization layer facing away from the first electrode is flush with the surface of the N-type semiconductor layer facing away from the first electrode.

[0015] Optionally, along the thickness direction of the epitaxial layer of the light-emitting core, the thickness of the N-type semiconductor layer overlapping the isolation trench is less than or equal to 2 μm.

[0016] Optionally, the N-type semiconductor layer includes an undoped layer and a doped contact layer, wherein, along the thickness direction of the substrate, the doped contact layer is located between the undoped light-emitting layer and the undoped layer, and the isolation trench penetrates at least through the doped contact layer and overlaps with the undoped layer.

[0017] Optionally, in two adjacent light-emitting cores, along the thickness direction of the epitaxial layer of the light-emitting core, the P-type electrode of one light-emitting core and the N-type electrode of the other light-emitting core are connected by a connecting part; the connecting part is located on the side of the planarization layer near the first electrode.

[0018] Optionally, the connection portion includes a first portion and a second portion that are electrically connected, wherein, along the thickness direction of the epitaxial layer of the light-emitting core, the first portion overlaps with the light-emitting core, and the second portion does not overlap with the light-emitting core; the second portion is located on the side of the N-type semiconductor layer near the first electrode.

[0019] Optionally, a first insulating layer is included between the connector and the N-type semiconductor layer, and the first insulating layer is located on the side of the planarization layer facing the first electrode; The connecting part is electrically connected to the P-type semiconductor layer in one light-emitting chip through a through-hole penetrating the first insulating layer, and is electrically connected to the N-type semiconductor layer in another light-emitting chip through a through-hole penetrating the first insulating layer.

[0020] Optionally, the light-emitting diode structure further includes a conductive layer corresponding to the light-emitting chip. The conductive layer is located on the side of the P-type semiconductor layer away from the light-emitting layer and is electrically connected to the P-type semiconductor layer. The refractive index of the first insulating layer is n3, the refractive index of the conductive layer is n4, and the refractive index of the N-type semiconductor layer is n2, where n3 < n4 < n2.

[0021] Optionally, the light-emitting diode structure also includes a conductive layer corresponding to the light-emitting chip, the conductive layer being located on the side of the P-type semiconductor layer away from the light-emitting layer and electrically connected to the P-type semiconductor layer; The surface of the planarization layer facing the first electrode is flush with the surface of the conductive layer facing the first electrode. The connecting part is electrically connected to the conductive layer corresponding to the P-type semiconductor layer in one light-emitting chip, and is electrically connected to the N-type semiconductor layer in another light-emitting chip through a via penetrating the planarization layer.

[0022] Optionally, along the thickness direction of the epitaxial layer, the center line connecting the orthographic projections of the first electrode and the second electrode overlaps with the orthographic projection of the connecting portion.

[0023] Optionally, along the thickness direction of the epitaxial layer, the widths of the orthographic projections of the first electrode and the second electrode along the first direction are S1 and S2, respectively, and the width of the orthographic projection of the connection part along the first direction is S3, where S1=S2=S3; the first direction is parallel to the plane where the epitaxial layer is located and perpendicular to the arrangement direction of the two light-emitting cores.

[0024] Optionally, along the thickness direction of the epitaxial layer, the line connecting the centers of the orthographic projections of the first electrode and the second electrode is the first line segment; in the two electrically connected light-emitting cores, the connecting part is electrically connected to the N-type electrode through the first connecting hole, and at least the center of the first connecting hole is located on one side of the first line segment along the first direction, the first direction being parallel to the plane where the epitaxial layer is located and perpendicular to the arrangement direction of the two light-emitting cores.

[0025] Optionally, along the thickness direction of the epitaxial layer of the light-emitting core, the center line connecting the first electrode and the first connecting hole is the second line segment, and there is an included angle θ between the first line segment and the second line segment, where θ > 0.

[0026] Optionally, along the first direction and the second direction, the first connecting hole overlaps with the light-emitting layer in the corresponding light-emitting core. The second direction is the arrangement direction of adjacent light-emitting cores. The first direction and the second direction intersect and are both parallel to the plane where the epitaxial layer is located.

[0027] Optionally, the width of the connecting portion along the first direction is smaller than the width of the first electrode and the second electrode along the first direction.

[0028] Optionally, it also includes a reflective layer, which is located between the first electrode and the second electrode and the light-emitting core. The first electrode and the second electrode are electrically connected to the corresponding light-emitting core through vias, and the vias penetrate the reflective layer.

[0029] Optionally, the surface of the epitaxial layer of the light-emitting core opposite to the first and second electrodes includes multiple protruding microstructures.

[0030] Secondly, based on the same inventive concept, this disclosure also provides a microdevice substrate, including a substrate and a plurality of light-emitting diode structures as provided in the first aspect, wherein the epitaxial layer in the light-emitting diode structure is fixed to the surface of the substrate by a first adhesive layer, and the first electrode and the second electrode are located on the side of the epitaxial layer away from the substrate.

[0031] Thirdly, based on the same inventive concept, this disclosure also provides a display panel, including an array layer and a plurality of light-emitting diode structures as provided in the first aspect, wherein the first electrode and the second electrode in the light-emitting diode structure are electrically connected to pads in the array layer, respectively.

[0032] Fourthly, based on the same inventive concept, this disclosure also provides a display device, including a display panel as provided in the third aspect.

[0033] The technical solution provided in this disclosure has the following advantages compared with the prior art: The LED structure, microdevice substrate, display panel, and display device disclosed herein integrate at least two light-emitting chips in the corresponding LED structure. These two chips can be connected in series, and the isolation trenches between different chips are filled with a planarization layer. By utilizing the planarization layer to solidify and enhance the connection between the chips, the current efficiency is successfully doubled when the same input current is applied. This also simplifies the mass transfer process and improves the mechanical reliability of the LED structure. Furthermore, this disclosure effectively improves the current efficiency of the LED structure without introducing complex sidewall repair processes or epitaxial optimization processes that may lead to structural instability, thus simplifying the manufacturing process and enhancing the stability of the LED structure. Attached Figure Description

[0034] The accompanying drawings, which are incorporated in and form a part of this specification, illustrate embodiments consistent with this disclosure and, together with the description, serve to explain the principles of this disclosure.

[0035] To more clearly illustrate the technical solutions in the embodiments of this disclosure or the prior art, the accompanying drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, for those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0036] Figure 1 The figure shown is a planar schematic diagram of a light-emitting diode structure provided in an embodiment of this disclosure; Figure 2 As shown Figure 1 A cross-sectional view of a light-emitting diode (LED) structure along the AA direction; Figure 3 The figure shown is another planar schematic diagram of a light-emitting diode structure provided in an embodiment of this disclosure; Figure 4 As shown Figure 3 A BB-axis cross-sectional view of a light-emitting diode structure; Figure 5 As shown Figure 3 Another BB-axis cross-sectional view of the light-emitting diode structure; Figure 6 The diagram shown is a schematic diagram of a film layer of an epitaxial wafer provided in an embodiment of this disclosure; Figure 7 The diagram shown is a structural schematic of an epitaxial wafer after initial etching. Figure 8 As shown Figure 3 A BB-axis cross-sectional view of a light-emitting diode structure; Figure 9 The diagram shown is a schematic diagram of a film layer of an N-type semiconductor layer provided in an embodiment of this disclosure; Figure 10 As shown Figure 3 Another BB-axis cross-sectional view of the light-emitting diode structure; Figure 11 As shown Figure 3 Another BB-axis cross-sectional view of the light-emitting diode structure; Figure 12 The figure shown is another planar schematic diagram of a light-emitting diode structure provided in an embodiment of this disclosure; Figure 13 The figure shown is another planar schematic diagram of a light-emitting diode structure provided in an embodiment of this disclosure; Figure 14 As shown Figure 3 Another BB-axis cross-sectional view of the light-emitting diode structure; Figure 15 The diagram shown is an intermediate structure diagram of a light-emitting diode structure provided in the embodiments of this disclosure; Figure 16 The diagram shown is an alternative intermediate structure diagram for forming the light-emitting diode structure provided in the embodiments of this disclosure; Figure 17 The diagram shown is an alternative intermediate structure diagram for forming the light-emitting diode structure provided in the embodiments of this disclosure; Figure 18 The diagram shown is an alternative intermediate structure diagram for forming the light-emitting diode structure provided in the embodiments of this disclosure; Figure 19The diagram shown is an alternative intermediate structure diagram for forming the light-emitting diode structure provided in the embodiments of this disclosure; Figure 20 The diagram shown is an alternative intermediate structure diagram for forming the light-emitting diode structure provided in the embodiments of this disclosure; Figure 21 The diagram shown is an alternative intermediate structure diagram for forming the light-emitting diode structure provided in the embodiments of this disclosure; Figure 22 The diagram shown is an alternative intermediate structure diagram for forming the light-emitting diode structure provided in the embodiments of this disclosure; Figure 23 The diagram shows a structure after bonding a light-emitting diode structure to a sapphire substrate. Figure 24 The diagram shows a structure after the light-emitting diode structure is bonded to a sapphire substrate and a base material, respectively. Figure 25 The diagram shown is a schematic representation of a microdevice substrate provided in an embodiment of this disclosure. Figure 26 The image shown is a plan view of a display panel provided in an embodiment of this disclosure; Figure 27 As shown Figure 26 A cross-sectional view of the display panel along the CC direction; Figure 28 The diagram shown is a structural schematic of a display device provided in an embodiment of this disclosure. Detailed Implementation

[0037] To better understand the above-mentioned objectives, features, and advantages of this disclosure, the solutions disclosed herein will be further described below. It should be noted that, unless otherwise specified, the embodiments and features described herein can be combined with each other.

[0038] Numerous specific details are set forth in the following description in order to provide a full understanding of this disclosure, but this disclosure may also be implemented in other ways different from those described herein; obviously, the embodiments in the specification are only some, and not all, of the embodiments of this disclosure.

[0039] Micro-LEDs are widely used in display products due to their advantages such as high brightness, high contrast, and high reliability. However, in practical applications, the smaller the size of a Micro-LED, the more severe the sidewall damage, especially at low currents, resulting in lower current efficiency. Currently, methods to improve the current efficiency of Micro-LEDs include sidewall repair and epitaxial optimization. However, sidewall repair increases the complexity and cost of chip manufacturing, and for extremely small Micro-LEDs (e.g., less than 10 μm), accurately and uniformly repairing the sidewalls is a significant challenge. Epitaxial optimization is often limited by physical laws; for example, optimizing the quantum well structure (increasing the compositional stress of the quantum well) may lead to an increase in dislocations or structural collapse.

[0040] Therefore, this disclosure provides a light-emitting diode structure, a microdevice substrate, a display panel, and a display device. By introducing at least two light-emitting cores into the light-emitting diode structure, the current efficiency is improved, which helps to simplify the manufacturing process and improve the stability of the light-emitting diode structure.

[0041] Figure 1 The figure shown is a plan view of a light-emitting diode structure 100 provided in an embodiment of this disclosure. Figure 2 As shown Figure 1 Please refer to the AA-axis cross-sectional view of a light-emitting diode structure. Figure 1 and Figure 2 This disclosure provides a light-emitting diode structure 100, including at least two light-emitting cores D0 electrically connected, a first electrode P1 and a second electrode P2; the first electrode P1 is connected to one light-emitting core D0, and the second electrode P2 is connected to the other light-emitting core D0; an isolation trench C0 is included between adjacent light-emitting cores D0, and a planarization layer 10 is disposed in the isolation trench C0.

[0042] The light-emitting diode (LED) structure 100 provided in this disclosure embodiment may include at least two light-emitting chips D0, which may be connected in series, for example. It should be noted that this disclosure only illustrates an LED structure including two light-emitting chips D0 as an example, but it does not impose specific limitations. In some other embodiments of this disclosure, an LED structure may also include three or more light-emitting chips. In the LED structure 100 provided in this disclosure embodiment, its first electrode P1 and second electrode P2 can be considered as two electrodes for receiving external electrical signals, for example, respectively representing the positive and negative electrodes of the LED structure. The first electrode P1 is connected to one of the light-emitting chips D0 in the LED structure. The two can be directly electrically connected or connected through an intermediate connector. That is, the signal received by one electrode of one of the light-emitting chips D0 is the same as the signal received by the first electrode P1 of the LED structure. The second electrode P2 is connected to another light-emitting chip D0 in the LED structure. The two can be directly electrically connected or connected through an intermediate connector. That is, the signal received by one electrode of the other light-emitting chip D0 is the same as the signal received by the second electrode P2 of the LED structure.

[0043] Optionally, in the light-emitting diode structure 100, the P electrode of one light-emitting chip D0 is connected to the N electrode of another light-emitting chip D0. When the light-emitting diode structure includes only two light-emitting chips D0, the N electrode of one light-emitting chip D0 is electrically connected to one of the first electrode P1 and the second electrode P2, and its P electrode is connected to the N electrode of the other light-emitting chip D0. The P electrode of the other light-emitting chip D0 is connected to the other of the first electrode P1 or the second electrode P2. In this way, at least two light-emitting chips D0 are connected in series in the same light-emitting diode structure. When the same photocurrent is input, the series-connected light-emitting chips D0 can all obtain the same current, thereby doubling the current efficiency of a single light-emitting diode structure.

[0044] In the light-emitting diode (LED) structure provided in this disclosure, an isolation trench C0 is provided between adjacent light-emitting chips D0. This isolation trench C0 can separate adjacent light-emitting chips D0, for example, by breaking the transmission path of electrical signals between the epitaxial layers of different light-emitting chips D0, so that different light-emitting chips D0 are formed during the fabrication of the epitaxial layers. In particular, a planarization layer 10 is provided in the isolation trench C0. Thus, adjacent light-emitting chips D0 can be fixed together by the planarization layer 10. The planarization layer 10 increases the overall strength of the LED structure. During mass transfer, different light-emitting chips D0 in the same LED structure can be transferred simultaneously as a whole. Moreover, due to the presence of the planarization layer 10, the phenomenon of different chips in the LED structure breaking apart during the transfer process is effectively avoided.

[0045] Therefore, the LED structure provided in this disclosure integrates at least two light-emitting cores DO, and utilizes the planarization layer 10 to solidify and enhance the connection between the light-emitting cores DO, successfully doubling the current efficiency when the input current is the same. This also simplifies the mass transfer process and improves the mechanical reliability of the LED structure. Furthermore, this disclosure effectively improves the current efficiency of the LED structure without introducing complex sidewall repair processes or epitaxial optimization processes that may lead to structural instability, which helps simplify the manufacturing process and improve the stability of the LED structure.

[0046] Optionally, the planarization layer 10 is an organic material. Compared to inorganic materials (such as SiO2 or SiNx), organic materials are generally softer and can better absorb and buffer mechanical stresses generated during manufacturing processes (such as bonding) and mass transfer. Moreover, organic materials have good flowability and coatability, making planarization easier and more conducive to filling the height difference between the light-emitting core particle D0 and the isolation trench C0. In addition, most organic adhesives can be deposited through simple spin coating or spray coating processes, simplifying the manufacturing process and potentially reducing equipment investment and manufacturing costs.

[0047] Figure 1 and Figure 2 The embodiments illustrate a scheme in which a planarization layer 10 is introduced only in the isolation trench C0, but this disclosure is not limited thereto. Figure 3 The figure shown is another planar schematic diagram of a light-emitting diode structure provided in an embodiment of this disclosure. Figure 4 As shown Figure 3 Please refer to the BB-axis cross-sectional view of a light-emitting diode structure. Figure 3 and Figure 4 In one optional embodiment of this disclosure, the planarization layer 10 is disposed around the epitaxial layer of the light-emitting core D0. In the light-emitting diode structure 100 provided by this disclosure, in addition to introducing the planarization layer 10 in the isolation trench C0 to fix adjacent light-emitting cores D0, a planarization layer 10 is also introduced around the light-emitting core D0. The planarization layer 10 completely covers the outer sidewall of the light-emitting core D0, which is equivalent to providing an additional fixing or supporting structure for each light-emitting core D0 and the entire light-emitting diode structure 100. This can more effectively prevent the light-emitting core D0 from breaking or collapsing due to stress concentration during subsequent mass transfer, bonding, or use. Optionally, the width of the planarization layer 10 disposed on the outer sidewall of the light-emitting core D0 is less than or equal to the width of the planarization layer 10 in the isolation trench. Further, the width of the planarization layer 10 disposed on the outer sidewall of the light-emitting core D0 is less than or equal to 1 μm, which, while achieving fixation and protection of the light-emitting core, also helps to reduce the overall size of the light-emitting diode structure.

[0048] Furthermore, as a dielectric material, the planarization layer 10, when tightly encasing the epitaxial sidewalls of the light-emitting die D0, can act as a protective layer similar to a sidewall passivation layer, isolating the die surface from the surrounding environment and further reducing sidewall damage and low current efficiency issues caused by size reduction. Moreover, the planarization layer 10 typically possesses good sealing properties. Completely encasing the sidewalls of the light-emitting die D0 can form a physical barrier, effectively preventing moisture, chemicals, or ionic contaminants from penetrating the sensitive epitaxial layer (especially the PN junction and quantum well regions) from the sides, thereby extending the lifespan of the light-emitting diode structure.

[0049] Optionally, when a planarization layer 10 is introduced in both the isolation trench C0 and the area surrounding the light-emitting core D0 (non-isolation trench C0), the thickness of the planarization layer 10 in different areas can be set to be the same to simplify the manufacturing process and improve production efficiency.

[0050] Of course, in some other embodiments of this disclosure, the thickness of the planarization layer 10 in the isolation trench C0 can be differentiated from the thickness of the planarization layer 10 in the non-isolation trench C0, for example, please refer to Figure 5 , Figure 5 As shown Figure 3 Another BB-direction cross-sectional view of the micro-LED structure. The thickness of the planarization layer 10 in the isolation trench C0 is set to be greater than the thickness of the planarization layer 10 in the non-isolation trench C0. Considering that the main function of the planarization layer 10 in the isolation trench C0 is to fix the light-emitting core D0, provide electrical isolation, and planarize the isolation trench C0, a thicker deposition or coating can be used to achieve the above effects, ensuring sufficient mechanical strength to connect adjacent light-emitting cores D0. However, considering that the function of the planarization layer 10 in the non-isolation trench C0 (other sidewalls of the light-emitting core D0) region is sidewall passivation, mechanical support, and photoelectric performance optimization, a thinner planarization layer 10 can serve as a dielectric layer with precisely controlled thickness to optimize the reflection and emission angles of light on the Micro-LED sidewalls and improve light extraction efficiency. If the planarization layer 10 is too thick, it may form additional optical interfaces at locations where light reflection or coupling is not needed, thus increasing light loss. A thinner layer thickness is easier to precisely control, facilitating both sidewall passivation and optical functionality. In addition, a thinner planar layer 10 is used in the non-isolation trench C0 region. Under the premise of passivation and protection, the thinner organic layer can more flexibly adapt to the deformation of the semiconductor material and reduce the mechanical stress on the Micro-LED chip during thermal cycling or high-temperature bonding.

[0051] In one optional embodiment of this disclosure, the light-emitting cores D0 electrically connected in the light-emitting diode structure are fabricated using the same epitaxial wafer. For example, the specific structure of the epitaxial wafer can be found in [reference needed]. Figure 6 , Figure 6The diagram shows a film layer of an epitaxial wafer provided in an embodiment of this disclosure. The epitaxial wafer includes a substrate 00, an N-type contact layer 01, a quantum well layer 02, and a P-type contact layer 03. After forming the light-emitting diode structure of this disclosure through the epitaxial layer, the original substrate 00 on the epitaxial layer is removed. The substrate 00 can be, for example, sapphire or silicon carbide. The N-type contact layer 01 is highly doped N-type GaN, used for electron injection and providing ohmic contact with the electrodes. The quantum well layer 02 can be composed of alternately stacked potential well layers and potential barrier layers. The potential well layer is where electrons and holes recombine to emit light, determining the wavelength of the emitted light. The potential barrier layer is used to confine electrons and holes within the potential well, improving recombination efficiency. The P-type contact layer 03 is, for example, P-type GaN, used for hole injection and providing good contact with the electrodes.

[0052] In the actual manufacturing process, please refer to... Figure 6 and Figure 7 Take an epitaxial wafer and photolithographically pattern a Mesa pattern (a Mesa pattern refers to a mesa or island-like structure formed on an epitaxial wafer through an etching step; each Mesa pattern will become an independent light-emitting core) on the wafer. Use dry etching or other methods to etch through the P-type contact layer 03 and the quantum well layer 02, forming two different light-emitting cores D0 corresponding to the P-type semiconductor layer P-GaN and the light-emitting layer MQW. Figure 7 The diagram shows a structural schematic after the epitaxial wafer has undergone initial etching. In subsequent chip fabrication processes, the N-type contact layer 01 is etched to form isolation trenches C0 between adjacent light-emitting particles D0. In subsequent processes, different light-emitting particles D0 can be connected via metal interconnects, thus avoiding the traditional method of transferring two light-emitting particles to a substrate separately and then connecting them in series via metal interconnects. Specific fabrication processes will be described in subsequent embodiments. This disclosure simplifies subsequent assembly by completing the Mesa pattern, isolation trenches C0, and metal interconnects of different light-emitting particles D0 on a single epitaxial wafer. It effectively improves current efficiency without introducing complex sidewall repair processes or epitaxial optimization processes that may lead to structural instability, thus simplifying the fabrication process.

[0053] Furthermore, since the two or more light-emitting chips in the LED structure originate from the same epitaxial wafer, they possess the same material quality, epitaxial structure, and growth conditions. This ensures extremely high consistency in the electrical and photoelectric properties of all light-emitting chips in the LED structure, contributing to improved reliability and performance stability of the entire LED structure. Moreover, after different light-emitting chips in the LED structure are fabricated on the same epitaxial wafer, they can be solidified into a single high-voltage chip (the LED structure mentioned in this disclosure) through a planarization layer. During mass transfer, this high-voltage chip can be transferred simultaneously as a whole. Simultaneously, the planarization layer increases the overall strength of the LED structure, effectively preventing breakage between different chips during the transfer process.

[0054] Please continue to refer to this. Figure 2 and Figure 4 In one optional embodiment of this disclosure, the first electrode P1 and the second electrode P2 in the light-emitting diode structure are located on the same side of the light-emitting core D0; the light-emitting core D0 includes an N-type semiconductor layer N-GaN, a P-type semiconductor layer P-GaN, and a light-emitting layer MQW, wherein the light-emitting layer MQW is located between the N-type semiconductor layer N-GaN and the P-type semiconductor layer P-GaN, and the N-type semiconductor layer N-GaN is located on the side of the light-emitting layer MQW away from the first electrode P1 and the second electrode P2; the isolation trench C0 penetrates the P-type semiconductor layer P-GaN, the light-emitting layer MQW, and at least a portion of the N-type semiconductor layer N-GaN.

[0055] In this disclosure, placing the first electrode P1 and the second electrode P2 on the same side of the light-emitting core D0 facilitates high-precision bonding and mass transfer of the light-emitting diode structure to the substrate. The isolation trench C0 penetrates the P-type semiconductor layer P-GaN and the light-emitting layer MQW to form an independent MESA pattern. Furthermore, the isolation trench C0 is etched into the N-type semiconductor layer N-GaN, forming a deeper trench to ensure complete electrical isolation of the epitaxial layers of adjacent light-emitting cores D0. Simultaneously, the planarization layer 10 fills at least part of the isolation trench C0, providing strong structural support and curing, effectively preventing the light-emitting core from breaking during transfer.

[0056] In one optional embodiment of this disclosure, the refractive index of the planarization layer 10 is n1, and the refractive index of the N-type semiconductor layer N-GaN is n2, where n1 < n2. When light enters the low-refractive-index medium (planarization layer 10) from the high-refractive-index medium (N-type semiconductor layer N-GaN), the lower-refractive-index planarization layer 10 forms a low-refractive-index optical isolation layer on the side of the N-type semiconductor layer. This effectively reflects the laterally leaked light back into the core, thereby improving the light extraction efficiency of the light-emitting diode structure. Furthermore, considering that light tends to propagate in the higher-refractive-index N-type semiconductor layer N-GaN, only a portion of the light will pass through the interface. Therefore, when the planarization layer 10 is an organic material, the design of n1 < n2 can reduce the amount of light entering the planarization layer 10, thereby reducing the risk of light absorption (such as yellowing) or photodecomposition that may occur in the organic material. This helps protect the planarization layer material and ensures its long-term stability.

[0057] Optionally, 0.7 ≤ n2 - n1 ≤ 1.3. If the difference between n2 and n1 is small, for example, less than 0.7, the refractive index difference between the sidewall of the N-type semiconductor layer N-GaN and the cross-section of the planarization layer 10 is small. According to the Fresnel equation, this will result in a larger total internal reflection angle, making it easier for more light to penetrate into the planarization layer 10. This makes it easier for light to leak from one core to an adjacent core, increasing optical crosstalk. If the planarization layer 10 is an organic material and has light absorption, the light entering the planarization layer 10 will be converted into heat and lost, reducing the light extraction efficiency. On the other hand, if the difference between n2 and n1 is large, for example, greater than 1.3, a strong reflection interface will be formed on the sidewall of the N-type semiconductor layer N-GaN. The reflected light at the sidewall is easily trapped at certain specific angles inside the N-type semiconductor layer N-GaN and is difficult to guide out of the light surface, which is also not conducive to improving the light extraction efficiency.

[0058] Therefore, in this embodiment of the present disclosure, when 0.7 ≤ n2 - n1 ≤ 1.3, a sufficient refractive index difference is formed between the N-type semiconductor layer N-GaN and the planarization layer 10, ensuring that most of the laterally leaked light is reflected back into the core, significantly reducing crosstalk between cores. The interaction between the sidewalls of the N-type semiconductor and the planarization layer 10 can redirect the originally trapped light to the front for emission through multiple reflections or scatterings, thus improving light extraction efficiency.

[0059] Please continue to refer to this. Figure 2 and Figure 4 In one optional embodiment of this disclosure, the light-emitting diode structure further includes a conductive layer 11 corresponding to the light-emitting core D0. The conductive layer 11 is located on the side of the P-type semiconductor layer P-GaN away from the light-emitting layer MQW. Along the thickness direction of the epitaxial layer of the light-emitting core D0, the conductive layer 11 overlaps with and is electrically connected to the P-type semiconductor layer P-GaN. Optionally, the conductive layer 11 includes a transparent conductive material such as ITO.

[0060] Considering the typically low conductivity of the P-type semiconductor layer P-GaN, without the introduction of the conductive layer 11, current may concentrate below the metal electrode (current congestion), leading to uneven light emission. Transparent conductive layers such as ITO have higher lateral conductivity. When the conductive layer 11 is introduced on the side of the P-type semiconductor layer P-GaN away from the light-emitting layer MQW, the conductive layer 11 can effectively conduct current from the electrode to the entire light-emitting area, ensuring that current is uniformly injected into the light-emitting layer MQW below the entire P-type semiconductor layer P-GaN. Uniform current injection reduces local high-resistance regions and decreases the contact resistance between the conductive layer 11 and the P-type semiconductor layer P-GaN, which helps reduce the overall resistance of the LED structure, thereby reducing the operating voltage of the LED structure and improving the electro-optical conversion efficiency.

[0061] Please refer to Figure 4 In one optional embodiment of this disclosure, the surface of the planarization layer 10 facing the first electrode P1 does not extend beyond the surface of the conductive layer 11 facing the first electrode P1 in the thickness direction of the epitaxial layer of the light-emitting die D0. That is, the distance h1 between the surface of the planarization layer 10 facing the first electrode P1 and the surface of the N-type semiconductor layer N-GaN facing away from the first electrode P1 is less than or equal to the distance h2 between the surface of the conductive layer 11 facing the first electrode P1 and the surface of the N-type semiconductor layer N-GaN facing away from the first electrode P1. If the surface of the planarization layer 10 (typically a binder) is higher than or significantly higher than the surface of the conductive layer 11, a bump will form on the chip, leading to severe step coverage defects or uneven exposure problems in subsequent deposition and photolithography processes, affecting yield and performance. Therefore, confining the surface of the planarization layer 10 to the surface or below the conductive layer 11 helps to achieve overall microplanarization. Precise alignment and bonding are crucial in the mass transfer process of light-emitting diode structures. The planarization layer 10 is limited to the surface of the conductive layer 11 facing the first electrode P1 or below that surface, which ensures that the planarization layer 10 will not interfere with the bonding interface between the final fabricated metal pads (i.e., the first electrode P1 and the second electrode P2) and the external substrate in the vertical direction.

[0062] Please continue to refer to this. Figure 4 In one optional embodiment of this disclosure, the surface of the planarization layer 10 facing the first electrode P1 is flush with the surface of the N-type semiconductor layer N-GaN facing the first electrode P1. That is, the distance h1 between the surface of the planarization layer 10 facing the first electrode and the surface of the N-type semiconductor layer N-GaN away from the first electrode P1 is equal to the thickness of the N-type semiconductor layer N-GaN. The N-type semiconductor layer N-GaN and the planarization layer 10 together form a planarization surface, which improves the flatness of the surface of the light-emitting diode structure on the side of the N-type semiconductor layer N-GaN facing the first electrode P1.

[0063] Optionally, the light-emitting diode structure further includes a first insulating layer 13, located on the side of the planarization layer 10 facing the first electrode P1, covering the P-type semiconductor layer P-GaN and the light-emitting layer MQW. Optionally, the first insulating layer 13 is a passivation layer. By using the first insulating layer 13 to cover the electrically sensitive P-type semiconductor layer P-GaN and the light-emitting layer MQW, the optimal protection of the P-type semiconductor layer P-GaN and the light-emitting layer MQW by the passivation layer is ensured, minimizing non-radiative recombination caused by sidewall defects and improving current efficiency.

[0064] Considering the deep trenches between the N-type semiconductor layers (N-GaN) corresponding to different light-emitting cores (D0) in the MESA patterned structure, the organic planarization layer 10 can efficiently and over a large area fill these height differences. This provides a flat substrate for the subsequent deposition of passivation and metal layers, improving the quality and yield of all subsequent processes. High-quality inorganic passivation layers (such as ALD deposition) are expensive and have a slow deposition rate. If an inorganic passivation layer is used to fill the large-area isolation trenches (C0) between the N-type semiconductor layers (N-GaN), it will consume a lot of time and cost, and is not conducive to achieving planarization. Therefore, the embodiment of this disclosure uses a low-cost, easy-to-coat organic planarization layer 10 to undertake the task of large-area filling and planarization, which is a more economical and efficient choice.

[0065] Please continue to refer to this. Figure 4 In one optional embodiment of this disclosure, an isolation trench C0 penetrates the N-type semiconductor layer N-GaN along the thickness direction of the epitaxial layer of the light-emitting chip D0. This completely disconnects any lateral electrical connections that may exist between adjacent light-emitting chips D0 in the N-type semiconductor layer N-GaN. If the N-type semiconductor layer N-GaN is not completely etched through, even a tiny residual layer may form a leakage path, causing a short circuit or current bypass between the two series-connected chips. The design of the isolation trench completely penetrating the N-type semiconductor layer N-GaN ensures that the current in each chip in the series structure must pass through a pre-defined NP metal interconnect path, guaranteeing the accuracy of the electrical design and the reliability of the series performance.

[0066] Considering that the N-type semiconductor layer N-GaN is usually the thickest layer in the epitaxial structure, the isolation trench C0 formed by completely penetrating the N-type semiconductor layer N-GaN is the deepest. After the planarization layer 10 is filled, it can provide the largest mechanical support volume, which is beneficial to improving the stress resistance of the light-emitting diode structure and the yield of mass transfer. In addition, the fact that the isolation trench C0 completely penetrates the N-type semiconductor layer N-GaN helps to clearly define the lateral boundary of each chip, simplifying the subsequent photolithographic pattern design of the metal wiring connecting adjacent light-emitting chips.

[0067] Please continue to refer to this. Figure 4In one optional embodiment of this disclosure, when the isolation trench C0 completely penetrates the N-type semiconductor layer N-GaN, the surface of the planarization layer 10 facing away from the first electrode P1 is flush with the surface of the N-type semiconductor layer N-GaN facing away from the first electrode P1, thus forming a planarized surface on the side of the light-emitting diode structure facing away from the first electrode P1 and the second electrode P2.

[0068] If the bottom of the planarization layer 10 is lower or higher than the bottom of the N-type semiconductor layer N-GaN, a height difference will appear at the bottom of the LED structure. A flush bottom ensures a complete and seamless contact interface when the LED structure is bonded to other substrates, greatly improving the reliability and uniformity of the bonding. In actual fabrication, the epitaxial layer is usually placed on a substrate before the light-emitting core DO is fabricated. After fabrication, the substrate is removed to form the LED structure. In this embodiment, the planarization layer 10 (as a curing material) is flush with the bottom of the N-type semiconductor layer N-GaN, forming a continuous and reinforced bottom plane. This helps prevent cracking or damage during substrate stress removal or subsequent roughening processes in the LED structure's production.

[0069] Figure 8 As shown Figure 3 Please refer to the BB-axis cross-sectional view of a light-emitting diode structure. Figure 8 In one optional embodiment of this disclosure, along the thickness direction of the epitaxial layer of the light-emitting core D0, the thickness S0 of the N-type semiconductor layer N-GaN overlapping with the isolation trench C0 is less than or equal to 2 μm.

[0070] Although the isolation trench C0 does not completely penetrate the N-type semiconductor layer N-GaN, it only retains 2 μm or less of the N-type semiconductor layer N-GaN. The etching depth is sufficient to effectively disconnect most of the lateral current channels of adjacent light-emitting chips, achieving adequate electrical isolation. This incomplete penetration method reduces the aspect ratio of the isolation trench C0, simplifies the difficulty of dry etching, and reduces damage to the deeper layers of the N-type semiconductor layer N-GaN.

[0071] Etching the N-type semiconductor layer N-GaN is a challenging process. The deeper the etching, the more difficult it is to control the sidewall tilt angle of the trench, and the longer the etching equipment runs, the more likely it is to introduce damage to the sidewalls. Therefore, using an incomplete etching method to retain a certain thickness of the N-type semiconductor layer N-GaN, reducing the etching depth, helps to improve the process yield and reduce lattice damage to the sidewalls of the N-type semiconductor layer N-GaN, thereby helping to protect the conductivity and optical conductivity properties of the N-type semiconductor layer N-GaN.

[0072] Figure 9The diagram shown is a schematic representation of an N-GaN film, an N-type semiconductor layer, provided in this embodiment. Please refer to the provided text. Figure 8 and Figure 9 In one optional embodiment of this disclosure, the N-type semiconductor layer N-GaN includes an undoped layer 91 and a doped contact layer 92. Along the thickness direction of the substrate, the doped contact layer 92 is located between the undoped layer 91 and the light-emitting layer MQW. An isolation trench C0 penetrates at least through the doped contact layer 92 and overlaps with the undoped layer 91. The doped contact layer 92 is typically a highly doped N+ film, located close to the light-emitting layer MQW, and is used to form a low-resistance ohmic contact with the metal structure (electrode or connector), serving as a key layer for power extraction from the N-electrode. The undoped layer 91 is typically intrinsic GaN and is located at the bottom of the N-type semiconductor layer.

[0073] In this embodiment, the isolation trench C0 penetrates the doped contact layer 92 and retains a portion of the undoped layer 91, effectively cutting off the lateral current between different chips, thereby effectively cutting off current crosstalk in the N-electrode region. In this embodiment, the undoped layer 91 is located on the side of the doped contact layer 92 away from the first electrode P1, and the isolation trench C0 does not penetrate the undoped layer 91. The undoped layer 91 has better crystal quality and lower light absorption. Limiting the depth of the isolation trench C0 to above the undoped layer 91 avoids excessive damage to the GaN crystal structure caused by deep etching. Simultaneously, if the undoped layer 91 is at the bottom, it may act as a light-reflecting layer 20 or a light-conducting layer; maintaining its integrity is beneficial for light extraction.

[0074] Please continue to refer to this. Figure 8 In one optional embodiment of this disclosure, in two adjacent light-emitting cores D0, along the thickness direction of the epitaxial layer of the light-emitting core D0, the P-type electrode of one light-emitting core D0 and the N-type electrode of the other light-emitting core D0 are connected by a connection portion 12; the connection portion 12 is located on the side of the planarization layer 10 near the first electrode P1. Optionally, the connection portion 12 is a metal trace. In this embodiment of the disclosure, the connection portion 12 is deposited on the surface that has been filled by the planarization layer 10. The planarization layer 10 effectively reduces the height difference of the isolation trench C0 between the N-type semiconductor layers N-GaN. This allows the connection portion 12 to be fabricated with a relatively uniform thickness, avoiding the risk of metal traces breaking, thinning, or experiencing a sharp increase in resistance when crossing large steps, thereby ensuring low resistance and high reliability of the series connection between different light-emitting cores D0.

[0075] Please continue to refer to this. Figure 8In one optional embodiment of this disclosure, a first insulating layer 13 is included between the connection portion 12 and the N-type semiconductor layer N-GaN. The first insulating layer 13 is located on the side of the planarization layer 10 facing the first electrode P1. The connection portion 12 is electrically connected to the P-type semiconductor layer P-GaN in one light-emitting chip D0 through a via penetrating the first insulating layer 13, and is electrically connected to the N-type semiconductor layer N-GaN in another light-emitting chip D0 through a via penetrating the first insulating layer 13.

[0076] The first insulating layer 13 mentioned in this embodiment can be, for example, an inorganic passivation layer, such as silicon oxide. It covers the sides and surfaces of the conductive layer 11, the P-type semiconductor layer P-GaN, the light-emitting layer MQW, and the N-type semiconductor layer N-GaN. As a high-quality inorganic dielectric, the first insulating layer 13 ensures that electrical connections can only be formed at the designed via locations, achieving protection and isolation of the epitaxial layer, minimizing non-radiative recombination caused by sidewall defects, and thus improving current efficiency.

[0077] In this embodiment, the connection hole is located on the side of the N-type semiconductor layer N-GaN and the P-type semiconductor layer P-GaN facing the first electrode P1, that is, above the N-type semiconductor layer N-GaN and the P-type semiconductor layer P-GaN. In chip manufacturing, depositing metal on a flat upper surface makes it easier to achieve uniform thin film coverage and stable ohmic contact than depositing it on inclined or irregular sidewalls. Forming a planar contact directly above the N-type semiconductor layer N-GaN and the P-type semiconductor layer P-GaN can maximize the contact area, uniformly inject current into the N-type semiconductor layer N-GaN and the P-type semiconductor layer P-GaN, and effectively reduce the current congestion effect and contact resistance in the contact area.

[0078] Please continue to refer to this. Figure 8 In one optional embodiment of this disclosure, the connecting portion 12 includes a first portion 121 and a second portion 122 that are electrically connected, wherein, along the thickness direction of the epitaxial layer of the light-emitting core D0, the first portion 121 overlaps with the light-emitting core D0, and the second portion 122 does not overlap with the light-emitting core D0; the second portion 122 is located on the side of the N-type semiconductor layer N-GaN near the first electrode P1.

[0079] In this embodiment, the planarization layer 10 fills the isolation trench C0, forming a functional pad layer for the connection portion 12. When a first insulating layer 13 is further included, the planarization layer 10 and the first insulating layer 13 together form the functional pad layer for the connection portion 12, creating a relatively flat and insulating platform. The connection portion 12 is raised above the N-type semiconductor layer N-GaN by the planarization layer 10 and the first insulating layer 13. By using the planarization layer 10 to fill the isolation trench C0, the height difference between the N-type semiconductors is eliminated, ensuring that the wiring of the connection portion 12 is fabricated on a relatively flat surface, reducing the risk of wiring breakage. The second part 122 in the connection portion 12 does not overlap with the light-emitting chip D0. That is, the second part 122 is located in the area above the isolation trench C0, arranging the functional series wiring above the non-light-emitting, non-GaN body isolation area, effectively utilizing the vertical space and horizontal non-functional space of the chip, and ensuring the effective area of ​​the light-emitting chip D0. The first part 121 overlaps with the light-emitting core D0. Through the via, the first part 121 can form a low-resistance ohmic contact with the exposed N-type semiconductor layer N-GaN, and at the same time, it can form a low-resistance ohmic contact with the exposed conductive layer 11 (e.g., ITO, located above the P-type semiconductor layer P-GaN and electrically connected to the P-type semiconductor layer P-GaN), ensuring uniform current injection.

[0080] Please continue to refer to this. Figure 8 In one optional embodiment of this disclosure, the light-emitting diode structure further includes a conductive layer 11 corresponding to the light-emitting core D0. The conductive layer 11 is located on the side of the P-type semiconductor layer P-GaN away from the light-emitting layer MQW and is electrically connected to the P-type semiconductor layer P-GaN. The refractive index of the first insulating layer 13 is n3, the refractive index of the conductive layer 11 is n4, and the refractive index of the N-type semiconductor layer N-GaN is n2, where n3 < n4 < n2. In this disclosure, the first insulating layer 13 may include, for example, silicon oxide, and the conductive layer 11 may include, for example, ITO.

[0081] In this embodiment, the refractive index n4 of the conductive layer 11 is less than the refractive index n2 of the N-type semiconductor layer N-GaN, and greater than the refractive index n3 of the first insulating layer 13. That is, the refractive index n4 of the conductive layer 11 is between the refractive index n2 of the N-type semiconductor layer N-GaN and the refractive index n3 of the first insulating layer 13, thus making the conductive layer 11 a good photoelectric dielectric layer. n4 < n2 ensures sufficient optical difference between the conductive layer 11 and the N-type semiconductor layer N-GaN without causing excessive interface reflection. n3 < n4 ensures a large optical difference between the conductive layer 11 and the first insulating layer 13, which helps the conductive layer 11 better fulfill its role as a conductive optical waveguide layer. This embodiment sets the refractive index to n3 < n4 < n2. By utilizing the refractive index difference of these three layers, the reflection loss of light at different interfaces can be minimized, ensuring the photoelectric performance of the conductive layer 11 in the multilayer structure.

[0082] Optionally, the refractive index of the N-type semiconductor layer N-GaN satisfies 2.2≤n2≤2.5, for example, 2.4, thereby ensuring the characteristics of the N-type semiconductor layer N-GaN as the main optical transmission medium. The refractive index of the first insulating layer 13 satisfies 1.4≤n3≤1.5, for example, 1.47. The extremely low refractive index ensures that the first insulating layer 13 can serve as an efficient optical isolation layer, while providing good electrical insulation performance. The refractive index of the conductive layer 11 satisfies 1.8≤n4≤2.1, for example, 1.96, which helps to reduce the reflection loss of light at the interface of the conductive layer 11, while ensuring the transparency and conductivity of the conductive layer 11. In this disclosure, the refractive index of the planarization layer 10 is n1, n1<n2, and optionally, 1.4≤n1≤1.9. In this way, the planarization layer 10 can be used to isolate the sidewall light of the N-type semiconductor layer N-GaN with different light-emitting cores D0, while helping the light to couple from the sidewall to the corresponding light-emitting core, which helps to improve the light extraction efficiency.

[0083] Figure 10 As shown Figure 3 Another BB-direction cross-sectional view of the light-emitting diode structure. In an optional embodiment of this disclosure, the light-emitting diode structure further includes a conductive layer 11 corresponding to the light-emitting core D0. The conductive layer 11 is located on the side of the P-type semiconductor layer P-GaN away from the light-emitting layer MQW and is electrically connected to the P-type semiconductor layer P-GaN. The surface of the planarization layer 10 facing the first electrode P1 is flush with the surface of the conductive layer 11 facing the first electrode P1. The connecting portion 12 is in contact with and electrically connected to the conductive layer 11 corresponding to the P-type semiconductor layer P-GaN in one light-emitting core D0, and is electrically connected to the N-type semiconductor layer N-GaN in another light-emitting core D0 through a via penetrating the planarization layer 10.

[0084] In this embodiment, since the surface of the planarization layer 10 is flush with the surface of the conductive layer 11, the connection portion 12 is fabricated on a very flat platform, ensuring a stable contact between the connection portion 12 and the conductive layer 11 on the P-type semiconductor layer P-GaN. The connection portion 12 contacts the upper surface of the N-type semiconductor layer N-GaN through a via on the planarization layer 10, which helps to reduce the connection resistance. Optionally, since the planarization layer 10 is flush with the surface of the conductive layer 11, the planarization layer 10 can cover the side surface of the epitaxial layer. Therefore, in this embodiment, the first insulating layer 13 (passivation layer) can be omitted, eliminating the steps of depositing and photolithographically etching the first insulating layer 13. The insulating properties of the planarization layer 10 itself can be directly utilized as the dielectric layer, reducing one thin film deposition, one photolithography, and one etching, simplifying the chip manufacturing process, and helping to reduce manufacturing costs and time. Of course, in some other embodiments of this disclosure, it can also be designed such that only the planarization layer 10 in the isolation trench C0 is flush with the surface of the conductive layer 11, and the thickness of the planarization layer in the peripheral region is less than the thickness of the planarization layer in the isolation trench. For example, the thickness of the planarization layer in the peripheral region can be the same as that of the N-type semiconductor layer. This disclosure does not specifically limit this.

[0085] It should be noted that, Figure 2 , Figure 4 and Figure 8 The embodiment only shows a scheme where the surface of the planarization layer 10 facing the first electrode P1 is flush with the surface of the N-type semiconductor layer N-GaN facing the first electrode P1. Figure 10 The illustrated embodiment only shows a configuration where the surface of the planarization layer 10 facing the first electrode P1 is flush with the surface of the conductive layer 11 facing the first electrode P1. However, this disclosure is not limited to this. In some other embodiments of this disclosure, the surface of the planarization layer 10 facing the first electrode P1 may also be located between the surface of the N-type semiconductor layer N-GaN facing the first electrode P1 and the surface of the conductive layer 11 facing the first electrode P1. For example, please refer to... Figure 5 , Figure 5 The illustrated embodiment is illustrated by taking the example that the surface of the planarization layer 10 in the isolation trench C0 facing the first electrode P1 is flush with the surface of the light-emitting layer MQW facing the first electrode P1. However, this is not a limitation. In some other embodiments of this disclosure, the surface of the planarization layer 10 in the isolation trench C0 facing the first electrode P1 may also be flush with the surface of the P-type semiconductor layer P-GaN facing the first electrode P1. Alternatively, the surface of the planarization layer 10 facing the first electrode P1 may be located at any position between the surface of the conductive layer 11 facing the first electrode P1 and the surface of the N-type semiconductor layer N-GaN facing the first electrode P1.

[0086] Figure 11 As shown Figure 3 Another BB-axis cross-sectional view of the light-emitting diode structure, compared with the aforementioned embodiment. Figure 11In the embodiment shown, the sides of the P-type semiconductor layer P-GaN, the light-emitting layer MQW, and the conductive layer 11 are inclined rather than perpendicular to the N-type semiconductor layer N-GaN. Thus, when the first insulating layer 13 is further formed, an inclined structure will also be formed on the side of the light-emitting core D0. This structure is more conducive to improving the adhesion between the film layers and improving the stability of the light-emitting diode structure.

[0087] Please refer to Figure 1 and Figure 3 In one optional embodiment of this disclosure, along the thickness direction of the epitaxial layer, the center line connecting the orthographic projections of the first electrode P1 and the second electrode P2 overlaps with the orthographic projection of the connecting portion 12.

[0088] In this disclosure, the center line connecting the orthographic projections of the first electrode P1 and the second electrode P2 connects to the center point of the positive and negative pads (first electrode P1 and second electrode P2) ultimately used to receive external signals, representing the main axis of current injection. The connecting portion 12 is used to realize the electrical connection between the P electrode and the N electrode in adjacent light-emitting cores D0. In this embodiment, the orthographic projection of the connecting portion 12 overlaps with the aforementioned center line, indicating that the connecting portion 12 is arranged on the central path between the first electrode P1 and the second electrode P2. If the connecting portion 12 deviates from the center line connecting the two main electrodes, the current path may be unbalanced as it passes through the pads, enters the connecting portion 12, and is redistributed to the two cores, leading to current congestion or increased local resistance. Placing the connecting portion 12 on the center line achieves uniform resistance distribution and minimal resistance loss, ensuring a high degree of consistency in the operating current and voltage of the two series-connected cores, which is beneficial for ensuring the current efficiency and stability of the light-emitting diode structure. Meanwhile, the above-mentioned arrangement helps to improve the geometric symmetry of the light-emitting diode structure. The symmetrical layout makes it easier to control process parameters (such as photolithography alignment, thin film uniformity, etc.) during the fabrication process. Especially when multilayer metal wiring and complex structures are involved, the symmetrical structure helps to improve the stress uniformity of the light-emitting diode structure under thermal cycling and mechanical stress. Optionally, along the thickness direction of the epitaxial layer, the center line connecting the orthographic projections of the first electrode P1 and the second electrode P2 is on the same straight line as the center line of the orthographic projection of the connecting portion 12.

[0089] Figure 12 The diagram shown is another planar schematic of a light-emitting diode structure provided in this embodiment of the present disclosure. Please refer to [the diagram]. Figure 12 In one optional embodiment of this disclosure, along the thickness direction of the epitaxial layer, the widths of the orthographic projections of the first electrode P1 and the second electrode P2 along the first direction D1 are S1 and S2, respectively, and the width of the orthographic projection of the connecting portion 12 along the first direction D1 is S3, where S1=S2=S3; the first direction D1 is parallel to the plane where the epitaxial layer is located and perpendicular to the arrangement direction of the two light-emitting cores.

[0090] In this embodiment, the widths of the first electrode P1, the second electrode P2, and the connector 12 are equal, which helps ensure consistent current transmission capacity throughout the path, thereby minimizing resistance and power consumption. In the direction perpendicular to the current flow (i.e., the width direction), the width of the metal line directly determines its cross-sectional area. If S1=S2=S3 and the thickness of the metal interconnect is uniform, the lateral resistance of the current transmission path on the final pad and connector 12 will be uniform. This avoids current bottlenecks and localized Joule heating caused by sudden narrowing of the trace. Furthermore, the equal width of these three key metal structures—the first electrode P1, the second electrode P2, and the connector 12—simplifies the design of the photomask, reduces process deviations in metal deposition and photolithography alignment, and improves production yield. Combined with the aforementioned center routing principle, the equal width ensures that the current flows through the connector 12 and the final power-taking pad at the same current density. This guarantees a high degree of consistency in the operating state of the series-connected light-emitting chips, contributing to the expected doubling of current efficiency.

[0091] Figure 13 The diagram shown is another planar schematic of a light-emitting diode structure provided in this embodiment of the present disclosure. Please refer to [the diagram]. Figure 13 In one optional embodiment of this disclosure, along the thickness direction of the epitaxial layer, the line connecting the centers of the orthogonal projections of the first electrode P1 and the second electrode P2 is the first line segment L1; among the two electrically connected light-emitting cores, the connecting part 12 is electrically connected to the N-type electrode through the first connecting hole K1, and the connecting part 12 is electrically connected to the P-type electrode through the second connecting hole K2. At least the center of the first connecting hole K1 is located on one side of the first line segment L1 along the first direction D1. The first direction D1 is parallel to the plane where the epitaxial layer is located and perpendicular to the arrangement direction of the two light-emitting cores.

[0092] In this embodiment, since the center of the first connection hole K1 corresponding to the N-type electrode is offset from the main axis (first line segment L1), the connection portion 12 (metal interconnect trace) will be shifted to that side. This offset prevents the metal trace (connection portion 12) from occupying too much of the central area between the chips. By placing the non-light-emitting, light-shielding metal structure (connection portion 12) on one side of the first line segment L1, the light-emitting layer MQW on the other side can obtain a larger lateral space, thereby increasing the effective light-emitting area of ​​the light-emitting chip D0, which is beneficial to improving the overall luminous brightness of the light-emitting diode structure.

[0093] Although deviating the first connection hole K1 corresponding to the N electrode from the center line may slightly increase the asymmetry of the current path (resulting in a slight increase in resistance or a slightly uneven current distribution), the light efficiency of the light-emitting diode structure is often more critical than the electrical efficiency in high-resolution displays. Therefore, the above asymmetric design is to pursue the largest light-emitting area and the highest brightness, which is especially suitable for display applications that require high brightness.

[0094] Optionally, the line connecting the center of the second connecting hole K2 corresponding to the P-type electrode and the center of the first connecting hole K1 corresponding to the N-type electrode is parallel to the aforementioned first line segment L1. In this way, the orthographic projection of the connecting part 12 can present a regular rectangular structure, which helps to simplify the manufacturing process of the connecting part 12.

[0095] Please continue to refer to this. Figure 13 In one optional embodiment of this disclosure, along the thickness direction of the epitaxial layer of the light-emitting core, the center line connecting the orthographic projections of the first electrode P1 and the first connecting hole K1 is a second line segment L2, and there is an included angle θ between the first line segment L1 and the second line segment L2, where θ > 0. The first line segment L1 connects the center point of the first electrode P1 and the second electrode P2, belonging to the external current axis. The second line segment L2 connects the center point of the first electrode P1 and the center point of the first connecting hole K1 corresponding to the N-type electrode. When the included angle is greater than 0, it means that the center of the N-type electrode is not located on the center line connecting the first electrode P1 and the second electrode P2, and the N-type electrode is offset relative to the aforementioned center line. This offset method frees up space for the light-emitting layer MQW, which is beneficial for increasing the area of ​​the light-emitting layer MQW and improving the effective light-emitting area of ​​the light-emitting diode structure.

[0096] Optionally, θ < 30°, and further, θ = 15°. This effectively pushes the N-type electrode and the wiring of the connecting portion 12, which act as light-shielding elements, away from the core region of the light-emitting core D0, freeing up space for an increased area of ​​the MQW light-emitting layer. Without increasing the unit size of the entire LED structure, the effective area of ​​the MQW light-emitting layer is maximized, thereby significantly improving the overall brightness of the LED structure. Furthermore, when θ = 15°, this angle ensures a small increase in the internal path length of the current from the first electrode P1 to the N-type electrode. Therefore, the resulting increase in series resistance and current distribution non-uniformity are acceptable and controllable, and do not negate the optical benefits brought by the increased light-emitting area. Of course, in other embodiments of this disclosure, the angle between the first segment L1 and the second segment L2 can be set according to actual needs, and this disclosure does not specifically limit this.

[0097] Please continue to refer to this. Figure 13 In one optional embodiment of this disclosure, along the first direction D1 and the second direction D2, the first connecting hole K1 overlaps with the luminescent layer MQW in the corresponding luminescent core D0. The second direction D2 is the arrangement direction of adjacent luminescent cores D0. The first direction D1 and the second direction D2 intersect and are both parallel to the plane where the epitaxial layer is located.

[0098] In this embodiment, since the first connection hole K1 corresponding to the N-type electrode is offset relative to the center line connecting the first electrode P1 and the second electrode P2, the area below the first connection hole K1 corresponding to the N-type electrode can serve as an area expansion region for the light-emitting layer MQW in the planar diagram, making the orthographic projection of the light-emitting layer MQW present an L-shaped structure. Thus, along the first direction D1 and the second direction D2, the first connection hole K1 corresponding to the N-type electrode is adjacent to the light-emitting layer MQW. Compared to a symmetrical layout, the L-shaped structure in this embodiment adds a net increase in the light-emitting area compared to the original square structure of the light-emitting layer MQW. Through a clever geometric layout, the N-type electrode is placed at the corner of the L-shaped light-emitting layer MQW, thereby leaving more lateral area for the main body of the light-emitting layer MQW, effectively increasing the area of ​​the light-emitting layer MQW and improving the overall brightness of the light-emitting diode structure.

[0099] Furthermore, the above design ensures that the N-type electrode is adjacent to the MQW light-emitting layer along both the first direction D1 and the second direction. This bidirectional adjacency guarantees that the N-type electrode can simultaneously receive current from two directions, maximizing the contact area and achieving optimal current diffusion and minimum contact resistance. Simultaneously, the N-type electrode avoids the main body region of the MQW light-emitting layer, ensuring that the main body region of the MQW remains continuous and unobstructed by metal, thereby guaranteeing light extraction efficiency.

[0100] Please continue to refer to this. Figure 13 In one optional embodiment of this disclosure, the width S01 of the connecting portion 12 along the first direction D1 is smaller than the widths of the first electrode P1 and the second electrode P2 along the first direction D1. In this embodiment, the first electrode P1 and the second electrode P2 are the final interfaces for current injection and extraction. Setting the widths of the first electrode P1 and the second electrode P2 to be larger helps to reduce contact resistance, ensure smooth current injection, and reduce current congestion at the final extraction end. At the same time, by narrowing the width of the connecting portion 12, its optical interference to the surrounding effective light-emitting area can be reduced, thereby improving light extraction efficiency.

[0101] Furthermore, when the width of the connecting part 12 is smaller, the resistance per unit length of the connecting part 12 will increase relatively due to the reduction in its cross-sectional area. This concentrates the resistance in the connecting part 12, ensuring that the connecting part 12 dominates the resistance of the electrical connection path, while also preventing excessive heat from being generated in the regions of the first electrode P1 and the second electrode P2.

[0102] Please refer to Figure 2 , Figure 4 and Figure 11In one optional embodiment of this disclosure, a reflective layer 20 is further included. The reflective layer 20 is located between the first electrode P1 and the second electrode P2 and the light-emitting core D0. The first electrode P1 and the second electrode P2 are electrically connected to the corresponding light-emitting core D0 through vias, which penetrate the reflective layer 20. Optionally, a first insulating layer 13 is also included. The emitting layer covers the light-emitting core D0 and protects it. The aforementioned vias further penetrate the first insulating layer 13.

[0103] This embodiment introduces a reflective layer 20 into the light-emitting diode (LED) structure. The reflective layer 20 is located between the first electrode P1, the second electrode P2, and the light-emitting core DO. The reflective layer 20 can reflect the light emitted by the light-emitting layer MQW to the N-type semiconductor layer N-GaN in the LED structure and then emit it, preventing the light from being absorbed by the top first electrode P1 and the second electrode P2, thereby improving the light extraction efficiency of the LED structure. Optionally, the reflective layer 20 may be composed of alternately stacked high and low refractive index dielectrics, achieving nearly 100% high reflectivity at a specific wavelength. Simultaneously, the reflective layer 20 covers the connection portion 12, protecting it from corrosion by subsequent processes or environmental water and oxygen, thus improving the long-term reliability of the LED structure.

[0104] It should be noted that in practical applications, the first insulating layer 13 and the planarization layer 10 can be designed to form a reflective cup structure in contact with the first insulating layer 13. For example, the surface of the planarization layer 10 can be controlled to not exceed the surface of the conductive layer 11. When fabricating the first insulating layer 13, the etching process can be controlled to form an inclined, non-vertical slope on the sidewall of the first insulating layer 13 around the P-type semiconductor layer P-GaN and the light-emitting layer MQW, thereby forming a trapezoidal interface. For example, please refer to [reference needed]. Figure 11 When the reflective layer 20 is deposited on the inclined first insulating layer 13, the reflective layer 20 covers the trapezoidal slope, thus forming the same inclined profile as the first insulating layer 13, thereby creating a reflective cup structure around the light-emitting core D0. Since the light emitted by the light-emitting layer MQW is directed in all directions, the inclined sidewalls of the reflective cup structure can capture large-angle light rays that are directed towards the inclined surface and reflect them to a more vertical direction using the principle of geometric reflection, or directly guide them to the light-emitting surface of the light-emitting diode structure. Through this geometric reflection and converging, multiple reflections and absorptions of light inside the chip can be minimized, significantly improving light extraction efficiency.

[0105] Figure 14 As shown Figure 3 For another BB-axis cross-sectional view of the LED structure, please refer to [reference needed]. Figure 14In one optional embodiment of this disclosure, the surface of the epitaxial layer of the light-emitting core D0 facing away from the first electrode P1 and the second electrode P2 includes a plurality of protruding microstructures 50. In practical applications, the above-mentioned protruding microstructures 50 can be formed on the surface of the N-type semiconductor layer N-GaN facing away from the first electrode P1 and the second electrode P2 using a surface roughening process, such as a conical, pyramidal, or hemispherical structure, etc.

[0106] The surface of the flat N-type semiconductor layer N-GaN has a very small critical angle with air, causing some of the light emitted by the MQW (Maximum Transmitter Wake-up) layer to become trapped inside the N-type semiconductor layer N-GaN and unable to escape. When raised microstructures 50 are introduced onto the surface of the N-type semiconductor layer N-GaN, these microstructures create irregular interfaces. When the trapped light encounters these inclined sidewalls, its incident angle is randomized. This allows the light to escape at an angle smaller than the critical angle, thereby greatly improving the light extraction efficiency.

[0107] The following will describe the method for fabricating the light-emitting diode structure provided in the embodiments of this disclosure: Step 1: Provide the epitaxial wafer, such as... Figure 6 As shown, an epitaxial wafer can be placed on a substrate 00. A MESA pattern is photolithographically etched on the side of the epitaxial wafer facing away from the substrate. The P-type semiconductor layer P-GaN and the light-emitting layer MQW are then etched through. Partial etching of the N-type semiconductor layer N-GaN is also possible. Please refer to [reference needed]. Figure 7 .

[0108] Step 2, please refer to Figure 15 A conductive layer 11 (ITO) is sputtered onto the surface of the P-type semiconductor layer P-GaN facing away from the substrate 00. The conductive layer 11 is then photolithographically patterned, leaving only the conductive layer 11 above the P-type semiconductor layer P-GaN. Figure 15 The diagram shown is an intermediate structure diagram of a light-emitting diode structure provided in the embodiments of this disclosure.

[0109] Step 3, please refer to Figure 16 Dry etching is used to etch through or retain only a portion of the N-type semiconductor layer N-GaN with a thickness not exceeding 2 μm in the epitaxial layer, forming isolation trenches CO between different light-emitting chips D0. Figure 16 The diagram shown is an alternative intermediate structure diagram for forming the light-emitting diode structure provided in the embodiments of this disclosure.

[0110] Step 4, please refer to Figure 17 A planarization layer 10 is coated to fill at least the isolation trench C0 between the N-type semiconductor layers N-GaN. Figure 17 The diagram shown is an alternative intermediate structure diagram for forming the light-emitting diode structure provided in the embodiments of this disclosure.

[0111] Step 5, please refer to Figure 18 A first insulating layer 13 is fabricated, and a via is formed above at least a portion of the N-type semiconductor layer N-GaN or P-type semiconductor layer P-GaN of the core chip. Figure 18 The diagram shown is an alternative intermediate structure diagram for forming the light-emitting diode structure provided in the embodiments of this disclosure.

[0112] Step 6, please refer to Figure 19 Photolithographic metal interconnect patterns are formed to create connection portions 12, through which adjacent light-emitting chips are electrically connected. Figure 19 The diagram shown is an alternative intermediate structure diagram for forming the light-emitting diode structure provided in the embodiments of this disclosure.

[0113] Step 7, please refer to Figure 20 A reflective layer 20 is fabricated, and holes are made in the reflective layer 20. Figure 20 The diagram shown is an alternative intermediate structure diagram for forming the light-emitting diode structure provided in the embodiments of this disclosure.

[0114] Step 8, please refer to Figure 21 A first electrode P1 and a second electrode P2 are fabricated, such that the first electrode P1 is electrically connected to a P-type semiconductor layer P-GaN in one light-emitting chip through an opening in the reflective layer 20, and the second electrode P2 is electrically connected to an N-type semiconductor layer N-GaN in another light-emitting chip through an opening in the reflective layer 20. Figure 21 The diagram shown is an alternative intermediate structure diagram for forming the light-emitting diode structure provided in the embodiments of this disclosure.

[0115] Step 9, please refer to Figure 22 Part of the planarization layer 10 around the light-emitting diode structure is removed, leaving only a planarization layer 10 of a certain width (e.g., less than 1 μm) in the non-isolation trench C0 region around the chip to cover the side surface of the N-type semiconductor layer N-GaN of the light-emitting chip D0. Figure 22 The diagram shown is an alternative intermediate structure diagram for forming the light-emitting diode structure provided in the embodiments of this disclosure.

[0116] Step 10: Peel off the substrate from step 9 to obtain the following... Figure 4 The illustration shows a light-emitting diode structure provided in an embodiment of this disclosure. Alternatively, please refer to... Figure 14A roughening process is used to form a raised microstructure 50 on the side of the N-type semiconductor layer N-GaN away from the first electrode P1 and the second electrode P2, forming another light-emitting diode structure provided in this embodiment. Since a planarization layer 10 is provided in the isolation trench C0 in this embodiment, the planarization layer 10 can fix adjacent light-emitting chips, thus helping to avoid the problem of light-emitting chips breaking during substrate peeling, and improving product stability. It should be noted that before substrate peeling, to provide support, the wafer source in step 9 can be first bonded to a sapphire substrate 60, for example, please refer to... Figure 23 ,in, Figure 23 The diagram shows a structure after bonding a light-emitting diode structure to a sapphire substrate.

[0117] Based on step 10, the light-emitting diode structure with the protruding microstructure 50 formed can be bonded to the substrate 72 through the first adhesive layer 71 (please refer to...). Figure 14 ), and then to the sapphire substrate 60 in step 10, for example, please refer to Figure 25 This forms a substrate for microdevices, such as Figure 25 As shown, where, Figure 24 The diagram shows a structure after the light-emitting diode structure is bonded to a sapphire substrate and a base material, respectively. Figure 25 The diagram shown is a structural schematic of a microdevice substrate provided in an embodiment of this disclosure. Please refer to it. Figure 25 This disclosure also provides a microdevice substrate, including a substrate 72 and a plurality of light-emitting diode structures 100 as mentioned in the foregoing embodiments. The epitaxial layer in the light-emitting diode structure 100 is fixed to the surface of the substrate 72 by a first adhesive layer 71, and the first electrode P1 and the second electrode P2 are located on the side of the epitaxial layer away from the substrate.

[0118] The microdevice substrate can be considered an intermediate product in the formation of a display panel. When a display panel needs to be formed using a light-emitting diode (LED) structure, the microdevice substrate can be transferred to one side of the array layer in the display panel via mass transfer. The first electrode P1 and the second electrode P2 are then bonded to the pads on the array layer. Finally, the substrate 72 and the first adhesive layer 71 in the microdevice substrate are removed. Because the light-emitting chips in the LED structure are solidified together by a planarization layer to form a high-strength integrated structure, multiple light-emitting chips in the same LED structure can be transferred simultaneously in mass transfer, solving the problems of numerous transfer steps and high difficulty in traditional methods. Furthermore, due to the solidification effect of the planarization layer, the breakage of the light-emitting chips in the final display panel can be effectively avoided during the subsequent peeling of the first adhesive layer 71 and the substrate 72, which helps improve the production yield of display products.

[0119] Based on the same inventive concept, this disclosure also provides a display panel. Figure 26 The image shown is a plan view of a display panel provided in an embodiment of this disclosure. Figure 27 As shown Figure 26 Please refer to a C-axis cross-sectional view of the display panel. Figure 26 and Figure 27 The display panel 000 provided in this embodiment includes an array layer 200 and a plurality of light-emitting diode (LED) structures 100 as described in the foregoing embodiments. The first electrode P1 and the second electrode P2 of the LED structure 100 are electrically connected to pads in the array layer 200, respectively. Optionally, the display panel includes a plurality of LED structures arranged in an array. Figure 26 This invention only illustrates the arrangement of the light-emitting diode (LED) structures 100 in the display panel and does not limit the actual number or arrangement of the LED structures 100 in the display panel. The display panel provided in this embodiment has the beneficial effects of the LED structure provided in this embodiment. For details, please refer to the specific descriptions of the display panel in the above embodiments; these descriptions will not be repeated here. The specific structure of the array layer 200 in the display panel can be found in related technologies, and this disclosure does not specifically limit it.

[0120] Based on the same inventive concept, this disclosure also provides a display device. Figure 28 The diagram shown is a structural schematic of a display device 300 provided in an embodiment of this disclosure. Please refer to it. Figure 28 The display device 300 includes the display panel 000 in any of the above embodiments. The display device 300 provided in this disclosure can be any electronic device with display function, such as a mobile phone, tablet computer, laptop computer, e-reader, or television, and is particularly suitable for display devices with extremely narrow bezels or no bezels. The display device 300 provided in this disclosure has the beneficial effects of the display panel provided in this disclosure; for details, please refer to the specific descriptions of the display panel in the above embodiments, which will not be repeated here. Optionally, the display device 300 may include two or more display panels to form a large-size display device.

[0121] Understandable, Figure 28 The rectangular structure is used as an example to illustrate one shape of the display device 300. In some other embodiments of this disclosure, the display device 300 may also be circular, elliptical or any other feasible shape, and this disclosure does not specifically limit it.

[0122] It should be noted that, in this document, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0123] The above description is merely a specific embodiment of this disclosure, enabling those skilled in the art to understand or implement it. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of this disclosure. Therefore, this disclosure is not to be limited to the embodiments described herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A light emitting diode structure, characterized by The light-emitting diode structure comprises at least two light-emitting core particles, a first electrode and a second electrode electrically connected; the first electrode is connected with one of the light-emitting core particles, and the second electrode is connected with another of the light-emitting core particles; The adjacent light-emitting core particles comprise an isolation groove, and a planar layer is arranged in the isolation groove.

2. The light emitting diode structure of claim 1, wherein, The planar layer is arranged around the epitaxial layer of the light-emitting core particle.

3. The light emitting diode structure of claim 1, wherein, The electrically connected light-emitting core particles are made of the same epitaxial wafer.

4. The light emitting diode structure of claim 1, wherein, The first electrode and the second electrode are located on the same side of the light-emitting core particle; the light-emitting core particle comprises an N-type semiconductor layer, a P-type semiconductor layer and a light-emitting layer, wherein the light-emitting layer is located between the N-type semiconductor layer and the P-type semiconductor layer, and the N-type semiconductor layer is located on the side of the light-emitting layer away from the first electrode and the second electrode; the isolation groove penetrates through the P-type semiconductor layer, the light-emitting layer and at least part of the N-type semiconductor layer.

5. The light emitting diode structure of claim 4, wherein, The refractive index of the planar layer is n1, and the refractive index of the N-type semiconductor layer is n2, wherein n1 < n2.

6. The light emitting diode structure of claim 4, wherein, The light-emitting diode structure further comprises a conductive layer corresponding to the light-emitting core particle, and the conductive layer is located on the side of the P-type semiconductor layer away from the light-emitting layer; along the thickness direction of the epitaxial layer of the light-emitting core particle, the conductive layer overlaps and is electrically connected with the P-type semiconductor layer.

7. The light emitting diode structure of claim 6, wherein, The surface of the planar layer facing the first electrode does not exceed the surface of the conductive layer facing the first electrode in the thickness direction of the epitaxial layer of the light-emitting core particle.

8. The light emitting diode structure of claim 7, wherein, The surface of the planar layer facing the first electrode is flush with the surface of the N-type semiconductor layer facing the first electrode.

9. The light emitting diode structure of claim 4, wherein, Along the thickness direction of the epitaxial layer of the light-emitting core particle, the isolation groove penetrates through the N-type semiconductor layer.

10. The light emitting diode structure of claim 9, wherein, The surface of the planar layer away from the first electrode is flush with the surface of the N-type semiconductor layer away from the first electrode.

11. The light emitting diode structure of claim 4, wherein, Along the thickness direction of the epitaxial layer of the light-emitting core particle, the N-type semiconductor layer overlapping the isolation groove has a thickness less than or equal to 2 μm.

12. The light emitting diode structure of claim 11, wherein, The N-type semiconductor layer comprises a non-doped layer and a doped contact layer, wherein along the thickness direction of the substrate, the doped contact layer is located between the non-doped layer and the light-emitting layer, the isolation groove penetrates through at least the doped contact layer, and the isolation groove overlaps the non-doped layer.

13. The light emitting diode structure of claim 4, wherein, Among the two adjacent light-emitting core particles, along the thickness direction of the epitaxial layer of the light-emitting core particle, the P-type electrode of one of the light-emitting core particles and the N-type electrode of the other of the light-emitting core particles are connected through a connecting part; the connecting part is located on the side of the planar layer close to the first electrode.

14. The light emitting diode structure of claim 13, wherein, The connecting part comprises a first part and a second part electrically connected, wherein along the thickness direction of the epitaxial layer of the light-emitting core particle, the first part overlaps the light-emitting core particle, and the second part does not overlap the light-emitting core particle; the second part is located on the side of the N-type semiconductor layer close to the first electrode.

15. The light emitting diode structure of claim 13, wherein, A first insulating layer is arranged between the connecting part and the N-type semiconductor layer, and the first insulating layer is located on the side of the planar layer facing the first electrode. The connecting part is electrically connected with the P-type semiconductor layer in one of the light-emitting core particles through a via hole penetrating the first insulating layer, and is electrically connected with the N-type semiconductor layer in the other of the light-emitting core particles through a via hole penetrating the first insulating layer.

16. The light emitting diode structure of claim 15, wherein, The light-emitting diode structure further comprises a conductive layer corresponding to the light-emitting core particle, the conductive layer is located on the side of the P-type semiconductor layer away from the light-emitting layer and is electrically connected with the P-type semiconductor layer; the refractive index of the first insulating layer is n3, the refractive index of the conductive layer is n4, and the refractive index of the N-type semiconductor layer is n2, n3 < n4 < n2.

17. The light emitting diode structure of claim 13, wherein, The light-emitting diode structure further comprises a conductive layer corresponding to the light-emitting core particle, the conductive layer is located on the side of the P-type semiconductor layer away from the light-emitting layer and is electrically connected with the P-type semiconductor layer; The surface of the flat layer facing the first electrode is flush with the surface of the conductive layer facing the first electrode, the connecting part is in contact with the conductive layer corresponding to the P-type semiconductor layer in one of the light-emitting core particles, and is electrically connected with the N-type semiconductor layer in the other of the light-emitting core particles through a via hole penetrating the flat layer.

18. The light emitting diode structure of claim 13, wherein, Along the thickness direction of the epitaxial layer, the center line of the projection of the first electrode and the second electrode intersects with the projection of the connecting part.

19. The light emitting diode structure of claim 18, wherein, Along the thickness direction of the epitaxial layer, the width of the projection of the first electrode and the second electrode along the first direction is S1 and S2 respectively, and the width of the projection of the connecting part along the first direction is S3, S1 = S2 = S3; the first direction is parallel to the plane in which the epitaxial layer is located, and is perpendicular to the arrangement direction of the two light-emitting core particles.

20. The light emitting diode structure of claim 13, wherein, Along the thickness direction of the epitaxial layer, the center line of the projection of the first electrode and the second electrode is a first line segment; among the two electrically connected light-emitting core particles, the connecting part is electrically connected with the N-type electrode through a first connecting hole, and the center of at least the first connecting hole is located on one side of the first line segment along a first direction, the first direction is parallel to the plane in which the epitaxial layer is located, and is perpendicular to the arrangement direction of the two light-emitting core particles.

21. The light emitting diode structure of claim 20, wherein, Along the thickness direction of the epitaxial layer of the light-emitting core particle, the center line of the projection of the first electrode and the first connecting hole is a second line segment, and there is an included angle θ between the first line segment and the second line segment, θ > 0.

22. The light emitting diode structure of claim 20, wherein, Along the first direction and the second direction, the first connecting hole overlaps with the light-emitting layer in the corresponding light-emitting core particle, the second direction is the arrangement direction of adjacent light-emitting core particles, the first direction intersects with the second direction, and both are parallel to the plane in which the epitaxial layer is located.

23. The light emitting diode structure of claim 20, wherein, The width of the connecting part along the first direction is smaller than the width of the first electrode and the second electrode along the first direction.

24. The light emitting diode structure of claim 1, wherein, Further comprising a reflective layer, the reflective layer is located between the first electrode and the second electrode and the light-emitting core particle, the first electrode and the second electrode are electrically connected with the corresponding light-emitting core particle through a via hole, and the via hole penetrates the reflective layer.

25. The light emitting diode structure of claim 1, wherein, The surface of the epitaxial layer of the light-emitting core particle away from the first electrode and the second electrode comprises a plurality of convex microstructures.

26. A micro device substrate, characterized by A light emitting diode structure as claimed in any one of claims 1 to 25, wherein the first electrode and the second electrode are electrically connected to pads in an array layer.

27. A display panel comprising: A display panel comprising the light emitting diode structure as claimed in any one of claims 1 to 25.

28. A display device comprising: A display panel comprising the light emitting diode structure as claimed in any one of claims 1 to 25.

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