Display substrate and display device

Abstract

The invention discloses a display substrate and a display device. The display substrate comprises a plurality of circuit units, each circuit unit comprises a pixel driving circuit, each pixel driving circuit comprises a storage capacitor and a plurality of oxide transistors, and the oxide transistors at least comprise a second transistor, a third transistor and a fifth transistor. The first electrode of the second transistor is connected with the gate electrode of the third transistor and the first polar plate of the storage capacitor, the second electrode of the second transistor is connected with the first electrode of the third transistor and the second electrode of the fifth transistor, the first electrode of the fifth transistor is connected with the first power line, and the second transistor at least comprises a second active layer; the third transistor at least comprises a third active layer, and the fifth transistor at least comprises a fifth active layer; the circuit unit further comprises a shielding block, and the orthographic projection of the shielding block on the substrate is at least partially overlapped with the orthographic projection of the second active layer or the fifth active layer on the substrate.

Description

[0001] This case is a divisional application of patent application 202280003395.3. The original application was filed on September 30, 2022, with the application number 202280003395.3 and the invention title: Display substrate and its preparation method, display device. Technical Field

[0002] This article relates to, but is not limited to, the field of display technology, specifically to a display substrate and a display device. Background Technology

[0003] Organic light-emitting diodes (OLEDs) and quantum dot light-emitting diodes (QLEDs) are active-matrix display devices with advantages such as self-illumination, wide viewing angle, high contrast, low power consumption, extremely high response speed, thinness, flexibility, and low cost. With the continuous development of display technology, flexible displays using OLEDs or QLEDs as light-emitting devices and controlled by thin-film transistors (TFTs) have become the mainstream products in the display field. Summary of the Invention

[0004] The following is an overview of the subject matter described in detail herein. This overview is not intended to limit the scope of the claims.

[0005] On one hand, this disclosure provides a display substrate, including a driving circuit layer disposed on a substrate. The driving circuit layer includes a plurality of circuit units constituting a plurality of cell rows and a plurality of cell columns. Each circuit unit includes at least a pixel driving circuit, which includes a storage capacitor and a plurality of oxide transistors. The plurality of oxide transistors include at least a second transistor, a third transistor, and a fifth transistor. The first electrode of the second transistor is connected to the gate electrode of the third transistor and the first electrode of the storage capacitor, respectively. The second electrode of the second transistor is connected to the first electrode of the third transistor and the second electrode of the fifth transistor, respectively. The first electrode of the fifth transistor is connected to a first power line. The second transistor includes at least a second active layer, the third transistor includes at least a third active layer, and the fifth transistor includes at least a fifth active layer. At least one circuit unit further includes a blocking block disposed on the side of the second, third, and fifth active layers away from the substrate. The orthographic projection of the blocking block on the substrate at least partially overlaps with the orthographic projection of the second or fifth active layer on the substrate.

[0006] In an exemplary embodiment, the blocking block includes a first blocking block, the orthographic projection of the first blocking block on the substrate at least partially overlapping the orthographic projection of the fifth active layer on the substrate.

[0007] In an exemplary embodiment, the first shielding block is connected to the first power line.

[0008] In an exemplary embodiment, the blocking block includes a second blocking block, the orthographic projection of the second blocking block on the substrate at least partially overlapping the orthographic projection of the second active layer on the substrate.

[0009] In an exemplary embodiment, the display substrate further includes a light-emitting structure layer disposed on the side of the driving circuit layer away from the substrate, the light-emitting structure layer including a plurality of light-emitting devices; the driving circuit layer further includes a plurality of first initial signal lines extending along a first direction, and a plurality of second initial signal lines and low-voltage power supply lines extending along a second direction, the first direction and the second direction intersecting, the first initial signal lines being configured to provide an initial voltage signal to the pixel driving circuit, the second initial signal lines being connected to the first initial signal lines, the low-voltage power supply lines being configured to provide a low power supply voltage signal to the light-emitting devices, and the second blocking block being connected to the second initial signal lines or the low-voltage power supply lines.

[0010] In an exemplary embodiment, at least one circuit unit further includes a first connection electrode, a first end of which is connected to a first plate of the storage capacitor through a first via, and a second end of which is connected to a first region of the second active layer through a via; in at least one circuit unit, the orthographic projection of the first connection electrode on the substrate does not overlap with the orthographic projection of the second initial signal line or the low-voltage power line on the substrate.

[0011] In an exemplary embodiment, at least one circuit unit further includes a first connection electrode, a first end of which is connected to a first plate of the storage capacitor via a first via, and a second end of which is connected to a first region of the second active layer via a via; in at least one circuit unit, the orthographic projection of the first via on the substrate at least partially overlaps with the orthographic projection of the second initial signal line or the low-voltage power line on the substrate.

[0012] In an exemplary embodiment, the driving circuit layer includes at least a shielding conductive layer, a first conductive layer, a second conductive layer, a third conductive layer, and a fourth conductive layer arranged sequentially along a direction away from the substrate. The shielding conductive layer includes at least the bottom gate electrodes of a plurality of oxide transistors. The first conductive layer includes at least the first plate of the storage capacitor and the top gate electrodes of the plurality of oxide transistors. The second conductive layer includes at least the second plate of the storage capacitor and the first initial signal line. The third conductive layer includes at least the first and second electrodes of the plurality of oxide transistors. The fourth conductive layer includes at least the second initial signal line and a low-voltage power supply line.

[0013] In an exemplary embodiment, the plurality of unit columns include at least a first unit column, a second unit column, and a third unit column. The pixel driving circuit of the plurality of circuit units in the first unit column is connected to a red light-emitting device that emits red light. The pixel driving circuit of the plurality of circuit units in the second unit column is connected to a green light-emitting device that emits green light. The pixel driving circuit of the plurality of circuit units in the third unit column is connected to a blue light-emitting device that emits blue light. The low-voltage power supply line is disposed in the first and second unit columns, and the second initial signal line is disposed in the third unit column.

[0014] In an exemplary embodiment, the blocking block includes a first blocking block and a second blocking block. The orthographic projection of the first blocking block on the substrate at least partially overlaps with the orthographic projection of the fifth active layer on the substrate. The orthographic projection of the second blocking block on the substrate at least partially overlaps with the orthographic projection of the second active layer on the substrate. The first blocking block and the second blocking block are connected to different constant voltage signal lines.

[0015] In an exemplary embodiment, the pixel driving circuit further includes a first transistor, a fourth transistor, and a sixth transistor. In at least one circuit unit, the first terminal of the first transistor is connected to a first initial signal line extending along a first direction, the second terminal of the first transistor is connected to the second plate of the storage capacitor and the second terminal of the sixth transistor, the first terminal of the fourth transistor is connected to a data signal line extending along a second direction, the second terminal of the fourth transistor is connected to the second terminal of the third transistor, the first terminal of the sixth transistor is connected to the second terminal of the third transistor, and the second terminal of the sixth transistor is connected to a light-emitting device. The first direction and the second direction intersect. The first transistor includes at least a first active layer, the fourth transistor includes at least a fourth active layer, and the sixth transistor includes at least a sixth active layer.

[0016] In an exemplary embodiment, the blocking block includes a third blocking block, the orthographic projection of the third blocking block on the substrate at least partially overlapping the orthographic projection of the fourth active layer on the substrate.

[0017] In an exemplary embodiment, the blocking block includes a fourth blocking block, the orthographic projection of the fourth blocking block on the substrate at least partially overlapping the orthographic projection of the first active layer on the substrate.

[0018] In an exemplary embodiment, the blocking block includes a fifth blocking block, the orthographic projection of the fifth blocking block on the substrate at least partially overlapping the orthographic projection of the sixth active layer on the substrate.

[0019] In an exemplary embodiment, in at least one circuit unit, the first transistor, the fourth transistor, and the sixth transistor are disposed on one side of the storage capacitor in the second direction, and the second transistor and the fifth transistor are disposed on the opposite side of the storage capacitor in the second direction; the fourth transistor is disposed on one side of the storage capacitor in the second direction, the sixth transistor is disposed on the side of the fourth transistor away from the storage capacitor, the first transistor is disposed on the side of the sixth transistor away from the storage capacitor, the second transistor is disposed on the opposite side of the storage capacitor in the second direction, and the fifth transistor is disposed on the side of the second transistor away from the storage capacitor.

[0020] In an exemplary embodiment, in at least one circuit unit, the second active layer and the fourth active layer are strip-shaped extending along the first direction, the third active layer is strip-shaped extending along the second direction, the first region of the third active layer and the second region of the second active layer are interconnected integral structures, the second region of the third active layer and the second region of the fourth active layer are interconnected integral structures, and the second region of the first active layer and the first region of the sixth active layer are interconnected integral structures.

[0021] In an exemplary embodiment, in at least one circuit unit, the third transistor further includes a bottom gate electrode and a top gate electrode, the bottom gate electrode being connected to the second terminal of the fourth transistor and the first terminal of the sixth transistor, respectively, and the top gate electrode and the first plate of the storage capacitor being an integral structure.

[0022] In an exemplary embodiment, the driving circuit layer further includes a first scan signal line, a second scan signal line, a third scan signal line, a first light emission control line, and a second light emission control line extending along the first direction. In at least one circuit unit, the first scan signal line is connected to the top gate electrode of the first transistor, the second scan signal line is connected to the top gate electrode of the fourth transistor, the third scan signal line is connected to the top gate electrode of the second transistor, the first light emission control line is connected to the top gate electrode of the sixth transistor, and the second light emission control line is connected to the top gate electrode of the fifth transistor.

[0023] In an exemplary embodiment, in at least one circuit unit, the second scan signal line is located on one side of the storage capacitor in the second direction, the first light emission control line is located on the side of the second scan signal line away from the storage capacitor, the third scan signal line is located on the side opposite to the second direction of the storage capacitor, the second light emission control line is located on the side of the third scan signal line away from the storage capacitor, and the first initial signal line is disposed on the side of the first scan signal line away from the storage capacitor.

[0024] On the other hand, this disclosure also provides a display device including the aforementioned display substrate.

[0025] After reading and understanding the accompanying diagrams and detailed descriptions, the other aspects can be understood. Attached Figure Description

[0026] The accompanying drawings are used to provide an understanding of the technical solutions of this disclosure and form part of the specification. They are used together with the embodiments of this disclosure to explain the technical solutions of this disclosure and do not constitute a limitation on the technical solutions of this disclosure.

[0027] Figure 1 This is a schematic diagram of the structure of a display device; Figure 2 This is a schematic diagram of a planar structure of a display substrate; Figure 3 This is a schematic diagram of a cross-sectional structure of a display substrate; Figure 4 An equivalent circuit diagram of a pixel driving circuit is provided as an exemplary embodiment of this disclosure. Figure 5 This is a schematic diagram of a planar structure of a display substrate, which is an exemplary embodiment of the present disclosure. Figure 6 This is a schematic diagram showing the formation of the shielding conductive layer pattern according to an embodiment of the present disclosure; Figure 7A and Figure 7BThis is a schematic diagram showing the semiconductor layer pattern formed according to an embodiment of the present disclosure; Figure 8A and Figure 8B This is a schematic diagram showing the formation of the first conductive layer pattern according to an embodiment of the present disclosure; Figure 9A and Figure 9B This is a schematic diagram showing the formation of the second conductive layer pattern according to an embodiment of the present disclosure; Figure 10 This is a schematic diagram showing the formation of the fourth insulating layer pattern according to an embodiment of the present disclosure; Figure 11A and Figure 11B This is a schematic diagram showing the formation of the third conductive layer pattern according to an embodiment of the present disclosure; Figure 12 This is a schematic diagram showing the formation of the first planarization layer pattern according to an embodiment of this disclosure; Figure 13A and Figure 13B This is a schematic diagram showing the formation of the fourth conductive layer pattern according to an embodiment of the present disclosure; Figure 14 This is a schematic diagram of a planar structure of another display substrate according to an exemplary embodiment of the present disclosure; Figure 15 This is a schematic diagram of a planar structure of another display substrate according to an exemplary embodiment of the present disclosure; Figure 16 This is a schematic diagram of a planar structure of another display substrate according to an exemplary embodiment of the present disclosure; Figure 17 This is a schematic diagram of a planar structure of another display substrate according to an exemplary embodiment of the present disclosure; Figure 18 This is a schematic diagram of a planar structure of another display substrate according to an exemplary embodiment of the present disclosure; Figure 19 This is a schematic diagram of a planar structure of another display substrate according to an exemplary embodiment of the present disclosure; Figure 20 This is a schematic diagram of a planar structure of another display substrate according to an exemplary embodiment of the present disclosure; Figure 21 This is a schematic diagram of a planar structure of another display substrate according to an exemplary embodiment of the present disclosure; Figure 22 This is a schematic diagram of a planar structure of another display substrate according to an exemplary embodiment of the present disclosure; Figure 23 This is a schematic diagram of a planar structure of another display substrate according to an exemplary embodiment of the present disclosure.

[0028] Explanation of reference numerals in the attached figures: 10—Base; 11—First shading line; 12—Second shading line; 13—Third occlusion line; 14—Fourth occlusion line; 15—Fifth occlusion line; 16—Shielding electrode; 20—Driver circuit layer; 21—First active layer; 22—Second active layer; 23—Third active layer; 24—Fourth active layer; 25—Fifth active layer; 26—Sixth active layer; 27—Seventh active layer; 30—Light-emitting structure layer; 31—First scan signal line; 32—Second scan signal line; 33—Third scan signal line; 34—First light emission control line; 35—Second light emission control line; 36—First electrode plate; 40—Encapsulation structure layer; 41—Initial sub-line; 42—Second electrode plate; 43—Opening; 50—Storage capacitor; 51—First connecting electrode; 52—Second connecting electrode; 53—Third connecting electrode; 54—Fourth connecting electrode; 55—Fifth connecting electrode; 56—Sixth connecting electrode; 57—Seventh connecting electrode; 58—Initial connecting electrode; 61—Anode connecting electrode; 62—First power supply line; 63—Data signal line; 70—First initial signal line; 80—Second initial signal line; 90—Low-voltage power supply line; 91—First insulation layer; 92—Second insulating layer; 93—Third insulating layer; 94—Fourth insulating layer; 95—Fifth insulating layer; 96—First planarization layer; 97—Second planarization layer; 101—First occlusion block; 102—Second occlusion block; 103—Third occlusion block; 104—Fourth shielding block; 105—Fifth shielding block; 111—Shielding block; 121—First capacitor block; 122—Second capacitor block. Detailed Implementation

[0029] To make the objectives, technical solutions, and advantages of this disclosure clearer, embodiments of this disclosure will be described in detail below with reference to the accompanying drawings. Note that the implementation methods can be carried out in many different forms. Those skilled in the art will readily understand that the methods and content can be varied in various forms without departing from the spirit and scope of this disclosure. Therefore, this disclosure should not be construed as limited to the content described in the following embodiments. Without conflict, the embodiments and features in the embodiments of this disclosure can be arbitrarily combined with each other.

[0030] The scale of the figures in this disclosure can be used as a reference in actual manufacturing processes, but is not limited thereto. For example, the aspect ratio of the channel, the thickness and spacing of each film layer, and the width and spacing of each signal line can be adjusted according to actual needs. The number of pixels in the display substrate and the number of sub-pixels in each pixel are not limited to the quantities shown in the figures. The figures described in this disclosure are only schematic diagrams of the structure, and one aspect of this disclosure is not limited to the shapes or values ​​shown in the figures.

[0031] The ordinal numbers “first,” “second,” and “third” used in this specification are used to avoid confusion among the constituent elements, not to limit their quantity.

[0032] In this specification, for convenience, terms such as "middle," "upper," "lower," "front," "rear," "vertical," "horizontal," "top," "bottom," "inner," and "outer" are used to indicate orientation or positional relationships in conjunction with the accompanying drawings. This is solely for the purpose of facilitating the description and simplification, and does not imply that the device or component referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, it should not be construed as a limitation of this disclosure. The positional relationships of the constituent elements may be appropriately varied depending on the orientation of each constituent element being described. Therefore, the use of terms not limited to those described in the specification may be appropriately replaced as needed.

[0033] In this specification, unless otherwise expressly specified and limited, the terms "installation," "connection," and "joining" should be interpreted broadly. For example, they may refer to a fixed connection, a detachable connection, or an integral connection; a mechanical connection or an electrical connection; a direct connection, an indirect connection via an intermediate component, or a connection within two components. Those skilled in the art will understand the specific meaning of these terms in this disclosure based on the specific circumstances.

[0034] In this specification, a transistor is a device that includes at least three terminals: a gate electrode, a drain electrode, and a source electrode. A transistor has a channel region between the drain electrode (drain electrode terminal, drain region, or drain electrode) and the source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. Note that in this specification, the channel region refers to the region through which current primarily flows.

[0035] In this specification, the first electrode can be the drain electrode and the second electrode can be the source electrode, or vice versa. In cases where transistors with opposite polarities are used or the current direction changes during circuit operation, the functions of the "source electrode" and "drain electrode" may sometimes be interchanged. Therefore, in this specification, the "source electrode" and "drain electrode" can be interchanged, and the "source terminal" and "drain terminal" can be interchanged.

[0036] In this specification, "electrical connection" includes the situation where components are connected together by elements that have a certain electrical function. There are no particular limitations on what constitutes an "electrical function," as long as it allows for the transmission and reception of electrical signals between the connected components. Examples of "electrical functions" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other elements with various functions.

[0037] In this specification, "parallel" refers to two straight lines forming an angle of -10° or more and less than 10°, and therefore also includes angles of -5° or more and less than 5°. Similarly, "perpendicular" refers to two straight lines forming an angle of 80° or more and less than 100°, and therefore also includes angles of 85° or more and less than 95°.

[0038] In this specification, the terms "film" and "layer" may be interchanged. For example, "conductive layer" may sometimes be replaced with "conductive film." Similarly, "insulating film" may sometimes be replaced with "insulating layer."

[0039] In this specification, triangles, rectangles, trapezoids, pentagons, or hexagons are not strictly defined; they can be approximate triangles, rectangles, trapezoids, pentagons, or hexagons, and may have minor deformations due to tolerances, and may include chamfers, curved edges, and other variations. The term "approximately" in this disclosure means that the limits are not strictly defined, and the values ​​are within the allowable range of process and measurement errors.

[0040] Figure 1 This is a schematic diagram of the structure of a display device. Figure 1As shown, the display device may include a timing controller, a data driver, a scan driver, a light-emitting driver, and a pixel array. The timing controller is connected to the data driver, the scan driver, and the light-emitting driver. The data driver is connected to multiple data signal lines (D1 to Dn), the scan driver is connected to multiple scan signal lines (S1 to Sm), and the light-emitting driver is connected to multiple light-emitting signal lines (E1 to Eo). The pixel array may include multiple sub-pixels Pxij, where i and j can be natural numbers. At least one sub-pixel Pxij may include a circuit unit and a light-emitting device connected to the circuit unit. The circuit unit may include a pixel driving circuit, which is connected to the scan signal lines, the light-emitting signal lines, and the data signal lines. In an exemplary embodiment, the timing controller may provide grayscale values ​​and control signals of specifications suitable for the data driver to the data driver, provide clock signals, scan start signals, etc. of specifications suitable for the scan driver to the scan driver, and provide clock signals, transmit stop signals, etc. of specifications suitable for the light-emitting driver to the light-emitting driver. The data driver can use grayscale values ​​and control signals received from the timing controller to generate data voltages to be provided to data signal lines D1, D2, D3, ..., Dn. For example, the data driver can sample grayscale values ​​using a clock signal and apply the data voltage corresponding to the grayscale value to data signal lines D1 to Dn in unit rows, where n can be a natural number. The scan driver can receive clock signals, scan start signals, etc., from the timing controller to generate scan signals to be provided to scan signal lines S1, S2, S3, ..., Sm. For example, the scan driver can sequentially provide scan signals with on-level pulses to scan signal lines S1 to Sm. For example, the scan driver can be configured as a shift register and can generate scan signals by sequentially transmitting scan start signals in the form of on-level pulses to the next stage circuit under the control of a clock signal, where m can be a natural number. The LED driver can receive clock signals, transmit stop signals, etc., from the timing controller to generate transmit signals to LED signal lines E1, E2, E3, ..., Eo. For example, an LED driver can sequentially provide transmit signals with cutoff level pulses to LED signal lines E1 to Eo. For example, the LED driver can be configured as a shift register and can generate transmit signals by sequentially transmitting transmit stop signals in the form of cutoff level pulses to the next stage circuit under the control of a clock signal, where o can be a natural number.

[0041] Figure 2 This is a schematic diagram of a planar structure of a display substrate. Figure 2As shown, the display substrate may include multiple pixel units P arranged in a matrix. At least one pixel unit P may include a first sub-pixel P1 emitting a first color light, a second sub-pixel P2 emitting a second color light, and a third sub-pixel P3 emitting a third color light. Each sub-pixel may include a circuit unit and a light-emitting device. The circuit unit may include at least a pixel driving circuit, which is connected to a scan signal line, a light-emitting signal line, and a data signal line, respectively. The pixel driving circuit is configured to receive the data voltage transmitted by the data signal line and output a corresponding current to the light-emitting device under the control of the scan signal line and the light-emitting signal line. The light-emitting device in each sub-pixel is connected to the pixel driving circuit of its respective sub-pixel, and the light-emitting device is configured to emit light of a corresponding brightness in response to the current output by the pixel driving circuit of its respective sub-pixel.

[0042] In an exemplary embodiment, the first sub-pixel P1 can be a red sub-pixel (R) that emits red light, the second sub-pixel P2 can be a blue sub-pixel (B) that emits blue light, and the third sub-pixel P3 can be a green sub-pixel (G) that emits green light. In an exemplary embodiment, the shape of the sub-pixels can be rectangular, rhomboid, pentagonal, or hexagonal, and the three sub-pixels can be arranged in a horizontal, vertical, or triangular manner, etc., which is not limited herein.

[0043] In an exemplary embodiment, a pixel unit may include four sub-pixels, which may be arranged in a horizontal, vertical, or square manner, etc., and this disclosure does not limit the arrangement.

[0044] Figure 3 This is a cross-sectional structural diagram of a display substrate, illustrating the structure of three sub-pixels. For example... Figure 3 As shown, on a plane perpendicular to the display substrate, the display substrate may include a driving circuit layer 20 disposed on the substrate 10, a light-emitting structure layer 30 disposed on the side of the driving circuit layer 20 away from the substrate 10, and an encapsulation structure layer 40 disposed on the side of the light-emitting structure layer 30 away from the substrate 10. In some possible implementations, the display substrate may include other film layers, such as a touch structure layer, etc., which are not limited herein.

[0045] In an exemplary embodiment, on a plane parallel to the display substrate, the driving circuit layer 20 may include multiple circuit units. Each circuit unit may include a pixel driving circuit, as well as scan signal lines, light emission control lines, data signal lines, and a first power supply line connected to the pixel driving circuit. The pixel driving circuit may include at least multiple transistors and a storage capacitor. In a plane perpendicular to the display substrate, the driving circuit layer 20 may include, sequentially disposed on the substrate, a shielding conductive layer 20-1, a first insulating layer 91, a semiconductor layer 20-2, a second insulating layer 92, a first conductive layer 20-3, a third insulating layer 93, a second conductive layer 20-4, a fourth insulating layer 94, a third conductive layer 20-5, a fifth insulating layer 95, a first planarization layer 96, a fourth conductive layer 20-6, and a second planarization layer 97. The shielding conductive layer 20-1 may include at least multiple shielding lines, the semiconductor layer 20-2 may include at least multiple active layers of transistors, the first conductive layer 20-3 may include at least the first electrode of the storage capacitor, the second conductive layer 20-4 may include at least the second electrode of the storage capacitor, the third conductive layer 20-5 may include at least the first and second electrodes of multiple transistors, and the fourth conductive layer 20-6 may include at least the anode connection electrode.

[0046] In an exemplary embodiment, the light-emitting structure layer 30 may include multiple light-emitting devices. Each light-emitting device may include at least an anode, a pixel definition layer, an organic light-emitting layer, and a cathode. The anode is connected to the pixel driving circuit, the organic light-emitting layer is connected to the anode, and the cathode is connected to the organic light-emitting layer. The organic light-emitting layer emits light of a corresponding color under the driving of the anode and cathode. The encapsulation structure layer 40 may include a first encapsulation layer, a second encapsulation layer, and a third encapsulation layer stacked together. The first and third encapsulation layers may be made of inorganic materials, and the second encapsulation layer may be made of organic materials. The second encapsulation layer is disposed between the first and third encapsulation layers, forming an inorganic / organic / inorganic material stacked structure, which can ensure that external moisture cannot enter the light-emitting structure layer 30.

[0047] In an exemplary embodiment, the organic light-emitting layer may include a light-emitting layer (EML) and any one or more of the following: a hole injection layer (HIL), a hole transport layer (HTL), an electron blocking layer (EBL), a hole blocking layer (HBL), an electron transport layer (ETL), and an electron injection layer (EIL). In an exemplary embodiment, one or more of the hole injection layer, hole transport layer, electron blocking layer, hole blocking layer, electron transport layer, and electron injection layer of all sub-pixels may be common layers connected together, and the light-emitting layers of adjacent circuit units may have a small amount of overlap or may be isolated from each other.

[0048] As OLED display technology matures and yield rates improve, the cost of OLED display devices continues to decrease, leading to their wider application in various fields, such as medium-to-large-sized electronic products. However, with the increasing size of display substrates, the yield of substrates using low-temperature polysilicon (LTPS) thin-film transistors has decreased, resulting in higher costs. Consequently, display substrates using only oxide thin-film transistors are gaining popularity.

[0049] An exemplary embodiment of this disclosure provides a display substrate, including a driving circuit layer disposed on a substrate and a light-emitting structure layer disposed on the side of the driving circuit layer away from the substrate. The driving circuit layer includes a plurality of circuit units forming a plurality of cell rows and a plurality of cell columns, a plurality of first initial signal lines extending along a first direction, and a plurality of second initial signal lines extending along a second direction and a low-voltage power supply line. The first direction and the second direction intersect. The circuit units include at least a pixel driving circuit, the pixel driving circuit including a storage capacitor and a plurality of oxide transistors. The light-emitting structure layer includes a plurality of light-emitting devices. The first initial signal lines are configured to provide an initial voltage signal to the pixel driving circuit. The low-voltage power supply lines are configured to provide a low power supply voltage signal to the light-emitting devices. The second initial signal lines are connected to the first initial signal lines. The first initial signal lines and the second initial signal lines form a mesh-like interconnected structure.

[0050] In an exemplary embodiment, the first initial signal line includes a plurality of initial sub-lines spaced apart along the first direction, and in at least one circuit unit, the initial sub-lines adjacent in the first direction are interconnected by an initial connection electrode.

[0051] In an exemplary embodiment, in at least one circuit unit, the second initial signal line is connected to the initial connection electrode.

[0052] In an exemplary embodiment, the plurality of unit columns include at least a first unit column, a second unit column, and a third unit column. The pixel driving circuit of the plurality of circuit units in the first unit column is connected to a red light-emitting device that emits red light. The pixel driving circuit of the plurality of circuit units in the second unit column is connected to a green light-emitting device that emits green light. The pixel driving circuit of the plurality of circuit units in the third unit column is connected to a blue light-emitting device that emits blue light. The low-voltage power supply line is disposed in the first and second unit columns, and the second initial signal line is disposed in the third unit column.

[0053] The following examples illustrate the display substrate of this embodiment.

[0054] Figure 4 This is an equivalent circuit diagram of a pixel driving circuit according to an exemplary embodiment of the present disclosure. In an exemplary embodiment, the pixel driving circuit may be a 3T1C, 4T1C, 5T1C, 5T2C, 6T1C, 7T1C, or 8T1C structure. Figure 4 As shown, the pixel driving circuit of the exemplary embodiment of this disclosure may include 6 transistors (first transistor T1 to sixth transistor T6) and 1 storage capacitor C. The pixel driving circuit is connected to 8 signal lines (first scan signal line S1, second scan signal line S2, first light emission signal line E1, second light emission signal line E2, initial signal line INIT, data signal line D, first power supply line VDD and second power supply line VSS).

[0055] In an exemplary embodiment, the pixel driving circuit may include a first node N1, a second node N2, a third node N3, and a fourth node N4. The first node N1 is connected to the first electrode of the second transistor T2, the gate electrode of the third transistor T3, and the first plate of the storage capacitor C. The second node N2 is connected to the second electrode of the second transistor T2, the first electrode of the third transistor T3, and the second electrode of the fifth transistor T5. The third node N3 is connected to the second electrode of the third transistor T3, the second electrode of the fourth transistor T4, and the first electrode of the sixth transistor T6. The fourth node N4 is connected to the second electrode of the first transistor T1, the second electrode of the sixth transistor T6, and the second plate of the storage capacitor C. The fourth node N4 is also connected to the first electrode of the light-emitting device EL.

[0056] In an exemplary embodiment, the first plate of the storage capacitor C is connected to the first node N1, the second plate of the storage capacitor C is connected to the fourth node N4, that is, the first end of the storage capacitor C is connected to the gate electrode of the third transistor T3, and the second end of the storage capacitor C is connected to the first electrode of the light-emitting device EL.

[0057] In an exemplary embodiment, the gate electrode of the first transistor T1 is connected to the first scan signal line S1, the first terminal of the first transistor T1 is connected to the initial signal line INIT, and the second terminal of the first transistor T1 is connected to the second plate of the storage capacitor C and the fourth node N4. When a conduction level scan signal is applied to the first scan signal line S1, the first transistor T1 is turned on, transmitting the initialization voltage to the second plate of the storage capacitor C and the first terminal of the light-emitting device EL, respectively, thereby initializing the storage capacitor C and the light-emitting device EL.

[0058] In an exemplary embodiment, the gate electrode of the second transistor T2 is connected to the first scan signal line S1, the first electrode of the second transistor T2 is connected to the first node N1, and the second electrode of the second transistor T2 is connected to the second node N2. When a conduction-level scan signal is applied to the first scan signal line S1, the second transistor T2 connects the gate electrode of the third transistor T3 to the first electrode of the third transistor T3.

[0059] In an exemplary embodiment, the gate electrode of the third transistor T3 is connected to the first node N1, that is, the gate electrode of the third transistor T3 is connected to the first plate of the storage capacitor C. The first plate of the third transistor T3 is connected to the second node N2, and the second plate of the third transistor T3 is connected to the third node N3. The third transistor T3 can be referred to as a driving transistor. The third transistor T3 determines the magnitude of the driving current flowing between the first power line VDD and the light-emitting device based on the potential difference between its gate electrode and the first plate.

[0060] In an exemplary embodiment, the gate electrode of the fourth transistor T4 is connected to the second scan signal line S2, the first electrode of the fourth transistor T4 is connected to the data signal line D, and the second electrode of the fourth transistor T4 is connected to the third node N3. When a conduction-level scan signal is applied to the second scan signal line S2, the fourth transistor T4 causes the data voltage of the data signal line D to be input to the third node N3.

[0061] In an exemplary embodiment, the gate electrode of the fifth transistor T5 is connected to the second light-emitting signal line E2, the first electrode of the fifth transistor T5 is connected to the first power supply line VDD, and the second electrode of the fifth transistor T5 is connected to the second node N2. The gate electrode of the sixth transistor T6 is connected to the first light-emitting signal line E1, the first electrode of the sixth transistor T6 is connected to the third node N3, and the second electrode of the sixth transistor T6 is connected to the fourth node N4. When a conduction-level light-emitting signal is applied to the first light-emitting signal line E1 and the second light-emitting signal line E2, the fifth transistor T5 and the sixth transistor T6 cause the light-emitting device to emit light by forming a driving current path between the first power supply line VDD and the light-emitting device.

[0062] In an exemplary embodiment, the light-emitting device EL can be an OLED, including a stacked first electrode (anode), an organic light-emitting layer, and a second electrode (cathode), or it can be a QLED, including a stacked first electrode (anode), a quantum dot light-emitting layer, and a second electrode (cathode).

[0063] In an exemplary embodiment, the six transistors in the pixel driving circuit can be N-type transistors. Using the same type of transistors in the pixel driving circuit can simplify the process flow, reduce the processing difficulty of the display substrate, and improve the product yield.

[0064] In an exemplary embodiment, the six transistors of the pixel driving circuit can be oxide thin-film transistors (OSTs). The active layer of the OSTs can be oxide semiconductor (Oxide). OSTs have advantages such as low leakage current. By using a display substrate with OSTs, low-frequency driving can be achieved, power consumption can be reduced, and display quality can be improved.

[0065] In an exemplary embodiment, the second electrode of the light-emitting device EL is connected to a second power line VSS. The first power line VDD can be configured to provide a constant first voltage signal to the pixel driving circuit, and the second power line VSS can be configured to provide a constant second voltage signal to the pixel driving circuit, wherein the first voltage signal is greater than the second voltage signal. The initial signal line INIT can be configured to provide an initial voltage signal to the pixel driving circuit. The initial voltage signal can be a constant voltage signal, and its magnitude can be between the first voltage signal provided by the first power line VDD and the second voltage signal provided by the second power line VSS; this disclosure does not limit this.

[0066] In some examples, assuming that the first transistor T1 to the sixth transistor T6 of the pixel driving circuit are all N-type transistors, the operation of the pixel driving circuit may include the following stages.

[0067] The first stage, A1, is called the initialization stage. A high-level signal provided by the first scan signal line S1 turns on the first transistor T1 and the second transistor T2, while a high-level signal provided by the second light-emitting signal line E2 turns on the fifth transistor T5. The conduction of the first transistor T1 allows the initial voltage signal provided by the initial signal line INIT to be supplied to the fourth node N4 and the second plate of the storage capacitor C, initializing the storage capacitor C and the light-emitting device EL. This clears the original data voltage in the storage capacitor C and clears the pre-stored voltage at the first plate of the light-emitting device EL, completing the initialization process; the light-emitting element EL does not emit light. The conduction of the second transistor T2 connects the first node N1 and the second node N2. The conduction of the fifth transistor T5 allows the first voltage signal output from the first power line VDD to charge the first plate of the storage capacitor C through the fifth transistor T5, the second node N2, and the first node N1. Since the first plate of the storage capacitor C is at a high level, the third transistor T3 is turned on.

[0068] The second stage, A2, is called the data writing stage or threshold compensation stage. The second scan signal line S2 provides a high-level signal, turning on the fourth transistor T4. The turning on of the fourth transistor T4 causes the data voltage output from the data signal line D to be supplied to the first node N1 via the third node N3, the turned-on third transistor T3, the second node N2, and the turned-on second transistor T2. The difference between the data voltage output from the data signal line D and the threshold voltage of the third transistor T3 is then charged into the first plate of the storage capacitor C.

[0069] The third stage, A3, is called the light-emitting stage. The first light-emitting control line E1 and the second light-emitting signal line E2 provide a high-level signal to turn on the fifth transistor T5 and the sixth transistor T6. The first voltage signal output from the first power supply line VDD provides a driving voltage to the first terminal of the light-emitting element EL through the turned-on fifth transistor T5, third transistor T3, and sixth transistor T6, driving the light-emitting element EL to emit light.

[0070] During the driving process of the pixel driving circuit, the current flowing through the light-emitting element EL is independent of the threshold voltage of the third transistor T3. Therefore, the pixel driving circuit can better compensate for the threshold voltage of the third transistor T3.

[0071] Figure 5 This is a schematic diagram of a planar structure of a display substrate according to an exemplary embodiment of the present disclosure, illustrating the planar structure of pixel driving circuits in three circuit units within a unit row. In an exemplary embodiment, in the direction perpendicular to the display substrate, the display substrate may include a driving circuit layer disposed on a substrate, a light-emitting structure layer disposed on the side of the driving circuit layer away from the substrate, and an encapsulation structure layer disposed on the side of the light-emitting structure layer away from the substrate. In the direction parallel to the display substrate, the driving circuit layer may include circuit units constituting multiple unit rows and multiple unit columns, at least one circuit unit may include at least a pixel driving circuit, and at least one pixel driving circuit may include a storage capacitor and multiple oxide transistors. The light-emitting structure layer includes multiple light-emitting devices, and at least one light-emitting device may include an anode, an organic light-emitting layer, and a cathode.

[0072] In an exemplary embodiment, the driving circuit layer further includes multiple first initial signal lines 70 extending along a first direction X, multiple second initial signal lines 80 extending along a second direction Y, and multiple low-voltage power supply lines 90 extending along the second direction Y, wherein the first direction X and the second direction Y intersect. The first initial signal lines 70 are configured to provide an initial voltage signal to the pixel driving circuit, the low-voltage power supply lines 90 are configured to provide a low power supply voltage signal to the cathode of the light-emitting device, and the second initial signal lines 80 are connected to the first initial signal lines 70, such that the first initial signal lines 70 extending along the first direction X and the second initial signal lines 80 extending along the second direction Y form a mesh-like interconnected structure.

[0073] In an exemplary embodiment, the first initial signal line 70 may include a plurality of initial sub-lines 41 spaced apart along the first direction X. In at least one circuit unit, adjacent initial sub-lines 41 in the first direction X are interconnected by an initial connection electrode 58 to form a first initial signal line 70 extending along the first direction X.

[0074] In an exemplary embodiment, in at least one circuit unit, the second initial signal line 80 is connected to the initial connection electrode 58. Since the initial connection electrode 58 is connected to the initial sub-line 41, the connection between the second initial signal line 80 and the first initial signal line 70 is realized.

[0075] In an exemplary embodiment, the driving circuit layer may include multiple conductive layers. The initial sub-line 41, the initial connection electrode 58, and the second initial signal line 80 may be disposed in different conductive layers. In at least one circuit unit, the initial connection electrode 58 is connected to the initial sub-line 41 through a via, and the second initial signal line 80 is connected to the initial connection electrode 58 through a via.

[0076] In an exemplary embodiment, the storage capacitor of the pixel driving circuit may include a first plate and a second plate, and the plurality of oxide transistors of the pixel driving circuit may include a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, and a sixth transistor T6. In at least one circuit unit, the first terminal of the first transistor T1 is connected to the first initial signal line 70, and the second terminal of the first transistor T1 is connected to the second plate of the storage capacitor 50 and the second terminal of the sixth transistor T6. The first terminal of the second transistor T2 is connected to the first plate of the storage capacitor 50, and the second terminal of the second transistor T2 is connected to the first terminal of the third transistor T3. The first terminal of the fourth transistor T4 is connected to the data signal line 63, and the second terminal of the fourth transistor T4 is connected to the second terminal of the third transistor T3. The first terminal of the fifth transistor T5 is connected to the first power supply line 62, and the second terminal of the fifth transistor T5 is connected to the first terminal of the third transistor T3. The first terminal of the sixth transistor T6 is connected to the second terminal of the third transistor T3, and the second terminal of the sixth transistor T6 is connected to the second terminal of the first transistor T1.

[0077] In an exemplary embodiment, in at least one circuit unit, the first transistor T1, the fourth transistor T4, and the sixth transistor T6 may be located on one side of the storage capacitor 50 in the second direction Y, and the second transistor T2 and the fifth transistor T5 may be located on the opposite side of the storage capacitor 50 in the second direction Y.

[0078] In an exemplary embodiment, in at least one circuit unit, the fourth transistor T4 may be located on one side of the storage capacitor 50 in the second direction Y, the sixth transistor T6 may be located on the side of the fourth transistor T4 away from the storage capacitor 50, the first transistor T1 may be located on the side of the sixth transistor T6 away from the storage capacitor 50, the second transistor T2 may be located on the side of the storage capacitor 50 in the opposite direction of the second direction Y, and the fifth transistor T5 may be located on the side of the second transistor T2 away from the storage capacitor 50.

[0079] In an exemplary embodiment, the driving circuit layer may further include a first scan signal line 31, a second scan signal line 32, a third scan signal line 33, a first light emission control line 34, and a second light emission control line 35. The shapes of the first scan signal line 31, the second scan signal line 32, the third scan signal line 33, the first light emission control line 34, and the second light emission control line 35 may be straight lines or broken lines extending along the first direction X.

[0080] In an exemplary embodiment, the first transistor T1 to the sixth transistor T6 each include a top gate electrode and a bottom gate electrode.

[0081] In an exemplary embodiment, a first scan signal line 31 can be connected to the top gate electrode of a first transistor T1, and the first scan signal line 31 is configured to control the on and off states of the first transistor T1. A second scan signal line 32 can be connected to the top gate electrode of a fourth transistor T4, and the second scan signal line 32 is configured to control the on and off states of the fourth transistor T4. A third scan signal line 33 can be connected to the top gate electrode of a second transistor T2, and the third scan signal line 33 is configured to control the on and off states of the second transistor T2. A first light-emitting control line 34 can be connected to the top gate electrode of a sixth transistor T6, and the first light-emitting control line 34 is configured to control the on and off states of the sixth transistor T6. A second light-emitting control line 35 can be connected to the top gate electrode of a fifth transistor T5, and the second light-emitting control line 35 is configured to control the on and off states of the fifth transistor T5.

[0082] In an exemplary embodiment, in at least one circuit unit, the second scan signal line 32 may be located on one side of the storage capacitor 50 in the second direction Y, the first light emission control line 34 may be located on the side of the second scan signal line 32 away from the storage capacitor 50, and the first scan signal line 31 may be located on the side of the first light emission control line 34 away from the storage capacitor 50. The third scan signal line 33 may be located on the side opposite to the second direction Y of the storage capacitor 50, and the second light emission control line 35 may be located on the side of the third scan signal line 33 away from the storage capacitor 50.

[0083] In an exemplary embodiment, the first initial signal line 70 may be located on the side of the first scan signal line 31 away from the storage capacitor 50.

[0084] In an exemplary embodiment, the plurality of unit columns may include at least a first unit column, a second unit column, and a third unit column. The pixel driving circuits of the plurality of circuit units in the first unit column are connected to a red light-emitting device emitting red light; the pixel driving circuits of the plurality of circuit units in the second unit column are connected to a green light-emitting device emitting green light; and the pixel driving circuits of the plurality of circuit units in the third unit column are connected to a blue light-emitting device emitting blue light. A low-voltage power supply line 90 may be disposed in the first and second unit columns, and a second initial signal line 80 may be disposed in the third unit column. For example, the (n-1)th column and the nth column may be the first and second unit columns, respectively, and the (n+1)th column may be the third unit column. The low-voltage power supply line 90 may be disposed in the circuit units of the (n-1)th and nth columns, respectively, and the second initial signal line 80 may be disposed in the circuit units of the (n+1)th column.

[0085] In an exemplary embodiment, the driving circuit layer may include at least a shielding conductive layer, a first insulating layer, a semiconductor layer, a second insulating layer, a first conductive layer, a third insulating layer, a second conductive layer, a fourth insulating layer, a third conductive layer, a fifth insulating layer, a first planarization layer, and a fourth conductive layer arranged sequentially along the direction away from the substrate. The shielding conductive layer may include at least the bottom gate electrodes of a plurality of oxide transistors. The semiconductor layer may include at least the active layer of a plurality of oxide transistors. The first conductive layer may include at least the first electrode of the storage capacitor 50 and the top gate electrodes of a plurality of oxide transistors. The second conductive layer may include at least the second electrode of the storage capacitor 50 and a first initial signal line 70. The third conductive layer may include at least the first and second electrodes of a plurality of oxide transistors. The fourth conductive layer may include at least the second initial signal line 80 and a low-voltage power supply line 90.

[0086] The following exemplary description illustrates the fabrication process of the display substrate using this exemplary embodiment. The "patterning process" described in this disclosure includes, for metallic, inorganic, or transparent conductive materials, processes such as photoresist coating, mask exposure, development, etching, and photoresist stripping; for organic materials, it includes processes such as organic material coating, mask exposure, and development. Deposition can be performed using any one or more of sputtering, evaporation, and chemical vapor deposition; coating can be performed using any one or more of spraying, spin coating, and inkjet printing; etching can be performed using any one or more of dry etching and wet etching, and this disclosure does not limit the methods. A "thin film" refers to a thin film made of a certain material on a substrate using deposition, coating, or other processes. If the "thin film" does not require a patterning process during the entire fabrication process, it can also be called a "layer." If the "thin film" requires a patterning process during the entire fabrication process, it is called a "thin film" before the patterning process and a "layer" after the patterning process. The "layer" after the patterning process contains at least one "pattern." The phrase "A and B are arranged in the same layer" in this disclosure means that A and B are formed simultaneously through the same patterning process, and the "thickness" of the film layer is the dimension of the film layer in the direction perpendicular to the display substrate. In the exemplary embodiments of this disclosure, "the orthographic projection of B is within the range of the orthographic projection of A" or "the orthographic projection of A includes the orthographic projection of B" means that the boundary of the orthographic projection of B falls within the boundary range of the orthographic projection of A, or the boundary of the orthographic projection of A overlaps with the boundary of the orthographic projection of B.

[0087] In an exemplary embodiment, the fabrication process of the display substrate may include the following operations.

[0088] (1) Forming a shielding conductive layer pattern. In an exemplary embodiment, forming a shielding conductive layer pattern may include: depositing a shielding film on a substrate, patterning the shielding film using a patterning process, and forming a shielding conductive layer pattern on the substrate, such as... Figure 6 As shown.

[0089] In an exemplary embodiment, the shielding conductive layer pattern may include at least: a first shielding line 11, a second shielding line 12, a third shielding line 13, a fourth shielding line 14, a fifth shielding line 15, and a shielding electrode 16.

[0090] In an exemplary embodiment, the shapes of the first blocking line 11, the second blocking line 12, the third blocking line 13, the fourth blocking line 14, and the fifth blocking line 15 can be straight lines or broken lines extending along the first direction X.

[0091] In this disclosure, "A extends along direction B" means that A may include a main part and a secondary part connected to the main part. The main part is a line, line segment, or strip-shaped body. The main part extends along direction B, and the length of the main part extending along direction B is greater than the length of the secondary part extending along other directions. In the following description, "A extends along direction B" refers to "the main body of A extends along direction B." In an exemplary embodiment, the second direction Y may be a direction from the display area to the binding area, and the opposite direction of the second direction Y may be a direction from the binding area to the display area.

[0092] In an exemplary embodiment, the first blocking line 11 may be located on one side of the blocking electrode 16 in the second direction Y. The first blocking line 11 is configured to block the first transistor T1, reducing the influence of light on the electrical characteristics of the first transistor T1, and is also configured as the bottom gate electrode of the first transistor T1.

[0093] In an exemplary embodiment, the second blocking line 12 may be located on one side of the blocking electrode 16 in the second direction Y, and between the blocking electrode 16 and the first blocking line 11. A fourth bottom gate electrode 12-1 is provided on the side of the second blocking line 12 near the blocking electrode 16. The fourth bottom gate electrode 12-1 is configured to block the fourth transistor T4, reducing the influence of light on the electrical characteristics of the fourth transistor T4, and is also configured as the bottom gate electrode of the fourth transistor T4.

[0094] In an exemplary embodiment, the third blocking line 13 may be located on the side opposite to the second direction Y of the blocking electrode 16, such that the blocking electrode 16 is located between the second blocking line 12 and the third blocking line 13. A second bottom gate electrode 13-1 is provided on the side of the third blocking line 13 near the blocking electrode 16. The second bottom gate electrode 13-1 is configured to block the second transistor T2, reducing the influence of light on the electrical characteristics of the second transistor T2, and is also configured as the bottom gate electrode of the second transistor T2.

[0095] In an exemplary embodiment, the fourth blocking line 14 may be located between the first blocking line 11 and the second blocking line 12. The fourth blocking line 14 is configured to block the sixth transistor T6, reducing the influence of light on the electrical characteristics of the sixth transistor T6, and is also configured as the bottom gate electrode of the sixth transistor T6.

[0096] In an exemplary embodiment, the fifth blocking line 15 may be located on the side of the third blocking line 13 away from the blocking electrode 16. The fifth blocking line 15 is configured to block the fifth transistor T5, reducing the influence of light on the electrical characteristics of the fifth transistor T5, and is also configured as the bottom gate electrode of the fifth transistor T5.

[0097] In an exemplary embodiment, the shape of the blocking electrode 16 can be a strip extending along the second direction Y. The blocking electrode 16 is configured to block the third transistor T3, reducing the influence of light on the electrical characteristics of the third transistor T3, and is also configured as the bottom gate electrode of the third transistor T3.

[0098] In an exemplary embodiment, a shielding connection block 16-1 is provided at the end of the shielding electrode 16 near the first shielding line 11, and the shielding connection block 16-1 is configured to be connected to the fifth connection electrode formed subsequently.

[0099] (2) Forming a semiconductor layer pattern. In an exemplary embodiment, forming a semiconductor layer pattern may include: sequentially depositing a first insulating film and a semiconductor film on a substrate, patterning the semiconductor film using a patterning process to form a first insulating layer covering the shielding conductive layer, and a semiconductor layer pattern disposed on the first insulating layer, such as... Figure 7A and Figure 7B As shown, Figure 7B for Figure 7A A planar schematic diagram of the semiconductor layer.

[0100] In an exemplary embodiment, the semiconductor layer pattern may include the first active layer 21 of the first transistor T1 to the sixth active layer 26 of the sixth transistor T6, and the second active layer 22, the third active layer 23 and the fourth active layer 24 are interconnected integral structures, and the first active layer 21 and the sixth active layer 26 are interconnected integral structures.

[0101] In an exemplary embodiment, in the second direction Y, the first active layer 21, the fourth active layer 24 and the sixth active layer 26 may be located on one side of the third active layer 23 in the second direction Y, and the second active layer 22 and the fifth active layer 25 may be located on the opposite side of the third active layer 23 in the second direction Y.

[0102] In an exemplary embodiment, the first active layer 21 to the sixth active layer 26 can be in the shape of an "I". The second active layer 22 and the fourth active layer 24 can be in the shape of a strip extending along a first reverse direction X, and the third active layer 23 can be in the shape of a strip extending along a second direction Y. The first end of the second active layer 22 is connected to one end of the third active layer 23, and the second end of the second active layer 22 extends along the first direction X. The first end of the fourth active layer 24 is connected to the other end of the third active layer 23, and the second end of the fourth active layer 24 extends along the first direction X, so that the integrally structured second active layer 22, third active layer 23 and fourth active layer 24 form a "C" shape.

[0103] In an exemplary embodiment, the orthographic projection of the third active layer 23 onto the substrate can be within the range of the orthographic projection of the shielding electrode 16 onto the substrate, so that the channel region of the third transistor T3 can be effectively shielded by the shielding electrode 16.

[0104] In an exemplary embodiment, the active layer of each transistor may include a first region, a second region, and a channel region located between the first and second regions. In an exemplary embodiment, the second region 21-2 of the first active layer 21 and the second region 26-2 of the sixth active layer 26 are interconnected as a single structure, meaning the second region 21-2 of the first active layer 21 can serve as the second region 26-2 of the sixth active layer 26. The second region 22-2 of the second active layer 22 and the first region 23-1 of the third active layer 23 are interconnected as a single structure, meaning the second region 22-2 of the second active layer 22 can serve as the first region 23-1 of the third active layer 23. The second region 24-2 of the fourth active layer 24 and the second region 23-2 of the third active layer 23 are interconnected as a single structure, meaning the second region 24-2 of the fourth active layer 24 can serve as the first region 23-1 of the third active layer 23. The first active layer 21, the first active layer 22, the first active layer 22, the first active layer 24, the first active layer 24, the first active layer 25, the second active layer 25, and the first active layer 26 can be set individually.

[0105] In an exemplary embodiment, the semiconductor layer may be an oxide layer, and the first transistor T1 through the sixth transistor T6 are all oxide transistors. In an exemplary embodiment, the semiconductor thin film may be indium gallium zinc oxide (IGZO), which has high electron mobility. The thickness of the semiconductor layer may be approximately 20 nm to 40 nm. For example, the thickness of the semiconductor layer may be approximately 30 nm.

[0106] (3) Forming a first conductive layer pattern. In an exemplary embodiment, forming a first conductive layer pattern may include: sequentially depositing a second insulating film and a first conductive film on a substrate on which the aforementioned pattern is formed; patterning the first conductive film using a patterning process to form a second insulating layer covering the semiconductor layer pattern; and a first conductive layer pattern disposed on the second insulating layer, such as... Figure 8A and Figure 8B As shown, Figure 8B for Figure 8A A planar schematic diagram of the first conductive layer. In an exemplary embodiment, the first conductive layer may be referred to as the first gate metal (GATE1) layer.

[0107] In an exemplary embodiment, the first conductive layer pattern includes at least: a first scan signal line 31, a second scan signal line 32, a third scan signal line 33, a first light emission control line 34, a second light emission control line 35, and a first electrode 36 of a storage capacitor.

[0108] In an exemplary embodiment, the first electrode plate 36 can be rectangular in shape, with chamfered corners. The orthographic projection of the first electrode plate 36 onto the substrate at least partially overlaps with the orthographic projection of the third active layer of the third transistor T3 onto the substrate. In an exemplary embodiment, the first electrode plate 36 can simultaneously serve as one electrode plate of a storage capacitor and the top gate electrode of the third transistor T3 (driving transistor), meaning the top gate electrode of the third transistor T3 and the first electrode plate 36 of the storage capacitor are an integral structure.

[0109] In an exemplary embodiment, the shapes of the first scan signal line 31, the second scan signal line 32, the third scan signal line 33, the first light emission control line 34, and the second light emission control line 35 can be straight lines or broken lines extending along the first direction X.

[0110] In an exemplary embodiment, the first scan signal line 31 may be located on one side of the first electrode plate 36 in the second direction Y. The area where the first scan signal line 31 overlaps with the first active layer serves as the top gate electrode of the first transistor T1. That is, the first scan signal line 31 and the top gate electrode of the first transistor T1 are an integral structure that is interconnected.

[0111] In an exemplary embodiment, the orthographic projection of the first scan signal line 31 on the substrate can be within the range of the orthographic projection of the first shielding line 11 on the substrate, so that the channel region of the first transistor T1 can be effectively shielded by the first shielding line 11.

[0112] In an exemplary embodiment, the second scan signal line 32 may be located on one side of the first electrode plate 36 in the second direction Y, and between the first electrode plate 36 and the first scan signal line 31. The side of the second scan signal line 32 closest to the first electrode plate 36 is connected to a fourth top gate electrode 32-1. The orthographic projection of the fourth top gate electrode 32-1 on the substrate at least partially overlaps with the orthographic projection of the fourth active layer on the substrate. The fourth top gate electrode 32-1 is configured as the top gate electrode of the fourth transistor T4.

[0113] In an exemplary embodiment, the orthogonal projection of the second scan signal line 32 on the substrate can be within the range of the orthogonal projection of the second shielding line 12 on the substrate, and the orthogonal projection of the fourth top gate electrode 32-1 on the substrate can be within the range of the orthogonal projection of the fourth bottom gate electrode 12-1 on the substrate, so that the channel region of the fourth transistor T4 can be effectively shielded by the fourth bottom gate electrode 12-1.

[0114] In an exemplary embodiment, the third scan signal line 33 may be located on the side opposite to the second direction Y of the first electrode plate 36, such that the first electrode plate 36 is located between the second scan signal line 32 and the third scan signal line 33. The side of the third scan signal line 33 closest to the first electrode plate 36 is connected to a second top gate electrode 33-1, and the orthographic projection of the second top gate electrode 33-1 on the substrate at least partially overlaps with the orthographic projection of the second active layer on the substrate. The second top gate electrode 33-1 is configured as the top gate electrode of the second transistor T2.

[0115] In an exemplary embodiment, the orthogonal projection of the third scan signal line 33 on the substrate can be within the range of the orthogonal projection of the third shielding line 13 on the substrate, and the orthogonal projection of the second top gate electrode 33-1 on the substrate can be within the range of the orthogonal projection of the second bottom gate electrode 13-1 on the substrate, so that the channel region of the second transistor T2 can be effectively shielded by the second bottom gate electrode 13-1.

[0116] In an exemplary embodiment, the first scan signal line 31 and the third scan signal line 33 can transmit the same scan signal, and the first scan signal line 31 and the third scan signal line 33 are connected to the same scan signal source.

[0117] In an exemplary embodiment, the first light-emitting control line 34 may be located on the side of the second scan signal line 32 away from the first electrode plate 36, and may be located between the first scan signal line 31 and the second scan signal line 32. The area where the first light-emitting control line 34 overlaps with the sixth active layer serves as the top gate electrode of the sixth transistor T6, that is, the first light-emitting control line 34 and the top gate electrode of the sixth transistor T6 are an integral structure that is interconnected.

[0118] In an exemplary embodiment, the orthogonal projection of the first light-emitting control line 34 onto the substrate can be within the range of the orthogonal projection of the fourth blocking line 14 onto the substrate, so that the channel region of the sixth transistor T6 can be effectively blocked by the fourth blocking line 14.

[0119] In an exemplary embodiment, the second light-emitting control line 35 may be located on the side of the third scan signal line 33 away from the first electrode plate 36. The area where the second light-emitting control line 35 overlaps with the fifth active layer serves as the top gate electrode of the fifth transistor T5. That is, the second light-emitting control line 35 and the top gate electrode of the fifth transistor T5 are an integral structure that is interconnected.

[0120] In an exemplary embodiment, the orthogonal projection of the second light-emitting control line 35 onto the substrate can be located within the range of the orthogonal projection of the fifth shielding line 15 onto the substrate, so that the channel region of the fifth transistor T5 can be effectively shielded by the fifth shielding line 15.

[0121] In an exemplary embodiment, after the first conductive layer pattern is formed, the first conductive layer can be used as a shield to conduct the semiconductor layer. The semiconductor layer in the region shielded by the first conductive layer forms the channel region of the first transistor T1 to the sixth transistor T6. The semiconductor layer in the region not shielded by the first conductive layer is conducted, that is, the first region and the second region of the first transistor T1 to the sixth active layer are both conducted.

[0122] (4) Forming a second conductive layer pattern. In an exemplary embodiment, forming a second conductive layer pattern may include: sequentially depositing a third insulating film and a second conductive film on a substrate on which the aforementioned pattern is formed; patterning the second conductive film using a patterning process to form a third insulating layer covering the first conductive layer; and a second conductive layer pattern disposed on the third insulating layer, such as... Figure 9A and Figure 9B As shown, Figure 9B for Figure 9A A schematic planar view of the second conductive layer. In an exemplary embodiment, the second conductive layer may be referred to as the second gate metal (GATE2) layer.

[0123] In an exemplary embodiment, the second conductive layer pattern of each circuit unit includes at least: an initial sub-line 41 and a second electrode 42 for storing capacitors.

[0124] In an exemplary embodiment, the outline of the second electrode plate 42 can be rectangular, and the corners of the rectangle can be chamfered. The orthographic projection of the second electrode plate 42 on the substrate at least partially overlaps with the orthographic projection of the first electrode plate 36 on the substrate. The second electrode plate 42 can serve as another electrode plate of the storage capacitor. The first electrode plate 36 and the second electrode plate 42 constitute the storage capacitor of the pixel driving circuit.

[0125] In an exemplary embodiment, the second electrode plate 42 is provided with an opening 43. The opening 43 may be rectangular in shape and may be located in the middle of the second electrode plate 42, so that the second electrode plate 42 forms an annular structure. The opening 43 exposes the third insulating layer covering the first electrode plate 36, and the orthographic projection of the first electrode plate 36 on the substrate includes the orthographic projection of the opening 43 on the substrate. In an exemplary embodiment, the opening 43 is configured to accommodate a subsequently formed first via, which is located within the opening 43 and exposes the first electrode plate 36, so that the second electrode of the subsequently formed first transistor T1 is connected to the first electrode plate 36.

[0126] In an exemplary embodiment, the initial sub-line 41 may be a line shape extending along the first direction X of the main body. In the first direction X, the initial sub-line 41 may be disposed between first regions of the first active layer of adjacent circuit units in the first direction X. In the second direction Y, the initial sub-line 41 may be located on the side of the first scan signal line 31 away from the second electrode 42. The initial sub-line 41 is configured to form a first initial signal line extending along the first direction X, transmitting an initial voltage signal, using subsequently formed initial connection electrodes.

[0127] (5) Forming a fourth insulating layer pattern. In an exemplary embodiment, forming a fourth insulating layer pattern may include: depositing a fourth insulating film on a substrate on which the aforementioned pattern is formed, patterning the fourth insulating film using a patterning process to form a fourth insulating layer covering the second conductive layer, wherein the fourth insulating layer has a plurality of vias, such as... Figure 10 As shown.

[0128] In an exemplary embodiment, the plurality of vias includes at least: a first via V1, a second via V2, a third via V3, a fourth via V4, a fifth via V5, a sixth via V6, a seventh via V7, an eighth via V8, a ninth via V9, a tenth via V10, an eleventh via V11, a twelfth via V12, and a thirteenth via V13.

[0129] In an exemplary embodiment, the orthographic projection of the first via V1 onto the substrate is within the range of the orthographic projection of the opening 43 onto the substrate. The fourth and third insulating layers within the first via V1 are etched away, exposing the surface of the first electrode plate 36. The first via V1 is configured to allow the second electrode of the subsequently formed first transistor T1 to be connected to the first electrode plate 36 through the via.

[0130] In an exemplary embodiment, the orthographic projection of the second via V2 onto the substrate is within the range of the orthographic projection of the second region of the first active layer (which is also the second region of the sixth active layer) onto the substrate. The fourth, third, and second insulating layers within the second via V2 are etched away, exposing the surface of the second region of the first active layer. The second via V2 is configured to allow the second electrode of the subsequently formed first transistor T1 (which is also the second electrode of the sixth transistor T6) to be connected to the second region of the first active layer (which is also the second region of the sixth active layer) through the via.

[0131] In an exemplary embodiment, the orthographic projection of the third via V3 onto the substrate is within the range of the orthographic projection of the first region of the fifth active layer onto the substrate. The fourth insulating layer, the third insulating layer, and the second insulating layer within the third via V3 are etched away, exposing the surface of the first region of the fifth active layer. The third via V3 is configured to allow the first electrode of the subsequently formed fifth transistor T5 to be connected to the first region of the fifth active layer through the via.

[0132] In an exemplary embodiment, the orthographic projection of the fourth via V4 onto the substrate is within the range of the orthographic projection of the second region of the fifth active layer onto the substrate. The fourth insulating layer, the third insulating layer, and the second insulating layer within the fourth via V4 are etched away, exposing the surface of the second region of the fifth active layer. The fourth via V4 is configured to allow the second electrode of the subsequently formed fifth transistor T5 to be connected to the second region of the fifth active layer through the via.

[0133] In an exemplary embodiment, the orthographic projection of the fifth via V5 onto the substrate is located within the range of the orthographic projection of the second region of the second active layer (which is also the first region of the third active layer) onto the substrate. The fourth insulating layer, the third insulating layer, and the second insulating layer within the fifth via V5 are etched away, exposing the surface of the second region of the second active layer. The fifth via V5 is configured to allow the second electrode of the subsequently formed second transistor T2 (which is also the first electrode of the third transistor T3) to be connected to the second region of the second active layer (which is also the first region of the third active layer) through the via.

[0134] In an exemplary embodiment, the orthographic projection of the sixth via V6 onto the substrate is within the range of the orthographic projection of the first region of the fourth active layer onto the substrate. The fourth insulating layer, the third insulating layer, and the second insulating layer within the sixth via V6 are etched away, exposing the surface of the first region of the fourth active layer. The sixth via V6 is configured to allow the first electrode of the subsequently formed fourth transistor T4 to be connected to the first region of the fourth active layer through the via.

[0135] In an exemplary embodiment, the orthographic projection of the seventh via V7 onto the substrate is located within the orthographic projection of the second region of the fourth active layer (which is also the second region of the third active layer) onto the substrate. The fourth insulating layer, the third insulating layer, and the second insulating layer within the seventh via V7 are etched away, exposing the surface of the second region of the fourth active layer. The seventh via V7 is configured to allow the second electrode of the subsequently formed fourth transistor T4 (which is also the second electrode of the third transistor T3) to be connected to the second region of the fourth active layer (which is also the second region of the third active layer) through the via.

[0136] In an exemplary embodiment, the orthographic projection of the eighth via V8 onto the substrate is within the range of the orthographic projection of the first region of the sixth active layer onto the substrate. The fourth, third, and second insulating layers within the eighth via V8 are etched away, exposing the surface of the first region of the sixth active layer. The eighth via V8 is configured to allow the first electrode of the subsequently formed sixth transistor T6 to be connected to the first region of the sixth active layer through the via.

[0137] In an exemplary embodiment, the orthographic projection of the ninth via V9 onto the substrate is within the range of the orthographic projection of the first region of the second active layer onto the substrate. The fourth, third, and second insulating layers within the ninth via V9 are etched away, exposing the surface of the first region of the second active layer. The ninth via V9 is configured to allow the first electrode of the subsequently formed second transistor T2 to be connected to the first region of the second active layer through the via.

[0138] In an exemplary embodiment, the orthographic projection of the tenth via V10 on the substrate is within the range of the orthographic projection of the shielding connection block 16-1 of the shielding electrode 16 on the substrate. The fourth insulating layer, the third insulating layer, the second insulating layer and the first insulating layer in the tenth via V10 are etched away, exposing the surface of the shielding connection block 16-1. The tenth via V10 is configured to allow the subsequently formed fifth connection electrode to be connected to the shielding electrode 16 through the via.

[0139] In an exemplary embodiment, the orthographic projection of the eleventh via V11 onto the substrate is within the range of the orthographic projection of the second electrode plate 42 onto the substrate. The fourth insulating layer within the eleventh via V11 is etched away, exposing the surface of the second electrode plate 42. The eleventh via V11 is configured to allow the subsequently formed seventh connection electrode to be connected to the second electrode plate 42 through the via.

[0140] In an exemplary embodiment, the orthographic projection of the twelfth via V12 onto the substrate is within the range of the orthographic projection of the first region of the first active layer onto the substrate. The fourth insulating layer, the third insulating layer, and the second insulating layer within the twelfth via V12 are etched away, exposing the surface of the first region of the first active layer. The twelfth via V12 is configured to allow the first electrode of the subsequently formed first transistor T1 to be connected to the first region of the first active layer through the via.

[0141] In an exemplary embodiment, the orthographic projection of the thirteenth via V13 onto the substrate is within the range of the orthographic projection of the end of the first region of the initial sub-line 41 near the first active layer onto the substrate. The fourth insulating layer within the thirteenth via V13 is etched away, exposing the surface of the end of the initial sub-line 41. The thirteenth via V13 is configured to allow the first electrode of the subsequently formed first transistor T1 to be connected to the initial sub-line 41 through the via.

[0142] (6) Forming a third conductive layer pattern. In an exemplary embodiment, forming the third conductive layer may include: depositing a third conductive film on the substrate on which the aforementioned pattern is formed, and patterning the third conductive film using a patterning process to form a third conductive layer disposed on the fourth insulating layer, such as... Figure 11A and Figure 11B As shown, Figure 11B for Figure 11AA planar schematic diagram of the third conductive layer. In an exemplary embodiment, the third conductive layer may be referred to as the first source / drain metal (SD1) layer.

[0143] In an exemplary embodiment, the third conductive layer of each circuit unit includes at least: a first connection electrode 51, a second connection electrode 52, a third connection electrode 53, a fourth connection electrode 54, a fifth connection electrode 55, a sixth connection electrode 56, a seventh connection electrode 57, and an initial connection electrode 58.

[0144] In an exemplary embodiment, the first connecting electrode 51 can be shaped like a broken line extending along the second direction Y of the main body. The first end of the first connecting electrode 51 is connected to the first electrode plate 36 through the first via V1, and the second end of the first connecting electrode 51 is connected to the first region of the second active layer through the ninth via V9, so that the first electrode plate 36 and the first electrode of the second transistor T2 have the same potential. In an exemplary embodiment, the first connecting electrode 51 can serve as the first electrode of the second transistor T2 (i.e., the first node N1 of the pixel driving circuit).

[0145] In an exemplary embodiment, the second connection electrode 52 may be polygonal in shape, and the second connection electrode 52 is connected to the first region of the fifth active layer through the third via V3. In an exemplary embodiment, the second connection electrode 52 may serve as the first electrode of the fifth transistor T5, and the second connection electrode 52 is configured to be connected to a subsequently formed first power line.

[0146] In an exemplary embodiment, the third connecting electrode 53 can be a strip shape in which the main body extends along the second direction Y. The first end of the third connecting electrode 53 is connected to the second region of the fifth active layer through the fourth via V4, and the second end of the third connecting electrode 53 is connected to the second region of the second active layer through the fifth via V5. In an exemplary embodiment, the third connecting electrode 53 can simultaneously serve as the second electrode of the second transistor T2, the first electrode of the third transistor T3, and the second electrode of the fifth transistor T5 (i.e., the second node N2 of the pixel driving circuit).

[0147] In an exemplary embodiment, the fourth connection electrode 54 may be polygonal in shape, and the fourth connection electrode 54 is connected to the first region of the fourth active layer through the sixth via V6. In an exemplary embodiment, the fourth connection electrode 54 may serve as the first electrode of the fourth transistor T4, and the fourth connection electrode 54 is configured to be connected to a subsequently formed data signal line.

[0148] In an exemplary embodiment, the fifth connecting electrode 55 can be L-shaped. The first end of the fifth connecting electrode 55 is connected to the first region of the sixth active layer through the eighth via V8. The second end of the fifth connecting electrode 55 is connected to the shielding connecting block 16-1 of the shielding electrode 16 through the tenth via V10. The third end of the fifth connecting electrode 55 is connected to the second region of the fourth active layer through the seventh via V7. The third end of the fifth connecting electrode 55 is located between the first and second ends. In an exemplary embodiment, the fifth connecting electrode 55 can simultaneously serve as the second electrode of the third transistor T3, the second electrode of the fourth transistor T4, and the first electrode of the sixth transistor T6 (i.e., the third node N3 of the pixel driving circuit). Since the shielding electrode 16 serves as the bottom gate electrode of the third transistor T3, the bottom gate electrode of the third transistor T3 is connected to the second electrode of the fourth transistor T4 and the first electrode of the sixth transistor T6 through the fifth connecting electrode 55.

[0149] In an exemplary embodiment, the sixth connection electrode 56 may be polygonal in shape, and the sixth connection electrode 56 is connected to the second region of the first active layer (which is also the second region of the sixth active layer) through the second via V2. In an exemplary embodiment, the sixth connection electrode 56 may simultaneously serve as the second electrode of both the first transistor T1 and the sixth transistor T6, and the sixth connection electrode 56 is configured to be connected to the subsequently formed anode connection electrode.

[0150] In an exemplary embodiment, the seventh connecting electrode 57 may be polygonal in shape, and the seventh connecting electrode 57 is connected to the second electrode plate 42 through the eleventh through-hole V11. In an exemplary embodiment, the seventh connecting electrode 57 is configured to connect to the subsequently formed anode connecting electrode.

[0151] In an exemplary embodiment, the initial connection electrode 58 can be a strip shape in which the main body extends along the first direction X. The middle part of the initial connection electrode 58 is connected to the first region of the first active layer through the twelfth via V12. The two ends of the initial connection electrode 58 are respectively connected to the ends of the adjacent initial sub-line 41 through the thirteenth via V13. On the one hand, the interconnection between multiple initial sub-lines 41 is realized to form the first initial signal line. On the other hand, the connection between the first initial signal line and the first electrode of the first transistor T1 is realized, so that the initial voltage transmitted by the first initial signal line is written into the first electrode of the first transistor T1.

[0152] (7) Forming a first planarization layer pattern. In an exemplary embodiment, forming the first planarization layer pattern may include: depositing a fifth insulating film on a substrate on which the aforementioned pattern is formed, then coating a first planarization film, and patterning the first planarization film and the fifth insulating film using a patterning process to form a fifth insulating layer covering the third conductive layer pattern and a first planarization layer disposed on the fifth insulating layer. The first planarization layer has a plurality of vias, such as... Figure 12 As shown.

[0153] In an exemplary embodiment, the plurality of vias in each circuit unit includes at least: a twenty-first via V21, a twenty-second via V22, a twenty-third via V23, and a twenty-fourth via V24.

[0154] In an exemplary embodiment, the orthographic projection of the 21st via V21 on the substrate is within the range of the orthographic projection of the second connection electrode 52 on the substrate. The first planarization layer and the fifth insulating layer within the 21st via V21 are etched away, exposing the surface of the second connection electrode 52. The 21st via V21 is configured to allow a subsequently formed first power line to be connected to the second connection electrode 52 through the via.

[0155] In an exemplary embodiment, the orthographic projection of the 22nd via V22 on the substrate is within the range of the orthographic projection of the fourth connection electrode 54 on the substrate. The first planarization layer and the fifth insulating layer within the 22nd via V22 are etched away, exposing the surface of the fourth connection electrode 54. The 22nd via V22 is configured to allow subsequently formed data signal lines to be connected to the fourth connection electrode 54 through the via.

[0156] In an exemplary embodiment, the orthographic projection of the 23rd via V23 on the substrate is within the range of the orthographic projection of the 6th connecting electrode 56 on the substrate. The first planarization layer and the fifth insulating layer within the 23rd via V23 are etched away, exposing the surface of the 6th connecting electrode 56. The 23rd via V23 is configured to allow the subsequently formed anode connecting electrode to be connected to the 6th connecting electrode 56 through the via.

[0157] In an exemplary embodiment, the orthographic projection of the 24th via V24 onto the substrate is within the range of the orthographic projection of the 7th connecting electrode 57 onto the substrate. The first planarization layer and the fifth insulating layer within the 24th via V24 are etched away, exposing the surface of the 7th connecting electrode 57. The 24th via V24 is configured to allow a subsequently formed anode connecting electrode to be connected to the 7th connecting electrode 57 through the via.

[0158] In an exemplary embodiment, some circuit units further include a 25th via V25, the orthographic projection of the 25th via V25 on the substrate at least partially overlapping the orthographic projection of the initial connection electrode 58 on the substrate, the first planarization layer and the fifth insulating layer within the 25th via V25 being etched away to expose the surface of the initial connection electrode 58, and the 25th via V25 being configured to allow a subsequently formed second initial signal line to be connected to the initial connection electrode 58 through the via.

[0159] In an exemplary embodiment, the 25th via V25 can be disposed in the circuit cell of the (n+1)th column, that is, the circuit cell of the (n+1)th column is provided with the second initial signal line, while the circuit cells in the (n-1)th column and the nth column are not provided with the 25th via V25.

[0160] (8) Forming a fourth conductive layer pattern. In an exemplary embodiment, forming the fourth conductive layer may include: depositing a fourth conductive film on the substrate on which the aforementioned pattern is formed, and patterning the fourth conductive film using a patterning process to form a fourth conductive layer disposed on the first planarization layer, such as... Figure 13A and Figure 13B As shown, Figure 13B for Figure 13A A schematic planar view of the fourth conductive layer. In an exemplary embodiment, the fourth conductive layer may be referred to as the second source / drain metal (SD2) layer.

[0161] In an exemplary embodiment, the fourth conductive layer of each circuit unit includes at least: an anode connection electrode 61, a first power line 62, and a data signal line 63.

[0162] In an exemplary embodiment, the anode connection electrode 61 can be shaped like a broken line extending along the second direction Y. The first end of the anode connection electrode 61 is connected to the sixth connection electrode 56 via the twenty-third via V23, and the second end of the anode connection electrode 61 is connected to the seventh connection electrode 57 via the twenty-fourth via V24. Since the sixth connection electrode 56 is connected to the second region of the sixth active layer (which is also the second region of the first active layer) via a via, and the seventh connection electrode 57 is connected to the second electrode plate 42 via a via, the second electrode plate 42, the second electrode of the first transistor T1, and the second electrode of the sixth transistor T6 all have the same potential (i.e., the fourth node N4 of the pixel driving circuit). In an exemplary embodiment, the anode connection electrode 61 is configured to connect with the subsequently formed anode, thus enabling the pixel driving circuit to output driving current to the light-emitting device.

[0163] In an exemplary embodiment, the shape of the first power line 62 can be a straight line or a broken line extending along the second direction Y. The first power line 62 is connected to the second connection electrode 52 through the twenty-first via V21. Since the second connection electrode 52 is connected to the first region of the fifth active layer through the via, the first power line 62 can write a constant first voltage signal into the first electrode of the fifth transistor T5.

[0164] In an exemplary embodiment, the data signal line 63 can be a straight line extending along the second direction Y, and the data signal line 63 is connected to the fourth connection electrode 54 through the twenty-second via V22. Since the fourth connection electrode 54 is connected to the first region of the fourth active layer through the via, the data signal line 63 can write data signals to the first electrode of the fourth transistor T4.

[0165] In an exemplary embodiment, the fourth conductive layer of a portion of the circuit unit may further include a second initial signal line 80. The shape of the second initial signal line 80 may be a straight line or a broken line extending along the second direction Y of the main body. The second initial signal line 80 is connected to the initial connection electrode 58 through the twenty-fifth via V25. Since the initial sub-line 41 forms a first initial signal line extending along the first direction X through the initial connection electrode 58, and the second initial signal line 80 is connected to the initial connection electrode 58, the first initial signal line extending along the first direction X and the second initial signal line 80 extending along the second direction Y form an initial signal line with a network connection structure in the display area. This can minimize the resistance of the initial signal line, reduce the voltage drop of the initial voltage, and effectively improve the uniformity of the initial voltage in the display substrate, thereby improving display uniformity, display quality, and display performance.

[0166] In an exemplary embodiment, the fourth conductive layer of a portion of the circuit unit may further include a low-voltage power line (second power line) 90. The low-voltage power line 90 may be a straight line or a broken line with its main body extending along the second direction Y, and may be located between the first power line 62 and the data signal line 63. The low-voltage power line 90 is configured to output a constant second voltage signal to the cathode of the light-emitting device.

[0167] In some exemplary embodiments, the multiple unit columns of the display panel may include at least a first unit column, a second unit column, and a third unit column. The pixel driving circuits of multiple circuit units in the first unit column are connected to red light-emitting devices that emit red light; the pixel driving circuits of multiple circuit units in the second unit column are connected to green light-emitting devices that emit green light; and the pixel driving circuits of multiple circuit units in the third unit column are connected to blue light-emitting devices that emit blue light. For example, the (n-1)th column may be the first unit column, the nth column may be the second unit column, and the (n+1)th column may be the third unit column. A low-voltage power line 90 may be disposed in the circuit units in the (n-1)th and nth columns, and a second initial signal line 80 may be disposed in the circuit units in the (n+1)th column.

[0168] In some possible exemplary embodiments, the second initial signal line 80 may be disposed in the circuit cells of the nth and n+1th columns, and the low-voltage power supply line 90 may be disposed in the circuit cells of the (n-1)th column, which is not limited herein.

[0169] Subsequently, a second planar thin film is coated on the substrate on which the aforementioned pattern is formed. The second planar thin film is patterned using a patterning process to form a second planar layer covering the pattern of the fourth conductive layer. An anode via is provided on the second planar layer. The orthogonal projection of the anode via on the substrate is located within the range of the orthogonal projection of the anode connection electrode on the substrate. The anode via is configured to allow the anode to be formed subsequently to be connected to the anode connection electrode through the via.

[0170] At this point, the driving circuit layer is fabricated on the substrate. In a plane parallel to the display substrate, the driving circuit layer may include multiple circuit units. Each circuit unit may include a pixel driving circuit, and a first scan signal line, a second scan signal line, a third scan signal line, a first light emission control line, a second light emission control line, a first initial signal line, a first power supply line, and a data signal line connected to the pixel driving circuit. In a plane perpendicular to the display substrate, the driving circuit layer may include, sequentially disposed on the substrate, a shielding conductive layer, a first insulating layer, a semiconductor layer, a second insulating layer, a first conductive layer, a third insulating layer, a second conductive layer, a fourth insulating layer, a third conductive layer, a fifth insulating layer, a first planarization layer, a fourth conductive layer, and a second planarization layer. The shielding conductive layer may include at least a shielding electrode and multiple shielding lines. The semiconductor layer may include at least the active layers of the first to sixth transistors. The first conductive layer may include at least the first electrode of a storage capacitor. The second conductive layer may include at least the second electrode of a storage capacitor. The third conductive layer may include at least the first and second electrodes of the first to sixth transistors. The fourth conductive layer may include at least an anode connection electrode.

[0171] In an exemplary embodiment, the substrate can be a flexible substrate or a rigid substrate. The rigid substrate can be, but is not limited to, one or more of glass and quartz. The flexible substrate can be, but is not limited to, polyethylene terephthalate, polyethylene terephthalate, polyetheretherketone, polystyrene, polycarbonate, polyarylate, polyarylate, polyimide, polyvinyl chloride, polyethylene, and textile fibers. In an exemplary embodiment, the flexible substrate can include a first flexible material layer, a first inorganic material layer, a semiconductor layer, a second flexible material layer, and a second inorganic material layer stacked on a glass substrate. The materials of the first and second flexible material layers can be polyimide (PI), polyethylene terephthalate (PET), or surface-treated polymer films, etc. The materials of the first and second inorganic material layers can be silicon nitride (SiNx) or silicon oxide (SiOx), etc., to improve the substrate's resistance to water and oxygen. The first and second inorganic material layers are also called barrier layers. The material of the semiconductor layer can be amorphous silicon (a-Si).

[0172] In an exemplary embodiment, the first, second, third, fourth, and fifth insulating layers can be any one or more of silicon oxide (SiOx), silicon nitride (SiNx), and silicon oxynitride (SiON), and can be single-layer, multi-layer, or composite layers. The first insulating layer can be called a buffer layer, the second and third insulating layers can be called gate insulating (GI) layers, the fourth insulating layer can be called an interlayer insulating (ILD) layer, and the fifth insulating layer can be called a passivation (PVX) layer. The shielding conductive layer, the first conductive layer, the second conductive layer, the third conductive layer, and the fourth conductive layer can be made of metallic materials, such as silver (Ag), copper (Cu), aluminum (Al), titanium (Ti), or molybdenum (Mo), or can be made of alloy materials composed of metals, such as aluminum-neodymium alloy (AlNd) or molybdenum-niobium alloy (MoNb), and can be a single-layer structure or a multi-layer composite structure, such as Ti / Al / Ti. The first and second planarization layers can be made of organic materials, such as resin or polyimide.

[0173] In an exemplary embodiment, after the driving circuit layer is fabricated, a light-emitting structure layer can be fabricated on the driving circuit layer, and an encapsulation structure layer can be fabricated on the light-emitting structure layer, which will not be described in detail here.

[0174] As can be seen from the above description of the display substrate structure and fabrication process, the pixel driving circuit of this exemplary embodiment only requires six oxide transistors to meet the driving requirements. Compared with the existing pixel driving circuit structure with seven transistors, this not only reduces the number of transistors and simplifies the structure of the pixel driving circuit, but also reduces the area occupied by the pixel driving circuit, which is beneficial for achieving high resolution (PPI) display. Furthermore, it ensures the yield of large-size display substrates and reduces production costs. In this exemplary embodiment, the bottom gate electrode is disposed in the shielding conductive layer, and the top gate electrode is disposed in the first conductive layer, which ensures the shielding effect and improves the electrical performance of the transistors. By providing a first initial signal line extending along the first direction X and a second initial signal line extending along the second direction Y in the display area, this disclosure forms a network-connected initial signal line structure in the display area. This minimizes the resistance of the initial signal lines, reduces the voltage drop of the initial voltage, and effectively improves the uniformity of the initial voltage in the display substrate, thereby improving display uniformity, display quality, and display performance. This disclosure achieves a VSS in pixel structure by incorporating low-voltage power lines within the display area. This not only effectively reduces the resistance of the low-voltage power lines and the voltage drop of the low-voltage power signal, resulting in low power consumption, but also effectively improves the uniformity of the low-voltage power signal in the display substrate, thereby enhancing display uniformity and improving display quality. The fabrication process disclosed herein is highly compatible with existing fabrication processes, is simple to implement, easy to execute, has high production efficiency, low production cost, and a high yield.

[0175] The structures and fabrication processes described above in this disclosure are merely illustrative examples. In the exemplary embodiments, the corresponding structures and patterning processes can be modified and added or reduced according to actual needs, and this disclosure does not limit them. For example, the display substrate may include two first initial signal lines (such as a first horizontal initial line and a second horizontal initial line) extending along a first direction and two second initial signal lines (such as a first vertical initial line and a second vertical initial line) extending along a second direction. In at least one circuit unit, the first horizontal initial line and the first vertical initial line can be connected through vias, and the second horizontal initial line and the second vertical initial line can be connected through vias, forming a dual-network interconnection structure of initial signal lines in the display area. As another example, the display substrate may include a first low-voltage power line extending along a first direction and a second low-voltage power line extending along a second direction. In at least one circuit unit, the first low-voltage power line and the second low-voltage power line are connected through vias, forming a network interconnection structure of low-voltage power lines in the display area.

[0176] Figure 14 This is a schematic diagram of a planar structure of another display substrate according to an exemplary embodiment of the present disclosure, illustrating the planar structure of the pixel driving circuit in three circuit units within a unit row. For example... Figure 14As shown, in the exemplary embodiment, the main structure of the display substrate of this exemplary embodiment is similar to... Figure 5 The main structures of the display substrates shown are basically the same, except that in at least one circuit unit, a first shielding block 101 is provided on the first power line 62 in the fourth conductive layer.

[0177] In an exemplary embodiment, the first blocking block 101 can be disposed on one side of the first power line 62 in the first direction X (near the data signal line 63), which is equivalent to providing a protrusion on the first power line 62. The orthographic projection of the first blocking block 101 on the substrate at least partially overlaps with the orthographic projection of the fifth active layer of the fifth transistor T5 on the substrate. The first blocking block 101 is configured to block the fifth transistor T5, reduce the influence of light on the electrical characteristics of the fifth transistor T5, and improve the working stability of the fifth transistor T5.

[0178] In an exemplary embodiment, the first shielding block 101 and the first power line 62 can be an integral structure that is interconnected, and the orthographic projection of the first shielding block 101 on the substrate at least partially overlaps with the orthographic projection of the channel region of the fifth active layer on the substrate.

[0179] Figure 15 This is a schematic diagram of a planar structure of a display substrate, illustrating an exemplary embodiment of the present disclosure. It shows the planar structure of the pixel driving circuit in three circuit units within a unit row. For example... Figure 15 As shown, in the exemplary embodiment, the main structure of the display substrate of this exemplary embodiment is similar to... Figure 5 The main structures of the display substrates shown are basically the same, except that in at least one circuit unit, a second blocking block 102 is provided on the second initial signal line 80 and / or low-voltage power supply line 90 in the fourth conductive layer.

[0180] In an exemplary embodiment, the second blocking block 102 may be disposed on the side opposite to the first direction X of the second initial signal line 80 and / or the low-voltage power line 90 (close to the first power line 62), which is equivalent to providing a protrusion on the second initial signal line 80 and / or the low-voltage power line 90. The orthographic projection of the second blocking block 102 on the substrate at least partially overlaps with the orthographic projection of the second active layer of the second transistor T2 on the substrate. The second blocking block 102 is configured to block the second transistor T2, reduce the influence of light on the electrical characteristics of the second transistor T2, and improve the working stability of the second transistor T2.

[0181] In an exemplary embodiment, the second shielding block 102 and the second initial signal line 80 of a portion of the circuit unit can be an integral structure interconnected with each other, and the second shielding block 102 and the low-voltage power line 90 of a portion of the circuit unit can be an integral structure interconnected with each other. The orthographic projection of the second shielding block 102 on the substrate at least partially overlaps with the orthographic projection of the channel region of the second active layer on the substrate.

[0182] Figure 16 This is a schematic diagram of a planar structure of a display substrate, illustrating an exemplary embodiment of the present disclosure. It shows the planar structure of the pixel driving circuit in three circuit units within a unit row. For example... Figure 16 As shown, in the exemplary embodiment, the main structure of the display substrate of this exemplary embodiment is similar to... Figure 5 The main structures of the display substrates shown are basically the same, except that in at least one circuit unit, a third blocking block 103 is provided on the second initial signal line 80 and / or low-voltage power supply line 90 in the fourth conductive layer.

[0183] In an exemplary embodiment, the third blocking block 103 may be disposed on the side opposite to the first direction X of the second initial signal line 80 and / or the low-voltage power line 90 (close to the first power line 62), which is equivalent to providing a protrusion on the second initial signal line 80 and / or the low-voltage power line 90. The orthographic projection of the third blocking block 103 on the substrate at least partially overlaps with the orthographic projection of the fourth active layer of the fourth transistor T4 on the substrate. The third blocking block 103 is configured to block the fourth transistor T4, reduce the influence of light on the electrical characteristics of the fourth transistor T4, and improve the working stability of the fourth transistor T4.

[0184] In an exemplary embodiment, the third shielding block 103 and the second initial signal line 80 of a portion of the circuit unit can be an integral structure interconnected with each other, and the third shielding block 103 and the low-voltage power line 90 of a portion of the circuit unit can be an integral structure interconnected with each other. The orthographic projection of the third shielding block 103 on the substrate and the orthographic projection of the channel region of the fourth active layer on the substrate at least partially overlap.

[0185] Figure 17 This is a schematic diagram of a planar structure of a display substrate, illustrating an exemplary embodiment of the present disclosure. It shows the planar structure of the pixel driving circuit in three circuit units within a unit row. For example... Figure 17 As shown, in the exemplary embodiment, the main structure of the display substrate of this exemplary embodiment is similar to... Figure 5 The main structures of the display substrates shown are basically the same, except that in at least one circuit unit, a fourth blocking block 104 is provided on the second initial signal line 80 and / or low-voltage power supply line 90 in the fourth conductive layer.

[0186] In an exemplary embodiment, the fourth blocking block 104 may be disposed on the side opposite to the first direction X of the second initial signal line 80 and / or the low-voltage power line 90 (close to the first power line 62), which is equivalent to providing a protrusion on the second initial signal line 80 and / or the low-voltage power line 90. The orthographic projection of the fourth blocking block 104 on the substrate at least partially overlaps with the orthographic projection of the first active layer of the first transistor T1 on the substrate. The fourth blocking block 104 is configured to block the first transistor T1, reduce the influence of light on the electrical characteristics of the first transistor T1, and improve the working stability of the first transistor T1.

[0187] In an exemplary embodiment, the fourth shielding block 104 and the second initial signal line 80 of a portion of the circuit unit can be an integral structure interconnected with each other, and the fourth shielding block 104 and the low-voltage power line 90 of a portion of the circuit unit can be an integral structure interconnected with each other. The orthographic projection of the fourth shielding block 104 on the substrate at least partially overlaps with the orthographic projection of the channel region of the first active layer on the substrate.

[0188] In some exemplary embodiments, the fourth blocking block 104 can be disposed on the first power line 62 near the first transistor T1, which is equivalent to setting a protrusion on the first power line 62 to block the first transistor T1.

[0189] In some other exemplary embodiments, depending on the layout of the circuit units, the fourth blocking block 104 of some circuit units may be disposed on the first power line 62, the fourth blocking block 104 of some circuit units may be disposed on the second initial signal line 80, and the fourth blocking block 104 of some circuit units may be disposed on the low-voltage power line 90. This disclosure does not limit the scope of the invention.

[0190] Figure 18 This is a schematic diagram of a planar structure of a display substrate, illustrating an exemplary embodiment of the present disclosure. It shows the planar structure of the pixel driving circuit in three circuit units within a unit row. For example... Figure 18 As shown, in the exemplary embodiment, the main structure of the display substrate of this exemplary embodiment is similar to... Figure 5 The main structures of the display substrates shown are basically the same, except that in at least one circuit unit, a fifth shielding block 105 is provided on the anode connection electrode 61 in the fourth conductive layer.

[0191] In an exemplary embodiment, the fifth blocking block 105 can be disposed on one side of the anode connection electrode 61 in the first direction X (near the data signal line 63), which is equivalent to increasing the size of the anode connection electrode 61. The orthographic projection of the fifth blocking block 105 on the substrate at least partially overlaps with the orthographic projection of the sixth active layer of the sixth transistor T6 on the substrate. The fifth blocking block 105 is configured to block the sixth transistor T6, reduce the influence of light on the electrical characteristics of the sixth transistor T6, and improve the working stability of the sixth transistor T6.

[0192] In an exemplary embodiment, the fifth shielding block 105 and the anode connection electrode 61 can be an integral structure that is interconnected, and the orthographic projection of the fifth shielding block 105 on the substrate at least partially overlaps with the orthographic projection of the channel region of the sixth active layer on the substrate.

[0193] Figure 19 This is a schematic diagram of a planar structure of a display substrate, illustrating an exemplary embodiment of the present disclosure. It shows the planar structure of the pixel driving circuit in three circuit units within a unit row. For example... Figure 19 As shown, in the exemplary embodiment, the main structure of the display substrate of this exemplary embodiment is similar to... Figure 5 The main structures of the display substrates shown are basically the same, except that in at least one circuit unit, a shielding block 111 is provided on the first power line 62 in the fourth conductive layer.

[0194] In an exemplary embodiment, the shielding block 111 may be disposed on one side of the first power line 62 in the first direction X (near the data signal line 63), which is equivalent to providing a protrusion on the first power line 62. The orthographic projection of the shielding block 111 on the substrate at least partially overlaps with the orthographic projection of the second electrode plate of the storage capacitor 50 on the substrate. The shielding block 111 is configured to shield the fourth node N4 of the pixel driving circuit to stabilize the anode potential.

[0195] In an exemplary embodiment, the shielding block 111 and the first power line 62 can be an integral structure that is interconnected.

[0196] Figure 20 This is a schematic diagram of a planar structure of a display substrate, illustrating an exemplary embodiment of the present disclosure. It shows the planar structure of the pixel driving circuit in three circuit units within a unit row. For example... Figure 20 As shown, in the exemplary embodiment, the main structure of the display substrate of this exemplary embodiment is similar to... Figure 5The main structure of the display substrates shown is basically the same, except that in at least one circuit unit, the second initial signal line 80 in the fourth conductive layer may include a first initial straight section 80A, a second initial straight section 80B, and an initial bend section 80C located between the first initial straight section 80A and the second initial straight section 80B, and / or, the low-voltage power line 90 may include a first power straight section 90A, a second power straight section 90B, and a power bend section 90C located between the first power straight section 90A and the second power straight section 90B.

[0197] In an exemplary embodiment, the first end of the initial bending portion 80C is connected to the first initial straight portion 80A, and the second end of the initial bending portion 80C is connected to the second initial straight portion 80B. The middle part of the initial bending portion 80C protrudes towards the first power line 62, so that the orthographic projection of the second initial signal line 80 on the substrate does not overlap with the orthographic projection of the first connecting electrode 51 (the first node N1 of the pixel driving circuit) on the substrate. The initial bending portion 80C of the second initial signal line 80 is configured to avoid the first node N1 of the pixel driving circuit, so as to reduce the voltage division of the first node N1 and improve the potential stability of the key node of the pixel driving circuit.

[0198] In an exemplary embodiment, the first end of the power supply bending portion 90C is connected to the first power supply straight portion 90A, and the second end of the power supply bending portion 90C is connected to the second power supply straight portion 90B. The middle part of the power supply bending portion 90C protrudes towards the first power line 62, so that the orthographic projection of the low-voltage power line 90 on the substrate does not overlap with the orthographic projection of the first connecting electrode 51 (the first node N1 of the pixel driving circuit) on the substrate. The power supply bending portion 90C of the low-voltage power line 90 is configured to avoid the first node N1 of the pixel driving circuit, so as to reduce the voltage division of the first node N1 and improve the potential stability of the key node of the pixel driving circuit.

[0199] Figure 21 This is a schematic diagram of a planar structure of a display substrate, illustrating an exemplary embodiment of the present disclosure. It shows the planar structure of the pixel driving circuit in three circuit units within a unit row. For example... Figure 21 As shown, in the exemplary embodiment, the main structure of the display substrate of this exemplary embodiment is similar to... Figure 5 The main structure of the display substrates shown is basically the same, except that a complete first initial signal line 70 is formed when the second conductive layer is formed.

[0200] In an exemplary embodiment, the shape of the first initial signal line 70 may be a broken line extending along the first direction X of the main body, and the first initial signal lines 70 of adjacent circuit units are connected to each other.

[0201] In an exemplary embodiment, the first initial signal line 70 may include an initial straight section 70A and an initial avoidance section 70B. The initial straight section 70A may be a line extending along a first direction X, and may be disposed between adjacent first active layers in the first direction X. The two ends of the initial avoidance section 70B in the first direction X are respectively connected to the initial straight section 70A, and the middle part of the initial avoidance section 70B protrudes in a direction away from the first active layer, so that the orthographic projection of the initial avoidance section 70B on the substrate does not overlap with the orthographic projection of the first active layer on the substrate.

[0202] In an exemplary embodiment, the initial straight portion 70A and the initial clearance portion 70B can be an integral structure connected to each other to form a complete first initial signal line 70. Since the complete first initial signal line 70 is formed when the second conductive layer is formed, subsequent processes can save on corresponding vias and initial connection electrodes, reducing process difficulty.

[0203] Figure 22 This is a schematic diagram of a planar structure of a display substrate, illustrating an exemplary embodiment of the present disclosure. It shows the planar structure of the pixel driving circuit in three circuit units within a unit row. For example... Figure 22 As shown, in the exemplary embodiment, the main structure of the display substrate of this exemplary embodiment is similar to... Figure 5 The main structures of the display substrates shown are basically the same, except that in at least one circuit unit, a first capacitor block 121 is provided on the anode connection electrode 61 in the fourth conductive layer.

[0204] In an exemplary embodiment, the first capacitor block 121 may be disposed on one side of the anode connection electrode 61 in the first direction X (near the data signal line 63), or it may be disposed on the opposite side of the anode connection electrode 61 in the first direction X (near the first power line 62), or it may be disposed on both sides of the anode connection electrode 61 in the first direction X. The orthographic projection of the first capacitor block 121 on the substrate and the orthographic projection of the second scan signal line 32 on the substrate at least partially overlap. The first capacitor block 121 is configured to increase the parasitic capacitance between the anode connection electrode 61 (the fourth node N4 of the pixel driving circuit) and the second scan signal line 32.

[0205] In an exemplary embodiment, by increasing the parasitic capacitance between the fourth node N4 of the pixel driving circuit and the second scan signal line 32, after the data is written and before the light-emitting element emits light, the falling edge of the signal on the second scan signal line 32 can pull down the potential of the fourth node N4, thereby enhancing the black screen display effect.

[0206] In an exemplary embodiment, by providing a first capacitor block 121, the parasitic capacitance between the anode connecting electrode 61 and the second scanning signal line 32 is greater than the parasitic capacitance between the anode connecting electrode 61 and the first light emission control line 34.

[0207] In an exemplary embodiment, the first capacitor block 121 and the anode connection electrode 61 can be an integral structure that is interconnected.

[0208] Figure 23 This is a schematic diagram of a planar structure of a display substrate, illustrating an exemplary embodiment of the present disclosure. It shows the planar structure of the pixel driving circuit in three circuit units within a unit row. For example... Figure 23 As shown, in the exemplary embodiment, the main structure of the display substrate of this exemplary embodiment is similar to... Figure 5 The main structures of the display substrates shown are basically the same, except that in at least one circuit unit, a second capacitor block 122 is provided on the anode connection electrode 61 in the fourth conductive layer.

[0209] In an exemplary embodiment, the second capacitor block 122 may be disposed on one side of the anode connection electrode 61 in the first direction X (near the data signal line 63), or it may be disposed on the opposite side of the anode connection electrode 61 in the first direction X (near the first power line 62), or it may be disposed on both sides of the anode connection electrode 61 in the first direction X. The orthographic projection of the second capacitor block 122 on the substrate at least partially overlaps with the orthographic projection of the first scan signal line 31 on the substrate. The second capacitor block 122 is configured to increase the parasitic capacitance between the anode connection electrode 61 (the fourth node N4 of the pixel driving circuit) and the first scan signal line 31.

[0210] In an exemplary embodiment, by increasing the parasitic capacitance between the fourth node N4 of the pixel driving circuit and the first scan signal line 31, the potential of the fourth node N4 can be lowered after the data is written and before the light-emitting element emits light, thereby enhancing the black screen display effect.

[0211] In an exemplary embodiment, by providing a second capacitor block 122, the parasitic capacitance between the anode connecting electrode 61 and the first scanning signal line 31 is greater than the parasitic capacitance between the anode connecting electrode 61 and the first light emission control line 34.

[0212] In an exemplary embodiment, the second capacitor block 122 and the anode connection electrode 61 can be an integral structure that is interconnected.

[0213] In an exemplary embodiment Figures 14 to 23 The schemes and structures shown can be combined arbitrarily, and this disclosure does not impose any restrictions on them.

[0214] In exemplary embodiments, the display substrate of this disclosure can be applied to other display devices with pixel driving circuits, such as quantum dot displays, etc., and this disclosure does not limit it.

[0215] This disclosure also provides a method for fabricating a display substrate to produce the display substrate provided in the above embodiments. In an exemplary embodiment, the fabrication method may include: A driving circuit layer is formed on a substrate. The driving circuit layer includes multiple circuit units constituting multiple cell rows and multiple cell columns, multiple first initial signal lines extending along a first direction, and multiple second initial signal lines and low-voltage power supply lines extending along a second direction. The first direction and the second direction intersect. Each circuit unit includes at least a pixel driving circuit. The pixel driving circuit includes a storage capacitor and multiple oxide transistors. The first initial signal lines are configured to provide an initial voltage signal to the pixel driving circuit. The second initial signal lines are connected to the first initial signal lines. The first initial signal lines and the second initial signal lines form a mesh interconnect structure. A light-emitting structure layer is formed on the driving circuit layer, the light-emitting structure layer including a plurality of light-emitting devices, and the low-voltage power line is configured to provide a low power supply voltage signal to the light-emitting devices.

[0216] This disclosure also provides a display device, which includes the aforementioned display substrate. The display device can be any product or component with display function, such as a mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, or navigator, and the embodiments of the present invention are not limited thereto.

[0217] While the embodiments disclosed herein are as described above, the content is merely for the purpose of facilitating understanding of this disclosure and is not intended to limit the invention. Any person skilled in the art may make any modifications and changes to the form and details of the implementation without departing from the spirit and scope of this disclosure; however, the patent protection scope of this invention shall still be determined by the scope defined in the appended claims.

Claims

1. A display substrate, comprising a driving circuit layer disposed on a substrate, the driving circuit layer comprising a plurality of circuit units constituting a plurality of cell rows and a plurality of cell columns, each circuit unit comprising at least a pixel driving circuit, the pixel driving circuit comprising a storage capacitor and a plurality of oxide transistors, the plurality of oxide transistors comprising at least a second transistor, a third transistor and a fifth transistor, a first electrode of the second transistor being connected to the gate electrode of the third transistor and a first electrode plate of the storage capacitor respectively, a second electrode of the second transistor being connected to the first electrode of the third transistor and the second electrode of the fifth transistor respectively, the first electrode of the fifth transistor being connected to a first power line, the second transistor comprising at least a second active layer, the third transistor comprising at least a third active layer, and the fifth transistor comprising at least a fifth active layer; at least one circuit unit further comprising a blocking block disposed on the side of the second active layer, the third active layer and the fifth active layer away from the substrate, the orthographic projection of the blocking block on the substrate at least partially overlapping the orthographic projection of the second active layer or the fifth active layer on the substrate. 2.The display substrate of claim 1, wherein, The shielding block includes a first shielding block, the orthographic projection of the first shielding block on the substrate at least partially overlapping the orthographic projection of the fifth active layer on the substrate.

3. The display substrate according to claim 2, wherein, The first shielding block is connected to the first power line.

4. The display substrate according to claim 1, wherein, The shielding block includes a second shielding block, the orthographic projection of the second shielding block on the substrate at least partially overlapping the orthographic projection of the second active layer on the substrate.

5. The display substrate according to claim 4, wherein, The display substrate further includes a light-emitting structure layer disposed on the side of the driving circuit layer away from the substrate, the light-emitting structure layer including a plurality of light-emitting devices; the driving circuit layer further includes a plurality of first initial signal lines extending along a first direction, and a plurality of second initial signal lines and low-voltage power supply lines extending along a second direction, the first direction and the second direction intersecting, the first initial signal lines being configured to provide an initial voltage signal to the pixel driving circuit, the second initial signal lines being connected to the first initial signal lines, the low-voltage power supply lines being configured to provide a low power supply voltage signal to the light-emitting devices, and the second blocking block being connected to the second initial signal lines or the low-voltage power supply lines.

6. The display substrate according to claim 5, wherein, At least one circuit unit further includes a first connection electrode, a first end of which is connected to the first plate of the storage capacitor through a first via, and a second end of which is connected to the first region of the second active layer through a via; in at least one circuit unit, the orthographic projection of the first connection electrode on the substrate does not overlap with the orthographic projection of the second initial signal line or the low-voltage power line on the substrate.

7. The display substrate according to claim 5, wherein, At least one circuit unit further includes a first connection electrode, a first end of which is connected to a first plate of the storage capacitor via a first via, and a second end of which is connected to a first region of the second active layer via a via; in at least one circuit unit, the orthographic projection of the first via on the substrate at least partially overlaps with the orthographic projection of the second initial signal line or the low-voltage power line on the substrate.

8. The display substrate according to claim 5, wherein, The driving circuit layer includes at least a shielding conductive layer, a first conductive layer, a second conductive layer, a third conductive layer, and a fourth conductive layer arranged sequentially along a direction away from the substrate. The shielding conductive layer includes at least the bottom gate electrodes of a plurality of oxide transistors. The first conductive layer includes at least the first plate of the storage capacitor and the top gate electrodes of the plurality of oxide transistors. The second conductive layer includes at least the second plate of the storage capacitor and the first initial signal line. The third conductive layer includes at least the first and second electrodes of the plurality of oxide transistors. The fourth conductive layer includes at least the second initial signal line and a low-voltage power supply line.

9. The display substrate according to claim 5, wherein, The plurality of unit columns include at least a first unit column, a second unit column, and a third unit column. The pixel driving circuit of the plurality of circuit units in the first unit column is connected to a red light-emitting device that emits red light. The pixel driving circuit of the plurality of circuit units in the second unit column is connected to a green light-emitting device that emits green light. The pixel driving circuit of the plurality of circuit units in the third unit column is connected to a blue light-emitting device that emits blue light. The low-voltage power supply line is disposed in the first unit column and the second unit column, and the second initial signal line is disposed in the third unit column.

10. The display substrate according to claim 1, wherein, The shielding block includes a first shielding block and a second shielding block. The orthographic projection of the first shielding block on the substrate at least partially overlaps with the orthographic projection of the fifth active layer on the substrate. The orthographic projection of the second shielding block on the substrate at least partially overlaps with the orthographic projection of the second active layer on the substrate. The first shielding block and the second shielding block are connected to different constant voltage signal lines.

11. The display substrate according to any one of claims 1 to 10, wherein, The pixel driving circuit further includes a first transistor, a fourth transistor, and a sixth transistor. In at least one circuit unit, the first terminal of the first transistor is connected to a first initial signal line extending along a first direction, the second terminal of the first transistor is connected to the second plate of the storage capacitor and the second terminal of the sixth transistor, the first terminal of the fourth transistor is connected to a data signal line extending along a second direction, the second terminal of the fourth transistor is connected to the second terminal of the third transistor, the first terminal of the sixth transistor is connected to the second terminal of the third transistor, and the second terminal of the sixth transistor is connected to a light-emitting device. The first direction and the second direction intersect. The first transistor includes at least a first active layer, the fourth transistor includes at least a fourth active layer, and the sixth transistor includes at least a sixth active layer.

12. The display substrate according to claim 11, wherein, The shielding block includes a third shielding block, the orthographic projection of the third shielding block on the substrate at least partially overlapping the orthographic projection of the fourth active layer on the substrate.

13. The display substrate according to claim 11, wherein, The shielding block includes a fourth shielding block, the orthographic projection of the fourth shielding block on the substrate at least partially overlapping the orthographic projection of the first active layer on the substrate.

14. The display substrate according to claim 11, wherein, The shielding block includes a fifth shielding block, the orthographic projection of the fifth shielding block on the substrate at least partially overlapping the orthographic projection of the sixth active layer on the substrate.

15. The display substrate according to claim 11, wherein, In at least one circuit unit, the first transistor, the fourth transistor, and the sixth transistor are disposed on one side of the storage capacitor in the second direction, and the second transistor and the fifth transistor are disposed on the opposite side of the storage capacitor in the second direction; the fourth transistor is disposed on one side of the storage capacitor in the second direction, the sixth transistor is disposed on the side of the fourth transistor away from the storage capacitor, the first transistor is disposed on the side of the sixth transistor away from the storage capacitor, the second transistor is disposed on the opposite side of the storage capacitor in the second direction, and the fifth transistor is disposed on the side of the second transistor away from the storage capacitor.

16. The display substrate according to claim 11, wherein, In at least one circuit unit, the second active layer and the fourth active layer are strip-shaped extending along the first direction, the third active layer is strip-shaped extending along the second direction, the first region of the third active layer and the second region of the second active layer are interconnected as an integral structure, the second region of the third active layer and the second region of the fourth active layer are interconnected as an integral structure, and the second region of the first active layer and the first region of the sixth active layer are interconnected as an integral structure.

17. The display substrate according to claim 11, wherein, In at least one circuit unit, the third transistor further includes a bottom gate electrode and a top gate electrode. The bottom gate electrode is connected to the second terminal of the fourth transistor and the first terminal of the sixth transistor, respectively. The top gate electrode and the first plate of the storage capacitor are an integral structure.

18. The display substrate according to claim 11, wherein, The driving circuit layer further includes a first scan signal line, a second scan signal line, a third scan signal line, a first light emission control line, and a second light emission control line extending along the first direction. In at least one circuit unit, the first scan signal line is connected to the top gate electrode of the first transistor, the second scan signal line is connected to the top gate electrode of the fourth transistor, the third scan signal line is connected to the top gate electrode of the second transistor, the first light emission control line is connected to the top gate electrode of the sixth transistor, and the second light emission control line is connected to the top gate electrode of the fifth transistor.

19. The display substrate according to claim 18, wherein, In at least one circuit unit, the second scan signal line is located on one side of the storage capacitor in the second direction, the first light emission control line is located on the side of the second scan signal line away from the storage capacitor, the third scan signal line is located on the side opposite to the second direction of the storage capacitor, the second light emission control line is located on the side of the third scan signal line away from the storage capacitor, and the first initial signal line is disposed on the side of the first scan signal line away from the storage capacitor.

20. A display device comprising a display substrate as described in any one of claims 1 to 19.

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