Signal transmission device, electronic equipment and vehicle

Abstract

A signal transmission device (400) includes a transmission circuit (411), a reception circuit (421), and an isolation element (431) that transmits a pulse signal between the transmission circuit (411) and the reception circuit (421) while achieving isolation therebetween. The transmission circuit (411) includes an input terminal (411a) for receiving an analog signal (AIN), a comparison circuit (411b) that compares the analog signal (AIN) with each of a plurality of thresholds (Vth1 to VthN) to generate a plurality of comparison signals (S1 to SN), and a pulse signal generation circuit (411c) that generates a pulse signal (PS) from the plurality of comparison signals (S1 to SN).

Description

Technical Field

[0001] This disclosure relates to a signal transmission device, electronic equipment, and vehicle. Background Technology

[0002] Today, signal transmission devices that transmit signals between primary and secondary circuit systems while electrically isolating them are used in a variety of applications, such as power supply equipment and motor drive equipment.

[0003] An example of the known technology related to the above can be found in the applicant's patent document 1 of this disclosure.

[0004] Reference List

[0005] Patent documents

[0006] Patent document 1: WO 2022 / 070944. Summary of the Invention

[0007] Technical issues

[0008] However, conventional signal transmission devices leave room for research into methods of changing settings on the receiving side from the transmitting side.

[0009] Solutions to technical problems

[0010] For example, according to one aspect of this disclosure, a signal transmission device includes a transmitting circuit, a receiving circuit, and an isolation element configured to transmit a pulse signal between the transmitting circuit and the receiving circuit while providing isolation between them. The transmitting circuit includes: an input terminal configured to receive an analog signal; a comparison circuit configured to compare the analog signal with each of a plurality of thresholds to generate a plurality of comparison signals; and a pulse signal generation circuit configured to generate a pulse signal based on the plurality of comparison signals. Attached Figure Description

[0011] Figure 1 It is a diagram showing the basic structure of a signal transmission device.

[0012] Figure 2 This is a diagram showing the basic structure of a transformer chip.

[0013] Figure 3 This is a three-dimensional view of a semiconductor device used as a dual-channel transformer chip.

[0014] Figure 4 yes Figure 3 A top view of the semiconductor device shown.

[0015] Figure 5 It means in Figure 3A top view of a layer in a semiconductor device in which a low-potential coil is formed.

[0016] Figure 6 It means in Figure 3 A top view of a layer in a semiconductor device in which a high-potential coil is formed.

[0017] Figure 7 It is along Figure 6 The cross-sectional view of line VIII-VIII shown.

[0018] Figure 8 It means Figure 7 The diagram shows an enlarged view (separated structure) of region XIII.

[0019] Figure 9 This is a schematic diagram illustrating an example of the layout of a transformer chip.

[0020] Figure 10 This is a diagram illustrating a signal transmission device according to a first embodiment (comparative example).

[0021] Figure 11 This is a diagram illustrating a signal transmission device according to a second embodiment.

[0022] Figure 12 This is a diagram illustrating a first example of a pulse signal generation operation.

[0023] Figure 13 This is a diagram illustrating a second example of a pulse signal generation operation.

[0024] Figure 14 This is a diagram illustrating a third example of a pulse signal generation operation.

[0025] Figure 15 It is a diagram showing the exterior of the vehicle. Detailed Implementation

[0026] <Signal Transmission Device (Basic Structure)>

[0027] Figure 1 This diagram illustrates the basic structure of a signal transmission device. In this example, the signal transmission device 200 is a semiconductor integrated circuit device (so-called an insulated gate driver IC) that insulates the primary circuit system 200p (VCC1-GND1 system) from the secondary circuit system 200s (VCC2-GND2 system), and transmits pulse signals from the primary circuit system 200p to the secondary circuit system 200s to drive the gate of a switching element (not shown) disposed in the secondary circuit system 200s. For example, the signal transmission device 200 is formed by sealing the controller chip 210, driver chip 220, and transformer chip 230 into a single package.

[0028] The controller chip 210 is a semiconductor chip that operates by receiving a power supply voltage VCC1 (e.g., a maximum of 7V based on GND1). The controller chip 210 integrates, for example, a pulse transmitting circuit 211, buffers 212 and 213.

[0029] The pulse transmitting circuit 211 is a pulse generator that generates transmit pulse signals S11 and S21 based on the input pulse signal IN. More specifically, the pulse transmitting circuit 211 drives the transmit pulse signal S11 (single or multiple transmit pulse outputs) when the input pulse signal IN is high, and drives the transmit pulse signal S21 when the input pulse signal IN is low. That is, the pulse transmitting circuit 211 drives either the transmit pulse signal S11 or S21 according to the logic level of the input pulse signal IN.

[0030] The buffer 212 receives the input of the transmission pulse signal S11 from the pulse transmission circuit 211 and performs pulse driving on the transformer chip 230 (specifically the transformer 231).

[0031] The buffer 213 receives the input of the transmission pulse signal S21 from the pulse transmission circuit 211 and performs pulse driving on the transformer chip 230 (specifically the transformer 232).

[0032] The driver chip 220 is a semiconductor chip that operates by receiving a power supply voltage VCC2 (e.g., a maximum of 30V based on GND2). The driver chip 220 integrates, for example, buffers 221 and 222, a pulse receiving circuit 223, and a driver 224.

[0033] The buffer 221 shapes the waveform of the received pulse signal S12 induced in the transformer chip 230 (specifically the transformer 231) and outputs it to the pulse receiving circuit 223.

[0034] The buffer 222 shapes the waveform of the received pulse signal S22 induced in the transformer chip 230 (specifically the transformer 232) and outputs it to the pulse receiving circuit 223.

[0035] The pulse receiving circuit 223 drives the driver 224 based on the received pulse signals S12 and S22 input via buffers 221 and 222, thereby generating an output pulse signal OUT. More specifically, the pulse receiving circuit 223 drives the driver 224 in such a way that it receives the pulse of the received pulse signal S12 to raise the output pulse signal OUT to a high level, and on the other hand, it receives the pulse of the received pulse signal S22 to lower the output pulse signal OUT to a low level. That is, the pulse receiving circuit 223 switches the logic level of the output pulse signal OUT according to the logic level of the input pulse signal IN. Furthermore, an RS flip-flop can be appropriately used as the pulse receiving circuit 223, for example.

[0036] The driver 224 generates an output pulse signal OUT according to the drive control of the pulse receiving circuit 223.

[0037] Transformer chip 230 uses transformers 231 and 232 to DC-ground insulate the controller chip 210 from the driver chip 220, and outputs the transmit pulse signals S11 and S21 input from the pulse transmit circuit 211 as receive pulse signals S12 and S22 to the pulse receive circuit 223. Furthermore, in this specification, "DC-ground insulation" means that the two objects to be insulated are not connected by a conductor.

[0038] More specifically, transformer 231 outputs a receiving pulse signal S12 from secondary coil 231s based on the transmitting pulse signal S11 input to primary coil 231p. On the other hand, transformer 232 outputs a receiving pulse signal S22 from secondary coil 232s based on the transmitting pulse signal S21 input to primary coil 232p.

[0039] Thus, due to the characteristics of the spiral coil used for communication between insulators, the input pulse signal IN is separated into two transmission pulse signals S11 and S21 (equivalent to rising and falling signals), and then transmitted from the primary circuit system 200p to the secondary circuit system 200s via two transformers 231 and 232.

[0040] Furthermore, the signal transmission device 200 of this embodiment differs from the controller chip 210 and the driver chip 220 in that it independently has a transformer chip 230 that only carries transformers 231 and 232, and these three chips are sealed into a single package.

[0041] By adopting this structure, both the controller chip 210 and the driver chip 220 can be formed using general low- to medium-voltage processes (a few volts to tens of volts), thus eliminating the need for a dedicated high-voltage process (a few thousand volts), which reduces manufacturing costs.

[0042] Furthermore, the signal transmission device 200 can be appropriately utilized, for example, by a power supply device or an electric motor drive device of an on-board device mounted on the vehicle. In addition to engine-powered vehicles, the aforementioned vehicles also include electric vehicles (BEV [pure electric vehicle], HEV [hybrid electric vehicle], PHEV / PHV [plug-in hybrid electric vehicle], or FCEV / FCV [fuel cell electric vehicle], etc.).

[0043] <Transformer Chip (Basic Structure)>

[0044] Next, the basic structure of the transformer chip 230 will be explained. Figure 2 This diagram illustrates the basic structure of transformer chip 230. In the transformer chip 230 of this diagram, transformer 231 includes a primary side coil 231p and a secondary side coil 231s opposite each other in the vertical direction. Transformer 232 includes a primary side coil 232p and a secondary side coil 232s opposite each other in the vertical direction.

[0045] Primary side coils 231p and 232p are both formed on the first wiring layer (lower layer) 230a of the transformer chip 230. Secondary side coils 231s and 232s are both formed on the second wiring layer (upper layer in this figure) 230b of the transformer chip 230. Furthermore, the secondary side coil 231s is positioned directly above the primary side coil 231p, opposite to it. Similarly, the secondary side coil 232s is positioned directly above the primary side coil 232p, opposite to it.

[0046] The primary side coil 231p is arranged in a spiral pattern, starting from the first end connected to the internal terminal X21 and spiraling clockwise around the internal terminal X21, with its second end connecting to the internal terminal X22. Conversely, the primary side coil 232p is arranged in a spiral pattern, starting from the first end connected to the internal terminal X23 and spiraling counterclockwise around the internal terminal X23, with its second end connecting to the internal terminal X22. The internal terminals X21, X22, and X23 are arranged in a straight line in the order shown in the diagram.

[0047] Internal terminal X21 is connected to external terminal T21 of the second layer 230b via conductive wiring Y21 and through-hole Z21. Internal terminal X22 is connected to external terminal T22 of the second layer 230b via conductive wiring Y22 and through-hole Z22. Internal terminal X23 is connected to external terminal T23 of the second layer 230b via conductive wiring Y23 and through-hole Z23. Furthermore, external terminals T21 to T23 are arranged in a straight line for wire connection with the controller chip 210.

[0048] The secondary-side coil 231s is spirally arranged around the external terminal T24 in a counter-clockwise direction, starting from the first end connected to the external terminal T24, and the second end, corresponding to its endpoint, is connected to the external terminal T25. On the other hand, the secondary-side coil 232s is spirally arranged around the external terminal T26 in a clockwise direction, starting from the first end connected to the external terminal T26, and the second end, corresponding to its endpoint, is connected to the external terminal T25. Furthermore, the external terminals T24, T25, and T26 are arranged linearly in the order shown in the figure for wire connection to the driver chip 220.

[0049] Secondary coils 231s and 232s are AC connected to primary coils 231p and 232p via magnetic coupling, respectively, and are DC insulated from primary coils 231p and 232p. That is, driver chip 220 is AC connected to controller chip 210 via transformer chip 230, and is DC insulated from controller chip 210 via transformer chip 230.

[0050] <Transformer Chip (Dual-Channel Type)>

[0051] Figure 3 This is a perspective view of a semiconductor device 5 used as a dual-channel transformer chip. Figure 4 yes Figure 3 A top view of the semiconductor device 5 shown. Figure 5 It means in Figure 3 The diagram shows a top view of the semiconductor device 5 in which a low-potential coil 22 (equivalent to the primary coil of a transformer) is formed. Figure 6 It means in Figure 3 The diagram shows a top view of the layer in the semiconductor device 5 in which a high-potential coil 23 (equivalent to the secondary coil of a transformer) is formed. Figure 7 It is along Figure 6 The cross-sectional view of line VIII-VIII shown. Figure 8 It means Figure 7 The diagram shows an enlarged view of region XIII, which illustrates the separation structure 130.

[0052] Reference Figures 3-7 The semiconductor device 5 includes a rectangular parallelepiped semiconductor chip 41. The semiconductor chip 41 includes at least one of silicon, a wide-bandgap semiconductor, and a compound semiconductor.

[0053] Wide bandgap semiconductors are composed of semiconductors with a bandgap exceeding that of silicon (approximately 1.12 eV). The bandgap of a wide bandgap semiconductor is preferably 2.0 eV or higher. Wide bandgap semiconductors can also be SiC (silicon carbide). Compound semiconductors can be III-V group compound semiconductors. Compound semiconductors can also contain at least one of AlN (aluminum nitride), InN (indium nitride), GaN (gallium nitride), and GaAs (gallium arsenide).

[0054] In this embodiment, the semiconductor chip 41 includes a silicon semiconductor substrate. The semiconductor chip 41 may also be an epitaxial substrate having a stacked structure comprising a silicon semiconductor substrate and a silicon epitaxial layer. The conductivity type of the semiconductor substrate may be n-type or p-type. The epitaxial layer may be n-type or p-type.

[0055] The semiconductor chip 41 has a first main surface 42 on one side, a second main surface 43 on the other side, and chip sidewalls 44A to 44D connecting the first main surface 42 and the second main surface 43. The first main surface 42 and the second main surface 43 are formed into a quadrilateral shape (rectangular shape in this embodiment) when viewed from their normal direction Z in a top view (hereinafter referred to as "top view").

[0056] The chip sidewalls 44A-44D include: a first chip sidewall 44A, a second chip sidewall 44B, a third chip sidewall 44C, and a fourth chip sidewall 44D. The first chip sidewall 44A and the second chip sidewall 44B form the long side of the semiconductor chip 41. The first chip sidewall 44A and the second chip sidewall 44B extend along a first direction X and are opposite each other along a second direction Y. The third chip sidewall 44C and the fourth chip sidewall 44D form the short side of the semiconductor chip 41. The third chip sidewall 44C and the fourth chip sidewall 44D extend along the second direction Y and are opposite each other along the first direction X. The chip sidewalls 44A-44D are formed by grinding surfaces.

[0057] The semiconductor device 5 further includes an insulating layer 51 formed on a first main surface 42 of the semiconductor chip 41. The insulating layer 51 has an insulating main surface 52 and insulating sidewalls 53A to 53D. In a top view, the insulating main surface 52 is formed as a quadrilateral shape (rectangular shape in this embodiment) that matches the first main surface 42. The insulating main surface 52 extends parallel to the first main surface 42.

[0058] The insulating sidewalls 53A-53D include: a first insulating sidewall 53A, a second insulating sidewall 53B, a third insulating sidewall 53C, and a fourth insulating sidewall 53D. The insulating sidewalls 53A-53D extend from the periphery of the insulating main surface 52 toward the semiconductor chip 41 and are connected to the chip sidewalls 44A-44D. Specifically, the insulating sidewalls 53A-53D are formed flush with the chip sidewalls 44A-44D. The insulating sidewalls 53A-53D form grinding surfaces flush with the chip sidewalls 44A-44D.

[0059] The insulating layer 51 is composed of a multilayer insulating stack structure including a lower insulating layer 55, an upper insulating layer 56, and multiple (11 layers in this embodiment) interlayer insulating layers 57. The lower insulating layer 55 is an insulating layer that directly covers the first main surface 42. The upper insulating layer 56 is an insulating layer that forms the insulating main surface 52. The multiple interlayer insulating layers 57 are insulating layers located between the lower insulating layer 55 and the upper insulating layer 56. In this embodiment, the lower insulating layer 55 has a single-layer structure containing silicon oxide. In this embodiment, the upper insulating layer 56 has a single-layer structure containing silicon oxide. The thickness of the lower insulating layer 55 and the thickness of the upper insulating layer 56 can be more than 1 μm and less than 3 μm (for example, about 2 μm).

[0060] The multiple interlayer insulating layers 57 each have a stacked structure comprising a first insulating layer 58 on the side of the lowest insulating layer 55 and a second insulating layer 59 on the side of the highest insulating layer 56. The first insulating layer 58 may also comprise silicon nitride. The first insulating layer 58 is formed as an etch stop layer relative to the second insulating layer 59. The thickness of the first insulating layer 58 may be greater than 0.1 μm and less than 1 μm (e.g., about 0.3 μm).

[0061] A second insulating layer 59 is formed on top of the first insulating layer 58. It comprises an insulating material different from the first insulating layer 58. The second insulating layer 59 may also comprise silicon oxide. The thickness of the second insulating layer 59 can be more than 1 μm and less than 3 μm (e.g., about 2 μm). Preferably, the thickness of the second insulating layer 59 exceeds the thickness of the first insulating layer 58.

[0062] The total thickness DT of the insulating layer 51 can be 5 μm or more and 50 μm or less. The total thickness DT of the insulating layer 51 and the number of layers of the interlayer insulating layer 57 are arbitrary and are adjusted according to the required insulation withstand voltage (insulation breakdown withstand capability). In addition, the insulating materials of the bottom insulating layer 55, the top insulating layer 56 and the interlayer insulating layer 57 are arbitrary and not limited to specific insulating materials.

[0063] The semiconductor device 5 includes a first functional device 45 formed on the insulating layer 51. The first functional device 45 includes one or more (in this embodiment, multiple) transformers 21 (equivalent to the previous transformers). That is, the semiconductor device 5 is a multi-channel device including multiple transformers 21. The multiple transformers 21 are formed at intervals and spaced apart from the insulating sidewalls 53A-53D inside the insulating layer 51. The multiple transformers 21 are formed at intervals and spaced apart along a first direction X.

[0064] Specifically, in the top view, the plurality of transformers 21 include a first transformer 21A, a second transformer 21B, a third transformer 21C, and a fourth transformer 21D, which are formed sequentially from the insulating sidewall 53C side toward the insulating sidewall 53D side. The plurality of transformers 21A to 21D each have the same construction. The construction of the first transformer 21A will be described below as an example. The description of the construction of the second transformer 21B, the third transformer 21C, and the fourth transformer 21D, applicable to the construction of the first transformer 21A, is omitted.

[0065] Reference Figures 5-7 The first transformer 21A includes a low-potential coil 22 and a high-potential coil 23. The low-potential coil 22 is formed within an insulating layer 51. The high-potential coil 23 is formed within the insulating layer 51 opposite to the low-potential coil 22 along the normal direction Z. In this embodiment, the low-potential coil 22 and the high-potential coil 23 are formed in the region sandwiched between the lowermost insulating layer 55 and the uppermost insulating layer 56 (i.e., multiple interlayer insulating layers 57).

[0066] The low-potential coil 22 is formed within the insulating layer 51 on the side of the lowest insulating layer 55 (semiconductor chip 41), and the high-potential coil 23 is formed within the insulating layer 51 relative to the low-potential coil 22 on the side of the uppermost insulating layer 56 (insulating main surface 52). That is, the high-potential coil 23 is positioned opposite the semiconductor chip 41, separated from the low-potential coil 22. The arrangement positions of the low-potential coil 22 and the high-potential coil 23 are arbitrary. In addition, the high-potential coil 23 only needs to be positioned opposite the low-potential coil 22, separated from it by one or more interlayer insulating layers 57.

[0067] The distance between the low-potential coil 22 and the high-potential coil 23 (i.e., the number of layers of interlayer insulation 57) is appropriately adjusted according to the insulation withstand voltage and electric field strength between the low-potential coil 22 and the high-potential coil 23. In this embodiment, the low-potential coil 22 is formed in the third layer of interlayer insulation 57 starting from the side of the bottommost insulation layer 55. In this embodiment, the high-potential coil 23 is formed in the first layer of interlayer insulation 57 starting from the side of the topmost insulation layer 56.

[0068] The low-potential coil 22 is embedded in the interlayer insulation layer 57, passing through the first insulation layer 58 and the second insulation layer 59. The low-potential coil 22 includes a first inner end 24, a first outer end 25, and a first helical portion 26 spirally wound between the first inner end 24 and the first outer end 25. In a top view, the first helical portion 26 is spirally wound in an elliptical shape (oblong shape). The portion forming the innermost periphery of the first helical portion 26 divides an elliptical first inner region 66 in a top view.

[0069] The number of turns in the first helical portion 26 can be 5 or more and 30 or less. The width of the first helical portion 26 can also be 0.1 μm or more and 5 μm or less. The width of the first helical portion 26 is preferably 1 μm or more and 3 μm or less. The width of the first helical portion 26 is defined by the width in the direction orthogonal to the helical direction. The first winding pitch of the first helical portion 26 can be 0.1 μm or more and 5 μm or less. The first winding pitch is preferably 1 μm or more and 3 μm or less. The first winding pitch is defined by the distance between two adjacent portions in the first helical portion 26 in the direction orthogonal to the helical direction.

[0070] The winding shape of the first spiral portion 26 and the planar shape of the first inner region 66 are arbitrary and not limited to any particular shape. Figure 5 As shown in the diagram. The first spiral portion 26 can also be wound into a polygonal shape such as a triangular shape or a quadrilateral shape or a circular shape in the top view. The first inner region 66 can also be divided into a polygonal shape such as a triangular shape or a quadrilateral shape or a circular shape in the top view according to the winding shape of the first spiral portion 26.

[0071] The low-potential coil 22 may also comprise at least one of titanium, titanium nitride, copper, aluminum, and tungsten. The low-potential coil 22 may also have a laminated structure comprising a barrier layer and a main body layer. The barrier layer divides recessed spaces within the interlayer insulating layer 57. The barrier layer may comprise at least one of titanium and titanium nitride. The main body layer may comprise at least one of copper, aluminum, and tungsten.

[0072] The high-potential coil 23 is embedded in the interlayer insulating layer 57, passing through the first insulating layer 58 and the second insulating layer 59. The high-potential coil 23 includes a second inner end 27, a second outer end 28, and a second spiral portion 29 wound in a spiral shape between the second inner end 27 and the second outer end 28. In a top view, the second spiral portion 29 is spirally wound in an elliptical shape (oblong shape). In this embodiment, the portion forming the innermost periphery of the second spiral portion 29 defines an elliptical second inner region 67 in a top view. The second inner region 67 of the second spiral portion 29 is opposite to the first inner region 66 of the first spiral portion 26 along the normal direction Z.

[0073] The number of turns in the second helical section 29 can be 5 or more and 30 or less. The number of turns in the second helical section 29 relative to the number of turns in the first helical section 26 is adjusted according to the voltage value to be boosted. Preferably, the number of turns in the second helical section 29 exceeds the number of turns in the first helical section 26. Of course, the number of turns in the second helical section 29 can be less than the number of turns in the first helical section 26, or it can be equal to the number of turns in the first helical section 26.

[0074] The width of the second helical portion 29 can be 0.1 μm or more and 5 μm or less. Preferably, the width of the second helical portion 29 is 1 μm or more and 3 μm or less. The width of the second helical portion 29 is defined by the width in the direction orthogonal to the helical direction. Preferably, the width of the second helical portion 29 is equal to the width of the first helical portion 26.

[0075] The second winding pitch of the second helical portion 29 can be 0.1 μm or more and 5 μm or less. Preferably, the second winding pitch is 1 μm or more and 3 μm or less. The second winding pitch is defined by the distance between two adjacent portions of the second helical portion 29 in a direction orthogonal to the helical direction. Preferably, the second winding pitch is equal to the first winding pitch of the first helical portion 26.

[0076] The winding shape of the second spiral section 29 and the planar shape of the second inner region 67 are arbitrary and not limited to... Figure 6 As shown in the diagram. The second spiral portion 29 can also be wound into a polygonal shape such as a triangle or a quadrilateral shape, or a circle in the top view. The second inner region 67 can also be divided into a polygonal shape such as a triangle or a quadrilateral shape, or a circle in the top view, depending on the winding shape of the second spiral portion 29.

[0077] The high-potential coil 23 is preferably formed of the same conductive material as the low-potential coil 22. That is, the high-potential coil 23 preferably includes a barrier layer and a main body layer in the same way as the low-potential coil 22.

[0078] Reference Figure 4 The semiconductor device 5 includes a plurality of (12 in this figure) low-potential terminals 11 and a plurality of (12 in this figure) high-potential terminals 12. The plurality of low-potential terminals 11 are electrically connected to the low-potential coils 22 of the corresponding transformers 21A to 21D. The plurality of high-potential terminals 12 are electrically connected to the high-potential coils 23 of the corresponding transformers 21A to 21D.

[0079] Multiple low-potential terminals 11 are formed on the insulating main surface 52 of the insulating layer 51. Specifically, the multiple low-potential terminals 11 are formed at intervals along the second direction Y and the multiple transformers 21A~21D in the region on the insulating sidewall 53B, and are arranged at intervals along the first direction X.

[0080] The plurality of low-potential terminals 11 includes: a first low-potential terminal 11A, a second low-potential terminal 11B, a third low-potential terminal 11C, a fourth low-potential terminal 11D, a fifth low-potential terminal 11E, and a sixth low-potential terminal 11F. In this embodiment, each of the plurality of low-potential terminals 11A to 11F is formed in twos. The number of the plurality of low-potential terminals 11A to 11F is arbitrary.

[0081] In the top view, the first low-potential terminal 11A is opposite to the first transformer 21A along the second direction Y. In the top view, the second low-potential terminal 11B is opposite to the second transformer 21B along the second direction Y. In the top view, the third low-potential terminal 11C is opposite to the third transformer 21C along the second direction Y. In the top view, the fourth low-potential terminal 11D is opposite to the fourth transformer 21D along the second direction Y. In the top view, the fifth low-potential terminal 11E is formed in the area between the first low-potential terminal 11A and the second low-potential terminal 11B. In the top view, the sixth low-potential terminal 11F is formed in the area between the third low-potential terminal 11C and the fourth low-potential terminal 11D.

[0082] The first low-potential terminal 11A is electrically connected to the first inner end 24 of the first transformer 21A (low-potential coil 22). The second low-potential terminal 11B is electrically connected to the first inner end 24 of the second transformer 21B (low-potential coil 22). The third low-potential terminal 11C is electrically connected to the first inner end 24 of the third transformer 21C (low-potential coil 22). The fourth low-potential terminal 11D is electrically connected to the first inner end 24 of the fourth transformer 21D (low-potential coil 22).

[0083] The fifth low-potential terminal 11E is electrically connected to the first outer end 25 of the first transformer 21A (low-potential coil 22) and the first outer end 25 of the second transformer 21B (low-potential coil 22). The sixth low-potential terminal 11F is electrically connected to the first outer end 25 of the third transformer 21C (low-potential coil 22) and the first outer end 25 of the fourth transformer 21D (low-potential coil 22).

[0084] Multiple high-potential terminals 12 and multiple low-potential terminals 11 are formed spaced apart on the insulating main surface 52 of the insulating layer 51. Specifically, the multiple high-potential terminals 12 are formed spaced apart from the multiple low-potential terminals 11 in the region of the insulating sidewall 53A, and are arranged spaced apart along the first direction X.

[0085] In the top view, multiple high-potential terminals 12 are respectively formed in areas close to the corresponding transformers 21A~21D. The high-potential terminals 12 are close to the transformers 21A~21D in the top view because the distance between the high-potential terminals 12 and the transformers 21 is less than the distance between the low-potential terminals 11 and the high-potential terminals 12.

[0086] Specifically, in the top view, a plurality of high-potential terminals 12 are formed at intervals along the first direction X, opposite to a plurality of transformers 21A-21D. More specifically, in the top view, the plurality of high-potential terminals 12 are formed at intervals along the first direction X, located in the second inner region 67 of the high-potential coil 23 and the region between adjacent high-potential coils 23. Thus, in the top view, the plurality of high-potential terminals 12 are arranged side by side in a row with the plurality of transformers 21A-21D along the first direction X.

[0087] The plurality of high-potential terminals 12 includes: a first high-potential terminal 12A, a second high-potential terminal 12B, a third high-potential terminal 12C, a fourth high-potential terminal 12D, a fifth high-potential terminal 12E, and a sixth high-potential terminal 12F. In this embodiment, each of the plurality of high-potential terminals 12A to 12F is formed in two. The number of the plurality of high-potential terminals 12A to 12F is arbitrary.

[0088] In the top view, a first high-potential terminal 12A is formed in the second inner region 67 of the first transformer 21A (high-potential coil 23). A second high-potential terminal 12B is formed in the second inner region 67 of the second transformer 21B (high-potential coil 23). A third high-potential terminal 12C is formed in the second inner region 67 of the third transformer 21C (high-potential coil 23). A fourth high-potential terminal 12D is formed in the second inner region 67 of the fourth transformer 21D (high-potential coil 23). A fifth high-potential terminal 12E is formed in the region between the first transformer 21A and the second transformer 21B in the top view. A sixth high-potential terminal 12F is formed in the region between the third transformer 21C and the fourth transformer 21D in the top view.

[0089] The first high-potential terminal 12A is electrically connected to the second inner end 27 of the first transformer 21A (high-potential coil 23). The second high-potential terminal 12B is electrically connected to the second inner end 27 of the second transformer 21B (high-potential coil 23). The third high-potential terminal 12C is electrically connected to the second inner end 27 of the third transformer 21C (high-potential coil 23). The fourth high-potential terminal 12D is electrically connected to the second inner end 27 of the fourth transformer 21D (high-potential coil 23).

[0090] The fifth high-potential terminal 12E is electrically connected to the second outer end 28 of the first transformer 21A (high-potential coil 23) and the second outer end 28 of the second transformer 21B (high-potential coil 23). The sixth high-potential terminal 12F is electrically connected to the second outer end 28 of the third transformer 21C (high-potential coil 23) and the second outer end 28 of the fourth transformer 21D (high-potential coil 23).

[0091] Reference Figures 5-7 The semiconductor device 5 includes a first low-potential wiring 31, a second low-potential wiring 32, a first high-potential wiring 33, and a second high-potential wiring 34, respectively formed within an insulating layer 51. In this embodiment, a plurality of first low-potential wirings 31, a plurality of second low-potential wirings 32, a plurality of first high-potential wirings 33, and a plurality of second high-potential wirings 34 are formed.

[0092] The first low-potential wiring 31 and the second low-potential wiring 32 fix the low-potential coil 22 of the first transformer 21A and the low-potential coil 22 of the second transformer 21B to the same potential. Furthermore, the first low-potential wiring 31 and the second low-potential wiring 32 fix the low-potential coil 22 of the third transformer 21C and the low-potential coil 22 of the fourth transformer 21D to the same potential. In this embodiment, the first low-potential wiring 31 and the second low-potential wiring 32 fix all the low-potential coils 22 of transformers 21A to 21D to the same potential.

[0093] The first high-potential wiring 33 and the second high-potential wiring 34 fix the high-potential coil 23 of the first transformer 21A and the high-potential coil 23 of the second transformer 21B to the same potential. Furthermore, the first high-potential wiring 33 and the second high-potential wiring 34 fix the high-potential coil 23 of the third transformer 21C and the high-potential coil 23 of the fourth transformer 21D to the same potential. In this embodiment, the first high-potential wiring 33 and the second high-potential wiring 34 fix all the high-potential coils 23 of transformers 21A to 21D to the same potential.

[0094] Multiple first low-potential wirings 31 are electrically connected to the corresponding low-potential terminals 11A-11D and the first inner ends 24 of the corresponding transformers 21A-21D (low-potential coils 22), respectively. The multiple first low-potential wirings 31 have the same structure. Hereinafter, the structure of the first low-potential wiring 31 connected to the first low-potential terminal 11A and the first transformer 21A will be described as an example. The description of the structure of the other first low-potential wirings 31 is omitted for the first low-potential wiring 31 connected to the first transformer 21A.

[0095] The first low-potential wiring 31 includes: a through wiring 71, a low-potential connection wiring 72, a lead wiring 73, a first connection plug electrode 74, a second connection plug electrode 75, one or more (in this embodiment, multiple) pad plug electrodes 76, and one or more (in this embodiment, multiple) substrate plug electrodes 77.

[0096] The through-wire 71, low-potential connection wire 72, lead-out wire 73, first connection plug electrode 74, second connection plug electrode 75, pad plug electrode 76, and substrate plug electrode 77 are preferably formed of the same conductive material as the low-potential coil 22. That is, the through-wire 71, low-potential connection wire 72, lead-out wire 73, first connection plug electrode 74, second connection plug electrode 75, pad plug electrode 76, and substrate plug electrode 77 are preferably the same as the low-potential coil 22, each including a barrier layer and a main body layer.

[0097] The through-wire 71 extends through multiple interlayer insulation layers 57 in the insulation layer 51, forming a columnar shape extending along the normal direction Z. In this embodiment, the through-wire 71 is formed in the region between the lowermost insulation layer 55 and the uppermost insulation layer 56 in the insulation layer 51. The through-wire 71 has an upper end portion on the side of the uppermost insulation layer 56 and a lower end portion on the side of the lowermost insulation layer 55. The upper end portion of the through-wire 71 is formed in the same interlayer insulation layer 57 as the high-potential coil 23 and is covered by the uppermost insulation layer 56. The lower end portion of the through-wire 71 is formed in the same interlayer insulation layer 57 as the low-potential coil 22.

[0098] In this embodiment, the through-wiring 71 includes a first electrode layer 78, a second electrode layer 79, and a plurality of wiring plug electrodes 80. In the through-wiring 71, the first electrode layer 78, the second electrode layer 79, and the wiring plug electrodes 80 are each formed of the same conductive material as the low-potential coil 22. That is, the first electrode layer 78, the second electrode layer 79, and the wiring plug electrodes 80, like the low-potential coil 22, each include a barrier layer and a main body layer.

[0099] The first electrode layer 78 forms the upper end of the through wiring 71. The second electrode layer 79 forms the lower end of the through wiring 71. The first electrode layer 78 is formed in an island shape and is opposite to the low potential terminal 11 (first low potential terminal 11A) along the normal direction Z. The second electrode layer 79 is formed in an island shape and is opposite to the first electrode layer 78 along the normal direction Z.

[0100] Multiple wiring plug electrodes 80 are embedded in multiple interlayer insulation layers 57 located between the first electrode layer 78 and the second electrode layer 79. The multiple wiring plug electrodes 80 are stacked from the lowest insulation layer 55 to the highest insulation layer 56 in an electrically interconnected manner, and electrically connect the first electrode layer 78 and the second electrode layer 79. Each of the multiple wiring plug electrodes 80 has a planar area smaller than the planar area of ​​the first electrode layer 78 and the planar area of ​​the second electrode layer 79.

[0101] Furthermore, the number of stacked layers of the plurality of wiring plug electrodes 80 is consistent with the number of stacked layers of the plurality of interlayer insulation layers 57. In this embodiment, six wiring plug electrodes 80 are embedded in each interlayer insulation layer 57, but the number of wiring plug electrodes 80 embedded in each interlayer insulation layer 57 is arbitrary. Of course, one or more wiring plug electrodes 80 that penetrate multiple interlayer insulation layers 57 can also be formed.

[0102] A low-potential connection wiring 72 is formed within the same interlayer insulation layer 57 as the low-potential coil 22 in the first inner region 66 of the first transformer 21A (low-potential coil 22). The low-potential connection wiring 72 is formed in an island shape, facing the high-potential terminal 12 (first high-potential terminal 12A) along the normal direction Z. The low-potential connection wiring 72 preferably has a planar area exceeding the planar area of ​​the wiring plug electrode 80. The low-potential connection wiring 72 is electrically connected to the first inner end 24 of the low-potential coil 22.

[0103] Lead-out wiring 73 is formed within interlayer insulating layer 57 in the region between semiconductor chip 41 and through wiring 71. In this embodiment, lead-out wiring 73 is formed within interlayer insulating layer 57, which is the first layer starting from the lowest insulating layer 55. Lead-out wiring 73 includes: a first end on one side, a second end on the other side, and a wiring portion connecting the first end and the second end. The first end of lead-out wiring 73 is located in the region between semiconductor chip 41 and the lower end of through wiring 71. The second end of lead-out wiring 73 is located in the region between semiconductor chip 41 and low-potential connection wiring 72. The wiring portion extends along the first main surface 42 of semiconductor chip 41 and extends in a strip shape in the region between the first end and the second end.

[0104] The first connection plug electrode 74 is formed within the interlayer insulating layer 57 in the region between the through wiring 71 and the lead wiring 73, and is electrically connected to the first end of the through wiring 71 and the lead wiring 73. The second connection plug electrode 75 is formed within the interlayer insulating layer 57 in the region between the low-potential connection wiring 72 and the lead wiring 73, and is electrically connected to the second end of the low-potential connection wiring 72 and the lead wiring 73.

[0105] Multiple pad plug electrodes 76 are formed within the uppermost insulating layer 56 in the region between the low-potential terminal 11 (first low-potential terminal 11A) and the through wiring 71, respectively, and are electrically connected to the upper ends of the low-potential terminal 11 and the through wiring 71. Multiple substrate plug electrodes 77 are formed within the lowermost insulating layer 55 in the region between the semiconductor chip 41 and the lead wiring 73. In this embodiment, the substrate plug electrodes 77 are formed in the region between the semiconductor chip 41 and the first ends of the lead wiring 73, respectively, and are electrically connected to the first ends of the semiconductor chip 41 and the lead wiring 73.

[0106] Reference Figure 6and Figure 7 Multiple first high-potential wirings 33 are electrically connected to the second inner ends 27 of the corresponding high-potential terminals 12A-12D and the corresponding transformers 21A-21D (high-potential coils 23), respectively. Each of the multiple first high-potential wirings 33 has the same structure. The following description uses the structure of the first high-potential wiring 33 connected to the first high-potential terminal 12A and the first transformer 21A as an example. The description of the structure of the other first high-potential wirings 33 is omitted for the first high-potential wiring 33 connected to the first transformer 21A.

[0107] The first high-potential wiring 33 includes a high-potential connection wiring 81 and one or more (in this embodiment, multiple) pad plug electrodes 82. The high-potential connection wiring 81 and the pad plug electrodes 82 are preferably formed of the same conductive material as the low-potential coil 22. That is, the high-potential connection wiring 81 and the pad plug electrodes 82 preferably include a barrier layer and a body layer, just like the low-potential coil 22.

[0108] The high-potential connection wiring 81 is formed within the same interlayer insulation layer 57 as the high-potential coil 23 in the second inner region 67 of the high-potential coil 23. The high-potential connection wiring 81 is formed in an island shape and is positioned opposite the high-potential terminal 12 (first high-potential terminal 12A) along the normal direction Z. The high-potential connection wiring 81 is electrically connected to the second inner end 27 of the high-potential coil 23. In the top view, the high-potential connection wiring 81 is formed with a gap from the low-potential connection wiring 72 and is not positioned opposite the low-potential connection wiring 72 along the normal direction Z. Therefore, the insulation distance between the low-potential connection wiring 72 and the high-potential connection wiring 81 is increased, and the insulation withstand voltage of the insulation layer 51 is improved.

[0109] Multiple pad plug electrodes 82 are formed within the uppermost insulating layer 56 in the region between the high-potential terminal 12 (first high-potential terminal 12A) and the high-potential connection wiring 81, respectively, and are electrically connected to the high-potential terminal 12 and the high-potential connection wiring 81. In a top view, each of the multiple pad plug electrodes 82 has a planar area smaller than the planar area of ​​the high-potential connection wiring 81.

[0110] Reference Figure 7Preferably, the distance D1 between the low-potential terminal 11 and the high-potential terminal 12 exceeds the distance D2 between the low-potential coil 22 and the high-potential coil 23 (D2 < D1). Distance D1 preferably exceeds the total thickness DT of the plurality of interlayer insulation layers 57 (DT < D1). The ratio of distance D2 to distance D1, D2 / D1, can be 0.01 or more and 0.1 or less. Distance D1 is preferably 100 μm or more and 500 μm or less. Distance D2 can be 1 μm or more and 50 μm or less. Distance D2 is preferably 5 μm or more and 25 μm or less. The values ​​of distance D1 and distance D2 are arbitrary and appropriately adjusted according to the insulation withstand voltage to be achieved.

[0111] Reference Figure 6 as well as Figure 7 In the top view, the semiconductor device 5 includes a dummy pattern 85 embedded in the insulating layer 51 in a manner that surrounds the transformers 21A to 21D.

[0112] The dummy pattern 85 is formed from a different pattern (a discontinuous pattern) than that of the high-potential coil 23 and the low-potential coil 22, and is independent of the transformers 21A-21D. That is, the dummy pattern 85 does not function as a component of the transformers 21A-21D. The dummy pattern 85 is formed as a shielding conductor layer that shields the electric field between the low-potential coil 22 and the high-potential coil 23 in the transformers 21A-21D, suppressing electric field concentration targeting the high-potential coil 23. In this embodiment, the dummy pattern 85 is wound with a linear density equal to that of the high-potential coil 23 per unit area. The linear density of the dummy pattern 85 being equal to that of the high-potential coil 23 means that the linear density of the dummy pattern 85 converges within ±20% of the linear density of the high-potential coil 23.

[0113] The depth of the dummy pattern 85 inside the insulating layer 51 is arbitrary and adjusted according to the electric field strength to be mitigated. The dummy pattern 85 is preferably formed in a region in the normal direction Z that is close to the low-potential coil 22 and the high-potential coil 23. Furthermore, "close to the high-potential coil 23 in the normal direction Z" means that the distance between the dummy pattern 85 and the high-potential coil 23 in the normal direction Z is less than the distance between the dummy pattern 85 and the low-potential coil 22.

[0114] In this case, electric field concentration against the high-potential coil 23 can be appropriately suppressed. The smaller the distance between the dummy pattern 85 and the high-potential coil 23 in the normal direction Z, the better the electric field concentration against the high-potential coil 23 can be suppressed. The dummy pattern 85 is preferably formed within the same interlayer insulating layer 57 as the high-potential coil 23. In this case, electric field concentration against the high-potential coil 23 can be suppressed more appropriately. The dummy pattern 85 comprises multiple dummy patterns with different electrical states. The dummy pattern 85 may also include a high-potential dummy pattern.

[0115] The depth of the high-potential dummy pattern 86 inside the insulating layer 51 is arbitrary and adjusted according to the electric field strength to be mitigated. The high-potential dummy pattern 86 is preferably formed in a region in the normal direction Z that is close to the high-potential coil 23 relative to the low-potential coil 22. "Close to the high-potential coil 23 in the normal direction Z" means that the distance between the high-potential dummy pattern 86 and the high-potential coil 23 in the normal direction Z is less than the distance between the high-potential dummy pattern 86 and the low-potential coil 22.

[0116] The dummy pattern 85 includes a dummy pattern that is formed in an electrically levitated state within the insulation layer 51 in a manner that is located around the transformers 21A to 21D.

[0117] In this embodiment, the suspended dummy pattern, in the top view, appears as a densely wound line that partially covers and exposes the area surrounding the high-potential coil 23. The suspended dummy pattern can be formed with ends or without ends.

[0118] The depth position of the suspended dummy pattern inside the insulating layer 51 is arbitrary and can be adjusted according to the electric field strength to be mitigated.

[0119] The number of levitation lines is arbitrary and can be adjusted according to the electric field to be mitigated. A levitation dummy pattern can also be composed of multiple levitation dummy patterns.

[0120] Reference Figure 7 The semiconductor device 5 includes a second functional device 60 formed in the device region 62 on the first main surface 42 of the semiconductor chip 41. The second functional device 60 is formed utilizing the surface portion of the first main surface 42 of the semiconductor chip 41 and / or the region above the first main surface 42 of the semiconductor chip 41, and is covered by an insulating layer 51 (lowest insulating layer 55). Figure 7 In the diagram, the second functional device 60 is simplified and shown through the dashed lines on the surface of the first main surface 42.

[0121] The second functional device 60 is electrically connected to the low-potential terminal 11 via a low-potential wiring and to the high-potential terminal 12 via a high-potential wiring. The low-potential wiring has the same structure as the first low-potential wiring 31 (second low-potential wiring 32), except that it is wound into the insulating layer 51 in order to connect to the second functional device 60. The high-potential wiring has the same structure as the first high-potential wiring 33 (second high-potential wiring 34), except that it is wound into the insulating layer 51 in order to connect to the second functional device 60. Detailed descriptions of the low-potential and high-potential wirings of the second functional device 60 are omitted.

[0122] The second functional device 60 may also include at least one of a passive device, a semiconductor rectifier, and a semiconductor switch. Among the passive devices, the second functional device 60 may also include a circuit network formed by selectively combining any two or more of the passive devices, semiconductor rectifiers, and semiconductor switch devices. The circuit network may also form part or all of an integrated circuit.

[0123] Passive devices may include semiconductor passive devices. Passive devices may also include any one or both of resistors and capacitors. Semiconductor rectifier devices may also include at least one of pn junction diodes, PIN diodes, Zener diodes, Schottky barrier diodes, and fast recovery diodes. Semiconductor switching devices may also include at least one of BJTs (bipolar junction transistors), MISFETs (metal-insulator field-effect transistors), IGBTs (insulated gate bipolar junction transistors), and JFETs (junction field-effect transistors).

[0124] Reference Figures 5-7 The semiconductor device 5 further includes a sealing conductor 61 embedded within an insulating layer 51. In a top view, the sealing conductor 61 is embedded in the insulating layer 51 in a wall-like manner, spaced apart from the insulating sidewalls 53A-53D, dividing the insulating layer 51 into a device region 62 and an outer region 63. The sealing conductor 61 inhibits the ingress of moisture from the outer region 63 into the device region 62 and the formation of cracks.

[0125] Device area 62 is the area that includes the following: first functional device 45 (multiple transformers 21), second functional device 60, multiple low-potential terminals 11, multiple high-potential terminals 12, first low-potential wiring 31, second low-potential wiring 32, first high-potential wiring 33, second high-potential wiring 34, and dummy pattern 85. Outer area 63 is the area outside device area 62.

[0126] The sealed conductor 61 is electrically isolated from the device region 62. Specifically, the sealed conductor 61 is electrically isolated from the first functional device 45 (multiple transformers 21), the second functional device 60, multiple low-potential terminals 11, multiple high-potential terminals 12, the first low-potential wiring 31, the second low-potential wiring 32, the first high-potential wiring 33, the second high-potential wiring 34, and the dummy pattern 85. More specifically, the sealed conductor 61 is fixed in an electrically levitated state. The sealed conductor 61 does not form a current path connected to the device region 62.

[0127] In the top view, the sealing conductor 61 is formed as a strip along the insulating sidewalls 53A-53D. In this embodiment, the sealing conductor 61 is formed as a four-sided ring (specifically, a rectangular ring) in the top view. Thus, the sealing conductor 61 divides the device region 62 into a four-sided (specifically, a rectangular) shape in the top view. In addition, the sealing conductor 61 divides the outer region 63 of the four-sided ring (specifically, a rectangular ring) surrounding the device region 62 in the top view.

[0128] Specifically, the sealing conductor 61 has an upper end portion on the insulating main surface 52 side, a lower end portion on the semiconductor chip 41 side, and a wall portion extending in a wall-like shape between the upper end portion and the lower end portion. In this embodiment, the upper end portion of the sealing conductor 61 is formed spaced apart from the insulating main surface 52 toward the semiconductor chip 41 side and is located within the insulating layer 51. In this embodiment, the upper end portion of the sealing conductor 61 is covered by the uppermost insulating layer 56. The upper end portion of the sealing conductor 61 may also be covered by one or more interlayer insulating layers 57. The upper end portion of the sealing conductor 61 may also be exposed from the uppermost insulating layer 56. The lower end portion of the sealing conductor 61 is formed spaced apart from the semiconductor chip 41 toward the upper end portion side.

[0129] Thus, in this embodiment, the sealing conductor 61 is embedded in the insulating layer 51 such that it is located on the semiconductor chip 41 side relative to the plurality of low-potential terminals 11 and the plurality of high-potential terminals 12. Furthermore, the sealing conductor 61 is positioned within the insulating layer 51 opposite to the first functional device 45 (the plurality of transformers 21), the first low-potential wiring 31, the second low-potential wiring 32, the first high-potential wiring 33, the second high-potential wiring 34, and the dummy pattern 85 in a direction parallel to the insulating main surface 52. Alternatively, the sealing conductor 61 may be positioned within the insulating layer 51 opposite to a portion of the second functional device 60 in a direction parallel to the insulating main surface 52.

[0130] The sealing conductor 61 comprises a plurality of sealing plug conductors 64 and one or more (in this embodiment, a plurality of) sealing through-hole conductors 65. The number of sealing through-hole conductors 65 is arbitrary. The uppermost sealing plug conductor 64 of the plurality of sealing plug conductors 64 forms the upper end of the sealing conductor 61. The plurality of sealing through-hole conductors 65 respectively form the lower end of the sealing conductor 61. The sealing plug conductors 64 and the sealing through-hole conductors 65 are preferably formed of the same conductive material as the low-potential coil 22. That is, the sealing plug conductors 64 and the sealing through-hole conductors 65 preferably include a barrier layer and a body layer, just like the low-potential coil 22.

[0131] Multiple hermetically sealed plug conductors 64 are embedded in multiple interlayer insulating layers 57, forming, in top view, four-sided rings (specifically rectangular rings) surrounding the device region 62. The multiple hermetically sealed plug conductors 64 are stacked from the bottom insulating layer 55 to the top insulating layer 56 in an interconnected manner. The number of stacks of the multiple hermetically sealed plug conductors 64 is the same as the number of stacks of the multiple interlayer insulating layers 57. Alternatively, one or more hermetically sealed plug conductors 64 may be formed that penetrate through multiple interlayer insulating layers 57.

[0132] If an assembly of multiple sealing plug conductors 64 forms a ring-shaped sealing conductor 61, it is not necessary for all of the multiple sealing plug conductors 64 to be formed in a ring shape. For example, at least one of the multiple sealing plug conductors 64 can also be formed in an end-shaped manner. Alternatively, at least one of the multiple sealing plug conductors 64 can also be divided into multiple end-shaped strips. However, given the risk of moisture ingress and crack formation within the device region 62, it is preferable that the multiple sealing plug conductors 64 be formed in an endless (ring-shaped) manner.

[0133] Multiple sealing via conductors 65 are formed in the lowermost insulating layer 55 in the region between the semiconductor chip 41 and the sealing plug conductor 64. The multiple sealing via conductors 65 are formed spaced apart from the semiconductor chip 41 and connected to the sealing plug conductor 64. The multiple sealing via conductors 65 have a planar area smaller than the planar area of ​​the sealing plug conductor 64. In the case where a single sealing via conductor 65 is formed, the single sealing via conductor 65 may also have a planar area greater than or equal to the planar area of ​​the sealing plug conductor 64.

[0134] The width of the sealing conductor 61 can be 0.1 μm or more and 10 μm or less. Preferably, the width of the sealing conductor 61 is 1 μm or more and 5 μm or less. The width of the sealing conductor 61 is defined by the width in a direction orthogonal to the direction in which the sealing conductor 61 extends.

[0135] Reference Figure 7 as well as Figure 8The semiconductor device 5 further includes a separation structure 130 located between the semiconductor chip 41 and the sealing conductor 61, electrically isolating the sealing conductor 61 from the semiconductor chip 41. The separation structure 130 preferably includes an insulator. In this embodiment, the separation structure 130 is formed of a field insulating film 131 formed on a first main surface 42 of the semiconductor chip 41.

[0136] The field insulating film 131 comprises at least one of an oxide film (silicon oxide film) and a nitride film (silicon nitride film). Preferably, the field insulating film 131 is composed of a LOCOS (Local Selective Oxidation of Silicon) film, which is an example of an oxide film formed by oxidation of the first main surface 42 of the semiconductor chip 41. The thickness of the field insulating film 131 is arbitrary, as long as it is sufficient to insulate the semiconductor chip 41 from the sealing conductor 61. The thickness of the field insulating film 131 can be 0.1 μm or more and 5 μm or less.

[0137] The separation structure 130 is formed on the first main surface 42 of the semiconductor chip 41 and extends in a strip shape along the sealing conductor 61 in a top view. In this embodiment, the separation structure 130 is formed as a four-sided ring (specifically a rectangular ring) in a top view. The separation structure 130 has a connection portion 132 that connects to the lower end of the sealing conductor 61 (sealing via conductor 65). The connection portion 132 may also be an anchoring portion recessed into the lower end of the sealing conductor 61 (sealing via conductor 65) toward the semiconductor chip 41. Of course, the connection portion 132 may also be formed flush with the main surface of the separation structure 130.

[0138] The separation structure 130 includes: an inner end portion 130A on the device region 62 side, an outer end portion 130B on the outer region 63 side, and a main body portion 130C between the inner end portion 130A and the outer end portion 130B. In the top view, the inner end portion 130A divides the region where the second functional device 60 is formed (i.e., device region 62). The inner end portion 130A may also be integrally formed with an insulating film (not shown) formed on the first main surface 42 of the semiconductor chip 41.

[0139] The outer end portion 130B exposes from and is connected to the chip sidewalls 44A-44D of the semiconductor chip 41. More specifically, the outer end portion 130B is formed flush with the chip sidewalls 44A-44D of the semiconductor chip 41. The outer end portion 130B forms a flush grinding surface between the chip sidewalls 44A-44D of the semiconductor chip 41 and the insulating sidewalls 53A-53D of the insulating layer 51. Of course, in other embodiments, the outer end portion 130B may also be formed spaced apart from the chip sidewalls 44A-44D within the first main surface 42.

[0140] The main body 130C has a flat surface that extends substantially parallel to the first main surface 42 of the semiconductor chip 41. The main body 130C has a connecting portion 132 that connects to the lower end of the sealing conductor 61 (sealing through-hole conductor 65). The connecting portion 132 is formed in the main body 130C in a portion spaced apart from the inner end portion 130A and the outer end portion 130B. The separation structure 130 can be implemented in various ways other than the field insulating film 131.

[0141] Reference Figure 7 The semiconductor device 5 further includes an inorganic insulating layer 140 formed on the insulating main surface 52 of the insulating layer 51 in a manner that covers the sealing conductor 61. The inorganic insulating layer 140 may also be referred to as a passivation layer. The inorganic insulating layer 140 protects the insulating layer 51 and the semiconductor chip 41 from the insulating main surface 52.

[0142] In this embodiment, the inorganic insulating layer 140 has a stacked structure comprising a first inorganic insulating layer 141 and a second inorganic insulating layer 142. The first inorganic insulating layer 141 may also comprise silicon oxide. Preferably, the first inorganic insulating layer 141 comprises undoped silicon oxide, i.e., USG (undoped silicon glass). The thickness of the first inorganic insulating layer 141 may be 50 nm or more and 5000 nm or less. The second inorganic insulating layer 142 may also comprise silicon nitride. The thickness of the second inorganic insulating layer 142 may be 500 nm or more and 5000 nm or less. By increasing the total thickness of the inorganic insulating layer 140, the insulation withstand voltage on the high-potential coil 23 can be improved.

[0143] When the first inorganic insulating layer 141 is made of USG and the second inorganic insulating layer 142 is made of silicon nitride, the insulation breakdown voltage (V / cm) of USG exceeds that of silicon nitride. Therefore, when the inorganic insulating layer 140 is made thicker, it is preferable to form a first inorganic insulating layer 141 that is thicker than the second inorganic insulating layer 142.

[0144] The first inorganic insulating layer 141 may also comprise at least one of BPSG (borosilicate glass) and PSG (phosphosilicate glass), which are examples of silicon oxide. However, in this case, impurities (boron or phosphorus) are contained in the silicon oxide. Therefore, it is particularly preferable to form the first inorganic insulating layer 141 composed of USG in order to improve the insulation withstand voltage on the high-potential coil 23. Of course, the inorganic insulating layer 140 may also have a single-layer structure composed of either the first inorganic insulating layer 141 or the second inorganic insulating layer 142.

[0145] The inorganic insulating layer 140 covers the entire area of ​​the sealing conductor 61 and has a plurality of low-potential pad openings 143 and a plurality of high-potential pad openings 144 formed outside the sealing conductor 61. The plurality of low-potential pad openings 143 expose a plurality of low-potential terminals 11 respectively. The plurality of high-potential pad openings 144 expose a plurality of high-potential terminals 12 respectively. The inorganic insulating layer 140 may also have an overlapping portion that overlaps the periphery of the low-potential terminals 11. The inorganic insulating layer 140 may also have an overlapping portion that overlaps the periphery of the high-potential terminals 12.

[0146] The semiconductor device 5 further includes an organic insulating layer 145 formed on the inorganic insulating layer 140. The organic insulating layer 145 may also contain a photosensitive resin. The organic insulating layer 145 may also contain at least one of polyimide, polyamide, and polybenzoxazole. In this embodiment, the organic insulating layer 145 contains polyimide. The thickness of the organic insulating layer 145 may be 1 μm or more and 50 μm or less.

[0147] The thickness of the organic insulating layer 145 is preferably greater than the total thickness of the inorganic insulating layer 140. Furthermore, the total thickness of the inorganic insulating layer 140 and the organic insulating layer 145 is preferably greater than the distance D2 between the low-potential coil 22 and the high-potential coil 23. In this case, the total thickness of the inorganic insulating layer 140 is preferably 2 μm or more and 10 μm or less. Additionally, the thickness of the organic insulating layer 145 is preferably 5 μm or more and 50 μm or less. Based on these structures, the thickening of the inorganic insulating layer 140 and the organic insulating layer 145 can be suppressed, while the insulation withstand voltage on the high-potential coil 23 can be appropriately increased through the laminated film of the inorganic insulating layer 140 and the organic insulating layer 145.

[0148] The organic insulating layer 145 includes a first portion 146 covering a region on the low-potential side and a second portion 147 covering a region on the high-potential side. The first portion 146 covers the sealing conductor 61 through the inorganic insulating layer 140. The first portion 146 has a plurality of low-potential terminal openings 148 in the region outside the sealing conductor 61, exposing a plurality of low-potential terminals 11 (low-potential pad openings 143). The first portion 146 may also have an overlap (overlap) that overlaps the periphery of the low-potential pad openings 143.

[0149] The second portion 147 is formed spaced apart from the first portion 146, such that the inorganic insulating layer 140 is exposed between the first portion 146 and the second portion 147. The second portion 147 has a plurality of high-potential terminal openings 149 that expose a plurality of high-potential terminals 12 (high-potential pad openings 144). The second portion 147 may also have an overlapping portion (overlapping portion) that overlaps the periphery of the high-potential pad openings 144.

[0150] Part 147 also covers transformers 21A-21D and dummy pattern 85. Specifically, Part 147 also covers multiple high-potential coils 23, multiple high-potential terminals 12, a first high-potential dummy pattern 87, a second high-potential dummy pattern 88, and a floating dummy pattern 121.

[0151] The present invention can also be implemented in other ways. In the described embodiments, an example having a first functional device 45 and a second functional device 60 has been illustrated. However, it is also possible to employ a configuration that does not have a first functional device 45 and only has a second functional device 60. In this case, the dummy pattern 85 can also be removed. According to this configuration, the second functional device 60 can achieve the same effect as described in the first embodiment (except for the effect of the dummy pattern 85).

[0152] That is, when a voltage is applied to the second functional device 60 via the low-potential terminal 11 and the high-potential terminal 12, undesirable conduction between the high-potential terminal 12 and the sealing conductor 61 can be suppressed. Furthermore, when a voltage is applied to the second functional device 60 via the low-potential terminal 11 and the high-potential terminal 12, undesirable conduction between the low-potential terminal 11 and the sealing conductor 61 can be suppressed.

[0153] Furthermore, in the described embodiment, an example with a second functional device 60 was given. However, the second functional device 60 is not necessary and may be omitted.

[0154] Furthermore, in the described embodiment, an example with a dummy pattern 85 was given. However, the dummy pattern 85 is not necessary and can be removed.

[0155] Furthermore, in the described embodiment, an example of a multi-channel type comprising multiple transformers 21 was given. However, a single-channel type comprising a single transformer 21 may also be used for the first functional device 45.

[0156] <Transformer Arrangement>

[0157] Figure 9 This is a top view (top view) schematically illustrating an example of the transformer arrangement in a dual-channel transformer chip 300 (equivalent to the previous semiconductor device 5). The transformer chip 300 in this figure includes: a first transformer 301, a second transformer 302, a third transformer 303, a fourth transformer 304, a first guard ring 305, a second guard ring 306, pads a1~a8, pads b1~b8, pads c1~c4, and pads d1~d4.

[0158] In the transformer chip 300, pads a1 and b1 are connected to one end of the secondary side coil L1s forming the first transformer 301, and pads c1 and d1 are connected to the other end of the secondary side coil L1s. Pads a2 and b2 are connected to one end of the secondary side coil L2s forming the second transformer 302, and pads c1 and d1 are connected to the other end of the secondary side coil L2s.

[0159] Additionally, pads a3 and b3 are connected to one end of the secondary coil L3s forming the third transformer 303, and pads c2 and d2 are connected to the other end of the secondary coil L3s. Pads a4 and b4 are connected to one end of the secondary coil L4s forming the fourth transformer 304, and pads c2 and d2 are connected to the other end of the secondary coil L4s.

[0160] Furthermore, the primary coils forming the first transformer 301, the second transformer 302, the third transformer 303, and the fourth transformer 304 are not explicitly shown in [the diagram / description]. Figure 9 However, the primary coils have essentially the same structure as the secondary coils L1s to L4s, and are arranged directly below each of the secondary coils L1s to L4s in a manner that is opposite to them.

[0161] That is, pads a5 and b5 are connected to one end of the primary coil forming the first transformer 301, and pads c3 and d3 are connected to the other end of the primary coil. In addition, pads a6 and b6 are connected to one end of the primary coil forming the second transformer 302, and pads c3 and d3 are connected to the other end of the primary coil.

[0162] Additionally, pads a7 and b7 are connected to one end of the primary winding of the third transformer 303, and pads c4 and d4 are connected to the other end of the primary winding. Similarly, pads a8 and b8 are connected to one end of the primary winding of the fourth transformer 304, and pads c4 and d4 are connected to the other end of the primary winding.

[0163] However, the aforementioned pads a5~a8, pads b5~b8, pads c3 and c4, and pads d3 and d4 are led out from the interior of the transformer chip 300 to the surface via through holes not shown.

[0164] Of the aforementioned pads, pads a1 to a8 correspond to the first current supply pads, and pads b1 to b8 correspond to the first voltage measurement pads. Additionally, pads c1 to c4 correspond to the second current supply pads, and pads d1 to d4 correspond to the second voltage measurement pads.

[0165] Therefore, in the case of the transformer chip 300 of this structural example, the series resistance of each coil can be accurately measured during defect inspection. Thus, not only can defective products with open circuits in each coil be rejected, but defective products with abnormal resistance values ​​in each coil (e.g., short circuits between coils) can also be appropriately rejected, thereby preventing defective products from entering the market.

[0166] Furthermore, for the transformer chip 300 that has passed the aforementioned defective product inspection, the aforementioned multiple pads can be used as connection units with the primary-side chip and the secondary-side chip (such as the previously mentioned controller chip 210 and driver chip 220).

[0167] Specifically, pads a1 and b1, pads a2 and b2, pads a3 and b3, and pads a4 and b4 can be connected to the signal input or signal output terminals of the secondary-side chip, respectively. In addition, pads c1 and d1, and pads c2 and d2 can be connected to the common voltage application terminal (GND2) of the secondary-side chip, respectively.

[0168] On the other hand, pads a5 and b5, pads a6 and b6, pads a7 and b7, and pads a8 and b8 can be connected to the signal input or signal output terminals of the primary-side chip, respectively. In addition, pads c3 and d3, and pads c4 and d4 can be connected to the common voltage application terminal (GND1) of the primary-side chip, respectively.

[0169] Here, as Figure 9 As shown, the first transformer 301 to the fourth transformer 304 are coupled together according to their respective signal transmission directions. Referring to this figure, for example, the first transformer 301 and the second transformer 302, which transmit signals from the primary side chip to the secondary side chip, form a first pair via the first guard ring 305. Furthermore, for example, the third transformer 303 and the fourth transformer 304, which transmit signals from the secondary side chip to the primary side chip, form a second pair via the second guard ring 306.

[0170] The reason for this coupling is to ensure a withstand voltage between the primary and secondary coils when the primary and secondary coils of the first transformer 301 to the fourth transformer 304 are stacked in a vertical configuration on the substrate of the transformer chip 300. However, the first guard ring 305 and the second guard ring 306 are not necessarily essential components.

[0171] In addition, the first protection ring 305 and the second protection ring 306 can be connected to low-impedance wiring such as the grounding terminal via pads e1 and e2, respectively.

[0172] Furthermore, in the transformer chip 300, pads c1 and d1 are shared between secondary-side coils L1s and L2s. Pads c2 and d2 are shared between secondary-side coils L3s and L4s. Pads c3 and d3 are shared between primary-side coils L1p and L2p. Pads c4 and d4 are shared with their respective primary-side coils. By adopting this structure, the number of pads can be reduced, enabling miniaturization of the transformer chip 300.

[0173] In addition, such as Figure 9 As shown, the primary and secondary coils of the first transformer 301 to the fourth transformer 304 are preferably wound in a rectangular shape (or a track-like shape with rounded corners) in the top view of the transformer chip 300. By arranging it in this way, the area of ​​the overlapping parts of the primary and secondary coils is increased, which can improve the transmission efficiency of the transformer.

[0174] Of course, the transformer arrangement in this diagram is just one example; the number, shape, and arrangement of the coils, as well as the arrangement of the pads, are arbitrary. Furthermore, the chip structure and transformer arrangement described so far can be applied to all semiconductor devices that integrate coils onto a semiconductor chip.

[0175] <Signal Transmission Device (First Implementation Scheme)>

[0176] Figure 10 This diagram illustrates a signal transmission device according to the first embodiment (corresponding to a comparative example of the second embodiment described later). The signal transmission device 400 according to this embodiment can be integrated into electronic device A along with a microcontroller, load, etc. The signal transmission device 400 includes a first chip 410, a second chip 420, and a third chip 430. The first chip 410, the second chip 420, and the third chip 430 can be sealed in a single package.

[0177] Similar to the previously described signal transmission device 200 ( Figure 1 The signal transmission device 400 may be a semiconductor integrated circuit device (commonly referred to as an insulated gate driver IC) that drives a switching device by generating an output pulse signal OUT based on an input pulse signal IN while isolating between the input and output.

[0178] In this case, the first chip 410 corresponds to the previously mentioned controller chip 210; the second chip 420 corresponds to the previously mentioned driver chip 220; and the third chip 430 corresponds to the previously mentioned transformer chip 230.

[0179] In addition to the main function of isolated communication (IN to OUT) not shown, the signal transmission device 400 may also have the function of setting parameters of the second chip 420 from the first chip 410. As shown in the figure, the signal transmission device 400 includes a transmitting circuit 411, a receiving circuit 421, and an isolation element 431 as functional blocks related to the parameter setting function just mentioned.

[0180] The transmitting circuit 411 is integrated into the first chip 410. The transmitting circuit 411 includes, for example, an input terminal 411x, a digital interface circuit 411y, and a pulse signal generation circuit 411z.

[0181] Input terminal 411x receives the digital signal DIN. The digital signal DIN can be a single-bit (0 or 1) logic signal. The digital signal DIN can conform to a predetermined communication protocol (e.g., I...). 2 Serial communication signals (C [Internal Integrated Circuit]) or SPI [Serial Peripheral Interface]).

[0182] The digital interface circuit 411y receives the digital signal DIN from the input terminal 411x, subjects it to given signal processing (such as waveform shaping or decoding), and then outputs the result to the pulse signal generation circuit 411z.

[0183] The pulse signal generation circuit 411z receives the digital signal DIN from the digital interface circuit 411y and generates the pulse signal PS based on the digital signal DIN.

[0184] The receiving circuit 421 is integrated into the second chip 420. The receiving circuit 421 sets the operating parameters of the second chip 420 based on the pulse signal PS transmitted from the transmitting circuit 411 via the isolation element 431. The operating parameters may be, for example, the switching rate of the output pulse signal OUT or the detection threshold or release threshold of any of the various protection functions.

[0185] Isolation element 431 is integrated into third chip 430. Isolation element 431 transmits the pulse signal PS between transmitting circuit 411 and receiving circuit 421 while providing isolation between them. Isolation element 431 can be a transformer or a capacitor.

[0186] Using the parameter setting function described above, the operating parameters of the second chip 420 can be set according to the digital signal DIN input to the first chip 410.

[0187] Note that when the digital signal DIN is a single-bit logic signal, only a binary setting value (0 or 1) can be set for a single input terminal 411x. Multiple input terminals 411x are required when transmitting operating parameters that can use ternary or higher parity values.

[0188] In addition, when the digital signal DIN is a serial communication signal conforming to a predetermined communication protocol, the digital interface circuit 411y has a larger circuit scale.

[0189] In view of these considerations, a second embodiment will be presented below, which allows the settings on the receiving side to be freely changed from the sending side without increasing the number of terminals or the circuit area.

[0190] <Signal Transmission Device (Second Embodiment)>

[0191] Figure 11 is a diagram showing a signal transmission device according to the second embodiment. The signal transmission device 400 according to this embodiment is based on the previously described first embodiment ( Figure 10 ), but has a transmission circuit 411 with a modified configuration. As shown in the figure, the transmission circuit 411 includes an input terminal 411a, a comparison circuit 411b, and a pulse signal generation circuit 411c.

[0192] The input terminal 411a receives the analog signal AIN.

[0193] The comparison circuit 411b compares the analog signal AIN with each of a plurality of threshold voltages Vth1 to VthN, and generates a plurality of comparison signals S1 to SN, where N is an integer of 2 or greater, and Vth1 < Vth2 <... < VthN.

[0194] As shown in the figure, the comparison circuit 411b includes a plurality of comparators 411b1 to 411bN that receive the analog signal AIN. The first input terminal (e.g., non-inverting input terminal) of the comparator 411bi (where i = 1, 2,..., N) is fed the analog signal AIN. The second input terminal (e.g., inverting input terminal) of the comparator 411bi is fed the threshold voltage Vthi. The comparison signal Si is, for example, at a high level when AIN ≥ Vthi, and at a low level when AIN < Vthi.

[0195] The pulse signal generation circuit 411c generates a pulse signal PS having different patterns corresponding to the plurality of comparison signals S1 to SN (details will be given later).

[0196] With the signal transmission device 400 according to this embodiment, by adjusting the signal value of the analog signal AIN, (N + 1) setting values can be set for one input terminal 411a. This allows operation parameters that can take ternary or higher - ary set values to be transmitted from the first chip 410 to the second chip 420 without unduly increasing the number of terminals or the circuit scale.

[0197] <Pulse Signal Generation Operation (First Example)>

[0198] Figure 12 This is a diagram showing a first example of the pulse signal generation operation. This diagram depicts the analog signal AIN, the comparison signals S1 and S2, and the pulse signal PS from top to bottom. That is, this diagram shows the pulse signal generation operation performed when N = 2.

[0199] When AIN < Vth1, S1 = S2 = L (low level). In this state, the pulse signal generation circuit 411c sets the number of pulses n in the pulse signal PS to "n1". In terms of what is shown in the diagram, the pulse signal generation circuit 411c generates n1 pulses (e.g., one pulse) at each pulse drive time that occurs during the pulse period T.

[0200] When Vth1 ≤ AIN < Vth2, S1 = H (high level) and S2 = L (low level). In this state, the pulse signal generation circuit 411c sets the number of pulses n in the pulse signal PS to "n2" (e.g., n2 > n1). In terms of what is shown in the diagram, the pulse signal generation circuit 411c generates n2 pulses (e.g., three pulses) at each pulse drive time that occurs during the pulse period T.

[0201] When Vth2 ≤ AIN, S1 = S2 = H (high level). In this state, the pulse signal generation circuit 411c sets the number of pulses n in the pulse signal PS to "n3" (e.g., n3 > n2). In terms of what is shown in the diagram, the pulse signal generation circuit 411c generates n3 pulses (e.g., five pulses) at each pulse drive time that occurs during the pulse period T.

[0202] In this way, the pulse signal generation circuit 411c switches the number of pulses n in the pulse signal PS among three values according to the multiple comparison signals S`1 and S2.

[0203] The receiving circuit 421 sets the operation parameters of the second chip 420 according to the number of pulses n in the pulse signal PS transmitted from the transmitting circuit 411 via the isolation element 431. That is, the operation parameters of the second chip 420 are switched among three set values according to the number of pulses n in the pulse signal PS.

[0204] <Pulse Signal Generation Operation (Second Example)>

[0205] Figure 13 This is a diagram showing a second example of the pulse signal generation operation. This diagram depicts the analog signal AIN, the comparison signals S1 and S2, and the pulse signal PS from top to bottom, as Figure 12 shown. That is, this diagram also shows the pulse signal generation operation performed when N = 2.

[0206] When AIN < Vth1, S1 = S2 = L (low level). In this state, the pulse signal generation circuit 411c sets the pulse period T of the pulse signal PS to "T1".

[0207] When Vth1 ≤ AIN < Vth2, S1 = H (high level) and S2 = L (low level). In this state, the pulse signal generation circuit 411c sets the pulse period T of the pulse signal PS to "T2" (for example, T2 < T1).

[0208] When Vth2 ≤ AIN, S1 = S2 = H (high level). In this state, the pulse signal generation circuit 411c sets the pulse period T of the pulse signal PS to "T3" (for example, T3 < T2).

[0209] In this way, the pulse signal generation circuit 411c switches the pulse period T of the pulse signal PS among three values according to the multiple comparison signals S1 and S2.

[0210] The receiving circuit 421 sets the operation parameters of the second chip 420 according to the pulse period T of the pulse signal PS transmitted from the transmitting circuit 411 via the isolation element 431. That is, the operation parameters of the second chip 420 are switched to the set points among the three values according to the pulse period T of the pulse signal PS.

[0211] <Pulse Signal Generation Operation (Third Example)>

[0212] Figure 14 is a diagram showing a third example of the pulse signal generation operation. Similar to the previously mentioned Figure 12 and Figure 13 This diagram depicts the analog signal AIN, the comparison signals S1 and S2, and the pulse signal PS from top to bottom. That is, this diagram also shows the pulse signal generation operation performed when N = 2.

[0213] When AIN < Vth1, S1 = S2 = L (low level). In this state, the pulse signal generation circuit 411c sets the conduction duty cycle d of the pulse signal PS to "d1". The conduction duty cycle d is calculated as the ratio of the conduction period Ton in the pulse period T (Ton / T). As shown in the figure, when the pulse period T is set to a fixed value, the pulse signal generation circuit 411c sets the conduction period Ton of the pulse signal PS to "Ton1".

[0214] When Vth1 ≤ AIN < Vth2, S1 = H (high level) and S2 = L (low level). In this state, the pulse signal generation circuit 411c sets the conduction duty ratio d of the pulse signal PS to d2 (for example, d2 > d1). As shown in the figure, when the pulse period T is set to a fixed value, the pulse signal generation circuit 411c sets the conduction period Ton of the pulse signal PS to "Ton2" (for example, Ton2 > Ton1).

[0215] When Vth2 ≤ AIN, S1 = S2 = H (high level). In this state, the pulse signal generation circuit 411c sets the conduction duty ratio d of the pulse signal PS to "d3" (for example, d3 > d2). As shown in the figure, when the pulse period T is set to a fixed value, the pulse signal generation circuit 411c sets the conduction period Ton of the pulse signal PS to "Ton3" (for example, Ton3 > Ton2).

[0216] In this way, the pulse signal generation circuit 411c switches the conduction duty ratio d of the pulse signal PS among three values according to the multiple comparison signals S1 and S2.

[0217] The receiving circuit 421 sets the operation parameters of the second chip 420 according to the conduction duty ratio d of the pulse signal PS transmitted from the transmitting circuit 411 via the isolation element 431. That is, the operation parameters of the second chip 420 are switched to the set points among the three values according to the conduction duty ratio d of the pulse signal PS.

[0218] <Applied to vehicles>

[0219] Figure 15 It is a diagram showing the appearance of a vehicle. The vehicle B of this configuration example incorporates various electronic devices that operate using the power supplied from a battery.

[0220] The vehicle B can be an engine vehicle or an electric vehicle (xEV, such as a BEV [battery electric vehicle], HEV [hybrid electric vehicle], PHEV / PHV [plug-in hybrid electric vehicle / plug-in hybrid vehicle], or FCEV / FCV [fuel cell electric vehicle / fuel cell vehicle]).

[0221] Here, the previously described signal transmission device 200 or 400 can be built in any of the electronic devices incorporated in the vehicle B.

[0222] <Overview>

[0223] The following is an overview of the above various embodiments.

[0224] For example, according to one aspect of this disclosure, a signal transmission device includes a transmitting circuit, a receiving circuit, and an isolation element configured to transmit a pulse signal between the transmitting circuit and the receiving circuit while simultaneously providing isolation between the transmitting circuit and the receiving circuit. The transmitting circuit includes: an input terminal configured to receive an analog signal; a comparison circuit configured to compare the analog signal with each of a plurality of thresholds to generate a plurality of comparison signals; and a pulse signal generation circuit configured to generate a pulse signal based on the plurality of comparison signals (first configuration).

[0225] In the signal transmission device according to the first configuration described above, the comparison circuit may include a plurality of comparators (second configuration) that receive analog signals.

[0226] In the signal transmission device according to the first or second configuration described above, the pulse signal generation circuit can switch the number of pulses in the pulse signal according to multiple comparison signals (third configuration).

[0227] In the signal transmission device according to the first or second configuration described above, the pulse signal generation circuit can switch the pulse period of the pulse signal according to multiple comparison signals (fourth configuration).

[0228] In the signal transmission device according to the first or second configuration described above, the pulse signal generation circuit can switch the duty cycle of the pulse signal according to multiple comparison signals (fifth configuration).

[0229] In the signal transmission device according to any of the first to fifth configurations described above, the isolation element may be a transformer or a capacitor (sixth configuration).

[0230] The signal transmission device according to any of the first to sixth configurations described above may further include a first chip in which a transmitting circuit is integrated, a second chip in which a receiving circuit is integrated, and a third chip in which an isolation element is integrated. The first, second, and third chips may be sealed in a single package (seventh configuration).

[0231] In the signal transmission device according to the seventh configuration described above, the receiving circuit can set the operating parameters of the second chip (eighth configuration) based on the pulse signal transmitted from the transmitting circuit via the isolation element.

[0232] For example, according to another aspect of this disclosure, an electronic device includes a signal transmission device (ninth configuration) according to any one of the first to eighth configurations described above.

[0233] For example, according to another aspect of this disclosure, a vehicle includes electronic equipment according to a ninth configuration (tenth configuration).

[0234] Using the signal transmission device according to this disclosure, the settings of the receiving side can be freely changed from the transmitting side without increasing the number of terminals or the circuit area.

[0235] <Note>

[0236] The various technical features disclosed in this specification can be implemented in any manner other than those specifically described above, and various modifications are permitted without departing from the spirit of its technical ingenuity. That is, the above embodiments should be considered illustrative rather than restrictive in every respect. The scope of this disclosure should be understood as defined by the appended claims and includes any variations within the scope equivalent to those claims.

[0237] Symbol Explanation

[0238] 5 Semiconductor Devices

[0239] 11, 11A~11F Low-potential terminals

[0240] 12, 12A~12F High-potential terminals

[0241] 21. Transformers 21A~21D

[0242] 22 Low-potential coil (primary side coil)

[0243] 23 High-potential coil (secondary coil)

[0244] 24 First inner end

[0245] 25 First lateral end

[0246] 26 First spiral section

[0247] 27 Second inner end

[0248] 28 Second lateral end

[0249] 29 Second spiral section

[0250] 31 First low-potential wiring

[0251] 32 Second Low Potential Wiring

[0252] 33 First High-Potential Wiring

[0253] 34 Second High Potential Wiring

[0254] 41 Semiconductor Chips

[0255] 42 First Main Face

[0256] 43 Second Main Face

[0257] 44A~44D chip sidewall

[0258] 45 First functional device

[0259] 51 Insulation layer

[0260] 52 Insulation Main Surface

[0261] 53A~53D Insulating sidewalls

[0262] 55 Bottom insulation layer

[0263] 56. Topmost insulating layer

[0264] 57 interlayer insulation

[0265] 58 First Insulation Layer

[0266] 59 Second Insulation Layer

[0267] 60 Secondary functional devices

[0268] 61 Sealed conductor

[0269] 62 Device Area

[0270] 63 Outer region

[0271] 64 Sealed plug conductor

[0272] 65 Sealed through-hole conductor

[0273] 66 First inner region

[0274] 67 Second inner region

[0275] 71 Through-wiring

[0276] 72 Low-potential connection wiring

[0277] 73 Lead-out wiring

[0278] 74 First connecting plug electrode

[0279] 75 Second connecting plug electrode

[0280] 76 Pad Plug Electrode

[0281] 77 Substrate plug electrode

[0282] 78 First Electrode Layer

[0283] 79 Second electrode layer

[0284] 80 Wiring plug electrode

[0285] 81 High-potential connection wiring

[0286] 82 Pad Plug Electrode

[0287] 85. Dummy Pattern

[0288] 86 High-potential dummy pattern

[0289] 87 First High Potential Dummy Pattern

[0290] 88 Second High Potential Dummy Pattern

[0291] 89 First District

[0292] 90 Second Zone

[0293] 91 Third Region

[0294] 92 First connecting part

[0295] 93 First Pattern

[0296] 94 Second Pattern

[0297] 95 Third Pattern

[0298] 96 First outer weekly line

[0299] 97 Second outer weekly line

[0300] 98 First median line

[0301] 99 First connecting line

[0302] 100 slits

[0303] 130 Separation Structure

[0304] 140 Inorganic Insulation Layer

[0305] 141 First Inorganic Insulation Layer

[0306] 142 Second Inorganic Insulation Layer

[0307] 143 Low-potential pad opening

[0308] 144 High-potential pad opening

[0309] 145 Organic Insulation Layer

[0310] 146 Part One

[0311] 147 Part Two

[0312] 148 Low-potential terminal opening

[0313] 149 High-potential terminal opening

[0314] 200 Signal Transmission Device

[0315] 200p primary circuit system

[0316] 200s secondary circuit system

[0317] 210 Controller Chip (First Chip)

[0318] 211 Pulse Transmission Circuit (Pulse Generator)

[0319] Buffers 212 and 213

[0320] 220 Driver Chip (Second Chip)

[0321] Buffers 221 and 222

[0322] 223 Pulse Receiving Circuit (RS Flip-Flop)

[0323] 224 drives

[0324] 230 Transformer Chip (Third Chip)

[0325] 230a First wiring layer (lower layer)

[0326] 230b Second wiring layer (upper layer)

[0327] Transformers 231 and 232

[0328] 231p, 232p primary side coil

[0329] 231s, 232s secondary coils

[0330] 300 Transformer Chip

[0331] 301 First Transformer

[0332] 302 Second Transformer

[0333] 303 Third Transformer

[0334] 304 Fourth Transformer

[0335] 305 First Protection Ring

[0336] 306 Second Protective Ring

[0337] 400 Signal Transmission Device

[0338] 410 First Chip

[0339] 411 Transmitting Circuit

[0340] 411a Input Terminal

[0341] 411b Comparator Circuit

[0342] 411b1 to 411bN comparators

[0343] 411c Pulse Signal Generation Circuit

[0344] 411x Input Terminals

[0345] 411y Digital Interface Circuit

[0346] 411z Pulse Signal Generation Circuit

[0347] 420 Second Chip

[0348] 421 Receiver Circuit

[0349] 430 Third Chip

[0350] 431 Isolation Element

[0351] pads a1~a8 (equivalent to pads for the first current supply)

[0352] pads b1~b8 (equivalent to pads used for the first voltage measurement)

[0353] C1~C4 pads (equivalent to pads for the second current supply)

[0354] d1~d4 pads (equivalent to the pads used for second voltage measurement)

[0355] e1, e2 pads

[0356] A electronic device

[0357] Vehicle B

[0358] L1p, L2p primary side coils

[0359] L1s, L2s, L3s, L4s secondary coils

[0360] Resistors R0, R1, R2, R3, R4, R5

[0361] T21, T22, T23, T24, T25, T26 external terminals

[0362] X First Direction

[0363] X21, X22, X23 internal terminals

[0364] Y Second Direction

[0365] Y21, Y22, Y23 wiring

[0366] Z-normal direction

[0367] Through holes Z21, Z22, and Z23.

Claims

1. A signal transmission device, comprising: Transmitting circuit; Receiver circuit; as well as An isolation element is configured to transmit a pulse signal between the transmitting circuit and the receiving circuit while simultaneously providing isolation between them. The transmitting circuit includes: The input terminal is configured to receive analog signals; A comparison circuit is configured to compare the analog signal with each of a plurality of thresholds to generate a plurality of comparison signals; and A pulse signal generation circuit is configured to generate the pulse signal based on the plurality of comparison signals.

2. The signal transmission device according to claim 1, wherein... The comparison circuit includes multiple comparators for receiving the analog signal.

3. The signal transmission device according to claim 1 or 2, wherein... The pulse signal generation circuit switches the number of pulses in the pulse signal according to the plurality of comparison signals.

4. The signal transmission device according to claim 1 or 2, wherein The pulse signal generation circuit switches the pulse period of the pulse signal according to the plurality of comparison signals.

5. The signal transmission device according to claim 1 or 2, wherein... The pulse signal generation circuit switches the duty cycle of the pulse signal according to the plurality of comparison signals.

6. The signal transmission device according to any one of claims 1 to 5, wherein The isolation element is a transformer or a capacitor.

7. The signal transmission device according to any one of claims 1 to 6, further comprising: The first chip, wherein the transmitting circuit is integrated into the first chip; The receiving circuit is integrated into the second chip; as well as The third chip, in which the isolation element is integrated. The first chip, the second chip, and the third chip are sealed in a single package.

8. The signal transmission device according to claim 7, wherein The receiving circuit sets the operating parameters of the second chip based on the pulse signal transmitted from the transmitting circuit via the isolation element.

9. An electronic device comprising a signal transmission device according to any one of claims 1 to 8.

10. A vehicle comprising the electronic device according to claim 9.

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