Storage circuit, processing device and electronic equipment

Abstract

Provided is a memory circuit having a reduced circuit area. The memory circuit includes first to third layers, the first layer including a first transistor and a second transistor, the second layer including a third transistor and a fourth transistor, and the third layer including a fifth transistor and a sixth transistor. In addition, the first transistor, the third transistor, and the fifth transistor overlap each other, and the second transistor, the fourth transistor, and the sixth transistor overlap each other. In addition, the first terminal of the fifth transistor is electrically connected to the gate of the third transistor, the first terminal of the fourth transistor, and the first terminal of the first transistor, and the first terminal of the sixth transistor is electrically connected to the gate of the fourth transistor, the first terminal of the third transistor, and the first terminal of the second transistor.

Description

Technical Field

[0001] One aspect of the present invention relates to a storage circuit, a processing device, and an electronic device.

[0002] Note that one aspect of the present invention is not limited to the aforementioned technical fields. The technical fields of the invention disclosed in this specification relate to an object, a method of operation, or a method of manufacturing. Furthermore, one aspect of the present invention relates to a process, a machine, a product, or a composition of matter. Therefore, specifically, examples of the technical fields of one aspect of the present invention disclosed in this specification include semiconductor devices, display devices (including liquid crystal display devices), light-emitting devices, energy storage devices, imaging devices, storage devices, processing devices, signal processing devices, sensors, arithmetic devices (including processors), electronic devices, systems, methods of driving them, methods of manufacturing them, or methods of inspecting them. Background Technology

[0003] In recent years, with the increase in the amount of data used, there is a need for storage devices with larger storage capacities. To increase the recording capacity per unit area, a structure in which multiple storage cells are stacked above the drive circuit is effective (Patent Document 1). By stacking storage cells, the recording capacity per unit area can be increased accordingly with the number of stacked storage cells.

[0004] Another example of a storage device is the cache memory included in a CPU (Central Processing Unit). For example, Non-Patent Document 1 discloses an SRAM (Static Random Access Memory) used in the cache memory of a CPU, employing transistors of indium gallium zinc oxide, which is an oxide semiconductor.

[0005] [Preliminary Technology Documents]

[0006] [Patent Literature]

[0007] [Patent Document 1] International Patent Application Publication No. 2022 / 238798

[0008] [Non-patent literature]

[0009] [Non-Patent Literature 1] S. Yamazaki and M. Fujita, “Physics and Technology of Crystalline Oxide Semiconductor CAAC-IGZO: Application to LSI”, Wiley-SID Series in Display Technology, 2016, pp.181-192 (USA). Summary of the Invention

[0010] The technical problem that the invention aims to solve

[0011] Generally, the memory circuitry (sometimes called memory cells) included in SRAM latches data through an inverter loop comprising two inverters. Since an inverter includes at least an n-channel transistor and a p-channel transistor, at least four transistors are required to form the inverter loop. Additionally, when latching complementary data in this memory circuitry, two selection transistors are needed to receive select or non-select signals. Therefore, the memory circuitry included in SRAM comprises a total of six transistors, making it easy to increase the circuit area of ​​the memory circuitry. In particular, with the anticipated miniaturization of electronic devices such as CPUs in recent years, the miniaturization of memory circuitry is being researched.

[0012] Furthermore, as memory circuits are miniaturized, the parasitic capacitance between wirings tends to increase due to smaller process nodes, sometimes resulting in a lower drive frequency. In particular, SRAM, including in CPUs, requires high drive frequencies, so it is important to design circuits in a way that prevents the increase of parasitic capacitance when considering memory circuit miniaturization.

[0013] One objective of this invention is to provide a memory circuit with a reduced circuit area. Another objective is to provide a memory circuit with low parasitic capacitance. Another objective is to provide a memory circuit with a high drive frequency. Another objective is to provide a memory device including the above-described memory circuit. Another objective is to provide an electronic device including the above-described memory device. Finally, another objective is to provide a novel memory circuit, a novel memory device, or a novel electronic device.

[0014] Note that the purpose of one aspect of the present invention is not limited to the objectives described above. The above objectives do not preclude the existence of other objectives. Furthermore, other objectives are those not mentioned above but will be described in the following description. Those skilled in the art can derive and appropriately extract objectives not mentioned above from the description, drawings, etc. Moreover, one aspect of the present invention achieves at least one of the above and other objectives. Therefore, one aspect of the present invention does not need to achieve all of the above and other objectives.

[0015] means of solving technical problems

[0016] One aspect of the present invention is a memory circuit for the purposes described above, the memory circuit comprising: a first layer including a first transistor and a second transistor as Si transistors (transistors containing silicon in the channel formation region); a second layer including a third transistor and a fourth transistor as OS transistors (transistors containing oxide semiconductors in the channel formation region); and a third layer including a fifth transistor and a sixth transistor as OS transistors.

[0017] When viewed from above, the semiconductor layer of the third transistor has a region overlapping with the first semiconductor region included in the first transistor, and the semiconductor layer of the fifth transistor has a region overlapping with the semiconductor layer of the third transistor. Similarly, the semiconductor layer of the fourth transistor has a region overlapping with the second semiconductor region included in the second transistor, and the semiconductor layer of the sixth transistor has a region overlapping with the semiconductor layer of the fourth transistor.

[0018] In addition, the third to sixth transistors are all vertical transistors (transistors in which at least a portion of the semiconductor layer having a channel forming region is disposed inside an opening formed in an insulating layer and the channel length direction has a height component).

[0019] Additionally, the first and fourth transistors are included in the first inverter, and the second and third transistors are included in the second inverter. The fifth and sixth transistors are selection transistors for the memory circuit.

[0020] The following describes a typical structural example of one aspect of the present invention. (1)

[0022] One aspect of the present invention is a memory circuit comprising a first layer, a second layer on the first layer, and a third layer on the second layer. The first layer includes a first low-resistance region, a second low-resistance region, a third low-resistance region, a first semiconductor region, a second semiconductor region, a first conductive layer, a second conductive layer, a third conductive layer, a fourth conductive layer, a fifth conductive layer, and a sixth conductive layer. The second layer includes a first insulating layer, a second insulating layer, a seventh conductive layer, an eighth conductive layer, a ninth conductive layer, a tenth conductive layer, an eleventh conductive layer, a twelfth conductive layer, a thirteenth conductive layer, a fourteenth conductive layer, a fifteenth conductive layer, a first semiconductor layer, and a second semiconductor layer. The third layer includes a sixteenth conductive layer and a seventeenth conductive layer.

[0023] In cross-section, the first semiconductor region is located between the first low-resistance region and the second low-resistance region, and the second semiconductor region is located between the second low-resistance region and the third low-resistance region. Additionally, the first conductive layer has a region overlapping with the first semiconductor region and a first region extending in a first direction, and the second conductive layer has a region overlapping with the second semiconductor region and a second region extending in a second direction. In top view, the first direction is one of the directions to the right and left when viewing the second semiconductor region from the first semiconductor region; in top view, the second direction is the other of the directions to the right and left when viewing the second semiconductor region from the first semiconductor region. The third conductive layer is located on the top surface of the first low-resistance region, the fourth conductive layer is located on the top surface of the first region, the fifth conductive layer is located on the top surface of the second region, and the sixth conductive layer is located on the top surface of the second low-resistance region. Furthermore, the seventh conductive layer is conductive to the third conductive layer, the eighth conductive layer is conductive to the fourth conductive layer through the eleventh conductive layer, the ninth conductive layer is conductive to the fifth conductive layer through the fourteenth conductive layer, and the tenth conductive layer is conductive to the sixth conductive layer.

[0024] Furthermore, the twelfth conductive layer has a third region overlapping the eleventh conductive layer across the first insulating layer and a fourth region overlapping the fourteenth conductive layer. The first insulating layer has a first opening in the third region and a second opening in the fourth region. Additionally, the first semiconductor layer has a region contacting the twelfth conductive layer in the third region, the eleventh conductive layer located at the bottom of the first opening, and the first insulating layer located on the side of the first opening. The second semiconductor layer has a region contacting the twelfth conductive layer in the fourth region, the fourteenth conductive layer located at the bottom of the second opening, and the first insulating layer located on the side of the second opening. The second insulating layer is located on the top surface of the first insulating layer, the top surface of the twelfth conductive layer, the top surface of the first semiconductor layer, and the top surface of the second semiconductor layer. Furthermore, the thirteenth conductive layer is located on the top surface of the second insulating layer in the region overlapping with the first semiconductor layer, and the fifteenth conductive layer is located on the top surface of the second insulating layer in the region overlapping with the second semiconductor layer.

[0025] In addition, the sixteenth conductive layer is connected to the seventh, ninth and thirteenth conductive layers, and the seventeenth conductive layer is connected to the eighth, tenth and fifteenth conductive layers.

[0026] When viewed from above, the first semiconductor layer has a region that overlaps with the first semiconductor region, and the second semiconductor layer has a region that overlaps with the second semiconductor region. (2)

[0028] In the above (1), one aspect of the present invention may also have the following structure: the third layer includes a third insulating layer, a fourth insulating layer, an eighteenth conductive layer, a nineteenth conductive layer, a twentieth conductive layer, a twenty-first conductive layer, a twenty-second conductive layer, a third semiconductor layer, and a fourth semiconductor layer.

[0029] Preferably, the eighteenth conductive layer has a fifth region overlapping the sixteenth conductive layer with a third insulating layer in between, and the nineteenth conductive layer has a sixth region overlapping the seventeenth conductive layer with a third insulating layer in between. The third insulating layer has a third opening in the fifth region and a fourth opening in the sixth region. Furthermore, preferably, the third semiconductor layer has a region contacting the eighteenth conductive layer in the fifth region, the sixteenth conductive layer at the bottom of the third opening, and the third insulating layer at the side of the third opening. The fourth semiconductor layer has a region contacting the nineteenth conductive layer in the sixth region, the seventeenth conductive layer at the bottom of the fourth opening, and the third insulating layer at the side of the fourth opening. The fourth insulating layer is located on the top surface of the third insulating layer, the top surface of the eighteenth conductive layer, the top surface of the nineteenth conductive layer, the top surface of the third semiconductor layer, and the top surface of the fourth semiconductor layer. The twentieth conductive layer is located on the top surface of the fourth insulating layer in the region overlapping with the third semiconductor layer, and the twenty-first conductive layer is located on the top surface of the fourth insulating layer in the region overlapping with the fourth semiconductor layer. Additionally, the twenty-second conductive layer preferably has a region contacting the twentieth conductive layer and a region contacting the twenty-first conductive layer.

[0030] Preferably, when viewed from above, the third semiconductor layer has a region that overlaps with the first semiconductor region, and the fourth semiconductor layer has a region that overlaps with the second semiconductor region. (3)

[0032] In (2) above, one aspect of the present invention may also have the following structure: the first low resistance region has a seventh region extending in the second direction, and the third low resistance region has an eighth region extending in the first direction.

[0033] Particularly preferred is that the third conductive layer is located on the top surface of the seventh region, and the sixth conductive layer is located on the top surface of the eighth region. Furthermore, it is preferred that the seventh conductive layer has a region overlapping with the third conductive layer, the eighth conductive layer has a region overlapping with the fourth conductive layer, the ninth conductive layer has a region overlapping with the fifth conductive layer, and the tenth conductive layer has a region overlapping with the sixth conductive layer. (4)

[0035] In the above (3), one aspect of the present invention may also have the following structure: the first layer includes a first transistor and a second transistor, the second layer includes a third transistor and a fourth transistor, and the third layer includes a fifth transistor and a sixth transistor.

[0036] Particularly preferred is that a portion of the first low-resistance region is used as one of the source and drain of the first transistor, a portion of the second low-resistance region is used as the other of the source and drain of the first transistor, a region of the first conductive layer overlapping with the first semiconductor region is used as the gate of the first transistor, and the first semiconductor region has a channel forming region of the first transistor.

[0037] Additionally, preferably, a portion of the second low-resistance region is used as one of the source and drain of the second transistor, a portion of the third low-resistance region is used as the other of the source and drain of the second transistor, a region of the second conductive layer that overlaps with the second semiconductor region is used as the gate of the second transistor, and the second semiconductor region has a channel forming region of the second transistor.

[0038] Additionally, preferably, a portion of the eleventh conductive layer is used as one of the source and drain of the third transistor, the first region is used as the other of the source and drain of the third transistor, a portion of the thirteenth conductive layer is used as the gate of the third transistor, and the first semiconductor layer has a channel forming region for the third transistor.

[0039] Additionally, preferably, a portion of the fourteenth conductive layer is used as one of the source and drain of the fourth transistor, the second region is used as the other of the source and drain of the fourth transistor, a portion of the fifteenth conductive layer is used as the gate of the fourth transistor, and the second semiconductor layer has a channel forming region for the fourth transistor.

[0040] Additionally, preferably, a portion of the sixteenth conductive layer is used as one of the source and drain of the fifth transistor, the fifth region is used as the other of the source and drain of the fifth transistor, a portion of the twentieth conductive layer is used as the gate of the fifth transistor, and the third semiconductor layer has a channel forming region for the fifth transistor.

[0041] Additionally, preferably, a portion of the seventeenth conductive layer is used as one of the source and drain of the sixth transistor, the sixth region is used as the other of the source and drain of the sixth transistor, a portion of the twenty-first conductive layer is used as the gate of the sixth transistor, and the fourth semiconductor layer has a channel forming region for the sixth transistor.

[0042] Furthermore, the first transistor and the second transistor are each preferably p-channel transistors containing silicon in the channel formation region. Additionally, the third to sixth transistors are each preferably n-channel transistors containing oxide semiconductor in the channel formation region. (5)

[0044] In (4) above, one aspect of the present invention may also have the following structure: the oxide semiconductor comprises one or more selected from indium, zinc and element M.

[0045] Element M is selected from one or more of the following: aluminum, gallium, silicon, yttrium, tin, copper, vanadium, chromium, manganese, beryllium, boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, calcium, strontium, barium, cobalt, and antimony. (6)

[0047] One aspect of the present invention is a processing apparatus comprising the storage circuit and the driving circuit described in any one of (1) to (5) above. (7)

[0049] One aspect of the present invention is an electronic device comprising the processing apparatus described above (6) and a housing.

[0050] Invention Effects

[0051] When viewed from above, the semiconductor regions of the first transistor, the semiconductor layers of the third transistor, and the semiconductor layers of the fifth transistor overlap with each other, and the semiconductor regions of the second transistor, the semiconductor layers of the fourth transistor, and the semiconductor layers of the sixth transistor overlap with each other, which reduces the circuit area of ​​the memory circuit compared to existing memory circuits.

[0052] Furthermore, by employing vertically channeled transistors as the third to sixth transistors, the transistor formation area can be reduced compared to planar transistors. Additionally, by employing vertically channeled transistors as the third and fourth transistors, the on-state current of each of the third and fourth transistors can be increased.

[0053] Furthermore, by employing vertical channel transistors as the third and fourth transistors, as shown in (3) above, the third and seventh conductive layers can be stacked on top of each other in the seventh region of the first low-resistance region, and the sixth, tenth, fourth, and eighth conductive layers, and fifth and ninth conductive layers can be stacked on top of each other in the eighth region of the third low-resistance region. This extends the distance between conductive layers (wiring), thereby reducing parasitic capacitance. Therefore, the driving frequency of the memory circuit can be increased.

[0054] According to one aspect of the present invention, a memory circuit with reduced circuit area can be provided. Additionally, according to one aspect of the present invention, a memory circuit with low parasitic capacitance can be provided. Furthermore, according to one aspect of the present invention, a memory circuit with high drive frequency can be provided. Furthermore, according to one aspect of the present invention, a memory device including the above-described memory circuit can be provided. Furthermore, according to one aspect of the present invention, an electronic device including the above-described memory device can be provided. Additionally, according to one aspect of the present invention, a novel memory circuit, a novel memory device, or a novel electronic device can be provided.

[0055] Note that the effects of one aspect of the present invention are not limited to those described above. The described effects do not preclude the existence of other effects. Furthermore, other effects are those not mentioned above but will be described in the following description. Those skilled in the art can derive and appropriately extract effects not mentioned above from the description in the specification or drawings, etc. Moreover, one aspect of the present invention has at least one of the above-described effects and other effects. Therefore, one aspect of the present invention may sometimes not have the above-described effects.

[0056] Brief description of the attached figures

[0057] Figure 1 This is a cross-sectional schematic diagram showing an example of the structure of a storage circuit.

[0058] Figures 2A to 2C This is a circuit diagram illustrating an example of the structure of a storage circuit.

[0059] Figure 3 This is a three-dimensional schematic diagram showing an example of the structure of a storage circuit.

[0060] Figure 4A This is a cross-sectional schematic diagram illustrating an example of the structure of layers included in a storage circuit. Figure 4B This is a planar schematic diagram illustrating an example of the structure of layers included in a storage circuit.

[0061] Figure 5 This is a cross-sectional schematic diagram showing an example of the structure of the layers included in a storage circuit.

[0062] Figure 6AThis is a cross-sectional schematic diagram illustrating an example of the structure of layers included in a storage circuit. Figure 6B This is a planar schematic diagram illustrating an example of the structure of layers included in a storage circuit.

[0063] Figure 7A and Figure 7B This is a cross-sectional schematic diagram showing an example of the structure of the layers included in a storage circuit.

[0064] Figure 8A and Figure 8B This is a cross-sectional schematic diagram showing an example of the structure of the layers included in a storage circuit.

[0065] Figure 9A This is a cross-sectional schematic diagram illustrating an example of the structure of layers included in a storage circuit. Figure 9B This is a planar schematic diagram illustrating an example of the structure of layers included in a storage circuit.

[0066] Figure 10A and Figure 10B This is a cross-sectional schematic diagram showing an example of the structure of the layers included in a storage circuit.

[0067] Figure 11A This is a cross-sectional schematic diagram illustrating an example of the structure of layers included in a storage circuit. Figure 11B This is a planar schematic diagram illustrating an example of the structure of layers included in a storage circuit.

[0068] Figure 12A and Figure 12B This is a cross-sectional schematic diagram showing an example of the structure of the layers included in a storage circuit.

[0069] Figure 13 This is a three-dimensional schematic diagram showing an example of the structure of a storage circuit.

[0070] Figure 14 This is a cross-sectional schematic diagram showing an example of the structure of the layers included in a storage circuit.

[0071] Figure 15 This is a three-dimensional schematic diagram showing an example of the structure of a storage circuit.

[0072] Figure 16A This is a cross-sectional schematic diagram illustrating an example of the structure of layers included in a storage circuit. Figure 16B This is a planar schematic diagram illustrating an example of the structure of layers included in a storage circuit.

[0073] Figure 17 This is a cross-sectional schematic diagram showing an example of the structure of the layers included in a storage circuit.

[0074] Figure 18A This is a cross-sectional schematic diagram illustrating an example of the structure of layers included in a storage circuit. Figure 18BThis is a planar schematic diagram illustrating an example of the structure of layers included in a storage circuit.

[0075] Figure 19 This is a cross-sectional schematic diagram showing an example of the structure of the layers included in a storage circuit.

[0076] Figure 20 This is a cross-sectional schematic diagram showing an example of the structure of a storage circuit.

[0077] Figure 21 This is a three-dimensional schematic diagram showing an example of the structure of a storage circuit.

[0078] Figure 22A This is a cross-sectional schematic diagram illustrating an example of the structure of layers included in a storage circuit. Figure 22B This is a planar schematic diagram illustrating an example of the structure of layers included in a storage circuit.

[0079] Figure 23A This is a cross-sectional schematic diagram illustrating an example of the structure of layers included in a storage circuit. Figure 23B This is a planar schematic diagram illustrating an example of the structure of layers included in a storage circuit.

[0080] Figure 24A This is a cross-sectional schematic diagram illustrating an example of the structure of layers included in a storage circuit. Figure 24B This is a planar schematic diagram illustrating an example of the structure of layers included in a storage circuit.

[0081] Figure 25A and Figure 25B This is a cross-sectional schematic diagram showing an example of the structure of the layers included in a storage circuit.

[0082] Figure 26A This is a cross-sectional schematic diagram illustrating an example of the structure of layers included in a storage circuit. Figure 26B This is a planar schematic diagram illustrating an example of the structure of layers included in a storage circuit.

[0083] Figure 27A and Figure 27B This is a cross-sectional schematic diagram showing an example of the structure of the layers included in a storage circuit.

[0084] Figure 28 This is a cross-sectional schematic diagram showing an example of the structure of a storage circuit.

[0085] Figure 29A This is a perspective diagram illustrating an example of the structure of a storage device. Figure 29B This is a block diagram illustrating an example of the structure of a semiconductor device.

[0086] Figure 30 This is a circuit diagram illustrating an example of the structure of a storage device.

[0087] Figure 31This is a three-dimensional schematic diagram showing an example of the structure of the processing device.

[0088] Figure 32A and Figure 32B It is a diagram showing the hierarchy of various storage devices.

[0089] Figures 33A to 33D This is a diagram showing an example of an electronic component.

[0090] Figure 34A and Figure 34B This is a diagram illustrating an example of an electronic device. Figure 34C This is a diagram illustrating an example of a large computer.

[0091] Figure 35 This is a diagram illustrating an example of a space device.

[0092] Figure 36 This is a diagram illustrating an example of a secondary storage system that can be used in a data center.

[0093] Methods of implementing the invention

[0094] (Notes regarding this instruction manual)

[0095] In this specification, etc., a semiconductor device refers to a device that utilizes the properties of semiconductors, as well as circuits that include semiconductor elements (e.g., transistors, diodes, photodiodes) and devices that include such circuits. Furthermore, a semiconductor device refers to all devices capable of functioning by utilizing the properties of semiconductors. An integrated circuit can be cited as an example of a semiconductor device. Additionally, a chip having an integrated circuit and an electronic component containing the chip in a package can be cited as examples of semiconductor devices. Furthermore, for example, storage devices, display devices, light-emitting devices, arithmetic devices, lighting devices, and electronic devices are sometimes semiconductor devices themselves, or sometimes include semiconductor devices.

[0096] Furthermore, in this specification, when it is stated as "X and Y are connected," it indicates that the following situations are disclosed in this specification: X and Y are electrically connected; X and Y are functionally connected; and X and Y are directly connected. Therefore, the connection relationships are not limited to those shown in the drawings or text; other connection relationships are also within the scope of the drawings or text. X and Y are objects (e.g., devices, components, circuits, wiring, electrodes, terminals, conductive films, or layers).

[0097] As an example of an electrical connection between X and Y, more than one component capable of electrically connecting X and Y (such as a switch, transistor, inductor, resistor, diode, display device, light-emitting device, load, etc.) can be connected between X and Y. Furthermore, the switch has the function of controlling whether it is turned on or off. In other words, whether current flows is controlled by placing the switch in a conducting state (on state) or a non-conducting state (off state).

[0098] As an example of a functional connection between X and Y, one or more circuits capable of functionally connecting X and Y can be connected between X and Y (e.g., logic circuits (e.g., inverters, NAND circuits, and NOR circuits), signal conversion circuits (e.g., digital-to-analog converters, analog-to-digital converters, and gamma correction circuits), potential level conversion circuits (e.g., power supply circuits such as boost or buck circuits, and level shifting circuits that change the potential level of a signal), voltage sources, current sources, switching circuits, amplification circuits (e.g., circuits that increase signal amplitude or current, operational amplifiers, differential amplifiers, source follower circuits, and buffer circuits), signal generation circuits, storage circuits, and control circuits). Note that, for example, even if other circuits are sandwiched between X and Y, when the signal output from X is transmitted to Y, it can be said that X and Y are functionally connected.

[0099] Furthermore, when explicitly stated as "X and Y are electrically connected", it includes the following cases: X and Y are electrically connected (in other words, X and Y are connected in a way that includes other components or other circuits); and X and Y are directly connected (in other words, X and Y are connected in a way that does not include other components or other circuits).

[0100] Furthermore, it can be represented, for example, as "X, Y, the source of the transistor (e.g., sometimes referred to as one of the first and second terminals) and the drain of the transistor (e.g., sometimes referred to as the other of the first and second terminals) are electrically connected to each other, and X, the source of the transistor, the drain of the transistor, and Y are electrically connected in sequence." Alternatively, it can be represented as "the source of the transistor is electrically connected to X, the drain of the transistor is electrically connected to Y, and X, the source of the transistor, the drain of the transistor, and Y are electrically connected in sequence." Or, it can be represented as "X is electrically connected to Y through the source and drain of the transistor, and X, the source of the transistor, the drain of the transistor, and Y are sequentially connected to each other." By specifying the connection order in the circuit structure using the same representation as these examples, the source and drain of the transistor can be distinguished, thus determining the scope of the technology. Note that this representation is an example and is not limited to the above representations. Here, X and Y are objects (e.g., devices, components, circuits, wiring, electrodes, terminals, conductive films or layers, etc.).

[0101] Furthermore, even when independent components are electrically connected to each other in a circuit diagram, sometimes one component performs the function of multiple components. For example, when a portion of a wiring is used as an electrode, a conductive film serves as both a wiring and an electrode. Therefore, the scope of "electrical connection" in this specification also includes such cases where a conductive film performs the function of multiple components.

[0102] Generally, an example of a "resistor" can be a circuit element with a resistance value higher than 0Ω or a wiring with a resistance value higher than 0Ω. Therefore, the "resistor" described in this specification includes wiring, diodes, or coils with resistance values. Therefore, "resistor" can sometimes be referred to as "resistance," "load," or "area with a resistance value." Conversely, "resistance," "load," or "area with a resistance value" can sometimes be referred to as "resistor." As for the resistance value, it is preferably 1mΩ or more and 10Ω or less, more preferably 5mΩ or more and 5Ω or less, and even more preferably 10mΩ or more and 1Ω or less. Furthermore, it can also be 1Ω or more and 1×10⁻⁶. 9 Below Ω.

[0103] Generally speaking, examples of a "capacitor" include circuit elements with a capacitance value greater than 0F, wiring regions with a capacitance value greater than 0F, or the region between the gate or back gate and the source or drain in a transistor with a capacitance value greater than 0F. Furthermore, "capacitor" or "gate capacitance" is sometimes used interchangeably with "capacitor" or "gate capacitance".

[0104] Furthermore, a "capacitor" (including a "capacitor" with three or more terminals) comprises an insulator and a pair of conductors clamping the insulator. Thus, the "pair of conductors" in a "capacitor" can be referred to as a "pair of electrodes," a "pair of conductive regions," a "pair of regions," or a "pair of terminals." Additionally, "one of the terminals" and "the other of the terminals" are sometimes referred to as the first terminal and the second terminal, respectively. Furthermore, the electrostatic capacitance value can, for example, be 0.05 fF or more and 10 pF or less. Alternatively, it can be, for example, 1 pF or more and 10 μF or less.

[0105] In this specification, a transistor includes three terminals: a gate, a source, and a drain. The gate is used as a control terminal to control the conduction state of the transistor. The two terminals used as the source or drain are the input and output terminals of the transistor. Depending on the transistor's conductivity type (n-channel or p-channel) and the potential applied to the three terminals, one of the two input / output terminals is used as the source and the other as the drain. Therefore, in this specification, the source and drain may sometimes be interchanged. In this specification, when describing the connection relationship of the transistor, the terms "one of the source and drain" and "the other of the source and drain" are used. In this specification, one of the source and drain is sometimes referred to as the "first electrode of the transistor" or "first terminal of the transistor," and the other is sometimes referred to as the "second electrode of the transistor" or "second terminal of the transistor." Furthermore, depending on the transistor's structure, sometimes a back gate is included in addition to the three terminals mentioned above. In this case, in this specification, one of the transistor's gate and back gate is sometimes referred to as the first gate, and the other is sometimes referred to as the second gate. Furthermore, in the same transistor, the "gate" and "back gate" can sometimes be interchanged. In addition, when a transistor includes three or more gates, each gate is sometimes referred to as the first gate, the second gate, the third gate, etc. in this specification.

[0106] For example, one example of a transistor described in this specification sometimes includes a multi-gate transistor with two or more gate electrodes. When a multi-gate structure is used, since the channel forming regions are connected in series, it becomes a structure of multiple transistors connected in series. Therefore, by using a multi-gate structure, the off-state current can be reduced, and the transistor's breakdown voltage (improved reliability) can be increased. Alternatively, by utilizing a multi-gate structure, when the transistor operates in the saturation region, even if the voltage between the drain and source changes, the change in the drain-source current is not significant, thus obtaining a voltage-current characteristic with a flat tilt angle. When utilizing a voltage-current characteristic with a flat tilt angle, ideal current source circuits or active loads with extremely high resistance values ​​can be realized. As a result, differential circuits or current mirror circuits with good characteristics can be realized.

[0107] Furthermore, circuit diagrams illustrating a single circuit element sometimes include cases where that circuit element comprises multiple circuit elements. For example, a circuit diagram illustrating a resistor may include cases where two or more resistors are connected in series. Similarly, a circuit diagram illustrating a capacitor may include cases where two or more capacitors are connected in parallel. Likewise, a circuit diagram illustrating a transistor may include cases where two or more transistors are connected in series and their gates are connected to each other. Likewise, a circuit diagram illustrating a switch may include cases where the switch comprises two or more transistors connected in series or in parallel and their gates are connected to each other.

[0108] In addition, in this specification, nodes may also be referred to as terminals, wiring, electrodes, conductive layers, conductors, or impurity regions, depending on the circuit structure and device structure. Furthermore, terminals, wiring, etc., may also be referred to as nodes.

[0109] Furthermore, in this specification, a selector sometimes refers to a circuit that includes multiple input terminals and one output terminal, and selects one of the multiple input terminals and establishes a conduction state between the selected input terminal and the output terminal. In other words, a selector sometimes refers to a circuit that selects one of the input signals input to each of the multiple input terminals and outputs the selected input signal to the output terminal. Alternatively, a selector sometimes refers to a circuit that includes multiple output terminals and one input terminal, and selects one of the multiple output terminals and establishes a conduction state between the selected output terminal and the input terminal. In other words, a selector sometimes refers to a circuit that selects one of the multiple output terminals and outputs the input signal input to the input terminal to the selected output terminal. That is to say, a selector sometimes refers to a multiplexer or a multiplexer. In particular, in the case of inputting or outputting analog potentials or analog currents, a selector sometimes refers to an analog multiplexer or an analog multiplexer.

[0110] Furthermore, in this specification, the terms "voltage" and "potential" may be interchanged as appropriate. "Voltage" refers to the potential difference between the reference potential and a ground potential. For example, when the reference potential is ground potential (grounding potential), "voltage" may also be referred to as "potential." Ground potential does not necessarily mean 0V. Moreover, potential is relative; the potential supplied to wiring, the potential applied to circuits, and the potential output from circuits also change according to changes in the reference potential.

[0111] Furthermore, in this specification, "high-level potential" and "low-level potential" do not imply specific potentials. For example, if two wirings are both labeled as "wirings used to supply high-level potentials," the high-level potentials supplied by the two wirings may be different. Similarly, if two wirings are both labeled as "wirings used to supply low-level potentials," the low-level potentials supplied by the two wirings may be different.

[0112] Furthermore, "current" refers to the phenomenon of charge migration (conductivity). For example, the description "conductivity occurs in a positively charged body" can be replaced with the description "conductivity occurs in a negatively charged body in the opposite direction." Therefore, in this specification, unless otherwise specified, "current" refers to the phenomenon of charge migration (conductivity) during charge carrier migration. Here, examples of charge carriers include electrons, holes, anions, cations, and complex ions, and the charge carriers vary depending on the system through which the current flows (e.g., semiconductors, metals, electrolytes, and vacuum). Furthermore, the "direction of current" in wiring, etc., refers to the direction of migration of positively charged charge carriers and is described as a positive current quantity. In other words, the direction of migration of negatively charged charge carriers is opposite to the direction of current and is described as a negative current quantity. Therefore, in this specification, unless otherwise specified, regarding the positive or negative (or direction) of the current, the description "current flows from element A to element B" can be replaced with the description "current flows from element B to element A." Furthermore, the description "current is input to element A" can be replaced with the description "current is output from element A."

[0113] Furthermore, in this specification, ordinal numbers such as "first," "second," and "third" are added to avoid confusion among the constituent elements. Therefore, these ordinal numbers do not limit the number of constituent elements. Furthermore, these ordinal numbers do not limit the order of constituent elements such as process sequence or stacking sequence. Furthermore, regarding terms for which ordinal numbers are not added in this specification, ordinal numbers are sometimes added in the claims to avoid confusion among the constituent elements. Furthermore, regarding terms for which ordinal numbers are added in this specification, different ordinal numbers are sometimes added in the claims. Furthermore, regarding terms for which ordinal numbers are added in this specification, auxiliary numbers are sometimes omitted in the claims. For example, a constituent element for which the ordinal number "first" is added in one embodiment of this specification may be a constituent element for which different ordinal numbers such as "second," "third," etc., are added in other embodiments or claims. Furthermore, for example, a constituent element for which the ordinal number "first" is added in one embodiment of this specification may be omitted in other embodiments or claims.

[0114] In this specification, for convenience, terms such as "upper" and "lower" are sometimes used to indicate the arrangement of components in conjunction with the accompanying drawings. Furthermore, the positional relationships of the components may be appropriately altered depending on the orientation in which each component is described. Therefore, the terminology used is not limited to that described in the specification, and may be appropriately changed as needed. For example, the expression "an insulator located on the top surface of a conductor" can be replaced with "an insulator located on the bottom surface of a conductor" by rotating the orientation of the illustrated drawings by 180 degrees.

[0115] Furthermore, terms like "above" or "below" are not limited to situations where the constituent elements are directly above or below each other and in direct contact. For example, if the expression is "electrode B on insulating layer A," it is not necessarily required that electrode B is formed in direct contact with insulating layer A; it may also include situations where other constituent elements are included between insulating layer A and electrode B. Similarly, for example, if the expression is "electrode B above insulating layer A," it is not necessarily required that electrode B is formed in direct contact with insulating layer A; it may also include situations where other constituent elements are included between insulating layer A and electrode B. Likewise, for example, if the expression is "electrode B below insulating layer A," it is not necessarily required that electrode B is formed in direct contact below insulating layer A; it may also include situations where other constituent elements are included between insulating layer A and electrode B.

[0116] Furthermore, in this specification, terms such as "row" and "column" are sometimes used to describe the matrix-like configuration of the constituent elements and their positional relationships. Moreover, the positional relationships of the constituent elements may be appropriately changed depending on the direction in which each constituent element is described. Therefore, the terminology used is not limited to that described in the specification, and may be appropriately replaced as needed. For example, by rotating the orientation of the accompanying drawings by 90 degrees, the expression "row direction" may sometimes be replaced with "column direction."

[0117] Furthermore, in this specification, the terms "film" and "layer" may be interchanged depending on the situation. For example, sometimes "conductive layer" may be replaced with "conductive film." Also, sometimes "insulating film" may be changed to "insulating layer." Furthermore, depending on the circumstances, other terms may be used instead of "film" and "layer." For example, sometimes "conductive layer" or "conductive film" may be changed to "conductor." Also, sometimes "insulating layer" or "insulating film" may be changed to "insulator."

[0118] Note that in this specification, the terms "electrode," "wiring," and "terminal" do not functionally limit their constituent elements. For example, sometimes "electrode" is used as part of "wiring," and vice versa. Furthermore, the terms "electrode" or "wiring" also include cases where multiple "electrodes" or "wiring" are formed as one unit. Additionally, for example, sometimes "terminal" is used as part of "wiring" or "electrode," and vice versa. Furthermore, the term "terminal" also includes cases where one or more of "electrode," "wiring," and "terminal" are formed as one unit. Therefore, for example, an "electrode" can be part of "wiring" or "terminal," and vice versa. Furthermore, the terms "electrode," "wiring," or "terminal" are sometimes replaced with terms such as "area," depending on the context.

[0119] In this manual, the terms "wiring," "signal line," or "power line" may be interchanged depending on the situation or condition. For example, sometimes "wiring" may be changed to "signal line." Similarly, sometimes "wiring" may be changed to "power line." Conversely, sometimes "signal line" or "power line" may be changed to "wiring." Sometimes "power line" may be changed to "signal line." Conversely, sometimes "signal line" may be changed to "power line." Furthermore, depending on the situation or condition, sometimes the "potential" applied to the wiring may be changed to "signal." Conversely, sometimes "signal" may be changed to "potential."

[0120] In this specification, "metal oxide" refers to oxides of metals in a broad sense. Metal oxides are classified as oxide insulators, oxide conductors (including transparent oxide conductors), and oxide semiconductors (also abbreviated as OS). For example, when the channel formation region of a transistor contains a metal oxide, the metal oxide is sometimes referred to as an oxide semiconductor. In other words, when a metal oxide can form the channel formation region of a transistor having at least one of amplification, rectification, and switching functions, the metal oxide can be called a metal oxide semiconductor. Furthermore, an OS transistor can be referred to as a transistor containing a metal oxide or an oxide semiconductor.

[0121] Furthermore, in this specification, nitrogen-containing metal oxides are sometimes referred to as metal oxides. Additionally, nitrogen-containing metal oxides may also be referred to as metal oxynitrides.

[0122] Furthermore, in this specification, impurities in a semiconductor refer to substances other than the main components constituting the semiconductor layer. For example, elements with a concentration of less than 0.1 at.% are considered impurities. For example, when impurities are present, one or more of the following may occur: increased defect state density, decreased carrier mobility, and decreased crystallinity in the semiconductor. When the semiconductor is an oxide semiconductor, impurities that alter the semiconductor properties include, for example, Group 1 elements, Group 2 elements, Group 13 elements, Group 14 elements, Group 15 elements, or transition metals other than the main components, especially, for example, hydrogen (contained in water), lithium, sodium, silicon, boron, phosphorus, carbon, and nitrogen.

[0123] In this specification, a switch refers to a component that controls whether current flows by changing to a conducting state (on state) or a non-conducting state (off state). Alternatively, a switch refers to a component that selects and switches current paths. Therefore, a switch sometimes includes two or more terminals for current flow in addition to control terminals. As an example of a switch, an electrical switch or a mechanical switch can be used. In other words, a switch is not limited to a specific component as long as it has the function of controlling current.

[0124] Examples of electrical switches include transistors (such as bipolar transistors or MOS transistors), diodes (such as PN diodes, PIN diodes, Schottky diodes, metal-insulator-metal (MIM) diodes, metal-insulator-semiconductor (MIS) diodes, or diode-connected transistors), or logic circuits combining these components. When a transistor is used as a switch, the "on state" of a transistor refers, for example, to a state where the source and drain electrodes of the transistor are electrically short-circuited or where current can flow between the source and drain electrodes. Conversely, the "off state" of a transistor refers to a state where the source and drain electrodes of the transistor are electrically disconnected. When a transistor is used solely as a switch, there are no particular restrictions on the transistor's polarity (conduction type).

[0125] As an example of a mechanical switch, a switch utilizing MEMS (microelectromechanical systems) technology can be cited. This switch has mechanically movable electrodes, and operates by controlling the on / off state by moving these electrodes.

[0126] In addition, in this specification, the term "conductivity" or "conductivity state" used when the conductive layers are in direct contact refers, for example, to a state that allows current to flow between the conductive layers.

[0127] In this specification, "parallel" means the angle between two straight lines is -10° or higher and less than 10°. Therefore, it also includes angles between -5° or higher and less than 5°. "Approximately parallel" means the angle between two straight lines is -30° or higher and less than 30°. Furthermore, "perpendicular" means the angle between two straight lines is 80° or higher and less than 100°. Therefore, it also includes angles between 85° or higher and less than 95°. "Approximately perpendicular" means the angle between two straight lines is 60° or higher and less than 120°.

[0128] Furthermore, the structures shown in each embodiment in this specification and the like can be appropriately combined with structures shown in other embodiments to constitute a mode of the present invention. Additionally, when multiple structural examples are shown in one embodiment, these structural examples can be appropriately combined.

[0129] Furthermore, the content described in one embodiment (part or all) may be applied / combined / replaced with at least one of the other content described in that embodiment (part or all) and the content described in one or more other embodiments (part or all).

[0130] Note that the content described in the embodiments refers to the content illustrated using various accompanying drawings or the content described using the text in the specification.

[0131] Furthermore, more figures can be formed by combining the figures shown in one embodiment (part or all) with other parts of the figures, other figures shown in that embodiment (part or all), and at least one figure shown in one or more other embodiments (part or all).

[0132] The embodiments described in this specification are illustrated with reference to the accompanying drawings. However, those skilled in the art will readily understand that the embodiments can be implemented in many different forms, and their manner and details can be varied in various ways without departing from the spirit and scope of the invention. Therefore, the invention should not be construed as being limited to the contents described in the embodiments. Note that in the structure of the invention in the embodiments, the same symbols are sometimes used in different drawings to denote the same parts or parts having the same function, and repeated descriptions are omitted. In perspective views, etc., illustrations of some constituent elements are sometimes omitted for clarity.

[0133] In this specification and other materials, when multiple elements use the same symbol and it is necessary to distinguish them, symbols such as "_1", "[n]", and "[m,n]" are sometimes added to the symbol for identification. Furthermore, in the accompanying drawings and other materials, when symbols such as "_1", "[n]", and "[m,n]" are added to the symbol for identification, if it is not necessary to distinguish them in this specification or other materials, sometimes these symbols are not added.

[0134] In the accompanying drawings, sizes, layer thicknesses, or areas are sometimes exaggerated for clarity. Therefore, the invention is not limited to the dimensions shown in the drawings. Furthermore, the drawings schematically illustrate ideal examples and are not limited to the shapes or values ​​shown. For example, non-uniformity in signals, voltages, or currents caused by noise or timing deviations may be included.

[0135] (Implementation Method 1)

[0136] In this embodiment, a storage circuit according to one aspect of the present invention is described.

[0137] Figure 2A This is a circuit diagram illustrating one aspect of the storage circuit of the present invention. Figure 2A The storage circuit MCR shown is a circuit capable of storing 1 bit of data. Furthermore, the storage circuit MCR includes, for example, transistors MWA, MWB, MNA, MNB, MPA, and MPB.

[0138] Transistors MWA, MWB, MNA, and MNB are all n-channel transistors. Additionally, transistors MPA and MPB are p-channel transistors.

[0139] The first terminal of transistor MWA is electrically connected to wiring BL. The second terminal of transistor MWA is electrically connected to the gate of transistor MNA, the first terminal of transistor MPA, the first terminal of transistor MNB, and the gate of transistor MPB. Additionally, the first terminal of transistor MMWB is electrically connected to wiring BLB, and the second terminal of transistor MMWB is electrically connected to the gate of transistor MNB, the first terminal of transistor MPB, the first terminal of transistor MNA, and the gate of transistor MPA. The gates of transistors MWA and MMWB are each electrically connected to wiring WRL. Furthermore, the second terminal of transistor MNA is electrically connected to wiring VE2, and the second terminal of transistor MPA is electrically connected to wiring VE1. Additionally, the second terminal of transistor MNB is electrically connected to wiring VE2, and the second terminal of transistor MPB is electrically connected to wiring VE1.

[0140] As an example, both the BL and BLB wires are used as bit line pairs in the memory circuit MCR. Therefore, the BL and BLB wires are used to transmit complementary data written to or read from the memory circuit MCR. Specifically, for example, when the BL wire is input with a high or low level as data to be written to the MCR, the other of the high or low level is input to the BLB wire as data that inverts the logic of the BL wire. Thus, the BLB wire is sometimes referred to as the bit complement or inverted bit line to the BL wire.

[0141] Wiring line WRL is used, for example, as a word line in a memory circuit MCR. Therefore, when a write or read operation is performed in the memory circuit MCR, wiring WRL is input with a high-level potential as a selection signal, and transistors MWA and MWB are both turned on. Conversely, when no write or read operation is performed in the memory circuit MCR, wiring WRL is input with a low-level potential as a non-selection signal, and transistors MWA and MWB are both turned off.

[0142] As an example, wirings VE1 and VE2 are used as wirings supplying a fixed potential. In particular, this fixed potential corresponds to the power supply potential used to drive the memory circuit MCR. The fixed potential supplied to wiring VE1 is preferably higher than the fixed potential supplied to wiring VE2. Therefore, it is preferable that wiring VE1 is supplied with a high power supply potential and wiring VE2 is supplied with a low power supply potential.

[0143] The storage circuit MCR can be a storage cell that can be used in a storage device called SRAM (Static Random Access Memory). SRAM has a faster write and read speed than DRAM (Dynamic Random Access Memory), so it can be used as an example in high-speed cache memory included in computing devices such as CPUs and GPUs.

[0144] SRAM latches data using an inverter loop that uses two inverters. Figure 2A In the storage circuit MCR, the first inverter includes transistor MNA and transistor MPB, and the second inverter includes transistor MNB and transistor MPA.

[0145] Figure 2B The storage circuit MCR shown is Figure 2A The equivalent circuit of the storage circuit MCR is shown. Inverter IV1 can be a first inverter including transistor MNA and transistor MPB, and inverter IV2 can be a second inverter including transistor MNB and transistor MPA.

[0146] In addition, transistors MWA and MFB are both selection transistors in the storage circuit MCR. They are turned on when writing or reading is performed in the storage circuit MCR, and turned off when data is stored in the storage circuit MCR.

[0147] When transistors MNA, MNB, MWA, and MWB are all OS transistors, a back gate can be disposed in these transistors. In particular, the number of charge carriers in the semiconductor layer with the channel formation region of the transistor can be changed according to the potential supplied to the back gate, and as a result, the threshold voltage of the transistor can be changed.

[0148] Figure 2C The diagram illustrates a memory circuit MCR with a back gate in each of transistors MNA, MNB, MWA, and MWB. The back gates of transistors MNA and MNB are electrically connected to wiring BGE2, and the back gates of transistors MWA and MWB are electrically connected to wiring BGE1.

[0149] Wiring BGE1 is used, for example, as a wiring for supplying a variable potential. By supplying a high-level potential or a low-level potential to wiring BGE1, the threshold voltages of transistors MWA and MWB can be varied. For example, by supplying a high-level potential to wiring BGE1, the threshold voltages of transistors MWA and MWB can be decreased. Conversely, by supplying a low-level potential to wiring BGE1, the threshold voltages of transistors MWA and MWB can be increased. Therefore, in order to vary the threshold voltages of transistors MWA and MWB to reduce the off-state current or increase the on-state current of the transistors, wiring BGE1 is preferably electrically connected to the circuit that generates the desired voltage.

[0150] For example, to prevent data degradation in the memory circuit MCR due to leakage currents (off-state currents) of transistors MWA and MMWB, the off-state currents can be reduced by supplying a low-level potential to wiring BGE1 to increase the threshold voltages of transistors MWA and MMWB. Conversely, to increase the write capability of the memory circuit MCR, the on-state currents can be increased by supplying a high-level potential to wiring BGE1 to decrease the threshold voltages of transistors MWA and MMWB.

[0151] Similar to wiring BGE1 described above, wiring BGE2 is used to supply a variable potential. Therefore, for details regarding wiring BGE2, please refer to the description of wiring BGE1 above. Depending on the potential supplied to wiring BGE2, the threshold voltages of transistors MNA and MNB can be varied.

[0152] For example, when transistors MPA and MPB are both Si transistors and transistors MNA and MNB are both OS transistors, generally speaking, the on-state current of transistors MNA and MNB is smaller than that of transistors MPA and MPB. Therefore, supplying a high-level potential to wiring BGE2 lowers the threshold voltages of transistors MNA and MNB, increasing their on-state currents. This allows the on-state currents of transistors MNA and MNB to approach those of transistors MPA and MPB.

[0153] As mentioned above, the memory circuit MCR includes at least six transistors in total. The more transistors there are, the larger the total area occupied by all transistors, and the more wiring is required, resulting in a larger circuit area.

[0154] <Structure Example>

[0155] One aspect of the present invention is a storage circuit that addresses the aforementioned issues, wherein transistors MPA and MPB, MNA and MNB, and MWA and MMB are stacked to reduce the circuit area.

[0156] Figure 1 The present invention illustrates a storage circuit MCRA according to one embodiment of the invention. Figure 1 This is a cross-sectional schematic diagram showing a portion of the MCRA (Memory Circuitry Association) memory circuit. Additionally, Figure 1 The structure of the storage circuit MCRA shown is Figure 2A An example of the structure of a storage circuit MCR.

[0157] To show Figure 1 Relationship with the planar and three-dimensional diagrams described later. Figure 1 Arrows indicating the X, Y, and Z directions are attached. Note that, as an example, the X, Y, and Z directions here represent directions that are orthogonal to each other. Furthermore, in this specification, one of the X, Y, and Z directions is sometimes referred to as the "first direction." Furthermore, one of them is sometimes referred to as the "second direction." Furthermore, the remaining one is sometimes referred to as the "third direction." Additionally, in this specification, for example, "+X direction" indicates a direction perpendicular to the X, Y, and Z directions. Figure 1 The arrows shown point in the X direction are in the same direction; "-X direction" indicates the same direction as the arrows in the X direction. Figure 1 The arrow pointing to the X direction is in the opposite direction. Note that the notation for "+Y direction", "-Y direction", "+Z direction" and "-Z direction" is the same as that for "+X direction" and "-X direction" mentioned above.

[0158] in addition, Figure 3This is a three-dimensional schematic diagram illustrating a structural example of a portion of the MCRA (Memory Circuit Replication Association). Note that in... Figure 3 In this diagram, to facilitate observation of the MCRA (Memory Module Array) structure, components such as the insulating layer have been omitted. Additionally, Figure 1 The cross-sectional diagram is along Figure 3 A schematic diagram of the XZ plane segmentation of a three-dimensional diagram.

[0159] The storage circuit MCRA includes, for example, layer SS1, layer SS2 on layer SS1, and layer SS3 on layer SS2.

[0160] Specifically, layer SS1 includes a substrate, transistors MPA and MPB formed on the substrate, layer SS2 includes transistors MNA and MNB, and layer SS3 includes transistors MWA and MWB.

[0161] exist Figure 1 and Figure 3 In the middle, layer SS1 includes, for example, a substrate BS, insulating layer GI1, insulating layer GI2, insulating layer IS1, insulating layer BI1, insulating layer IS2, insulating layer BI2, insulating layer IS3, conductive layer ME0, conductive layer ME1a, conductive layer ME1b, conductive layer ME2da, conductive layer ME2db and conductive layer ME2c.

[0162] In addition, the substrate BS contains low-resistance regions LRAa, LRAb, LRAc, semiconductor regions SCAa, SCAb, and a device separation layer DDV.

[0163] In addition, Figure 1 or Figure 3 In the middle, layer SS2 includes, for example, insulating layers BI3, IS4, IS5, BI4, GI3, conductive layers ME3da, ME3db, ME3ga, ME3gb, ME4da, ME4db, ME4ga, ME4gb, ME6a, ME6b, semiconductor layers SC1a and SC1b. Additionally, in Figure 1 or Figure 3 In the middle, layer SS3 includes, for example, insulating layers BI5, IS6, BI6, GI4, IS7, BI7, IS8, conductive layers ME7a, ME7b, ME8a, ME8b, ME9a, ME9b, ME10a, ME10b, and ME11.

[0164] First, the layer SS1, from the substrate BS to the insulating layer IS3, included in the memory circuit MCRA, will be described. Specifically, the transistors MPA and MPB in layer SS1 and their surroundings will be described.

[0165] Figure 4A This is a summary showing Figure 1 A schematic cross-sectional view of layer SS1, which forms the stack from substrate BS to insulating layer IS3. Additionally, Figure 4B This is a planar schematic diagram of layer SS1, which forms the stack from substrate BS to insulating layer IS3. Note that... Figure 4A The cross-sectional diagram is equivalent to along Figure 4B The diagram shows a cross-sectional view of layer SS1, which forms the stack from substrate BS to insulating layer IS3, as indicated by the dotted lines A1-A2. Additionally, Figure 5 It is along Figure 4B The diagram shows a cross-sectional view of layer SS1, which is the stack from substrate BS to insulating layer IS3, as shown by the dotted lines A3-A4.

[0166] Note that in Figure 4B In order to clearly show the positional relationship between the conductive layer and the semiconductor layer, the insulating layer and other components included in the memory circuit MCRA are omitted.

[0167] exist Figure 4A and Figure 5 In the substrate BS, a source region, a drain region, and a semiconductor region are formed for each of transistors MPA and MPB. Transistor MPA includes: a conductive layer ME1a serving as a gate; an insulating layer GI1 serving as a gate insulating film; an insulating layer GI2 formed on the side of the gate; a low-resistance region LRAa serving as one of the source and drain regions; and a low-resistance region LRAc serving as the other of the source and drain regions. Transistor MPB includes: a conductive layer ME1b serving as a gate; an insulating layer GI1 serving as a gate insulating film; an insulating layer GI2 formed on the side of the gate; a low-resistance region LRAb serving as one of the source and drain regions; and a low-resistance region LRAc serving as the other of the source and drain regions. Furthermore, transistor MPA includes a semiconductor region SCAa having a channel formation region, and transistor MPB includes a semiconductor region SCAb having a channel formation region.

[0168] Specifically, on the substrate BS, low-resistance region LRAa, semiconductor region SCAa, low-resistance region LRAc, semiconductor region SCAb, and semiconductor region SCAb are sequentially arranged in the X direction. Furthermore, conductive layer ME1a has a region that partially overlaps with semiconductor region SCAa, and conductive layer ME1b has a region that partially overlaps with semiconductor region SCAb. Additionally, both conductive layers ME1a and ME1b have regions extending along the Y direction.

[0169] In particular, the conductive layer ME1a has the properties shown in top view. Figure 4B In the region extending along the -Y direction, the conductive layer ME1b has a top view Figure 4B This refers to the region extending along the +Y direction. Note that conductive layers ME1a and ME1b extend in different directions perpendicular to the X direction on the XY plane, but the directions in which conductive layers ME1a and ME1b extend are not limited to the top view. Figure 4B The direction of the time. For example, the direction in which conductive layers ME1a and ME1b extend may not be perpendicular to the X direction. As an example, in a top view... Figure 4B At this time, the direction in which the conductive layer ME1a extends can also be either the right or left direction when viewed from the semiconductor region SCAa towards the semiconductor region SCAb, and in a top-down view... Figure 4B In this case, the direction in which the conductive layer ME1b extends can also be either the right or left direction when looking at the semiconductor region SCAb from the semiconductor region SCAa.

[0170] A conductive layer ME2c is disposed on the low-resistance region LRAc, and a conductive layer ME0 is disposed on the conductive layer ME2c. In particular, the conductive layer ME0 extends along the Y direction, and is therefore used, for example, as wiring. Furthermore, this wiring is equivalent to… Figure 2A and Figure 2B The wiring VE1 is described. Therefore, the conductive layer ME2c is used as wiring to supply a fixed potential.

[0171] Furthermore, as mentioned above, both transistor MPA and transistor MPB are p-channel transistors.

[0172] As the substrate BS, a semiconductor substrate can be used, for example. As mentioned above, examples of such semiconductor substrates include single-crystal substrates made of silicon and single-crystal substrates made of germanium. Alternatively, a compound semiconductor substrate can be used as the substrate BS, for example. As mentioned above, examples of such compound semiconductor substrates include substrates made of silicon carbide, silicon germanium, gallium arsenide, aluminum gallium arsenide, indium phosphide, zinc oxide, gallium nitride, or gallium oxide.

[0173] like Figure 5As shown, the transistor MPA has the following structure: a portion of the semiconductor substrate is processed into a bump, which is formed as a semiconductor region SCAa, and a conductive layer ME1a is formed on the top surface of the bump, separated by an insulating layer GI1. That is, the sidewalls of the transistor MPA in the channel width direction overlap with the conductive layer ME1a, separated by the insulating layer GI1. Thus, by using a Fin-type transistor as the transistor MPA, the effective channel width is increased, thereby improving the on-state characteristics of the transistor MPA. Furthermore, since the effect of the electric field at the gate electrode can be enhanced, the off-state characteristics of the transistor MPA can be improved.

[0174] Similarly, although not illustrated, the MPB transistor is a Fin-type transistor in which a portion of the semiconductor substrate is processed into a bump, which is formed as a semiconductor region SCAb, and a conductive layer ME1b is formed on the top surface of the bump, separated by an insulating layer GI1. Therefore, the effective channel width of the MPB transistor is increased, thereby improving its on-state characteristics. Furthermore, since the effect of the electric field at the gate electrode can be enhanced, the off-state characteristics of the MPB transistor can be improved.

[0175] Note that although the case shown here is that a portion of the semiconductor substrate is processed into a convex shape, it is also possible to process an SOI (Silicon On Insulator) substrate to form a semiconductor film with a convex shape.

[0176] The channel formation region of the semiconductor region SCAa or the semiconductor region SCAb, the region theren, the low-resistance region LRAa, the low-resistance region LRAb, and the low-resistance region LRAc used as source or drain regions preferably contain silicon-based semiconductors, and more specifically, preferably contain monocrystalline silicon. That is, a monocrystalline silicon substrate is used as the substrate BS, for example, preferably as a semiconductor substrate.

[0177] Alternatively, silicon can be used to control the effective mass by applying stress to the crystal lattice and changing the interplanar spacing. Alternatively, the MPA and MPB transistors can be HEMTs (High Electron Mobility Transistors) using gallium arsenide and aluminum gallium arsenide.

[0178] In this embodiment, a single-crystal silicon substrate, which serves as a semiconductor substrate, is described as the substrate BS.

[0179] In the low-resistance regions LRAa, LRAb, and LRAAc, in addition to the semiconductor materials used in the semiconductor regions SCAa and SCAb, elements such as boron or aluminum, which impart p-type conductivity, are also included. Furthermore, when both transistor MPA and transistor MPB are n-channel transistors, it is preferable that in the low-resistance regions LRAa, LRAb, and LRAAc, in addition to the semiconductor materials used in the semiconductor regions SCAa and SCAb, elements such as arsenic or phosphorus, which impart n-type conductivity, are doped, but elements imparting p-type conductivity are not doped.

[0180] A portion of the conductive layer ME1a is used as the gate electrode of the transistor MPA. A portion of the conductive layer ME1b is used as the gate electrode of the transistor MPB. The conductive layers ME1a and ME1b, used as gate electrodes, can be made of conductive materials such as semiconductor materials (e.g., silicon), metal materials, alloy materials, or metal oxide materials, containing elements that impart n-type conductivity (e.g., arsenic or phosphorus) or elements that impart p-type conductivity (e.g., boron or aluminum).

[0181] Furthermore, since the work function is determined by the material of the conductive layer, the threshold voltages of transistors MPA and MPB can be adjusted by selecting the material of the conductive layer. Specifically, titanium nitride or tantalum nitride is preferably used as the conductive layers ME1a and ME1b. In order to have both conductivity and embeddability, a stack of metal materials such as tungsten or aluminum is preferably used as the conductive layers ME1a and ME1b, and tungsten is particularly preferred in terms of heat resistance.

[0182] The insulating layer GI1 may be, for example, a single film selected from silicon oxide, silicon nitride, silicon oxynitride, silicon oxynitride, or a multilayer structure selected from the above materials.

[0183] In this specification, etc., "oxynitride" refers to a material in which the oxygen content is greater than the nitrogen content in its composition, while "nitrogen oxide" refers to a material in which the nitrogen content is greater than the oxygen content in its composition. For example, when described as "silicon oxynitride", it refers to a material in which the oxygen content is greater than the nitrogen content in its composition, while when described as "silicon oxynitride", it refers to a material in which the nitrogen content is greater than the oxygen content in its composition.

[0184] To separate multiple transistors formed on a substrate BS from each other, a device separation layer (DDV) is provided. The DDV can be formed, for example, using methods such as LOCOS (Local Oxidation of Silicon), STI (Shallow Trench Isolation), or mesa isolation.

[0185] Notice, Figure 1 , Figure 3, Figure 4A , Figure 4B and Figure 5 The transistors MPA and MPB shown are merely examples, and the structure of the transistors MPA and MPB included in one embodiment of the storage circuit of the present invention is not limited. The transistors MPA and MPB included in one embodiment of the storage circuit of the present invention can be any appropriate transistors depending on the circuit structure and driving method. For example, Figure 1 , Figure 3 , Figure 4A , Figure 4B and Figure 5 The transistors MPA and MPB shown can also be planar transistors.

[0186] Figure 1 , Figure 4A and Figure 5 The transistors MPA and MPB shown, as well as the component separation layer DDV, are sequentially stacked with insulating layers IS1, BI1, IS2, BI2, and IS3.

[0187] Insulating layers IS1, IS2, and IS3 may be made of materials such as silicon oxide, silicon oxynitride, silicon oxynitride, silicon nitride, aluminum oxide, aluminum oxynitride, aluminum oxynitride, or aluminum nitride.

[0188] In particular, the insulating layer IS1 can also be used as a planarization film to planarize the steps caused by the shapes of transistors MPA and MPB. For example, in order to improve the flatness of the top surface of the insulating layer IS1, its top surface can also be planarized by a planarization process using chemical mechanical polishing (CMP).

[0189] Furthermore, insulating layers B1 and BI2 preferably use barrier films to prevent impurities such as water or hydrogen from diffusing from the substrate BS, transistor MPA, and transistor MPB into the region of the transistor disposed above insulating layer IS3. For example, the transistor here corresponds to Figure 1 The transistors shown are MNA, MNB, MWA, and MWB.

[0190] As an example of a hydrogen-blocking film, silicon nitride formed by CVD (Chemical Vapor Deposition) can be used. Here, when hydrogen diffuses into semiconductor devices containing oxide semiconductors, such as transistors MNA, MNB, MWA, and MWB, it can sometimes lead to a deterioration in the characteristics of the semiconductor device. Therefore, it is preferable to provide a film that inhibits hydrogen diffusion between transistors MNA, MNB, MWA, and MWB and transistors MPA and MPB. Specifically, a film that inhibits hydrogen diffusion refers to a film with a low amount of hydrogen detachment.

[0191] Furthermore, the dielectric constant of one or more selected from insulating layers IS1 to IS3 is preferably lower than that of insulating layers BI1 and BI2. For example, the relative dielectric constant of one or more selected from insulating layers IS1 to IS3 is preferably less than 4, more preferably less than 3. Additionally, for example, the relative dielectric constant of one or more selected from insulating layers IS1 to IS3 is preferably less than 0.7 times the relative dielectric constant of insulating layers BI1 and BI2, more preferably less than 0.6 times. By using a material with a low dielectric constant in the interlayer film, parasitic capacitance generated between wirings can be reduced.

[0192] The insulating layers IS1, BI1, IS2, BI2, and IS3 contain embedded conductive layers ME2da, ME2db, ME2ga, ME2gb, and ME2c. Specifically, in... Figure 1 and Figure 4A In this structure, each of the insulating layers IS1, BI1, IS2, BI2, and IS3 has an opening KK1da extending to the low-resistance region LRAa in the region overlapping with it, and a conductive layer ME2da is disposed therein, with the opening KK1da embedded in the opening. Similarly, each of the insulating layers IS1, BI1, IS2, BI2, and IS3 has an opening KK1db extending to the low-resistance region LRAb in the region overlapping with it, and a conductive layer ME2db is disposed therein, with the opening KK1db embedded in the opening. Furthermore, the insulating layer IS1 has an opening KK1c extending to the low-resistance region LRAc in the region overlapping with it, and a conductive layer ME2c is disposed therein, with the opening KK1c embedded in the opening. Additionally, in... Figure 5In this configuration, each of the insulating layers IS1, BI1, IS2, BI2, and IS3 has an opening KK1ga extending to the conductive layer ME1a in the region overlapping with the conductive layer ME1a, and a conductive layer ME2ga is disposed in such a way that the opening KK1ga is embedded therein. Note that, although not shown in the diagram, each of the insulating layers IS1, BI1, IS2, BI2, and IS3 has an opening extending to the conductive layer ME1b in the region overlapping with the conductive layer ME1b, and a conductive layer ME2gb is disposed in such a way that the opening is embedded therein.

[0193] Therefore, the low-resistance region LRAa is electrically connected to the conductive layer ME2da, the low-resistance region LRAb is electrically connected to the conductive layer ME2db, the conductive layers ME1a and ME2ga are electrically connected, and the conductive layers ME1b and ME2gb are electrically connected. Furthermore, the low-resistance region LRAc is electrically connected to the conductive layer ME2c.

[0194] Conductive layers ME2da, ME2db, ME2ga, ME2gb, and ME2c are used as plugs or wiring. Note that sometimes the same symbol is used to represent multiple conductive layers used as plugs or wiring. Furthermore, in this specification, wiring and plugs connected to the wiring may be formed as a single unit. That is, a portion of the conductor is sometimes used as wiring, and a portion of the conductor is sometimes used as a plug.

[0195] In addition, Figure 1 , Figure 4A and Figure 5 In this context, the plugs or wiring formed in insulating layers IS1, BI1 and IS2, and BI2 and IS3 are collectively referred to as conductive layers ME2da or ME2db. Thus, by forming plugs or wiring in insulating layers IS1, BI1 and IS2, and BI2 and IS3, one or more wiring layers selected from insulating layers IS1, BI1 and IS2, and BI2 and IS3 can be provided. For example, in... Figure 1 , Figure 4A and Figure 5 In this context, insulating layers BI1 and IS2 can be wiring layers.

[0196] Especially in Figure 1 and Figure 4A In this configuration, the conductive layer ME0 is embedded in the region of the insulating layer IS2 that overlaps with the conductive layer ME2c. As an example, the conductive layer ME0 is used as... Figure 2A The wiring shown is VE1.

[0197] As an example, conductive layers ME2da, ME2db, ME2ga, ME2gb, and 2c can be single layers or stacks of conductive materials such as metals, alloys, metal nitrides, or metal oxides. High-melting-point materials such as tungsten or molybdenum, which combine heat resistance and conductivity, are preferred; tungsten is particularly favored. Alternatively, low-resistance conductive materials such as aluminum or copper are preferred. Using low-resistance conductive materials reduces wiring resistance.

[0198] Next, layer SS2, which is the stack of insulating layers BI2 to IS5 included in the storage circuit MCRA, will be described.

[0199] Figure 6A This is a summary showing Figure 1 A cross-sectional schematic diagram of the stacked structure from insulating layer BI2 to conductive layers ME6a and ME6b is shown, omitting insulating layer IS5. Additionally, Figure 6B This is a planar schematic diagram of the stacked structure from insulating layer BI2 to conductive layers ME6a and ME6b. Note that... Figure 6A The cross-sectional diagram is equivalent to along Figure 6B The diagram shows a cross-sectional view of the laminate from the insulating layer BI2 to the conductive layers ME6a and ME6b, as indicated by the dotted lines A1-A2. Additionally, Figure 7A It is along Figure 6B The diagram shows a cross-sectional view of the laminate from the insulating layer BI2 to the conductive layers ME6a and ME6b, as indicated by the dotted lines A3-A4. Additionally, Figure 7B It is along Figure 6B The diagram shows a cross-sectional view of the stacked structure from the insulating layer BI2 to the conductive layers ME6a and ME6b, as shown by the dotted lines A5-A6.

[0200] Note that in Figure 6B In order to clearly show the positional relationship between the conductive layer and the semiconductor layer, the insulating layer and other components included in the memory circuit MCRA are omitted.

[0201] exist Figure 6A , Figure 6B , Figure 7A and Figure 7BIn the insulating layer IS3, conductive layers ME3da, ME3ga, ME3gb, and ME3db are arranged sequentially in the X direction. Additionally, conductive layers ME3da, ME3ga, ME3gb, and ME3db are positioned along the Y direction. Therefore, it can be said that conductive layers ME3da, ME3ga, ME3gb, and ME3db are positioned perpendicular to the X direction; however, they can also be positioned in a direction not perpendicular to the X direction.

[0202] In particular, such as Figure 6A As shown, conductive layer ME3da is disposed on insulating layer IS3 and conductive layer ME2da, and conductive layer ME3db is disposed on insulating layer IS3 and conductive layer ME2db. Furthermore, as... Figure 7A As shown, the conductive layer ME3ga is disposed on the insulating layer IS3 and the conductive layer ME2ga. Furthermore, although not shown, the conductive layer ME3gb is disposed on the insulating layer IS3 and the conductive layer ME2gb.

[0203] Thus, conductive layers ME2da and ME3da are interconnected, conductive layers ME2db and ME3db are interconnected, conductive layers ME2ga and ME3ga are interconnected, and conductive layers ME2gb and ME3gb are interconnected.

[0204] Conductive layers ME3da, ME3db, ME3ga, and ME3gb are used as wiring to connect transistors MPA and MPB located below insulating layer IS3, transistors MNA and MNB located above insulating layer IS3, and transistors MWA and MWB.

[0205] Additionally, the conductive layer ME3ga is used as one of the source and drain electrodes in the transistor MNA. Conversely, the conductive layer ME3gb is used as one of the source and drain electrodes in the transistor MNB.

[0206] As conductive layers ME3da, ME3db, ME3ga, and ME3gb, it is preferable to use metal elements selected from aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium, and lanthanum, alloys composed of two or more of the aforementioned metal elements, or combinations of alloys composed of two or more of the aforementioned metal elements.

[0207] Furthermore, as conductive layers ME3da, ME3db, ME3ga, and ME3gb, tantalum nitride, titanium nitride, tungsten, nitrides containing titanium and aluminum, nitrides containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, or oxides containing lanthanum and nickel are preferably used. Tantalum nitride, titanium nitride, nitrides containing titanium and aluminum, nitrides containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, and oxides containing lanthanum and nickel are conductive materials that are not easily oxidized or that maintain conductivity even after absorbing oxygen, and are therefore preferred. Additionally, as conductors, semiconductors with high conductivity, such as polycrystalline silicon containing impurity elements (e.g., phosphorus or arsenic), or silicides (e.g., nickel silicides) can also be used.

[0208] In addition, such as Figure 1 , Figure 6A , Figure 7A and Figure 7B As shown, conductive layers ME3da, ME3db, ME3ga, and ME3gb can also be stacked in multiple layers to form conductive films from the aforementioned materials. For example, a stacked structure combining materials containing the aforementioned metallic elements and conductive materials containing oxygen can also be used. Furthermore, a stacked structure combining materials containing the aforementioned metallic elements and conductive materials containing nitrogen can also be used. Additionally, a stacked structure combining materials containing the aforementioned metallic elements, conductive materials containing oxygen, and conductive materials containing nitrogen can also be used.

[0209] Specifically, for example, each of the conductive layers ME3da, ME3db, ME3ga, and ME3gb may also include a stack, which includes a first conductive layer, a second conductive layer on the first conductive layer, and a third conductive layer on the second conductive layer.

[0210] As the first and third conductive layers, conductive materials with oxygen-suppressing properties, such as titanium, titanium nitride, tantalum, tantalum nitride, ruthenium, or ruthenium oxide, can be used. As the second conductive layer, conductive materials with high conductivity, such as tungsten, copper, or aluminum, can be used as the main components. By sandwiching the second conductive layer between the first and third conductive layers, the decrease in conductivity of the second conductor due to oxidation can be prevented. Furthermore, the third conductive layer can also be used as a hard mask for forming conductive layers ME3da, ME3db, ME3ga, and ME3gb. Additionally, the third conductive layer can also be used as an etch stop layer for forming the following openings: KK2va, KK2vb, KK2da, KK2ga, the opening embedded in conductive layer ME4gb, and the opening embedded in conductive layer ME4db.

[0211] An insulating layer BI3 is disposed on the insulating layer IS3, the conductive layer ME3da, the conductive layer ME3db, the conductive layer ME3ga, and the conductive layer ME3ga.

[0212] Insulating layer BI3, for example, is used as a barrier insulating film to separate insulating layer IS3 from insulating layer IS4 described below, similar to insulating layers BI1 and BI2. Specifically, insulating layer BI3 is used as a barrier insulating film to prevent the permeation of impurities that diffuse into semiconductor layers SC1a and SC1b, thereby increasing the carrier concentration. When semiconductor layers SC1a and SC1b contain oxide semiconductors, examples of such impurities include hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules (e.g., N2O, NO, or NO2), copper atoms, etc. When such impurities diffuse into semiconductor layers SC1a and SC1b, the reliability of transistor MNA and transistor MNB decreases; therefore, insulating layer BI3 is preferably made of a material used as a barrier insulating film to prevent the diffusion of such impurities.

[0213] Alternatively, insulating layer BI3 can also be used as a barrier insulating film to separate conductive layers ME3da, ME3db, ME3ga, and ME3gb from insulating layer IS4. Specifically, insulating layer BI3 is used as a barrier insulating film to inhibit the diffusion of impurities from insulating layer IS4 into conductive layers ME3da, ME3db, ME3ga, and ME3gb. Examples of such impurities include oxygen.

[0214] As a barrier insulating film that inhibits the permeation of water, hydrogen, and oxygen, a single layer or stack of insulators selected from one or more of boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium, and tantalum can be used. Specifically, examples of insulators that inhibit the permeation of water, hydrogen, and oxygen include metal oxides such as aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, and tantalum oxide. Additionally, examples of insulators that inhibit the permeation of water, hydrogen, and oxygen include oxides containing aluminum and hafnium (hafnium aluminate). Furthermore, examples of insulators that inhibit the permeation of water, hydrogen, and oxygen include metal nitrides such as aluminum nitride, titanium aluminum nitride, titanium nitride, silicon oxynitride, and silicon nitride.

[0215] In particular, the barrier insulating film is preferably made of aluminum oxide or silicon nitride. This, for example, can suppress the diffusion of water and hydrogen from beneath the insulating layer IS3 into the transistor MNA and transistor MNB.

[0216] An insulating layer IS4 is disposed on an insulating layer BI3. Furthermore, an insulating layer BI4 is disposed on an insulating layer IS4. Furthermore, a conductive layer ME5 is disposed on an insulating layer BI4. In particular, the conductive layer ME5 extends along the X direction.

[0217] Insulating layers IS4 and BI4 are used, for example, as interlayer films to separate each of conductive layers ME3da, ME3db, ME3ga, and ME3gb from conductive layer ME5. By providing insulating layer IS3 or insulating layer BI4, direct contact and short circuits between each of conductive layers ME3da, ME3db, ME3ga, and ME3gb and conductive layer ME5 can be prevented.

[0218] Insulating layer IS4 is used as an example of an interlayer film. Therefore, insulating layer IS4 preferably contains an insulating material with a low relative permittivity. By using an insulating material with a low relative permittivity in the interlayer film, the parasitic capacitance generated between the wirings can be reduced. Therefore, as insulating layer IS4, an insulating material with a low relative permittivity that can be used in any of insulating layers IS1 to IS3 can be used.

[0219] Insulating layer BI4 is used as an example of a barrier insulating film separating insulating layer IS4 from conductive layer ME5. Specifically, insulating layer BI4 is used as a barrier insulating film to inhibit the diffusion of impurities from insulating layer IS4 to conductive layer ME5. Here, impurities can be exemplified by, for example, oxygen, which causes a decrease in conductivity of conductive layer ME5 due to oxidation. Therefore, as insulating layer BI4, an insulating material that can be used as a barrier insulating film to inhibit the diffusion of oxygen, suitable for any of insulating layers BI1 to BI3, can be used.

[0220] A portion of the conductive layer ME5 is used, for example, as another of the source and drain electrodes in a transistor MNA.

[0221] Additionally, the conductive layer ME5 extends along the X direction, so it is used, for example, as wiring. Furthermore, this wiring is equivalent to... Figure 2A and Figure 2B The wiring VE2 is illustrated. Therefore, the conductive layer ME5 is used as the wiring to supply a fixed potential.

[0222] In addition, such as Figure 6A As shown, insulating layer IS4, insulating layer BI4, and conductive layer ME5 have regions overlapping with conductive layer ME3ga and regions overlapping with conductive layer ME3gb. Furthermore, in insulating layer IS4, insulating layer BI4, and conductive layer ME5, an opening KK2va reaching conductive layer ME3ga is provided in the region overlapping with conductive layer ME3ga, and an opening KK2vb reaching conductive layer ME3gb is provided in the region overlapping with conductive layer ME3gb.

[0223] A semiconductor layer SC1a is disposed on each side of the insulating layer IS4, insulating layer BI3, and conductive layer ME5 corresponding to the side of the opening KK2va, the top surface of the conductive layer ME3ga corresponding to the bottom of the opening KK2va, and the top surface of the conductive layer ME5. In other words, it can be said that the semiconductor layer SC1a has a region that contacts the conductive layer ME3ga at the bottom of the opening KK2va, the insulating layer IS4, insulating layer BI3, and conductive layer ME5 on the side of the opening KK2va.

[0224] Similarly, a semiconductor layer SC1b is disposed on each side of the insulating layer IS4, insulating layer BI3, and conductive layer ME5 corresponding to the side of the opening KK2vb, the top surface of the conductive layer ME3gb corresponding to the bottom of the opening KK2va, and the top surface of the conductive layer ME5. In other words, it can be said that the semiconductor layer SC1b has a region that contacts the conductive layer ME3gb, insulating layer IS4, insulating layer BI3, and conductive layer ME5 at the bottom of the opening KK2vb.

[0225] Semiconductor layers SC1a and SC1b can be, for example, metal oxides used as oxide semiconductors. In this case, the subsequently formed transistors MNA and MNB are OS transistors. The metal oxide preferably contains at least indium or zinc, and is particularly preferably composed of indium and zinc. In addition, it preferably contains element M. Element M can be selected from one or more of aluminum, gallium, silicon, yttrium, tin, copper, vanadium, chromium, manganese, beryllium, boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, calcium, strontium, barium, cobalt, and antimony. In particular, element M is preferably one or more of aluminum, gallium, yttrium, and tin. Furthermore, element M more preferably contains one or both of gallium and tin.

[0226] As an example, semiconductor layers SC1a and SC1b preferably use indium gallium zinc oxide (hereinafter referred to as In-Ga-Zn oxide). In particular, as In-Ga-Zn oxide, it is more preferable to use a metal oxide with an In:Ga:Zn ratio of 1:1:1 or closer, a 4:2:3 or closer, or a 3:1:2 or closer. Furthermore, as another example, semiconductor layers SC1a and SC1b preferably use In-Zn oxide. In particular, as In-Zn oxide, it is more preferable to use a metal oxide with an In:Zn ratio of 4:1 or closer.

[0227] In particular, semiconductor layers SC1a and SC1b preferably use oxide semiconductors with low carrier concentrations. For example, the carrier concentration in the channel formation region of the oxide semiconductor is preferably 1 × 10⁻⁶. 18 cm -3Below, less than 1×10 is preferred. 17 cm -3 Further optimization of less than 1×10 16 cm -3 Further optimization is to select those with a value lower than 1×10 13 cm -3 Furthermore, it is preferred to have a value lower than 1×10 10 cm -3 Furthermore, the carrier concentration in the channel formation region of an oxide semiconductor can be 1 × 10⁻⁶. -9 cm -3 The above. When the aim is to reduce the carrier concentration in an oxide semiconductor film, it is preferable to reduce the impurity concentration in the oxide semiconductor film to reduce the defect state density. In this specification, a state with low impurity concentration and low defect state density is referred to as high-purity intrinsic or substantially high-purity intrinsic. Furthermore, an oxide semiconductor with low carrier concentration is sometimes referred to as a high-purity intrinsic or substantially high-purity intrinsic oxide semiconductor.

[0228] Because high-purity intrinsic or substantially high-purity intrinsic oxide semiconductors have a low defect state density, they sometimes have a low trapped state density. Furthermore, the charge trapped in the trapped states of oxide semiconductors takes a long time to dissipate, sometimes acting like a fixed charge. Therefore, transistors forming channel formation regions in oxide semiconductors with high trapped state densities sometimes exhibit unstable electrical characteristics.

[0229] Therefore, reducing the impurity concentration in the oxide semiconductor is effective in stabilizing the electrical characteristics of the transistor. To further reduce the impurity concentration in the oxide semiconductor, it is preferable to also reduce the impurity concentration in the adjacent film. Examples of impurities include hydrogen or nitrogen. Note that impurities in an oxide semiconductor refer, for example, to elements other than the main components constituting the oxide semiconductor. For example, elements with a concentration less than 0.1 atomic percent can be considered impurities.

[0230] In transistors including oxide semiconductors (OS transistors), impurities or oxygen vacancies (hereinafter sometimes referred to as V0) exist in the channel formation region of the oxide semiconductor. O When this occurs, the electrical characteristics are prone to change, sometimes leading to reduced reliability. Furthermore, in OS transistors, hydrogen formation can enter the Vo within the oxide semiconductor. O The defect (hereinafter sometimes referred to as V) O H), sometimes generating electrons that become charge carriers. Additionally, when V forms in the channel-forming region... O At H, the donor concentration in the channel formation region sometimes increases. As the donor concentration in the channel formation region increases, the threshold voltage sometimes becomes uneven. Therefore, the channel formation region in an oxide semiconductor contains V OAt this time, the transistor is prone to being in a constantly on state (the channel exists even when the gate-source voltage is 0V, and current can flow through the transistor). Therefore, in the channel formation region of the oxide semiconductor, it is preferable to minimize impurities, oxygen vacancies, and V0. O H.

[0231] For example, the semiconductor layer SC1a is preferably a stacked structure of multiple oxide layers having different ratios of the number of metal atoms. For example, as... Figure 8A As shown, the semiconductor layer SC1a can have a stacked structure including semiconductor layer SC1a[1] and semiconductor layer SC1a[2]. Figure 8A It is magnification Figure 7A The diagram shows a cross-sectional view of a transistor MNA. (As shown) Figure 8A As shown, semiconductor layer SC1b[2] is located on the top surface of semiconductor layer SC1a[1].

[0232] Here, the conductivity of the material used for semiconductor layer SC1a[1] is preferably different from the conductivity of the material used for semiconductor layer SC1a[2]. For example, semiconductor layer SC1a[1] can be made of a material with higher conductivity than semiconductor layer SC1a[2]. Figure 8A As shown, the semiconductor layer SC1a[1] has a region that contacts the conductive layers ME3ga and ME5, which are used as the source or drain. Therefore, by increasing the conductivity of the material used for the semiconductor layer SC1a[1], the contact resistance between the semiconductor layer SC1a and the conductive layer ME3ga and the contact resistance between the semiconductor layer SC1a and the conductive layer ME5 can be reduced. As a result, the on-state current of the transistor MNA can be increased.

[0233] Furthermore, the carrier concentration of the semiconductor material used for semiconductor layer SC1a[1] is preferably higher than that of the semiconductor material used for semiconductor layer SC1a[2]. By increasing the carrier concentration of the semiconductor material used for semiconductor layer SC1a[1], the conductivity of semiconductor layer SC1a[1] can be improved.

[0234] The band gap of the first oxide semiconductor used in the semiconductor layer SC1a[1] is preferably different from the band gap of the second oxide semiconductor used in the semiconductor layer SC1a[1]. For example, the difference between the band gap of the first semiconductor material and the band gap of the second oxide semiconductor is preferably 0.1 eV or more, more preferably 0.2 eV or more, and even more preferably 0.3 eV or more. By making the band gap of the first oxide semiconductor lower than that of the second oxide semiconductor, the contact resistance between the semiconductor layer SC1a and the conductive layer ME3ga and the contact resistance between the semiconductor layer SC1a and the conductive layer ME5 can be reduced. Depending on the circumstances, the band gap of the first oxide semiconductor may also be higher than that of the second oxide semiconductor.

[0235] As described above, the band gap of the first oxide semiconductor used in semiconductor layer SC1a[1] can be smaller than the band gap of the second oxide semiconductor used in semiconductor layer SC1a[2]. The composition of the first oxide semiconductor is preferably different from that of the second oxide semiconductor. By making the composition of the first oxide semiconductor different from that of the second oxide semiconductor, the band gap can be controlled. For example, the content of element M in the first oxide semiconductor is preferably lower than the content of element M in the second oxide semiconductor. Specifically, when both the first and second oxide semiconductors are In-M-Zn oxides, the first oxide semiconductor can have an In:M:Zn ratio of 1:1:1 or similar, an In:M:Zn ratio of 4:2:3 or similar, or an In:M:Zn ratio of 3:1:2 or similar. The second oxide semiconductor can have an In:M:Zn ratio of 1:3:2 or similar, an In:Ga:Zn ratio of 1:3:4 or similar, or an In:M:Zn ratio of 1:1:0.5 or similar. The "similar" composition includes a range of ±30% of the desired atomic ratio.

[0236] Furthermore, the semiconductor layer SC1a[1] can also adopt a structure in which the first oxide semiconductor does not contain element M. For example, the first oxide semiconductor used for the semiconductor layer SC1a[1] can be In-Zn oxide, and the second oxide semiconductor used for the semiconductor layer SC1a[2] can be In-M-Zn oxide. Specifically, the first oxide semiconductor can be In-Zn oxide, and the second oxide semiconductor can be In-Ga-Zn oxide. More specifically, the first oxide semiconductor can be an In:Zn = 1:1 [atomic ratio] or a composition close to it, or an In:Zn = 4:1 [atomic ratio] or a composition close to it, and the second oxide semiconductor can be an In:Ga:Zn = 1:1:1 [atomic ratio] or a composition close to it.

[0237] Here, although an example is shown where the content of element M in the first oxide semiconductor is lower than that in the second oxide semiconductor, the present invention is not limited to this. The content of element M in the first oxide semiconductor may also be higher than that in the second oxide semiconductor. Note that it is sufficient to make the compositions of the first oxide semiconductor and the second oxide semiconductor different, and it is also possible to make the contents of elements other than element M different.

[0238] exist Figure 8AIn this case, when a material with high conductivity is used as the semiconductor layer SC1a[2], the distance between the semiconductor layer SC1a[2] and the conductive layer ME6a used as the gate is shorter than the distance between the semiconductor layer SC1a[1] and the conductive layer ME6a. Therefore, the transistor MNA may sometimes become always-on. In other words, when the gate-source voltage is 0V, the drain current (sometimes called the cutoff current) flowing through the source-drain may sometimes increase. At this time, if the transistor MNA is an n-channel transistor, the threshold voltage may sometimes decrease. Therefore, the conductivity of the material used for the semiconductor layer SC1a[2] is preferably at least lower than the conductivity of the material used for the semiconductor layer SC1a[1].

[0239] The thickness of the semiconductor layer SC1a is preferably 5 nm or more and 20 nm or less, more preferably 5 nm or more and 15 nm or less, even more preferably 3 nm or more and 12 nm or less, and even more preferably 1 nm or more and 10 nm or less.

[0240] The thickness of the semiconductor layers (here, semiconductor layer SC1a[1] and semiconductor layer SC1a[2]) included in semiconductor layer SC1a can be determined in such a way that the thickness of semiconductor layer SC1a is within the aforementioned range. The thickness of semiconductor layer SC1a can be determined in such a way that the contact resistance between semiconductor layer SC1a and conductive layer ME3ga and the contact resistance between semiconductor layer SC1a and conductor ME5 are within the required range. In addition, the thickness of semiconductor layer SC1a[2] can be determined in such a way that the threshold voltage of transistor is within the required range. Furthermore, the thickness of semiconductor layer SC1a[1] can be equal to or different from the thickness of semiconductor layer SC1a[2].

[0241] In addition, between semiconductor layer SC1a[1] and semiconductor layer SC1a[2], the ratio of the thickness of the portion of the top surface of conductive layer ME5 that becomes the formed surface to the thickness of the portion of the side surface of conductive layer ME5 and the portion of the side surface of insulating layer IS4 that becomes the formed surface is sometimes different.

[0242] Note that the above examples show a single-layer structure of semiconductor layer SC1a and a two-layer stacked structure of semiconductor layer SC1a[1] and semiconductor layer SC1a[2], but the present invention is not limited to these. Semiconductor layer SC1a may also have a stacked structure of three or more layers.

[0243] Figure 8B This is a cross-sectional schematic diagram of a transistor MNA, in which the semiconductor layer SC1a has a stacked structure including semiconductor layer SC1a[1], semiconductor layer SC1a[2], and semiconductor layer SC1a[3]. Furthermore, with... Figure 8A same, Figure 8B Also magnified Figure 7AThe diagram shows a cross-sectional view of a transistor MNA. (As shown) Figure 8B As shown, semiconductor layer SC1a[2] is located on the top surface of semiconductor layer SC1a[1], and semiconductor layer SC1a[3] is located on the top surface of semiconductor layer SC1a[2].

[0244] The atomic ratio of element M relative to In in the oxide semiconductor used for semiconductor layer SC1a[1] is preferably greater than the atomic ratio of element M relative to In in the oxide semiconductor used for semiconductor layer SC1a[2]. By adopting such a structure, the diffusion of impurities and oxygen from the structures formed on the outside of semiconductor layer SC1a to semiconductor layer SC1a[2] can be suppressed. In addition, the diffusion of elements contained in insulating layer IS4, conductive layer ME3ga or conductive layer ME5 to semiconductor layer SC1a[2] can be suppressed.

[0245] exist Figure 8B In this configuration, the distance between the semiconductor layer SC1a[3] and the conductive layer ME6a used as the gate is shorter than the distance between the semiconductor layers SC1a[1] and SC1a[2] and the conductive layer ME6a. Therefore, the conductivity of the material used for the semiconductor layer SC1a[3] is preferably lower than the conductivity of the materials used for the semiconductor layers SC1a[1] and SC1a[2]. As a result, when the transistor MNA is an n-channel transistor, its threshold voltage can be increased, and a transistor with a small cutoff current can be realized.

[0246] Furthermore, the carrier concentration of the second oxide semiconductor contained in the semiconductor layer SC1a[2] is preferably higher than that of the third oxide semiconductor contained in the semiconductor layer SC1a[3]. By increasing the carrier concentration of the second oxide semiconductor contained in the semiconductor layer SC1a[2], the conductivity increases, thereby enabling the realization of a transistor with a large on-state current. Furthermore, by decreasing the carrier concentration of the third oxide semiconductor contained in the semiconductor layer SC1a[3], the conductivity decreases, thereby enabling the realization of a normally off transistor.

[0247] Here, although an example is shown of using a material with higher conductivity than semiconductor layer SC1a[3] for semiconductor layer SC1a[2], one aspect of the invention is not limited thereto. Semiconductor layer SC1a[2] may also use a material with lower conductivity than semiconductor layer SC1a[3]. Furthermore, the carrier concentration of the second oxide semiconductor contained in semiconductor layer SC1a[2] may be lower than the carrier concentration of the third oxide semiconductor contained in semiconductor layer SC1a[3].

[0248] The band gap of the second oxide semiconductor used in the semiconductor layer SC1a[2] is preferably different from the band gap of the third oxide semiconductor used in the semiconductor layer SC1a[3]. For example, the difference between the band gap of the second oxide semiconductor and the band gap of the third oxide semiconductor is preferably 0.1 eV or more, more preferably 0.2 eV or more, and even more preferably 0.3 eV or more.

[0249] The band gap of the second oxide semiconductor used in semiconductor layer SC1a[2] can be lower than that of the third oxide semiconductor used in semiconductor layer SC1a[3]. This increases the on-state current of transistor MNA. Furthermore, when transistor MNA is an n-channel transistor, its threshold voltage can be increased, enabling a normally off transistor.

[0250] Here, although an example is shown where the band gap of the second oxide semiconductor is smaller than that of the third oxide semiconductor, the invention is not limited to this. The band gap of the second oxide semiconductor may also be larger than that of the third oxide semiconductor.

[0251] In addition, the composition of the first oxide semiconductor used for semiconductor layer SC1a[1] may be the same as or different from the composition of the third oxide semiconductor used for semiconductor layer SC1a[3].

[0252] For example, as the semiconductor layer SC1a[1], a metal oxide with an In:Ga:Zn ratio of 1:1:1 or similar can also be used as the semiconductor layer SC1a[2]. Alternatively, a metal oxide with an In:Zn ratio of 1:1 or similar, a metal oxide with an In:Zn ratio of 4:1 or similar, or an indium oxide can also be used as the semiconductor layer SC1a[3]. Furthermore, a metal oxide with an In:Ga:Zn ratio of 1:1:1 or similar can also be used. By adopting this structure, the on-state current of the transistor MNA can be increased, and a high-reliability transistor structure with less non-uniformity can be realized.

[0253] Furthermore, by using an oxide semiconductor as the semiconductor layer SC1a and providing a conductive layer in contact with the semiconductor layer SC1a (in... Figure 6A and Figure 7A In the case of conductive layers ME3ga and ME5, the oxygen concentration near the conductor of semiconductor layer SC1a sometimes decreases. Furthermore, a metal compound layer containing the metal from the conductor and components of semiconductor layer SC1a may sometimes form near the conductor of semiconductor layer SC1a. In this case, the carrier concentration in the region near the conductor of semiconductor layer SC1a increases, and this region becomes a low-resistance region.

[0254] The semiconductor layer SC1a can be made of materials containing silicon, in addition to metal oxides. Examples of silicon include amorphous silicon, microcrystalline silicon, polycrystalline silicon (including low-temperature polycrystalline silicon (LTPS)), or monocrystalline silicon. Furthermore, during the formation of the semiconductor layer SC1a in the opening KK2va, the interface and vicinity of the semiconductor region of the semiconductor layer SC1a that contacts the conductive layers ME3ga and ME5 are preferably formed as low-resistance regions. Thus, a low-resistance region and a semiconductor region are formed in the semiconductor layer SC1a, so the transistor MNA can be a Si transistor.

[0255] Note that in this embodiment, the case where the semiconductor layer SC1a contains a metal oxide used as an oxide semiconductor is described.

[0256] Furthermore, the above description of semiconductor layer SC1a can also be applied to semiconductor layer SC1b, semiconductor layer SC2a and semiconductor layer SC2b disposed in opening KK2gb.

[0257] like Figure 6A and Figure 7A As shown, an insulating layer GI3 is disposed on the top surface of the insulating layer BI4, the side and top surfaces of the conductive layer ME5, and the top surface of the semiconductor layer SC1a. Additionally, the insulating layer GI3 is also disposed on the top surface of the semiconductor layer SC1a in the opening KK2va. Similarly, the insulating layer GI3 is also disposed on the top surface of the semiconductor SC1b in the opening KK2vb.

[0258] Insulating layer GI3 is used, for example, as the gate insulating film of transistors MNA and MNB. By disposing insulating layer GI3 on ​​the top surface of insulating layer BI4, the side and top surfaces of conductive layer ME5, the top surface of semiconductor layer SC1a, and the top surface of semiconductor layer SC1b, direct contact between conductive layer ME6a and semiconductor layer SC1a, and short circuit, can be prevented. Similarly, direct contact between conductive layer ME6b and semiconductor layer SC1b, and short circuit, can also be prevented.

[0259] As the insulating layer GI3, it is preferable to use an insulator containing so-called high-k materials such as alumina, hafnium oxide, tantalum oxide, zirconium oxide, lead zirconate titanate (PZT), strontium titanate (SrTiO3), or (Ba,Sr)TiO3 (BST) as a single layer or in a stack. Alternatively, the insulating layer GI3 may also use an insulator with a relatively high dielectric constant, such as oxides containing aluminum and hafnium, oxynitrides containing aluminum and hafnium, oxides containing silicon and hafnium, oxynitrides containing silicon and hafnium, or nitrides containing silicon and hafnium.

[0260] As transistors become miniaturized or highly integrated, problems such as leakage current sometimes occur due to the thinning of the gate insulating film. By using a high-k material as the insulating layer used as the gate insulating film, the gate potential during transistor operation can be reduced while maintaining the physical thickness.

[0261] Alternatively, the insulating layer GI3 can also be an insulating layer stacked with the aforementioned high-k material and silicon oxide or silicon oxynitride. Thus, an insulating layer with a high relative permittivity and thermal stability can be used as the gate insulating film for transistors MNA and MNB.

[0262] The insulating layer GI3 can be a single-layer structure or a stacked structure obtained by sequentially depositing two or more layers of insulating material. For example, when the insulating layer GI3 has a single-layer structure, the distance between the conductive layer ME6a, which serves as the gate, and the semiconductor layer SC1a is shorter, thereby making it easier for the electric field generated from the conductive layer ME6a to affect the channel formation region formed in the semiconductor layer SC1a. As a result, the on-state current of the transistor MNA can be increased and the frequency characteristics can be improved. Similarly, the distance between the conductive layer ME6b, which serves as the gate, and the semiconductor layer SC1b is shorter, thereby making it easier for the electric field generated from the conductive layer ME6b to affect the channel formation region formed in the semiconductor layer SC1b. As a result, the on-state current of the transistor MNB can be increased and the frequency characteristics can be improved.

[0263] Furthermore, when the insulating layer GI3 has a stacked structure, in the region where the conductive layer ME6a used as the gate overlaps with the conductive layer ME5 used as the source or drain, the gate capacitance formed between the conductive layers ME5 and ME6a is reduced, thus preventing a decrease in the switching characteristics of the transistor MNA. Similarly, in the region where the conductive layer ME6b used as the gate overlaps with the conductive layer ME5 used as the source or drain, the gate capacitance formed between the conductive layers ME5 and ME6b is reduced, thus preventing a decrease in the switching characteristics of the transistor MNA.

[0264] Note that when semiconductor layers SC1a and SC1b contain metal oxides used as oxide semiconductors, it is preferable to perform microwave processing in an oxygen-containing atmosphere after the formation of insulating layer GI3 (at the latest before the formation of conductive layers ME6a and ME6b). Here, microwave processing refers, for example, to processing using a device including a power supply that generates high-density plasma using microwaves. Furthermore, in this specification, microwaves refer to electromagnetic waves with frequencies of 300 MHz or higher and 300 GHz or lower. Note that when insulating layer GI1 has a stacked structure, microwave processing can also be performed during the stage of depositing the film that forms insulating layer GI3. For example, when insulating layer GI3 comprises a silicon oxide film or a silicon oxynitride film, this microwave processing can also be performed during the stage of depositing the silicon oxide film or the silicon oxynitride film.

[0265] Furthermore, microwave processing can utilize high frequencies such as microwaves or RF, oxygen plasma, oxygen free radicals, etc. Moreover, when performing microwave processing, it is preferable to use a microwave processing apparatus that includes a power supply for generating high-density plasma using microwaves. Here, the frequency of the microwave processing apparatus is set to 300 MHz or more and 300 GHz or less, preferably 2.4 GHz or more and 2.5 GHz or less, for example, 2.45 GHz. By using high-density plasma, high-density oxygen free radicals can be generated. Additionally, the power of the power supply for applying microwaves to the microwave processing apparatus can be 1000 W or more and 10000 W or less, preferably 2000 W or more and 5000 W or less. Furthermore, the microwave processing apparatus may also include a power supply that applies RF to one side of the substrate. Furthermore, by applying RF to one side of the substrate, oxygen ions generated by high-density plasma can be efficiently introduced into the semiconductor SC1a and semiconductor layer SC1b, which are metal oxides. Through the action of plasma, microwaves, etc., the Vo contained in the regions of semiconductor layer SC1a and semiconductor layer SC1b can be increased. O H separates to remove hydrogen from this region. In other words, the amount of V contained in this region can be reduced. O H. This can reduce oxygen vacancies and V in this region. O H reduces the carrier concentration. Furthermore, by supplying oxygen free radicals generated in the oxygen plasma to the oxygen vacancies formed in this region, the oxygen vacancies in this region can be further reduced, thereby reducing the carrier concentration.

[0266] like Figure 6A and Figure 7A As shown, as an example, the conductive layer ME6a is formed by embedding an opening KK2va in the region where the conductive layers ME3ga and ME5 overlap on the insulating layer GI3. Furthermore, as... Figure 6A As shown, as an example, the conductive layer ME6b is formed by embedding an opening KK2vb in the region where the conductive layer ME3gb and the conductive layer ME5 overlap on the insulating layer GI3.

[0267] A portion of the conductive layer ME6a is used, for example, as the gate electrode of the transistor MNA. Similarly, a portion of the conductive layer ME6b is used, for example, as the gate electrode of the transistor MNB.

[0268] The conductive layers ME6a and ME6b may, for example, be made of materials or structures that can be used for conductive layers ME2ga, ME2gb, ME2da, ME2db, ME3ga, ME3gb, ME3da, ME3db, or ME5.

[0269] The above-mentioned transistor MNA, such as Figure 6A , Figure 6B and Figure 7A As shown, it has the following structure: the conductive layer used as the source and the conductive layer used as the drain are located at different heights, and the current flowing through the semiconductor layer SC1a flows in the height direction. Similarly, the transistor MNB is also as shown... Figure 6A and Figure 6B The structure shown has the following configuration: the conductive layer used as the source and the conductive layer used as the drain are located at different heights, and the current flowing through the semiconductor layer SC1b flows in the height direction. In other words, it can be said that the channel length direction includes a component in the height direction (vertical direction or Z direction). Therefore, transistors MNA and MNB can also be called VFET (Vertical Field Effect Transistor), vertical transistor, vertical channel transistor, vertical channel type transistor, etc. Furthermore, the channel length of each transistor MNA and MNB includes a component along the side of the opening, so for example, it is easy to make the channel length of transistors MNA and MNB shorter than the channel length of planar transistors. In addition, compared with planar transistors, transistors MNA and MNB can reduce their formation area.

[0270] Therefore, by employing a vertically channeled transistor in each of the transistors MNA and MNB, the on-state current of each transistor can be increased. Furthermore, generally, the on-state current of a Si transistor is greater than that of an OS transistor. However, by using Si transistors as transistors MPA and MPB, and vertically channeled transistors with an oxide semiconductor layer in the semiconductor layer as transistors MNA and MNB, the on-state currents of each transistor MNA and MNB can be made closer to those of each transistor MPA and MPB. In other words, the balance between charge carriers (electrons) flowing through transistor MNA and those (holes) flowing through transistor MPB is more balanced, and similarly, the balance between charge carriers (electrons) flowing through transistor MNB and those (holes) flowing through transistor MPA is more balanced. Therefore, this can sometimes lead to more proper operation of the memory circuit MCR.

[0271] Next, the contact between conductive layer ME6a of layer SS2 and conductive layer ME7a of layer SS3, and the contact between conductive layer ME6b of layer SS2 and conductive layer ME7b of layer SS3, included in the memory circuit MCRA, will be explained. Furthermore, the conductive layers ME4ga, ME4gb, ME4da, and ME4db included in layer SS2 will also be explained in the following description.

[0272] Figure 9A This is a summary showing Figure 1A cross-sectional schematic diagram of the laminated structure of insulating layers IS4 to IS6. Additionally, Figure 9B This is a planar schematic diagram of the stack of insulating layers IS4 to IS6. Figure 9A It is along Figure 9B The diagram shows a cross-sectional view of the laminate from insulating layer IS4 to conductive layer IS6, as indicated by the dotted lines A1-A2. Additionally, Figure 10A It is along Figure 9B The diagram shows a cross-sectional view of the laminated structure of insulating layers IS4 to IS6, as indicated by the dotted lines A3-A4. Additionally, Figure 10B It is along Figure 9B The diagram shows a cross-sectional view of the laminated structure of insulating layers IS4 to IS6, as indicated by the dotted lines A5-A6. Note that this is for convenience. Figure 10A and Figure 10B The stack of insulating layers BI2 to BI3 is also shown in the abstract.

[0273] Note that in Figure 9B In order to clearly show the positional relationship between the conductive layer and the semiconductor layer, the insulating layer and other components included in the memory circuit MCRA are omitted.

[0274] exist Figure 9A , Figure 10A and Figure 10B In the middle, an insulating layer IS5 is provided on the insulating layer GI3, the conductive layer ME6a and the conductive layer ME6b.

[0275] Insulating layer IS5 is used as an example of an interlayer film. Therefore, insulating layer IS5 preferably contains an insulating material with a low relative permittivity. By using an insulating material with a low relative permittivity in the interlayer film, the parasitic capacitance generated between the wirings can be reduced. Therefore, as insulating layer IS5, an insulating material with a low relative permittivity that can be used in any of insulating layers IS1 to IS4 can be used.

[0276] In addition, such as Figure 10A As shown, in insulating layers IS4, BI4, GI3, and IS5, an opening KK2ga is provided in the region overlapping with conductive layer ME3ga, extending to conductive layer ME3ga. Additionally, as... Figure 10B As shown, in insulating layers IS4, BI4, GI3, and IS5, an opening KK2da leading to the conductive layer ME3da is provided in the region overlapping with the conductive layer ME3da. Additionally, although not shown, in insulating layers IS4, BI4, GI3, and IS5, an opening leading to the conductive layer ME3gb is provided in the region overlapping with the conductive layer ME3db, and an opening leading to the conductive layer ME3db is provided in the region overlapping with the conductive layer ME3db.

[0277] A conductive layer ME4ga is embedded in opening KK2ga. Furthermore, a conductive layer ME4da is embedded in opening KK2da. Additionally, although not shown, a conductive layer ME4gb is embedded in openings in insulating layers IS4, BI4, GI3, and IS5 that lead to conductive layer ME3gb. Furthermore, although not shown, a conductive layer ME4db is embedded in openings in insulating layers IS4, BI4, GI3, and IS5 that lead to conductive layer ME3db.

[0278] Thus, conductive layers ME3ga and ME4ga are interconnected, conductive layers ME3gb and ME4gb are interconnected, conductive layers ME3da and ME4da are interconnected, and conductive layers ME3db and ME4db are interconnected.

[0279] Conductive layers ME4ga, ME4gb, ME4da, and ME4db are used as plugs or wiring. Furthermore, similar to each of conductive layers ME2da, ME2db, ME2ga, ME2gb, and ME2c, conductive layers ME4ga, ME4gb, ME4da, and ME4db can also integrate wiring and plugs connected to the wiring. That is, a portion of the conductive layer is sometimes used as wiring, and a portion of the conductive layer is sometimes used as a plug.

[0280] The conductive layers ME4ga, ME4gb, ME4da, and ME4db can, for example, use materials or structures that are also suitable for conductive layers ME2ga, ME2gb, ME2da, ME2db, ME2c, ME3ga, ME3gb, ME3da, ME3db, ME5, ME6a, and ME6b. In particular, since conductive layers ME4ga, ME4gb, ME4da, and ME4db all function as plugs or wiring, it is preferable to use materials or structures that are also suitable for conductive layers ME2ga, ME2gb, ME2da, ME2db, or ME2c, which similarly function as plugs or wiring.

[0281] exist Figure 9A and Figure 10A In the middle, the insulating layer IS5 has an opening in the region overlapping with the conductive layer ME6a, allowing access to the conductive layer ME6a. Additionally, in... Figure 9A In the middle, the insulating layer IS5 has an opening in the region that overlaps with the conductive layer ME6b to reach the conductive layer ME6b.

[0282] In addition, Figure 9A and Figure 10A In this structure, a conductive layer ME7a is formed on the top surface of the insulating layer IS5, the side surface of the insulating layer IS5 corresponding to the side surface of the opening reaching the conductive layer ME6a, and the top surface of the conductive layer ME6a corresponding to the bottom of the opening. Additionally, in... Figure 10B In this configuration, a conductive layer ME7a is also formed on the top surface of the conductive layer ME4da. Additionally, although not shown, a conductive layer ME7a is also formed on the top surface of the conductive layer ME4gb. Therefore, as... Figure 9B As shown, the conductive layer ME7a has a T-shape when viewed from above.

[0283] In addition, Figure 9A In this structure, a conductive layer ME7b is formed on the top surface of the insulating layer IS5, the side surface of the insulating layer IS5 corresponding to the side surface reaching the opening of the conductive layer ME6b, and the top surface of the conductive layer ME6b corresponding to the bottom of the opening. Additionally, in... Figure 10A In this configuration, a conductive layer ME7b is also formed on the top surface of the conductive layer ME4ga. Additionally, although not shown, a conductive layer ME7b is also formed on the top surface of the conductive layer ME4db. Therefore, as... Figure 9B As shown, the conductive layer ME7b also has a T-shape when viewed from above.

[0284] Thus, conductive layers ME6a, ME4da, and ME4gb are interconnected through conductive layer ME7a. Similarly, conductive layers ME6b, ME4db, and ME4ga are interconnected through conductive layer ME7b. Therefore, both conductive layers ME7a and ME7b are used for wiring.

[0285] Note that in Figure 9B In this invention, both conductive layers ME7a and ME7b have a T-shape, but the structure of the storage circuit according to one embodiment of the invention is not limited to this. The shape of conductive layers ME7a or ME7b can also be a three-way Y-shape similar to the T-shape. Furthermore, in conductive layer ME7a, if conductive layers ME6a, ME4da, and ME4gb are interconnected, the shape of conductive layer ME7a may not be a T-shape or a Y-shape. Similarly, in conductive layer ME7b, if conductive layers ME6b, ME4db, and ME4ga are interconnected, the shape of conductive layer ME7a may not be a T-shape or a Y-shape.

[0286] Additionally, conductive layer ME7a is used as one of the source and drain electrodes of transistor MWA. Conversely, conductive layer ME7b is used as one of the source and drain electrodes of transistor MWB.

[0287] The conductive layers ME7a and 7b may, for example, be made of materials applicable to conductive layers ME1a, ME1b, ME2a, ME2b, ME2c, ME3da, ME3db, ME3ga, ME3gb, ME4da, ME4db, ME4ga, ME4gb, ME5, ME6a, and ME6b. In particular, the conductive layers ME7a and 7b are preferably made of materials or structures applicable to conductive layers ME3da, ME3db, ME3ga, and ME3gb that have wiring functionality.

[0288] Insulating layer BI5 and insulating layer IS6 are sequentially disposed on insulating layer IS5, conductive layer ME7a and conductive layer ME7b.

[0289] Insulating layer BI5 is used as an example to serve as a barrier insulating film separating insulating layer IS6 from conductive layers ME7a and ME7b. Specifically, insulating layer BI5 serves as a barrier insulating film to inhibit the diffusion of impurities from insulating layer IS6 into conductive layers ME7a or ME7b. Here, impurities can be exemplified by, for example, oxygen, which causes a decrease in conductivity of conductive layers ME7a or ME7b due to oxidation. Therefore, as insulating layer BI5, an insulating material that can be used as a barrier insulating film to inhibit the diffusion of oxygen, suitable for any of insulating layers BI1 to BI4, can be used.

[0290] Insulating layer IS6 is used as an example of an interlayer film. Therefore, insulating layer IS6 preferably comprises an insulating material with a low relative permittivity. By using an insulating material with a low relative permittivity in the interlayer film, parasitic capacitance generated between the wirings can be reduced. Therefore, as insulating layer IS6, an insulating material with a low relative permittivity that can be used in any of insulating layers IS1 to IS5 can be used.

[0291] Next, the layer SS3, which is the stack of conductive layer ME7a and conductive layer ME7b to insulating layer IS8 included in the storage circuit MCRA, will be described.

[0292] Figure 11A This is a summary showing Figure 1 A schematic cross-sectional view of layer SS3 from conductive layer ME7a and conductive layer ME7b to insulating layer IS8. Additionally, Figure 11B This is a schematic plan view of layer SS3, which is a stack consisting of conductive layers ME7a and ME7b to insulating layer IS8. Note that... Figure 11A The cross-sectional diagram is equivalent to along Figure 11BThe diagram shown, with dotted lines A1-A2, illustrates a cross-sectional view of layer SS3, which forms the stack of conductive layers ME7a, ME7b, and IS8. Additionally, Figure 12A It is along Figure 11B The diagram shows a cross-sectional view of the stack from conductive layer ME7a and conductive layer ME7b to insulating layer IS8, as indicated by the dotted lines A3-A4. Additionally, Figure 12B It is along Figure 11B The diagram shown in the dotted lines A5-A6 is a cross-sectional view of layer SS3, which is the stack of conductive layer ME7a and conductive layer ME7b to insulating layer IS8.

[0293] Note that in Figure 11B In order to clearly show the positional relationship between the conductive layer and the semiconductor layer, the insulating layer and other components included in the memory circuit MCRA are omitted.

[0294] exist Figure 1 , Figure 11A and Figure 11B In the insulating layer IS6, an insulating layer BI6 is provided. Furthermore, conductive layers ME8a and ME8b are provided on the insulating layer BI6. Specifically, conductive layer ME8a extends along the -Y and +Y directions with a region overlapping with conductive layer ME6a. Similarly, conductive layer ME8b extends along the -Y and +Y directions with a region overlapping with conductive layer ME6b.

[0295] Insulating layer BI6 is used as an example to serve as a barrier insulating film separating insulating layer IS6 from conductive layers ME8a and ME8b. Specifically, insulating layer BI6 serves as a barrier insulating film to inhibit the diffusion of impurities from insulating layer IS6 into conductive layers ME8a or ME8b. Here, impurities can be exemplified by, for example, oxygen, which causes a decrease in conductivity of conductive layers ME8a or ME8b due to oxidation. Therefore, as insulating layer BI6, an insulating material that can be used as a barrier insulating film to inhibit oxygen diffusion in any of insulating layers BI1 to BI5 can be used.

[0296] A portion of the conductive layer ME8a is used as one of the source and drain electrodes of transistor MWA, and a portion of the conductive layer ME8b is used as one of the source and drain electrodes of transistor MWB.

[0297] Conductive layers ME8a and ME8b extend along the Y direction, and are therefore used, for example, as wiring. Furthermore, this wiring is equivalent to... Figure 2A and Figure 2B The described wiring BL and wiring BLB are as follows: that is, the conductive layer ME8a is used as the wiring BL for transmitting or reading data, and the conductive layer ME8b is used as the wiring BLB for transmitting or reading data.

[0298] Conductive layers ME8a and ME8b may, for example, use materials or structures applicable to conductive layers ME1a, ME1b, ME2da, ME2db, ME2ga, ME2gb, ME2c, ME3da, ME3db, ME3ga, ME3gb, ME4da, ME4db, ME4ga, ME4gb, ME5, ME6a, ME6b, ME7a, and ME7b. In particular, conductive layers ME8a and ME8b preferably use materials or structures applicable to conductive layer ME5, which has a wiring function.

[0299] In addition, such as Figure 1 , Figure 11A and Figure 12A As shown, insulating layer IS6, insulating layer BI6, and conductive layer ME8a have regions overlapping with conductive layers ME6a and ME7a. Furthermore, insulating layer IS6, insulating layer BI6, and conductive layer ME8a have openings KK3va in these regions that extend to conductive layer ME7a. Additionally, as... Figure 1 and Figure 11A As shown, insulating layer IS6, insulating layer BI6, and conductive layer ME8b have regions that overlap with conductive layers ME6b and ME7b. Furthermore, insulating layer IS6, insulating layer BI6, and conductive layer ME8b are provided with openings KK3vb in these regions that extend to conductive layer ME7b.

[0300] A semiconductor layer SC2a is disposed on each side of the insulating layer IS6, the insulating layer BI6, and the conductive layer ME8a, corresponding to the side of the opening KK3va; on the top surface of the conductive layer ME7a, corresponding to the bottom of the opening KK3va; and on the top surface of the conductive layer ME8a. In other words, it can be said that the semiconductor layer SC2a has a region that contacts the top surface of the conductive layer ME7a, the side of the insulating layer IS6, the side of the insulating layer BI6, and the side and top surfaces of the conductive layer ME8a.

[0301] Similarly, a semiconductor layer SC2b is disposed on each side of the insulating layer IS6, the insulating layer BI6, and the conductive layer ME8b, corresponding to the side of the opening KK3vb; on the top surface of the conductive layer ME7b, corresponding to the bottom of the opening KK3vb; and on the top surface of the conductive layer ME8b. In other words, it can be said that the semiconductor layer SC2b has a region that contacts the top surface of the conductive layer ME7b, the side of the insulating layer IS6, the side of the insulating layer BI6, and the side and top surfaces of the conductive layer ME8b.

[0302] Semiconductor layers SC2a and SC2b can, for example, be made of materials suitable for semiconductor layers SC1a and SC1b. Therefore, semiconductor layers SC2a and SC2b can, for example, be metal oxides used as oxide semiconductors. Note that in this embodiment, the case where semiconductor layers SC2a and SC2b comprise metal oxides used as oxide semiconductors is described.

[0303] like Figure 11A and Figure 12A As shown, an insulating layer GI4 is disposed on the top surface of the insulating layer BI6, the side and top surfaces of the conductive layer ME8a, the side and top surfaces of the conductive layer ME8b, the top surface of the semiconductor layer SC2a, and the top surface of the semiconductor layer SC2b. Additionally, the insulating layer GI4 is also disposed on the top surface of the semiconductor layer SC2a in the opening KK3va. Similarly, the insulating layer GI4 is also disposed on the top surface of the semiconductor layer SC2b in the opening KK3vb.

[0304] The insulating layer GI4 is used, for example, as the gate insulating film of transistors MWA and MVB. By providing the insulating layer GI4 on the top surface of the insulating layer BI6, the side and top surfaces of the conductive layer ME8a, the top surface of the semiconductor layer SC2a, and the top surface of the semiconductor layer SC2b, direct contact between the conductive layer ME9a (described later) and the semiconductor layer SC2a and short circuit can be prevented. Similarly, direct contact between the conductive layer ME9b (described later) and the semiconductor layer SC2b and short circuit can be prevented.

[0305] For example, insulating layer GI4 can use materials or structures that are also suitable for insulating layer GI3.

[0306] like Figure 1 , Figure 11A and Figure 12A As shown, as an example, the conductive layer ME9a is formed by embedding an opening KK3va in the region where the conductive layers ME6a, ME7a, and ME8a overlap on the insulating layer GI4. Furthermore, as... Figure 11A As shown, as an example, the conductive layer ME9b is formed by embedding an opening KK3vb in the region where the conductive layers ME6b, ME7b and ME8b overlap on the insulating layer GI4.

[0307] A portion of the conductive layer ME9a is used, for example, as the gate electrode of transistor MWA. Similarly, a portion of the conductive layer ME9b is used, for example, as the gate electrode of transistor MWB.

[0308] The conductive layers ME9a and ME9b can, for example, use materials that are also suitable for conductive layers ME1a, ME1b, ME2da, ME2db, ME2ga, ME2gb, ME2c, ME3da, ME3db, ME3ga, ME3gb, ME4da, ME4db, ME4ga, ME4gb, ME5, ME6a, ME6b, ME7a, ME7b, ME8a, and ME8b. In particular, the conductive layers ME9a and ME9b are preferably made of materials or structures that are also suitable for conductive layers ME6a and ME6b, which similarly function as the gate of a transistor.

[0309] As mentioned above, such as Figure 11A , Figure 11B and Figure 12A As shown, transistors MWA and MWB can both be the same vertical channel transistors as transistors MNA and MNB. Therefore, for the structures of transistors MWA and MWB, please refer to the descriptions of transistors MNA and MNB.

[0310] exist Figure 11A , Figure 12A and Figure 12B In the middle, an insulating layer IS7 is provided on the insulating layer GI4, the conductive layer ME9a and the conductive layer ME9b.

[0311] Insulating layer IS7 is used as an example of an interlayer film. Therefore, insulating layer IS7 preferably comprises an insulating material with a low relative permittivity. By using an insulating material with a low relative permittivity in the interlayer film, parasitic capacitance generated between wirings can be reduced. Therefore, as insulating layer IS7, an insulating material with a low relative permittivity that can be used in any of insulating layers IS1 to IS6 can be used.

[0312] In addition, such as Figure 11A and Figure 12A As shown, the insulating layer IS7 has an opening in the region overlapping with the conductive layer ME9a, allowing access to the conductive layer ME9a. Similarly, as... Figure 11A As shown, the insulating layer IS7 has an opening in the region overlapping with the conductive layer ME9b that leads to the conductive layer ME9b.

[0313] The conductive layer ME10a is embedded in the opening of the insulating layer IS7 to reach the conductive layer ME9a, and the conductive layer ME10b is embedded in the opening of the insulating layer IS7 to reach the conductive layer ME9b.

[0314] Thus, conductive layer ME10a and conductive layer ME9a are interconnected, and conductive layer ME10b and conductive layer ME9b are interconnected.

[0315] Conductive layers ME10a and ME10b are used as plugs or wiring. Furthermore, similar to each of conductive layers ME2da, ME2db, ME2ga, ME2gb, and ME2c, conductive layers ME10a and ME10b can also integrate wiring and a plug for connecting to the wiring. Similarly, similar to each of conductive layers ME3da, ME3db, ME3ga, and ME3gb, wiring and a plug for connecting to the wiring can also be integrated. That is, a portion of the conductive layer is sometimes used as wiring, and a portion of the conductive layer is sometimes used as a plug.

[0316] The conductive layers ME10a and ME10b can, for example, be made of materials that are also applicable to conductive layers ME1a, ME1b, ME2da, ME2db, ME2ga, ME2gb, ME2c, ME3da, ME3db, ME3ga, ME3gb, ME4da, ME4db, ME4ga, ME4gb, ME5, ME6a, ME6b, ME7a, ME7b, ME8a, ME8b, ME9a, and ME9b. In particular, conductive layers ME10a and ME10b are preferably made of materials or structures that can also be used for conductive layers ME2da, ME2db, ME2ga, ME2gb, ME2c, ME3da, ME3db, ME3ga, or ME3gb, which also have the function of wiring or plugging.

[0317] exist Figure 11A , Figure 12A and Figure 12B In this structure, an insulating layer IS7, a conductive layer ME10a, and a conductive layer ME10b are provided with a conductive layer ME11. In particular, the conductive layer ME11 extends along the X direction such that it has a region that overlaps with the conductive layers ME10a and ME10b.

[0318] The conductive layer ME11 extends along the X direction, so it is used, for example, as wiring. This wiring is equivalent to... Figure 2A and Figure 2B The wiring WRL is described. That is, the conductive layer ME11 is used as the wiring WRL for transmitting the select signal or non-select signal in the storage circuit MCRA.

[0319] The conductive layer ME11 can, for example, use materials that are also suitable for conductive layers ME1a, ME1b, ME2da, ME2db, ME2ga, ME2gb, ME2c, ME3da, ME3db, ME3ga, ME3gb, ME4da, ME4db, ME4ga, ME4gb, ME5, ME6a, ME6b, ME7a, ME7b, ME8a, ME8b, ME9a, ME9b, ME10a, and ME10b. In particular, the conductive layer ME11 is preferably made of materials or structures that are also suitable for conductive layers ME3da, ME3db, ME3ga, ME3gb, ME5, ME7a, ME7b, ME8a, or ME8b, which also have wiring functionality.

[0320] exist Figure 11A , Figure 12A and Figure 12B In the middle, an insulating layer BI7 is provided on the insulating layer IS7 and the conductive layer ME11. In addition, an insulating layer IS8 is provided on the insulating layer BI7.

[0321] Insulating layer BI7 is used as an example of a barrier insulating film separating insulating layer IS8 from conductive layer ME11. Specifically, insulating layer BI7 is used as a barrier insulating film to inhibit the diffusion of impurities from insulating layer IS8 to conductive layer ME11. Here, impurities can be exemplified by, for example, oxygen, which causes a decrease in conductivity of conductive layer ME11 due to oxidation. Therefore, as insulating layer BI7, an insulating material that can be used as a barrier insulating film to inhibit the diffusion of oxygen, suitable for any of insulating layers BI1 to BI6, can be used.

[0322] Insulating layer IS8 is used as an example of an interlayer film. Therefore, insulating layer IS8 preferably contains an insulating material with a low relative permittivity. By using an insulating material with a low relative permittivity in the interlayer film, parasitic capacitance generated between the wirings can be reduced. Therefore, as insulating layer IS8, an insulating material with a low relative permittivity that can be used in any of insulating layers IS1 to IS7 can be used.

[0323] As described above, by constituting Figure 1 , Figures 3 to 12B The MCRA storage circuit shown can realize a storage circuit with a smaller circuit area.

[0324] Furthermore, when forming n-channel and p-channel transistors on the substrate BS, existing techniques require designing the n-channel and p-channel transistors separately from each other. However, as mentioned above, by using p-channel transistors as transistors MPA and MPB in layer SS1, transistors MPA and MPB can be formed close together. This also helps to reduce the area of ​​the memory circuit MCRA.

[0325] Furthermore, by setting transistors MNA and MNB as n-channel transistors in layer SS2, it is not necessary to form wiring for supplying low power potential on the substrate BS of layer SS1 (equivalent to...). Figure 1 and Figure 3 The conductive layer ME5 or Figure 2A (VE2 in the diagram). In other words, since it is not necessary to form both sides of the wiring supplying the low power supply potential and the wiring supplying the high power supply potential on the substrate BS, this also helps to reduce the area of ​​the memory circuit MCRA.

[0326] Note that the storage circuit of one embodiment of the present invention is not limited to the one described above. Figure 1 , Figures 3 to 12B The structure of the storage circuit MCRA shown is illustrated. For example, the storage circuit of one embodiment of the present invention can also be modified according to the circumstances.

[0327] <Example of Variation 1>

[0328] For example, such as Figure 13 As shown in the three-dimensional schematic diagram, the conductive layer ME5 can also extend along the Y direction but not along the X direction. In this case, Figure 13 The storage circuit MCRA0 shown has a structure in which conductive layers ME5 and ME0 overlap. That is, wiring VE1, which supplies a high power supply potential to operate conductive layer ME0, and wiring VE2, which supplies a low power supply potential to operate conductive layer ME5, can be along the same direction (…). Figure 13 (All are in the Y direction) overlapping.

[0329] in addition, Figure 14 The cross-sectional schematic diagram is in Figure 13 A schematic diagram divided along the XZ plane in a three-dimensional illustration. For example... Figure 14 As shown, the wiring ME5 in the storage circuit MCRA0 is... Figure 1 and Figure 3 Unlike the MCRA1 memory circuit, which extends along the Y direction instead of the X direction, the conductive layer ME5 and conductive layer ME0 extend overlapping each other along the same Y direction. Note that in Figure 14 In order to clearly show wiring VE1 and wiring VE2, the symbols for wiring VE1 and wiring VE2 are also shown.

[0330] As described above, by making the low-resistance region LRAc, which is part of wiring VE1, and the conductive layer ME0, which is part of wiring VE2, extend in the same direction, the circuit for generating a high power supply potential and the circuit for generating a low power supply potential can be configured together in one of the row driver and the column driver. This reduces the circuit area of ​​the memory device, including the memory circuitry.

[0331] <Example 2 of the variation>

[0332] In addition, for example, such as Figure 15 Similar to the storage circuit MCRA1 shown, it can also adopt the following structure: conductive layers ME2da and ME4da overlap each other, conductive layers ME2db and ME4db overlap each other, conductive layers ME2ga and ME4ga overlap each other, and conductive layers ME2gb and ME4gb overlap each other. Therefore, the regions where conductive layers ME1a and ME1b are formed, and the regions where low-resistance regions LRAa and LRAb are formed, differ from those in storage circuit MCRA1.

[0333] Figure 16B This is a plan view of layer SS1 at this point. Additionally, Figure 16A It is along Figure 16B The cross-sectional diagram of the dotted line A1-A2 shown is as follows. Figure 17 It is along Figure 16B The cross-sectional diagram of the dotted line A3-A4 is shown.

[0334] Note that in Figure 16B In order to clearly show the positional relationship between the conductive layer and the semiconductor layer, the insulating layer and other components included in the memory circuit MCRA are omitted.

[0335] like Figure 16A As shown, conductive layers ME2da and ME2db are not located on the dashed lines A1-A2, as... Figure 16B and Figure 17 As shown, the conductive layer ME2da is positioned at a offset location in the -Y direction. Additionally, as... Figure 16B As shown, the conductive layer ME2db is positioned at a offset location in the +Y direction.

[0336] Therefore, in Figure 15 and Figure 16B In the storage circuit MCRA1, the low-resistance region LRAa has a region extending in the -Y direction, on which the conductive layer ME2da is located, and the low-resistance region LRAb has a region extending in the +Y direction, on which the conductive layer ME2db is located. Additionally, in Figure 15 and Figure 16BIn the storage circuit MCRA1, the conductive layer ME1a has a region extending in the +Y direction, the conductive layer ME2ga is located on this region, and the conductive layer ME1b has a region extending in the -Y direction, the conductive layer ME2gb is located on this region.

[0337] Note that the low-resistance region LRAa and the low-resistance region LRAb each have regions extending in different directions perpendicular to the X direction in the XY plane, but these directions are not limited to... Figure 16B The direction when viewed from above. For example, when viewed from above. Figure 16B At that time, the direction of the low-resistance region LRAa can also be either the right or left direction when looking at the semiconductor region SCAa from the semiconductor region SCAa, and in the top view Figure 16B At this time, the direction of the low-resistance region LRAb's extension can also be either the right or left direction when viewed from the semiconductor region SCAa towards the semiconductor region SCAAb. In this case, when viewed from above... Figure 16B At the same time, the conductive layer ME1a may also have a region extending in a direction facing either the right or the left when viewed from the semiconductor region SCAa towards the semiconductor region SCAb, and in a top view Figure 16B In this case, the conductive layer ME1b may also have a region extending in one of the directions to the right and left when the semiconductor region SCAa is viewed from the semiconductor region SCAb.

[0338] then, Figure 18B This is a plan view of a portion of layer SS2. Additionally, Figure 18A It is along Figure 18B The cross-sectional diagram of the dotted line A1-A2 shown is as follows. Figure 19 It is along Figure 18B The cross-sectional diagram of the dotted line A3-A4 is shown.

[0339] Note that in Figure 18B In order to clearly show the positional relationship between the conductive layer and the semiconductor layer, the insulating layer and other components included in the memory circuit MCRA are omitted.

[0340] By using vertically channeled transistors as transistors MNA and MNB, and extending the low-resistance regions LRAa and LRAb in the desired direction, such as Figure 15 and Figure 18BAs shown, the electrical layer ME2da can overlap with the conductive layer ME4da, the conductive layer ME2db can overlap with the conductive layer ME4db, the conductive layer ME2ga can overlap with the conductive layer ME4ga, and the conductive layer ME2gb can overlap with the conductive layer ME4gb. This can shorten the wiring length of the conductive layers ME3da, ME3db, ME3ga, and ME3gb. In other words, when viewed from the Y direction, the overlap of conductive layers ME3da and ME3ga, ME3ga and ME3gb, and ME3db and ME3gb can be compared to... Figure 6B The case where the parasitic capacitance is small (as shown in the planar schematic of layer SS2 of the storage circuit MCRA) can be reduced. Therefore, in the XY plane, the parasitic capacitance between conductive layers ME3da and ME3ga, between conductive layers ME3db and ME3gb, and between conductive layers ME3ga and ME3gb can be reduced.

[0341] In addition, such as Figure 19 As shown, the conductive layer ME3da and the conductive layer ME5 do not overlap, so the parasitic capacitance between the conductive layer ME3da and the conductive layer ME5 can be reduced.

[0342] Therefore, it can be said that Figures 15 to 19 The parasitic capacitance ratio of the storage circuit MCRA1 shown is... Figure 1 and Figures 3 to 12B The storage circuit MCRA shown is small. Therefore, the driving speed of storage circuit MCRA1 can be increased.

[0343] <Example 3 of the variation>

[0344] in addition, Figure 3 storage circuit MCRA and Figure 15 The low-resistance region LRAC of the memory circuit MCRA1 is used as another source and drain region of transistor MPA and another source and drain region of transistor MPB. However, the other source and drain region of transistor MPA and the other source and drain region of transistor MPB can also be formed by different low-resistance regions.

[0345] Figure 20 The storage circuit MCRA2 shown is Figure 15 A modified example of the memory circuit MCRA1, in which transistors MPA and MPB are separated by the element separation layer DDV, in this respect... Figure 15 The storage circuit MCRA1 is different. Therefore, the structures of layers SS2 and SS3 are different.

[0346] in addition, Figure 20The storage circuit MCRA2 shown is... Figure 15 The difference in the storage circuit MCRA1 is that: Figure 20 In the storage circuit MCRA2 shown, wiring is formed by extending the low-resistance regions LRAc1 and LRAc2 (described later) in the Y direction without using the conductive layer ME0. Alternatively, wiring can also be formed in... Figure 20 The storage circuit MCRA2 shown is related to Figure 15 The storage circuit MCRA1 is similarly provided with a conductive layer ME0.

[0347] in addition, Figure 21 This is a three-dimensional schematic diagram showing a structural example of a portion of the MCRA2 memory circuit. Note that... Figure 21 In order to facilitate observation of the structure of the MCRA2 memory circuit, some components such as the insulating layer have been omitted. Additionally, Figure 20 The cross-sectional diagram is along Figure 21 A schematic diagram of the XZ plane segmentation of a three-dimensional diagram.

[0348] Figure 22A This is a summary showing Figure 20 A schematic cross-sectional view of layer SS1, which forms the stack from substrate BS to insulating layer IS3. Additionally, Figure 22B This is a planar schematic diagram of layer SS1, which forms the stack from substrate BS to insulating layer IS3. Note that... Figure 20 The cross-sectional diagram is equivalent to along Figure 22B The diagram shows a cross-sectional view of layer SS1, which forms the stack from substrate BS to insulating layer IS3, as indicated by the dashed lines C1-C2. Note that along... Figure 22B The cross-sectional schematic diagram of layer SS1, which forms the stack from substrate BS to insulating layer IS3, shown by the dotted lines C3-C4, can be referred to Figure 17 Explanation of the cross-sectional schematic diagram, along Figure 22B The cross-sectional schematic diagram of layer SS1, which forms the stack from substrate BS to insulating layer IS3, shown by the dashed lines C5-C6, can be referred to... Figure 5 Explanation of the cross-sectional schematic diagram.

[0349] Figure 20 The storage circuit MCRA2 shown has a low-resistance region LRAc1 and a low-resistance region LRAc2 in its layer SS1, but no low-resistance region LRAc. The low-resistance region LRAc1 is used as another of the source and drain regions of transistor MPA, and the low-resistance region LRAc2 is used as another of the source and drain regions of transistor MPB.

[0350] Next, an example of the structure of layer SS2 of the storage circuit MCRA2 will be described.

[0351] Figure 23AThis is a summary showing Figure 20 A cross-sectional schematic diagram of the stacked structure from insulating layer BI2 to conductive layers ME6a and ME6b is shown, omitting insulating layer IS5. Additionally, Figure 23B This is a planar schematic diagram of the stacked structure from insulating layer BI2 to conductive layers ME6a and ME6b. Note that... Figure 23A The cross-sectional diagram is equivalent to along Figure 23B The diagram shows a cross-sectional view of the stacked structure from the insulating layer BI2 to the conductive layers ME6a and ME6b, as shown by the dotted lines C1-C2.

[0352] like Figure 20 , Figure 23A and Figure 23B As shown, by replacing the low-resistance region LRAc with low-resistance regions LRAc1 and LRAc2 in layer SS1 of the storage circuit MCRA2, the distance between transistors MNA and MNB is longer compared to storage circuits MCRA and MCRA1. In other words, the distance between conductive layers ME3ga and ME3gb can be extended, thus further reducing the parasitic capacitance between them.

[0353] Next, the contact between conductive layer ME6a of layer SS2 and conductive layer ME7a of layer SS3, and the contact between conductive layer ME6b of layer SS2 and conductive layer ME7b of layer SS3, included in the storage circuit MCRA2, will be explained. Furthermore, conductive layers ME4ga, ME4gb, ME4da, and ME4db, included in layer SS2, will also be explained in the following description.

[0354] Figure 24A This is a summary showing Figure 20 A cross-sectional schematic diagram of the laminated structure of insulating layers IS4 to IS6. Additionally, Figure 24B This is a schematic plan view of the stack of insulating layers IS4 to IS6. Note that... Figure 24A The cross-sectional diagram is equivalent to along Figure 24B The diagram shows a cross-sectional view of the laminated structure of insulating layers IS4 to IS6, as indicated by the dotted lines C1-C2. Additionally, Figure 25A It is along Figure 24B The diagram shows a cross-sectional view of the laminated structure from insulating layer IS4 to insulating layer IS6, as indicated by the dotted lines C3-C4. Additionally, Figure 25B It is along Figure 24B The diagram shows a cross-sectional view of the laminated structure of insulating layers IS4 to IS6, as indicated by the dotted lines C5-C6. Note that this is for convenience. Figure 25A and Figure 25B The stack of insulating layers BI2 to BI3 is also shown in the abstract.

[0355] like Figure 24B As shown, by replacing the low-resistance region LRAc with low-resistance regions LRAc1 and LRAc2 in layer SS1 of the memory circuit MCRA2, the conductive layers ME7a and ME7b can potentially become L-shaped. This is because, as mentioned above, the distance between transistors MNA and MNB is longer compared to the memory circuits MCRA and MCRA1. The L-shape of the conductive layers ME7a and ME7b further separates them, thereby reducing the parasitic capacitance between them.

[0356] Next, an example of the structure of layer SS3 of the storage circuit MCRA2 will be described.

[0357] Figure 26A This is a summary showing Figure 20 A cross-sectional schematic diagram of layer SS3, which forms the stack from conductive layer ME7a and conductive layer ME7b to insulating layer IS8. Additionally, Figure 26B This is a planar schematic diagram of layer SS3, which is the stack of conductive layers ME7a and ME7b to insulating layer IS8. Note that... Figure 26A The cross-sectional diagram is equivalent to along Figure 26B The diagram shown, with dotted lines C1-C2, illustrates a cross-sectional view of layer SS3, which forms the stack of conductive layers ME7a and ME7b to insulating layer IS8. Additionally, Figure 27A Equivalent to along Figure 26B The diagram shown, with dotted lines C3-C4, illustrates a cross-sectional view of layer SS3, which forms the stack of conductive layers ME7a and ME7b to insulating layer IS8. Additionally, Figure 27B Equivalent to along Figure 26B The diagram shown shows a cross-sectional view of layer SS3, which is the stack of conductive layer ME7a and conductive layer ME7b to insulating layer IS8, as indicated by the dotted lines C5-C6.

[0358] like Figure 26B As shown, by replacing the low-resistance region LRAc with low-resistance regions LRAc1 and LRAc2 in layer SS1 of the storage circuit MCRA2, the distance between conductive layers ME8a and ME8b can be longer compared to the storage circuit MCRA and MCRA1. This reduces the parasitic capacitance between conductive layers ME8a and ME8b.

[0359] By Figure 20 The storage circuit MCRA2 shown is used as Figure 2AThe storage circuit MCR can reduce its area and parasitic capacitance. This allows for miniaturization of the processing device including the storage circuit MCR and increases its driving frequency.

[0360] <Example 4 of the variation>

[0361] like Figure 2C As shown, Figure 1 The storage circuit MCRA shown can be modified to have a back gate in each of transistors MNA, MNB, MWA, and MWB.

[0362] Figure 28 The storage circuit MCRA3 shown has in Figure 1 The memory circuit MCRA has a back gate structure in each of the transistors MNA, MNB, MWA and MWB.

[0363] Figure 28 The storage circuit MCRA3, in addition to Figure 1 In addition to the constituent elements of the storage circuit MCRA, it also includes insulating layer BGI1a, insulating layer BGI1b, insulating layer BI11, insulating layer BI12, conductive layer BM1a, conductive layer BM1b, insulating layer BGI2a, insulating layer BI13, insulating layer BI14, insulating layer BGI2b, conductive layer BM2a, and conductive layer BM2b.

[0364] in addition, Figure 28 The storage circuit MCRA3 is equipped with a function equivalent to Figure 1 The insulating layers IS4x and IS4y of the storage circuit MCRA, and the equivalent Figure 1 The insulating layers IS5, IS6x, and IS6y of the storage circuit MCRA.

[0365] The following only explains Figure 28 The storage circuit MCRA3 in the and Figure 1 Different parts of the storage circuit MCRA.

[0366] In layer SS2, insulating layer IS4x, insulating layer BI11, conductive layer BM1a and conductive layer BM1b are sequentially stacked on insulating layer BI3.

[0367] In particular, conductive layer BM1a is formed in a region that overlaps with the opening formed on the upper part of conductive layer ME3ga, and conductive layer BM1b is formed in a region that overlaps with the opening formed on the upper part of conductive layer ME3gb. Furthermore, conductive layers BM1a and BM1b are disposed extending along the Y direction.

[0368] Conductive layers BM1a and BM1b extend along the Y direction, and are therefore used, for example, as wiring. This wiring is equivalent to... Figure 2C The wiring described is BGE2. Note that although in Figure 28 The conductive layers BM1a and BM1b are represented as different wirings, but as... Figure 2C As shown, conductive layers BM1a and BM1b can also be combined into the same wiring.

[0369] The conductive layers BM1a and BM1b may, for example, use materials or structures applicable to conductive layers ME1a, ME1b, ME2a, ME2b, ME3da, ME3db, ME3ga, ME3gb, ME4da, ME4db, ME4ga, ME4gb, ME5, ME6a, ME6b, ME7a, ME7b, ME8a, and ME8b. In particular, the conductive layers BM1a and BM1b are preferably made of materials or structures applicable to conductive layers ME5, ME8a, and ME8b that have wiring functionality.

[0370] As described above, the insulating layer IS4x is equivalent to Figure 1 The insulating layer IS4 of the storage circuit MCRA is used as an interlayer film.

[0371] Insulating layer BI11 is used, for example, as a barrier insulating film to inhibit the diffusion of oxygen, etc., to prevent oxidation of conductive layers BM1a and BM1b. Therefore, insulating layer BI11 can be used for... Figure 1 The material of any one of the insulating layers BI1 to BI7 of the storage circuit MCRA.

[0372] An insulating layer BI12 is disposed on the insulating layer BI11, the conductive layer BM1a, and the conductive layer BM1b. In addition, an insulating layer IS4y is disposed on the insulating layer BI12.

[0373] Similar to insulating layer BI11, insulating layer BI12 serves as a barrier insulating film to inhibit the diffusion of oxygen and other substances, thus preventing the oxidation reaction of conductive layers BM1a and BM1b. Therefore, insulating layer BI12 can be used for... Figure 1 The material of any one of the insulating layers BI1 to BI7 and BI11 of the storage circuit MCRA.

[0374] As described above, the insulating layer IS4y is equivalent to Figure 1 The insulating layer IS4 of the storage circuit MCRA is used as an interlayer film.

[0375] Furthermore, insulating layers IS4x, BI11, BM1a, BM1b, BI12, IS4y, BI4, and GI3 have openings formed in the regions overlapping with conductive layers ME3ga or ME3gb. Additionally, insulating layer BGI1a is formed on the side of the opening overlapping with conductive layer ME3ga, and insulating layer BGI1b is formed on the side of the opening overlapping with conductive layer ME3gb.

[0376] Insulating layer BGI1a is used as the back gate insulating film in transistor MNA, and insulating layer BGI1b is used as the back gate insulating film in transistor MNB.

[0377] Insulating layers BGI1a and BGI1b can, for example, be made of the same materials used in insulating layers GI3 and GI4. Furthermore, the thicknesses of insulating layers BGI1a and BGI1b are preferably greater than the thicknesses of insulating layers GI3 and GI4.

[0378] For information on semiconductor layer SC1a and semiconductor layer SC1b to conductive layer ME6a and conductive layer ME6b, please refer to... Figure 1 Description of the MCRA storage circuit.

[0379] In layer SS3, insulating layers IS6x, BI13, BM2a and BM2b are sequentially stacked on insulating layer BI5.

[0380] In particular, conductive layer BM2a is formed in a region that overlaps with the opening formed on the upper part of conductive layer ME7ga, and conductive layer BM2b is formed in a region that overlaps with the opening formed on the upper part of conductive layer ME7gb. Furthermore, like conductive layers BM1a and BM1b, conductive layers BM2a and BM2b are disposed extending along the Y direction.

[0381] Conductive layers BM2a and BM2b extend along the Y direction, and are therefore used, for example, as wiring. This wiring is equivalent to... Figure 2C The wiring described is BGE1. Note that although in Figure 28 The conductive layers BM2a and BM2b are represented by different wiring patterns, but as... Figure 2C As shown, conductive layers BM2a and BM2b can also be combined into the same wiring.

[0382] The conductive layers BM2a and BM2b may, for example, use materials or structures applicable to conductive layers ME1a, ME1b, ME2a, ME2b, ME3da, ME3db, ME3ga, ME3gb, ME4da, ME4db, ME4ga, ME4gb, ME5, ME6a, ME6b, ME7a, ME7b, ME8a, and ME8b. In particular, the conductive layers BM2a and BM2b are preferably made of materials or structures applicable to conductive layers BM1a and BM1b that have wiring functionality.

[0383] Insulation layer IS6x is equivalent to Figure 1 The insulating layer IS6 of the storage circuit MCRA is used as an interlayer film.

[0384] Similar to insulating layer BI11, insulating layer BI13 is used, for example, as a barrier insulating film to inhibit the diffusion of oxygen, etc., to prevent oxidation of conductive layers BM2a and BM2b. Therefore, insulating layer BI13 can be used for... Figure 1 The material of any one of the insulating layers BI1 to BI7 of the storage circuit MCRA.

[0385] An insulating layer BI14 is disposed on the insulating layer BI13, the conductive layer BM2a, and the conductive layer BM2b. In addition, an insulating layer IS6y is disposed on the insulating layer BI14.

[0386] Similar to insulating layer BI13, insulating layer BI14 serves as a barrier insulating film to inhibit the diffusion of oxygen and other substances, thereby preventing the oxidation of conductive layers BM1a and BM1b. Therefore, insulating layer BI14 can be used for... Figure 1 The material of any one of the insulating layers BI1 to BI7 and BI13 of the storage circuit MCRA.

[0387] Insulating layer IS6y is equivalent to Figure 1 The insulating layer IS6 of the storage circuit MCRA is used as an interlayer film.

[0388] Furthermore, insulating layers IS6x, BI13, BM2a, BM2b, BI14, IS6y, BI6, and GI4 have openings in the regions overlapping with conductive layers ME7ga or ME7gb. Additionally, insulating layer BGI2a is formed on the side of the opening overlapping with conductive layer ME7ga, and insulating layer BGI2b is formed on the side of the opening overlapping with conductive layer ME7gb.

[0389] Insulating layer BGI2a is used as the back gate insulating film in transistor MWA, and insulating layer BGI2b is used as the back gate insulating film in transistor MMWB.

[0390] Insulating layers BGI2a and BGI2b can, for example, be made of the same materials used in insulating layers GI3 and GI4. Furthermore, the thicknesses of insulating layers BGI2a and BGI2b are preferably greater than the thicknesses of insulating layers GI3 and GI4.

[0391] For information on semiconductor layers SC2a and SC2b to conductive layers ME9a and ME9b, please refer to... Figure 1 Description of the MCRA storage circuit.

[0392] exist Figure 28 In the storage circuit MCRA3, transistors MNA, MNB, MWA, and MWB can all be equipped with back gates, so the threshold voltage of each of transistors MNA, MNB, MWA, and MWB can be changed arbitrarily.

[0393] For example, in the memory circuit MCRA3, to expand the drive voltage range for the purpose of preventing malfunctions, it is preferable to apply a high-level potential to the conductive layers BM2a and BM2b. This reduces the threshold voltage of each of transistors MWA and MMWB, thereby increasing the on-state current of transistors MWA and MMWB. As a result, the drive voltage range of the memory circuit MCRA3 can be expanded.

[0394] Furthermore, for example, in the memory circuit MCRA3, a low-level potential can be applied to the conductive layers BM1a and BM1b to reduce power consumption during standby. This reduces the threshold voltage of each of the transistors MNA and MNB, thereby decreasing the off-state current of the transistors MNA and MNB. As a result, the power consumption of the memory circuit MCRA3 can be reduced.

[0395] Note that this embodiment can be appropriately combined with the same or other embodiments shown in this specification. For example, the configurations, structures, methods, etc. shown in this embodiment can be appropriately combined with other configurations, structures, methods, etc. shown in this embodiment. In addition, for example, the configurations, structures, methods, etc. shown in this embodiment can be appropriately combined with configurations, structures, methods, etc. shown in other embodiments, etc.

[0396] (Implementation Method 2)

[0397] In this embodiment, a metal oxide used as an oxide semiconductor as described in the above embodiments will be explained.

[0398] The metal oxides described in this specification are preferably crystalline. Examples of structures for crystalline metal oxides include the CAAC (c-axis aligned crystal) structure, polycrystalline structure, and nanocrystalline (nc: nano-crystal) structure. By using crystalline metal oxides as oxide semiconductors, the defect state density in the oxide semiconductor can be reduced. Therefore, the reliability of transistors using oxide semiconductors can be improved, and the reliability of memory circuits, processing devices, electronic devices, etc., according to one aspect of the present invention in which such transistors are mounted can be improved.

[0399] Oxide semiconductors are particularly preferably metal oxides having a CAAC structure. A CAAC structure is a crystal structure in which multiple microcrystals (typically multiple microcrystals with a hexagonal crystal structure) are c-axis oriented and connected without orientation on the ab plane. When a cross-section of an oxide semiconductor with a CAAC structure is observed using a high-resolution transmission electron microscope (TEM), it can be confirmed that the metal atoms are arranged in layers within the crystalline region. Therefore, it can also be said that an oxide semiconductor with a CAAC structure has layered crystalline regions.

[0400] The crystallinity of oxide semiconductors can be analyzed, for example, by X-ray diffraction (XRD), TEM, or electron diffraction (ED). Alternatively, a combination of these methods can be used for analysis.

[0401] There are no particular restrictions on the crystallinity of the semiconductor material contained in an oxide semiconductor. For example, an oxide semiconductor may sometimes contain one or more of the following: amorphous semiconductor (a semiconductor with an amorphous structure), single-crystal semiconductor (a semiconductor with a single-crystal structure), and semiconductor with crystallinity other than single crystal (microcrystalline semiconductor, polycrystalline semiconductor, or semiconductor with partially crystalline regions). When an oxide semiconductor is crystallinous, it can sometimes suppress the degradation of transistor characteristics.

[0402] Examples of metal oxides included in oxide semiconductors include indium oxide, gallium oxide, and zinc oxide. Preferably, the metal oxide contains one or both of indium (In) and zinc (Zn). Furthermore, the metal oxide preferably contains two or three elements selected from indium, element M, and zinc. Note that element M is a metallic or semi-metallic element with a high bond energy with oxygen, for example, a metallic or semi-metallic element with a higher bond energy with oxygen than indium. Specifically, elements M include aluminum, gallium, silicon, yttrium, tin, copper, vanadium, chromium, manganese, beryllium, boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, calcium, strontium, barium, cobalt, and antimony. Element M included in the metal oxide is preferably any one or more of the above elements, more preferably one or more selected from aluminum, gallium, tin, and yttrium, and even more preferably gallium. When element M included in the metal oxide is gallium, the metal oxide preferably contains one or both of indium and zinc. Note that in this specification, metallic elements and half-metallic elements are sometimes collectively referred to as "metallic elements," and the "metallic elements" described in this specification may sometimes include half-metallic elements.

[0403] Furthermore, the metal oxides included in the oxide semiconductor can be, for example, indium zinc oxide (In-Zn oxide), indium tin oxide (In-Sn oxide), indium titanium oxide (In-Ti oxide), indium gallium oxide (In-Ga oxide), indium gallium aluminum oxide (In-Ga-Al oxide), indium gallium tin oxide (In-Ga-Sn oxide, also denoted as IGTO), gallium zinc oxide (Ga-Zn oxide, also denoted as GZO), and aluminum zinc oxide (Al-Zn oxide, also denoted as AZO). Examples of indium aluminum zinc oxide (In-Al-Zn oxide, also known as IAZO), indium tin zinc oxide (In-Sn-Zn oxide, also known as ITZO (registered trademark)), indium titanium zinc oxide (In-Ti-Zn oxide), indium gallium zinc oxide (In-Ga-Zn oxide, also known as IGZO), indium gallium tin zinc oxide (In-Ga-Sn-Zn oxide, also known as IGZTO), and indium gallium aluminum zinc oxide (In-Ga-Al-Zn oxide, also known as IGAZO or IAGZO) are examples. Alternatively, examples include silicon-containing indium tin oxide (also known as ITSO), gallium tin oxide (Ga-Sn oxide), and aluminum tin oxide (Al-Sn oxide).

[0404] In transistors containing oxide semiconductors in the channel formation region, when the ratio of the number of indium atoms to the total number of atoms of all metal elements contained in the oxide semiconductor is increased, the transistor can achieve a large on-state current and high frequency characteristics.

[0405] Note that the metal oxide contained in an oxide semiconductor can also contain one or more metals with high period numbers in the periodic table instead of indium. Alternatively, the metal oxide can also contain one or more metals with high period numbers in the periodic table in addition to indium. There is a tendency for greater overlap of the orbitals of metal elements to result in greater carrier conduction in the metal oxide. Therefore, by including metals with high period numbers in the periodic table, the field-effect mobility of transistors can sometimes be improved. Examples of metals with high period numbers in the periodic table include metals belonging to period 5 and period 6. Specifically, examples of such metals include yttrium, zirconium, silver, cadmium, tin, antimony, barium, lead, bismuth, lanthanum, cerium, praseodymium, neodymium, promethium, samarium, and europium. Note that lanthanum, cerium, praseodymium, neodymium, promethium, samarium, and europium are called light rare earth elements.

[0406] Furthermore, in transistors containing oxide semiconductors in the channel formation region, the metal oxide contained in the oxide semiconductor may also contain one or more non-metallic elements. When the metal oxide contains non-metallic elements, the field-effect mobility of the transistor can sometimes be improved. Examples of non-metallic elements include carbon, nitrogen, phosphorus, sulfur, selenium, fluorine, chlorine, bromine, and hydrogen.

[0407] Furthermore, by increasing the ratio of zinc atoms to the total number of atoms of all metal elements in the metal oxide, the metal oxide can be made highly crystallizable, thereby suppressing the diffusion of impurities in the metal oxide. As a result, variations in the electrical characteristics of the transistor are suppressed, and reliability is improved.

[0408] Furthermore, by increasing the ratio of the number of atoms of element M to the total number of atoms of all metal elements in the metal oxide, the formation of oxygen vacancies in the metal oxide can be suppressed. Therefore, carrier generation caused by oxygen vacancies is suppressed, thereby reducing the off-state current of the transistor. In addition, variations in the electrical characteristics of the transistor are suppressed, thus improving reliability.

[0409] Next, a method for forming a metal oxide used as an oxide semiconductor will be described.

[0410] As an example, the metal oxide can be formed by a first deposition method and a second deposition method. Note that an oxide semiconductor comprising a metal oxide formed by the first deposition method and the second deposition method can also be referred to as a Hybrid OS.

[0411] The metal oxide formed by the first and second deposition methods is crystalline. In particular, the metal oxide has a CAAC structure.

[0412] In the first deposition method, a crystalline metal oxide is deposited. The deposited metal oxide preferably has a CAAC structure. For example, metal oxide films deposited using sputtering tend to be crystalline.

[0413] When forming a metal oxide using a first deposition method, a mixed layer sometimes forms at the interface between the metal oxide and the layer that is the surface to be formed. For example, when sputtering is used as the first deposition method, this mixed layer sometimes forms due to particles released from a target or the like (also called sputtered particles) or energy supplied to the substrate side by the sputtered particles or the like. This mixed layer may hinder the crystallization of the metal oxide.

[0414] For example, when an insulating layer containing silicon, such as silicon oxide, is used as the surface to be formed, silicon may be mixed into the metal oxide when a metal oxide is formed on the silicon oxide using a first deposition method. The inclusion of impurities such as silicon in the metal oxide may hinder the crystallization of the metal oxide.

[0415] Therefore, it is preferable to form the metal oxide using a second deposition method before forming the metal oxide using the first deposition method. Specifically, a first metal oxide layer is first formed using the second deposition method, and then a second metal oxide layer is formed on the first metal oxide layer using the first deposition method. At this time, an oxide semiconductor layer, which is a stack of the first and second metal oxide layers, is formed on an insulating layer whose formed surface includes silicon.

[0416] At this point, as a second deposition method, it is preferable to use a deposition method that causes less damage to the surface to be formed compared to the first deposition method. By using a deposition method that causes less damage to the surface to be formed as the second deposition method, the formation of a mixed layer at the interface between the first metal oxide layer and the layer that serves as the surface to be formed of the first metal oxide layer can be suppressed. Furthermore, in the second metal oxide layer, the introduction of impurities such as silicon from the layer that serves as the surface to be formed can be suppressed, so it is possible to further improve crystallinity. For example, compared with sputtering, atomic layer deposition (ALD) and chemical vapor deposition (CVD) can suppress damage to the surface to be formed, so they are suitable as the second deposition method.

[0417] Furthermore, the first metal oxide layer may sometimes be a microcrystalline or amorphous structure having a lower crystallinity than the CAAC structure. By forming a highly crystalline second metal oxide layer on the low-crystallinity first metal oxide layer, or by performing heat treatment after forming the second metal oxide layer, the crystallinity of the first metal oxide layer can sometimes be improved using the second metal oxide layer as a nucleus. Thus, the crystallinity of the entire oxide semiconductor layer, including the area near the interface with the formed surface, can sometimes be improved.

[0418] As described above, when forming an oxide semiconductor layer, it is preferable to first form a metal oxide on the surface to be formed using a second deposition method, and then form a metal oxide on top of it using a first deposition method.

[0419] Examples of primary deposition methods include sputtering and pulsed laser deposition (PLD).

[0420] Examples of secondary deposition methods include ALD (Alternating Layer Deposition), Plasma Enhanced CVD (PECVD), Thermal CVD, PhotoCVD, Metal-Organic CVD (MOCVD), and Molecular Beam Epitaxy (MBE). MBE is a deposition method that grows thin films reflecting the crystal structure of the substrate, and it is considered one of the deposition methods that causes minimal damage to the surface being formed. Furthermore, wet deposition methods can be used as secondary deposition methods. Wet deposition methods are also among the deposition methods that cause minimal damage to the surface being formed. Examples of wet deposition methods include spray coating.

[0421] As an example, the oxide semiconductor layer can be fabricated by forming a second metal oxide layer using a first deposition method after forming a first metal oxide layer using a second deposition method. Specifically, the second deposition method can be ALD, and the first deposition method can be sputtering. Furthermore, the second metal oxide layer formed using the first deposition method preferably has a CAAC structure.

[0422] For example, as described in the above embodiments Figure 8A In the transistor MNA, a semiconductor layer SC1a[1] is formed as the first metal oxide layer using a second deposition method, and a semiconductor layer SC1a[2] is formed as the second metal oxide layer using a first deposition method, thereby manufacturing a transistor MNA including a highly crystalline semiconductor layer SC1a (semiconductor layer SC1a[1] and semiconductor layer SC1a[2]).

[0423] Furthermore, a third metal oxide layer can also be formed on the second metal oxide layer. Since the second metal oxide layer has high crystallinity, the third metal oxide layer can be grown using the crystals of the second metal oxide layer as nuclei or seeds. Therefore, even without using a deposition method that readily produces crystals as the deposition method for the third metal oxide layer, it is possible to crystallize the third metal oxide layer. Here, for example, by using a deposition method with higher coverage than the second metal oxide layer to form the third metal oxide layer, both high crystallinity and high coverage can be achieved throughout the oxide semiconductor layer. Furthermore, for example, by using a deposition method that causes less damage than the second metal oxide layer to form the third metal oxide layer, damage to the second metal oxide layer can be reduced, thereby achieving high crystallinity throughout the oxide semiconductor layer.

[0424] Furthermore, by setting a first metal oxide layer to reduce the influence of the formed surface, the crystallinity of the second metal oxide layer is improved, resulting in extremely excellent crystallinity. Therefore, it is expected that a layer with extremely excellent crystallinity will also be formed in the third metal oxide layer that crystallizes using the second metal oxide layer as a nucleus or seed.

[0425] Furthermore, the third metal oxide layer is the uppermost layer of the oxide semiconductor layer. When the oxide semiconductor layer is used as the semiconductor layer of a transistor, the third metal oxide layer is, for example, the layer in contact with the gate insulating layer. By increasing the crystallinity of the layer in contact with the gate insulating layer, the carrier mobility of the transistor in the on state can be improved.

[0426] As an example, an oxide semiconductor layer can be manufactured by forming a first metal oxide layer using a second deposition method, then forming a second metal oxide layer using a first deposition method, and finally forming a third metal oxide layer using a second deposition method. Specifically, the second deposition method can be ALD, and the first deposition method can be sputtering. In this case, an oxide semiconductor layer, which is a stack of the first, second, and third metal oxide layers, is formed on an insulating layer whose formed surface includes silicon.

[0427] Furthermore, the metal oxide formed by the first deposition method preferably has a CAAC structure. The ALD method is a deposition method with higher coverage than sputtering; by using the ALD method as the deposition method for both the first and third metal oxide layers, the coverage of the oxide semiconductor layer can be improved. Therefore, the oxide semiconductor layer can effectively cover steps, openings, and other areas with high aspect ratios.

[0428] For example, as described in the above embodiments Figure 8BIn the transistor MNA, a semiconductor layer SC1a[1] is formed as the first metal oxide layer using a second deposition method, a semiconductor layer SC1a[2] is formed as the second metal oxide layer using a first deposition method, and a semiconductor layer SC1a[3] is formed as the third metal oxide layer using a second deposition method. Thus, a transistor MNA including a highly crystalline semiconductor layer SC1a (semiconductor layer SC1a[1], semiconductor layer SC1a[2] and semiconductor layer SC1a[3]) can be manufactured.

[0429] Note that this embodiment can be appropriately combined with the same or other embodiments shown in this specification. For example, the configurations, structures, methods, etc. shown in this embodiment can be appropriately combined with other configurations, structures, methods, etc. shown in this embodiment. In addition, for example, the configurations, structures, methods, etc. shown in this embodiment can be appropriately combined with configurations, structures, methods, etc. shown in other embodiments, etc.

[0430] (Implementation Method 3)

[0431] In this embodiment, a storage device including the storage circuit MCRA described in the above embodiments will be described.

[0432] Figure 29A This is a three-dimensional schematic diagram showing an example of the structure of the storage device MDVO. Figure 29B This is a block diagram illustrating an example of the structure of a storage device MDV0. The storage device MDV0 includes layers SS1 to SS3 as described in Embodiment 1. Note that in this embodiment, layer SS1 has a drive circuit region 50.

[0433] in addition, Figure 29A The storage cell 10 shown corresponds to the storage circuit MCRA described in the above embodiments. The storage cell 10 is composed of circuits included in layers SS1 to SS3. Furthermore, the storage device MDVO includes a storage cell array MCA, which includes a plurality of storage cells 10. Figure 29A In the storage cell array MCA, multiple storage cells 10 are arranged in a matrix of m rows and n columns. Figure 29B An example is shown in which a memory cell array MCA is configured with memory cells 10[1,1], memory cells 10[m,1] (where m is an integer greater than or equal to 1), memory cells 10[1,n] (where n is an integer greater than or equal to 1), memory cells 10[m,n], and memory cells 10[i,j] (where i is an integer greater than or equal to 1 and less than or equal to m, and j is an integer greater than or equal to 1 and less than or equal to n).

[0434] <Structural Example of the Driving Circuit Region>

[0435] The drive circuit area 50 includes PSW22 (power switch), PSW23 and peripheral circuit 31. Peripheral circuit 31 includes peripheral circuit 41, control circuit 32 and voltage generation circuit 33.

[0436] In the storage device MDV0, circuits, signals, and voltages can be appropriately selected or omitted as needed. Alternatively, other circuits or signals can be added. Signals BW, CE, GW, CLK, WAKE, ADDR, WDA, PON1, and PON2 are externally input signals, while signal RDA is an output signal. Signal CLK is the clock signal.

[0437] In addition, signals BW, CE, and GW are control signals. Signal CE is the chip enable signal, signal GW is the global write enable signal, and signal BW is the byte write enable signal. Signal ADDR is the address signal. Signal WDA is for writing data, and signal RDA is for reading data. Signals PON1 and PON2 are power gating control signals. Alternatively, signals PON1 and PON2 can also be generated in control circuit 32.

[0438] The control circuit 32 is a logic circuit that controls the overall operation of the storage device MDV0. For example, the control circuit performs logical operations on signals CE, GW, and BW to determine the operating mode of the storage device MDV0 (e.g., write operation, read operation). Alternatively, the control circuit 32 generates control signals for the peripheral circuit 41 to execute the aforementioned operating mode.

[0439] The voltage generation circuit 33 has the function of generating a negative voltage. The signal WAKE has the function of controlling the input signal CLK to the voltage generation circuit 33. For example, when a signal of level H is applied as the signal WAKE, the signal CLK is input to the voltage generation circuit 33, and the voltage generation circuit 33 generates a negative voltage.

[0440] The peripheral circuit 41 is used to write and read data from the storage unit 10. The peripheral circuit 41 includes a row decoder 42, a column decoder 44, a row driver 43, a column driver 45, an input circuit 47, an output circuit 48, and a sense amplifier 46.

[0441] Row decoder 42 and column decoder 44 are used to decode the signal ADDR. Row decoder 42 is used to specify the row to be accessed, and column decoder 44 is used to specify the column to be accessed. That is, row decoder 42 and column decoder 44 are sometimes referred to as selection circuits for selecting the memory cell 10 to be written to or read from.

[0442] The line driver 43 has the function of selecting the write and read word lines specified by the line decoder 42.

[0443] The column driver 45 has the following functions: writing data to the memory cell 10; reading data from the memory cell 10; and holding the read data. The column driver 45 also has the function of selecting the write and read bit lines specified by the column decoder 44. As described above, the column driver 45 facilitates the writing operation to the memory cell 10, and is therefore sometimes referred to as a write circuit that sends write data to the memory cell 10. Similarly, the column driver 45 also facilitates the reading operation to the memory cell 10, and is therefore sometimes referred to as a read circuit that reads read data from the memory cell 10.

[0444] Input circuit 47 has the function of holding signal WDA. The data held in input circuit 47 is output to column driver 45. The output data of input circuit 47 is the data written to memory cell 10 (Din). The data read from memory cell 10 (Dout) is amplified by readout amplifier 46 and output to output circuit 48. Output circuit 48 has the function of holding Dout. In addition, output circuit 48 has the function of outputting Dout to the external storage device MDVO. The data output from output circuit 48 is signal RDA.

[0445] PSW22 controls the supply of VDD to the peripheral circuit 31. PSW23 controls the supply of VHM to the row driver 43. Here, the high supply voltage of the storage device MDVO is VDD, and the low supply voltage is GND (ground potential). Furthermore, VHM is a high supply voltage used to make the word line high, which is higher than VDD. The on and off states of PSW22 are switched using signal PON1, and the on and off states of PSW23 are switched using signal PON2. Figure 29B In the peripheral circuit 31, the number of power domains supplied with VDD is 1, but it can also be multiple. In this case, a power switch can be set for each power domain.

[0446] <Memory Cell Array and Peripheral Circuits>

[0447] Next, the electrical connection between the memory cell array MCA and the peripheral circuit 41 will be explained.

[0448] Figure 30 This is a block diagram illustrating an example structure of the peripheral circuitry 41 and the memory cell array MCA. Figure 30In the diagram, row decoder 42 and row driver 43 are electrically connected to wiring WRL[i] (where i is an integer greater than 1 and less than m), and column decoder 44, column driver 45, and sense amplifier 46 are electrically connected to each of wiring BL[j] and wiring BLB[j] (where j is an integer greater than 1 and less than n). Note that, for convenience, in... Figure 30 The column decoder 44, column driver 45, and readout amplifier 46 are shown in the figure.

[0449] As described in Embodiment 1, wiring WRL[i] is used as a word line for memory cell 10[i,j]. Furthermore, as described in Embodiment 1, wiring BL[j] and wiring BLB[j] are used, for example, as bit line pairs.

[0450] The storage cell 10[i,j] configured in the i-th row and j-th column is electrically connected to the wiring WRL[i], wiring BL[j] and wiring BLB[j]. Figure 30 The abstract shows storage cell 10[i,j].

[0451] Regarding each storage unit 10, please refer to the description in Embodiment 1. Figure 2A The storage circuit MCR is recorded.

[0452] The readout amplifier 46 is electrically connected to wiring OL[j]. Wiring OL[j] can be electrically connected to the output circuit 48 shown in Figure 29.

[0453] The wiring OL[j] is used as the wiring for the data read from the storage unit 10 from the output of the sense amplifier 46.

[0454] As described above, by providing a drive circuit region 50 in layer SS1, a memory device can be constructed using a memory circuit such as MCRA as described in Embodiment 1. This allows for miniaturization of the memory device and increases its drive frequency.

[0455] Note that this embodiment can be appropriately combined with the same or other embodiments shown in this specification. For example, the configurations, structures, methods, etc. shown in this embodiment can be appropriately combined with other configurations, structures, methods, etc. shown in this embodiment. In addition, for example, the configurations, structures, methods, etc. shown in this embodiment can be appropriately combined with configurations, structures, methods, etc. shown in other embodiments, etc.

[0456] (Implementation Method 4)

[0457] In this embodiment, a processing apparatus according to one aspect of the present invention will be described.

[0458] Figure 31 A three-dimensional schematic diagram of the processing device 960 is shown. Figure 31 The processing device 960 shown can be used, for example, as a CPU. Alternatively, the processing device 960 can also be used with processors such as GPUs, TPUs (Tensor Processing Units), and NPUs (Neural Processing Units) that have multiple (tens to hundreds) processor cores capable of parallel processing compared to a CPU.

[0459] Figure 31 The processing device 960 shown includes, on a substrate 990: an ALU 991 (ALU: Arithmetic Logic Unit), an ALU controller 992, an instruction decoder 993, an interrupt controller 994, a timing controller 995, a register 996, a register controller 997, a bus interface 998, a cache 999, and a cache interface 989. The substrate 990 may be a semiconductor substrate, an SOI substrate, a glass substrate, etc. It may also include a rewritable ROM and a ROM interface. The cache 999 and the cache interface 989 may also be located on different chips.

[0460] Cache 999 is connected to the main memory located on different chips via cache interface 989. Cache interface 989 has the function of supplying a portion of the data stored in the main memory to cache 999. In addition, cache interface 989 has the function of outputting a portion of the data held in cache 999 to ALU 991 or register 996 via bus interface 998.

[0461] The cache 999 can be, for example, the storage device described in the above embodiments. In this case, the processing device 960 includes the storage circuit MCRA and the drive circuit described in Embodiment 1. As a result, the processing device 960 can be miniaturized, and the drive frequency of the processing device 960 can sometimes be increased.

[0462] Figure 31 The processing device 960 shown is merely an example with a simplified structure; therefore, the actual processing device 960 has a wide variety of structures depending on its application. For example, it is preferable to include... Figure 31The processing device 960 shown has a single core structure, employing a so-called multi-core architecture that includes multiple cores and allows them to operate simultaneously. The more cores, the better the computing performance. A higher number of cores is preferred; for example, two cores are preferred, four cores are more preferred, eight cores are even more preferred, twelve cores are still more preferred, sixteen cores are even more preferred, and more than sixteen cores are still preferred. Furthermore, when used in servers or other applications requiring very high computing performance, the multi-core architecture preferably includes sixteen or more cores, more preferably thirty-two or more, and even more preferably sixty-four or more cores. Additionally, the number of bits that the processing device 960 can process in its internal processing circuits, data bus, etc., can be, for example, 8 bits, 16 bits, 32 bits, 64 bits, 128 bits, or more.

[0463] Instructions input to the processing unit 960 via the bus interface 998 are input to the instruction decoder 993 and decoded, and then input to the ALU controller 992, interrupt controller 994, register controller 997 and timing controller 995.

[0464] The ALU controller 992, interrupt controller 994, register controller 997, and timing controller 995 perform various controls based on the decoded instructions. Specifically, the ALU controller 992 generates signals to control the operation of the ALU 991. Furthermore, when the processing device 960 executes a program, the interrupt controller 994 determines and processes interrupt requests from external input / output devices, peripheral circuits, etc., based on their priority and mask status. The register controller 997 generates the address of register 996 and reads or writes register 996 according to the state of the processing device 960.

[0465] In addition, the timing controller 995 generates signals to control the operating timing of the ALU 991, ALU controller 992, instruction decoder 993, interrupt controller 994, and register controller 997. For example, the timing controller 995 has an internal clock generator that generates an internal clock signal based on a reference clock signal and supplies the internal clock signal to the aforementioned circuits.

[0466] exist Figure 31 In the processing apparatus 960 shown, the register controller 997 selects the holding operation in register 996 according to instructions from ALU 991. For example, the register controller 997 can select whether to write data to register 996 or read data from register 996 according to instructions from ALU 991.

[0467] Note that this embodiment can be appropriately combined with the same or other embodiments shown in this specification. For example, the configurations, structures, methods, etc. shown in this embodiment can be appropriately combined with those shown in this embodiment. Furthermore, for example, the configurations, structures, methods, etc. shown in this embodiment can be appropriately combined with those shown in other embodiments, etc.

[0468] (Implementation Method 5)

[0469] This embodiment describes an application example of a storage device that includes a storage circuit according to one aspect of the present invention.

[0470] Generally speaking, various storage devices are used in semiconductor devices such as computers, depending on their purpose. Figure 32A The various memory devices used in semiconductor devices are shown in a hierarchical manner. Higher-level memory devices are required to operate at faster speeds, while lower-level memory devices are required to have larger storage capacities and higher recording densities. Figure 32A In a system, from the top layer, there are memory stored as registers in the CPU and other arithmetic processing units (sometimes referred to as processing units), L1 cache, L2 cache, L3 cache, main memory, secondary storage, etc. Note that although an example including up to L3 cache is shown here, it may also include caches at lower levels.

[0471] Note that the memory circuit MCRA described in the above embodiments can be used as a memory included in an arithmetic processing device. For example, the memory circuit MCRA can be used as a register, L1 cache to L3 cache, or other memory.

[0472] Because the memory installed along with registers in arithmetic processing devices such as CPUs is used for temporary storage of calculation results, it is accessed frequently by the processing device. Therefore, a faster operating speed is required compared to storage capacity. In addition, registers also have the function of holding settings information of the processing device.

[0473] A cache is a system that copies and maintains a portion of the information held in main memory. By copying frequently used data to the cache, the speed of data access can be improved. A cache requires less storage capacity than main memory, but its processing speed is higher. Additionally, data that is modified in the cache is copied and provisioned to main memory.

[0474] Main memory has the function of storing programs, data, etc. read from secondary storage.

[0475] Secondary storage serves to hold data that needs to be preserved long-term and various programs used by computing devices. Therefore, compared to faster operating speeds, secondary storage requires larger storage capacity and higher recording density. For example, high-capacity non-volatile storage devices such as 3D NAND can be used.

[0476] According to one aspect of the present invention, a storage device using oxide semiconductors (OS memory) operates at high speed and can retain data for a long time. For example, the OS memory has the features shown in Table 1.

[0477] [Table 1]

[0478]

[0479] By utilizing the features of the OS memory shown in Table 1, such as Figure 32A As shown, a storage device according to one aspect of the present invention can be used for both a cache level and a main memory level. Additionally, a storage device according to one aspect of the present invention can also be used for a level including secondary storage.

[0480] in addition, Figure 32B An example is shown where SRAM is used for a portion of the cache and the OS memory of one aspect of the invention is used for the other portion.

[0481] The lowest level cache can be referred to as an LLC (Last Level Cache). LLCs do not require faster operating speeds than their parent caches, but are required to have larger storage capacity. One embodiment of the OS memory of this invention has a fast operating speed and can retain data for long periods, making it suitable for use with LLCs. Note that one embodiment of the OS memory of this invention can also be used with FLCs (Final Level Cache).

[0482] For example, such as Figure 32B As shown, SRAM can be used for higher-level caches (L1 cache, L2 cache, etc.), and the OS memory of one embodiment of the present invention can be used for LLC. Additionally, as... Figure 32B As shown, DRAM can also be used in main memory in addition to OS memory.

[0483] Furthermore, the high power consumption of L3 cache and DRAM, which serve as main memory in supercomputers and servers using supercomputers, is one of the causes of global warming. Figure 32A In this system, both the L3 cache and main memory use OS memory. Additionally, in... Figure 32BIn this method, the OS memory is used for the LLC. Thus, by using oxide semiconductors according to one aspect of the invention for the storage device, the power consumption of the supercomputer can be reduced, thereby enabling the supercomputer to consume power at a level comparable to that of a personal computer.

[0484] Note that this embodiment can be appropriately combined with the same or other embodiments shown in this specification. For example, the configurations, structures, methods, etc. shown in this embodiment can be appropriately combined with other configurations, structures, methods, etc. shown in this embodiment. In addition, for example, the configurations, structures, methods, etc. shown in this embodiment can be appropriately combined with configurations, structures, methods, etc. shown in other embodiments, etc.

[0485] (Implementation Method 6)

[0486] In this embodiment, electronic components, electronic devices, mainframe computers, space devices, and data centers (also known as DCs) that can use the storage circuit or storage device including the storage circuit described in the above embodiments are explained. Electronic components, electronic devices, mainframe computers, space devices, and data centers using a storage circuit or storage device including the storage circuit of one aspect of the present invention are highly effective in achieving high performance such as low power consumption.

[0487] [Electronic Components]

[0488] Figure 33A A three-dimensional view of electronic component 700 is shown. Figure 33A The illustrated electronic component 700 includes a substrate 701, a semiconductor device 710 on the substrate 701, and a mold 711. Specifically, the semiconductor device 710 is sealed by the mold 711. Note that in... Figure 33A In the text, a portion of the description of electronic component 700 is omitted to indicate its internal structure.

[0489] As the substrate 701, for example, a ceramic substrate, a plastic substrate, or a glass epoxy substrate can be used.

[0490] Electronic component 700 is provided with, for example, a lead frame 712. A portion of the lead frame 712 located on substrate 701 is covered by mold 711, and another portion of the lead frame 712 is exposed outside of mold 711. In particular, the lead frame 712 exposed outside of mold 711 is used, for example, as a terminal for mounting electronic component 700 to a printed circuit board.

[0491] In mold 711, lead frame 712 has electrode pads 713, which are electrically connected to semiconductor device 710 via leads 714. Electronic component 700 is mounted on printed circuit board, for example, by making lead frame 712 contact with wiring on one side of printed circuit board. In this way, by combining multiple electronic components and electrically connecting them on printed circuit board, a circuit board is completed.

[0492] Next, the semiconductor device 710 will be described. For example, such as Figure 33B As shown, the semiconductor device 710 includes a driving circuit layer 715 and a memory layer 716. The memory layer 716 may have a structure in which multiple memory cell arrays are stacked. Alternatively, the semiconductor device 710 may also include the memory circuit or memory device described in the above embodiments.

[0493] The stacked structure of the driver circuit layer 715 and the memory layer 716 can be a monolithic stacked structure. In a monolithic stacked structure, bonding techniques such as through-electrode technology (e.g., TSV (Through Silicon Via)) and Cu-Cu (copper-copper) direct bonding can be used to connect the layers. When the driver circuit layer 715 and the memory layer 716 are stacked monolithically, for example, a so-called on-chip memory structure in which memory is directly formed on the processor can be realized. By adopting an on-chip memory structure, high-speed operation of the interface between the processor and the memory can be achieved.

[0494] Furthermore, by employing an on-chip memory structure, the size of interconnect wiring can be reduced compared to through-electrode techniques such as TSVs, thus allowing for an increase in the number of pins. Increasing the number of pins enables parallel operation, thereby improving the memory's bandwidth.

[0495] Furthermore, it is preferable to use OS transistors to form multiple memory cell arrays in memory layer 716, and to stack these multiple memory cell arrays monolithically. When multiple memory cell arrays are stacked monolithically, one or both of the memory bandwidth and memory access latency can be improved. Bandwidth refers to the amount of data transferred per unit time, and access latency refers to the time between accessing and starting data exchange. When using Si transistors in memory layer 716, it is more difficult to stack them monolithically compared to OS transistors. Therefore, in a monolithic stacked structure, OS transistors are superior to Si transistors.

[0496] Alternatively, the semiconductor device 710 may be referred to as a bare die. In this specification, a bare die refers to a chip obtained by forming a circuit pattern on a disk-shaped substrate (also called a wafer) and cutting it into small rectangular pieces during the semiconductor chip manufacturing process. Examples of semiconductor materials that can be used for bare dies include silicon (Si), silicon carbide (SiC), and gallium nitride (GaN). For example, a bare die obtained from a silicon substrate (also called a silicon wafer) is sometimes referred to as a silicon wafer.

[0497] then, Figure 33C A variation of electronic component 700 is shown. Unlike electronic component 700, Figure 33C In the illustrated electronic component 700A, an electrode 733 is provided at the bottom of the substrate 701 instead of a lead frame 712. The electrode 733 is used as a connection terminal for mounting the electronic component 700A onto a printed circuit board.

[0498] Figure 33C An example of forming electrode 733 using solder balls is shown. BGA (Ball Grid Array) mounting can be achieved by arranging solder balls in a matrix at the bottom of substrate 701. Furthermore, substrate 701 is therefore provided with through-holes, on which conductive layers 732 for wiring are disposed. Electrode pads 713 are disposed on substrate 701 above the conductive layer 732 in contact with ground, and electrodes 733 are disposed on substrate 701 below the conductive layer 732 in contact with ground.

[0499] Alternatively, electrode 733 can be formed using conductive pins instead of solder balls. By arranging conductive pins in a matrix on the bottom of substrate 701, PGA (Pin Grid Array) packaging can be achieved.

[0500] The 700A electronic component can be mounted on other substrates using various mounting methods, not limited to BGA and PGA. Examples of mounting methods include SPGA (Staggered Pin Grid Array), LGA (Land Grid Array), QFP (Quad Flat Package), QFJ (Quad Flat J-leaded package), and QFN (Quad Flat Non-leaded package).

[0501] Additionally, the electronic components of the storage circuit, including one aspect of the present invention, can also be in the form of SiP (System in Package) or MCM (Multi-Chip Module). For example, in Figure 33D In the electronic component 700C shown, an interposer 731 is provided on the packaging substrate 734 (printed circuit board), and a semiconductor device 735 and a plurality of semiconductor devices 710 are provided on the interposer 731.

[0502] exist Figure 33D In the electronic component 700C, an example is shown where the semiconductor device 710 is used as a high-bandwidth memory (HBM). Additionally, the semiconductor device 735 can be used, for example, as a computing circuit in an integrated circuit such as a CPU, GPU, or FPGA (Field Programmable Gate Array).

[0503] Similar to substrate 701, packaging substrate 734 can be, for example, a ceramic substrate, a plastic substrate, or a glass epoxy substrate. Through-hole 731 can be, for example, a silicon through-hole or a resin through-hole.

[0504] The through-hole board 731 has multiple wirings and multiple integrated circuits with different spacing between their electrical connection terminals. The multiple wirings can be arranged in a single layer or multiple layers. Furthermore, the through-hole board 731 has the function of electrically connecting the integrated circuits disposed on the through-hole board 731 to electrodes disposed on the package substrate 734. Therefore, the through-hole board is sometimes referred to as a "rewiring substrate" or "intermediate substrate." Additionally, sometimes a through electrode is provided in the through-hole board 731, through which the integrated circuits are electrically connected to the package substrate 734. Furthermore, in the case of using a silicon through-hole board, a TSV can also be used as the through electrode.

[0505] In HBM, a large number of wires are required to achieve a wide memory bandwidth. Therefore, the mounting board for HBM needs to be able to form fine wires at a high density. Thus, silicon mounting boards are preferred as mounting boards for HBM.

[0506] Furthermore, in SiP and MCM using silicon interposers, reliability degradation due to differences in the coefficients of thermal expansion between the integrated circuit and the interposer is less likely to occur. Additionally, due to the high surface flatness of the silicon interposer, poor connection between the integrated circuit and the interposer is less likely to occur. Silicon interposers are particularly preferred for 2.5D packaging (2.5D mounting), in which multiple integrated circuits are arranged horizontally on the interposer.

[0507] On the other hand, when multiple integrated circuits with different terminal pitches are electrically connected using silicon interposers and TSVs, space is required, such as the width of the terminal pitch. Therefore, when it is desired to reduce the size of the electronic component 700C, the width of the aforementioned terminal pitch becomes a problem, and it is sometimes difficult to set to achieve the required amount of wiring to achieve a wider memory bandwidth. Thus, as described above, a monolithic stacked structure using OS transistors is preferred. Alternatively, for example, a memory cell array utilizing TSV stacks and a memory cell array stacked monolithically can be combined. Furthermore, the structure combining a memory cell array utilizing TSV stacks and a memory cell array stacked monolithically is sometimes referred to as a composite structure.

[0508] Furthermore, when the temperature of the electronic component 700C rises due to current heat or other reasons, the characteristics of the circuit components (e.g., transistors) included in the electronic component 700C may degrade. Therefore, it is preferable to provide a heat sink (heat plate) overlapping the electronic component 700C. When a heat sink is provided, it is preferable to make the heights of the integrated circuits provided on the insert 731 consistent. For example, in the electronic component 700C shown in this embodiment, it is preferable to make the heights of the semiconductor device 710 and the semiconductor device 735 consistent.

[0509] [Electronic Devices]

[0510] then, Figure 34A A 3D view of electronic device 6500 is shown. Figure 34A The illustrated electronic device 6500 is a portable information terminal device that can be used as a smartphone. The electronic device 6500 includes a housing 6501, a display unit 6502, a power button 6503, a button 6504, a speaker 6505, a microphone 6506, a camera 6507, a light source 6508, and a control device 6509. The control device 6509 includes, for example, one or more components selected from a CPU, a GPU, and a memory circuit. The memory circuitry of one embodiment of the present invention can be used in the display unit 6502, the control device 6509, etc.

[0511] Figure 34B The illustrated electronic device 6600 is an information terminal that can be used as a notebook personal computer. The electronic device 6600 includes a housing 6611, a keyboard 6612, a pointing device 6613, an external port 6614, a display unit 6615, and a control device 6616. The control device 6616 includes, for example, one or more components selected from a CPU, a GPU, and a memory circuit. The memory circuitry of one embodiment of the present invention can be used in the display unit 6615, the control device 6616, etc.

[0512] By using the storage circuit of one aspect of the present invention in the above-described control device 6509 and control device 6616, power consumption can be reduced, and therefore it is preferred.

[0513] [Mainframe Computer]

[0514] then, Figure 34C A perspective view shows multiple large-scale computers 5600 installed in server rooms, etc. Figure 34C In the mainframe computer 5600 shown, multiple rack-mounted computers 5620 are housed in rack 5610. Additionally, the mainframe computer 5600 is sometimes referred to as a supercomputer.

[0515] The computer 5620 includes a motherboard with multiple slots, multiple connection terminals, etc. For example, one or more PC cards can be inserted into the slots.

[0516] This PC card is an example of a processing board that includes computing devices such as CPU and GPU. For example, electronic component 700 can be used as this computing device.

[0517] The 5600 mainframe computer can be used as a parallel computer. By using the 5600 mainframe computer as a parallel computer, large-scale computations required for artificial intelligence learning and inference can be performed, for example.

[0518] [Space Equipment]

[0519] The storage circuit of one aspect of the present invention can be applied to space devices (e.g., devices with the function of processing and storing information).

[0520] One embodiment of the storage circuit of the present invention may include an OS transistor. The OS transistor exhibits minimal change in electrical characteristics due to exposure to radiation. In other words, it has high resistance to radiation, making it suitable for environments where radiation may be incident. For example, the OS transistor is suitable for use in space.

[0521] exist Figure 35 The image shows an artificial satellite 6800 as an example of a space device. The artificial satellite 6800 includes a main body 6801, a solar panel 6802, an antenna 6803, a secondary battery 6805, and a control unit 6807. Additionally, Figure 35 An example of a planet 6804 in outer space is shown. Note that outer space, for example, refers to an altitude of 100 km or higher, but outer space as described in this specification sometimes includes the thermosphere, mesosphere, and stratosphere.

[0522] In addition, although Figure 35 Although not illustrated, a battery management system (also known as a BMS) or battery control circuit can also be incorporated into the secondary battery 6805. Using an OS transistor in the aforementioned battery management system or battery control circuit is preferred because it allows for low power consumption and high reliability, even in space.

[0523] Furthermore, outer space is an environment where the radiation dose is more than 100 times that of the Earth's surface. Other examples of radiation include electromagnetic waves (electromagnetic radiation), represented by X-rays and gamma rays; and particle radiation, represented by alpha rays, beta rays, neutron rays, proton rays, heavy ion rays, and meson rays.

[0524] The solar panel 6802 generates the power required for the satellite 6800 to operate when sunlight shines on it. However, the generated power decreases, for example, when sunlight does not reach the solar panel or when the amount of sunlight reaching the solar panel is low. Therefore, it is possible that the power required for the satellite 6800 to operate may not be generated. In order to enable the satellite 6800 to operate even when the generated power is low, it is preferable to install a secondary battery 6805 in the satellite 6800. Additionally, the solar panel is sometimes referred to as a solar cell module.

[0525] Satellite 6800 can generate a signal. This signal is transmitted via antenna 6803 and can be received, for example, by a ground receiver or other satellites. By receiving the signal transmitted by satellite 6800, the position of the receiver can be measured. Thus, satellite 6800 can constitute a satellite positioning system.

[0526] Furthermore, the control device 6807 has the function of controlling the artificial satellite 6800. The control device 6807 uses, for example, one or more components selected from a CPU, GPU, and memory circuitry. Additionally, the memory circuitry of one embodiment of the present invention is preferably used as the control device 6807. Compared to Si transistors, OS transistors exhibit less variation in electrical characteristics due to radiation exposure. In other words, OS transistors have high reliability and are suitable for use even in environments where radiation is likely to be incident.

[0527] Additionally, satellite 6800 may include sensors. For example, by including a visible light sensor, satellite 6800 may be able to detect sunlight reflected from objects on the ground. Alternatively, by including a thermal infrared sensor, satellite 6800 may be able to detect thermal infrared radiation emitted from the Earth's surface. Thus, satellite 6800 can be used, for example, as an Earth observation satellite.

[0528] Note that in this embodiment, an artificial satellite is shown as an example of a space device, but the invention is not limited thereto. For example, the storage circuitry of one aspect of the invention can also be applied to space devices such as spacecraft, space capsules, and space probes.

[0529] As explained above, OS transistors offer superior performance compared to Si transistors, such as enabling wider memory bandwidth and higher radiation resistance.

[0530] [Data Center]

[0531] For example, the storage circuitry of one embodiment of the present invention can be suitable for secondary storage systems used in data centers, etc. Data centers are required to manage data over long periods, ensuring data immutability, etc. Long-term data management necessitates large-scale facilities, such as setting up secondary storage and servers to store massive amounts of data, ensuring a stable power supply to maintain the data, or ensuring the necessary cooling equipment for data retention.

[0532] By using the storage circuit of one embodiment of the present invention in a secondary storage system employed in a data center, the power consumption required to retain data can be reduced, and the storage circuit for retaining data can be miniaturized. Therefore, miniaturization of the secondary storage system, miniaturization of the power supply used to retain data, and reduction in the size of cooling equipment are possible. This results in space savings in the data center.

[0533] Furthermore, the storage circuit of one embodiment of the present invention has low power consumption, thereby reducing circuit heat generation. This reduces the negative impact of heat generation on the circuit itself, peripheral circuits, and modules. Additionally, by using the storage circuit of one embodiment of the present invention, a data center can operate stably even in high-temperature environments. Therefore, the reliability of the data center can be improved.

[0534] Figure 36 This illustrates a secondary storage system that can be used in data centers. Figure 36 The secondary storage system 7000 shown serves as a host 7001 (illustrated as a main computer) and includes multiple servers 7001sb. Additionally, it serves as secondary storage 7003 (illustrated as secondary storage) and includes multiple storage devices 7003md. The host 7001 and secondary storage 7003 are shown connected via a secondary storage area network 7004 (illustrated as a SAN) and a secondary storage control circuit 7002 (illustrated as a secondary storage controller).

[0535] The host computer 7001 is equivalent to a computer that accesses data stored in secondary storage 7003. Host computers 7001 are sometimes connected to each other via a network.

[0536] In the secondary storage 7003, flash memory is used to shorten data access speed, i.e., to shorten the time required for data storage and output. However, this time is much longer than that required by DRAM (Dynamic Random Access Memory), which can be used as cache memory in secondary storage. In secondary storage systems, to address the issue of the long access speed of the secondary storage 7003, cache memory is generally incorporated into the secondary storage to shorten data storage and output.

[0537] The aforementioned cache memory is used in the secondary storage control circuit 7002 and the secondary storage 7003. Data exchanged between the host 7001 and the secondary storage 7003 is output to the host 7001 or the secondary storage 7003 after being stored in the cache memory in the storage control circuit 7002 and the secondary storage 7003.

[0538] When OS transistors are used to maintain the voltage corresponding to the data in the aforementioned cache memory, the refresh rate can be reduced to lower power consumption. Furthermore, miniaturization can be achieved through stacked memory cell arrays.

[0539] Note that by using the storage circuit of one aspect of the present invention in any one or more selected from electronic components, electronic devices, mainframe computers, space equipment, and data centers, a reduction in power consumption can be expected. Therefore, it is currently believed that with the increasing energy demands of high-performance or highly integrated semiconductor devices, the use of the storage circuit of one aspect of the present invention can also reduce emissions of greenhouse gases, such as carbon dioxide (CO2). Furthermore, the storage circuit of one aspect of the present invention has low power consumption, and is therefore effective as a measure against global warming.

[0540] Note that this embodiment can be appropriately combined with the same or other embodiments shown in this specification. For example, the configurations, structures, methods, etc. shown in this embodiment can be appropriately combined with other configurations, structures, methods, etc. shown in this embodiment. In addition, for example, the configurations, structures, methods, etc. shown in this embodiment can be appropriately combined with configurations, structures, methods, etc. shown in other embodiments, etc.

[0541] [Symbol Explanation]

[0542] ADDR: Signal, BI11: Insulating layer, BI12: Insulating layer, BI13: Insulating layer, BI14: Insulating layer, BL: Wiring, BLB: Wiring, BS: Substrate, BW: Signal, CE: Signal, CLK: Signal, DDV: Component separation layer, GI: Insulating layer, GW: Signal, LRAa: Low resistance region, LRAb: Low resistance region, LRAc: Low resistance region, MCA: Memory cell array, MCR: Memory circuit, MCRA: Memory circuit, MCRA1: Memory circuit, MCRA2: Memory circuit, MCRA3: Memory circuit, ME10a: Conductive layer, ME10b: Conductive layer, ME11: Conductive layer, MNA: Transistor, MNB: Transistor, M PA: Transistor, MPB: Transistor, MWA: Transistor, MMWB: Transistor, RDA: Signal, SCAa: Semiconductor area, SCAb: Semiconductor area, WAKE: Signal, WDA: Signal, WRL: Wiring, 10: Memory cell, 22: PSW, 23: PSW, 31: Peripheral circuit, 32: Control circuit, 33: Voltage generation circuit, 41: Peripheral circuit, 42: Row decoder, 43: Row driver, 44: Column decoder, 45: Column driver, 46: Sensing amplifier, 47: Input circuit, 48: Output circuit, 50: Drive circuit area, 700A: Electronic component, 700C: Electronic component, 700: Electronic component, 701: Substrate, 710: Semiconductor Device, 711: Mold, 712: Lead frame, 713: Electrode pad, 714: Lead, 715: Driver circuit layer, 716: Storage layer, 731: Through-hole board, 732: Conductive layer, 733: Electrode, 734: Package substrate, 735: Semiconductor device, 960: Processing device, 989: Cache interface, 990: Substrate, 991: ALU, 992: ALU controller, 993: Instruction decoder, 994: Interrupt controller, 995: Timing controller, 996: Register, 997: Register controller, 998: Bus interface, 999: Cache, 5600: Mainframe computer, 5610: Rack, 5620: Computer, 6500: Electronic equipment, 6501: Frame 6502: Display unit; 6503: Power button; 6504: Button; 6505: Speaker; 6506: Microphone; 6507: Camera; 6508: Light source; 6509: Control device; 6600: Electronic device; 6611: Frame; 6612: Keyboard; 6613: Pointing device; 6614: External connection port; 6615: Display unit; 6616: Control device; 6800: Artificial satellite; 6801: Main body; 6802: Solar panel; 6803: Antenna; 6804: Planet; 6805: Secondary battery; 6807: Control device; 7000: Secondary storage system; 7001sb: Server; 7001: Main unit; 7002: Secondary storage control circuit.7003md: Storage device; 7003: Secondary storage.

Claims

1. A memory circuit comprising: a first layer; a second layer over the first layer; and a third layer over the second layer, wherein the first layer includes a first low-resistance region, a second low-resistance region, a third low-resistance region, a first semiconductor region, a second semiconductor region, a first conductive layer, a second conductive layer, a third conductive layer, a fourth conductive layer, a fifth conductive layer, and a sixth conductive layer, the second layer includes a first insulating layer, a second insulating layer, a seventh conductive layer, an eighth conductive layer, a ninth conductive layer, a tenth conductive layer, an eleventh conductive layer, a twelfth conductive layer, a thirteenth conductive layer, a fourteenth conductive layer, a fifteenth conductive layer, a first semiconductor layer, and a second semiconductor layer, the third layer includes a sixteenth conductive layer and a seventeenth conductive layer, in a cross section, the first semiconductor region is between the first low-resistance region and the second low-resistance region, the second semiconductor region is between the second low-resistance region and the third low-resistance region, the first conductive layer has a region overlapping the first semiconductor region and a first region extending in a first direction, the second conductive layer has a region overlapping the second semiconductor region and a second region extending in a second direction, in a plan view, the first direction is a direction toward one of right and left when the second semiconductor region is seen from the first semiconductor region, in the plan view, the second direction is a direction toward the other of right and left when the second semiconductor region is seen from the first semiconductor region, the third conductive layer is on a top surface of the first low-resistance region, the fourth conductive layer is on a top surface of the first region, the fifth conductive layer is on a top surface of the second region, the sixth conductive layer is on a top surface of the second low-resistance region, the seventh conductive layer is in conduction with the third conductive layer, the eighth conductive layer is in conduction with the fourth conductive layer through the eleventh conductive layer, the ninth conductive layer is in conduction with the fifth conductive layer through the fourteenth conductive layer, the tenth conductive layer is in conduction with the sixth conductive layer, the twelfth conductive layer has a third region overlapping the eleventh conductive layer through the first insulating layer and a fourth region overlapping the fourteenth conductive layer, the first insulating layer has a first opening in the third region and a second opening in the fourth region, the first semiconductor layer has a region in contact with the twelfth conductive layer in the third region, the eleventh conductive layer on a bottom of the first opening, and the first insulating layer on a side of the first opening, the second semiconductor layer has a region in contact with the twelfth conductive layer in the fourth region, the fourteenth conductive layer on a bottom of the second opening, and the first insulating layer on a side of the second opening, the second insulating layer is on a top surface of the first insulating layer, a top surface of the twelfth conductive layer, a top surface of the first semiconductor layer, and a top surface of the second semiconductor layer, the thirteenth conductive layer is on a top surface of the second insulating layer in a region overlapping the first semiconductor layer, the fifteenth conductive layer is positioned on a top surface of the second insulating layer in a region overlapping with the second semiconductor layer, the sixteenth conductive layer is in conduction with the seventh conductive layer, the ninth conductive layer, and the thirteenth conductive layer, the seventeenth conductive layer is in conduction with the eighth conductive layer, the tenth conductive layer, and the fifteenth conductive layer, and, when viewed from above, the first semiconductor layer has a region overlapping with the first semiconductor region, the second semiconductor layer has a region overlapping with the second semiconductor region.

2. The memory circuit according to claim 1, wherein the third layer includes a third insulating layer, a fourth insulating layer, an eighteenth conductive layer, a nineteenth conductive layer, a twentieth conductive layer, a twenty-first conductive layer, a twenty-second conductive layer, a third semiconductor layer, and a fourth semiconductor layer, the eighteenth conductive layer has a fifth region overlapping with the sixteenth conductive layer with the third insulating layer interposed therebetween, the nineteenth conductive layer has a sixth region overlapping with the seventeenth conductive layer with the third insulating layer interposed therebetween, the third insulating layer has a third opening in the fifth region and a fourth opening in the sixth region, the third semiconductor layer has a region in contact with the eighteenth conductive layer in the fifth region, the sixteenth conductive layer positioned at a bottom of the third opening, and the third insulating layer positioned at a side of the third opening, the fourth semiconductor layer has a region in contact with the nineteenth conductive layer in the sixth region, the seventeenth conductive layer positioned at a bottom of the fourth opening, and the third insulating layer positioned at a side of the fourth opening, the fourth insulating layer is positioned on a top surface of the third insulating layer, a top surface of the eighteenth conductive layer, a top surface of the nineteenth conductive layer, a top surface of the third semiconductor layer, and a top surface of the fourth semiconductor layer, the twentieth conductive layer is positioned on a top surface of the fourth insulating layer in a region overlapping with the third semiconductor layer, the twenty-first conductive layer is positioned on a top surface of the fourth insulating layer in a region overlapping with the fourth semiconductor layer, the twenty-second conductive layer has a region in contact with the twentieth conductive layer and a region in contact with the twenty-first conductive layer, and, when viewed from above, the third semiconductor layer has a region overlapping with the first semiconductor region, the fourth semiconductor layer has a region overlapping with the second semiconductor region.

3. The memory circuit according to claim 2, wherein the first low-resistance region has a seventh region extending in the second direction, the third low-resistance region has an eighth region extending in the first direction, the third conductive layer is positioned on a top surface of the seventh region, the sixth conductive layer is positioned on a top surface of the eighth region, the seventh conductive layer has a region overlapping with the third conductive layer, the eighth conductive layer has a region overlapping with the fourth conductive layer, the ninth conductive layer has a region overlapping with the fifth conductive layer, and the tenth conductive layer has a region overlapping with the sixth conductive layer.

4. The memory circuit according to claim 3, wherein a part of the first low-resistance region is used as one of a source and a drain of the first transistor, a part of the second low-resistance region is used as the other of the source and the drain of the first transistor, a region of the first conductive layer overlapping with the first semiconductor region is used as a gate of the first transistor, the first semiconductor region has a channel formation region of the first transistor, a part of the second low-resistance region is used as one of a source and a drain of the second transistor, a part of the third low-resistance region is used as the other of the source and the drain of the second transistor, a region of the second conductive layer overlapping with the second semiconductor region is used as a gate of the second transistor, the second semiconductor region has a channel formation region of the second transistor, a part of the eleventh conductive layer is used as one of a source and a drain of a third transistor, the first region is used as the other of the source and the drain of the third transistor, a part of the thirteenth conductive layer is used as a gate of the third transistor, the first semiconductor layer has a channel formation region of the third transistor, a part of the fourteenth conductive layer is used as one of a source and a drain of a fourth transistor, the second region is used as the other of the source and the drain of the fourth transistor, a part of the fifteenth conductive layer is used as a gate of the fourth transistor, the second semiconductor layer has a channel formation region of the fourth transistor, a part of the sixteenth conductive layer is used as one of a source and a drain of a fifth transistor, the fifth region is used as the other of the source and the drain of the fifth transistor, a part of the twentieth conductive layer is used as a gate of the fifth transistor, the third semiconductor layer has a channel formation region of the fifth transistor, a part of the seventeenth conductive layer is used as one of a source and a drain of a sixth transistor, the sixth region is used as the other of the source and the drain of the sixth transistor, a part of the twenty-first conductive layer is used as a gate of the sixth transistor, the fourth semiconductor layer has a channel formation region of the sixth transistor, the first transistor and the second transistor each are a p-channel transistor including silicon in a channel formation region, and the third transistor to the sixth transistor each are an n-channel transistor including an oxide semiconductor in a channel formation region.

5. The memory circuit according to claim 4, wherein the oxide semiconductor includes one or more selected from indium, zinc, and an element M, and the element M is one or more selected from aluminum, gallium, silicon, yttrium, tin, copper, vanadium, chromium, manganese, beryllium, boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, calcium, strontium, barium, cobalt, and antimony.

6. A processing device comprising: the memory circuit according to any one of claims 1 to 5; and a driver circuit.

7. An electronic device comprising: the processing device according to claim 6; and a housing.

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