TSV-RDL interconnection structure failure test analysis system and method

Abstract

The invention relates to the technical field of electronic packaging, and particularly discloses a TSV-RDL interconnection structure failure test analysis system and method, through the whole-process standardized design of a test structure, data acquisition and a criterion model, and in combination with the technical innovation of cross-scale characterization and multi-parameter early warning, accurate capture of early failure of a TSV-RDL interconnection structure is realized, and the accuracy of the TSV-RDL interconnection structure failure test analysis is improved. And a unified comparable evaluation system is established, and standardized technical support is provided for process optimization and product reliability improvement.

Description

Technical Field

[0001] This invention relates to the field of electronic packaging technology, and in particular to a failure testing and analysis system and method for TSV-RDL interconnect structures. Background Technology

[0002] Three-dimensional through-silicon vias (TSVs), as a core technology of advanced electronic packaging, are a key means to meet the demands for smaller, more powerful, and smarter electronic systems and to surpass Moore's Law. They are widely used in processor and memory architectures in high-performance computing; for example, AMD graphics cards use TSV technology to achieve high-density integration of high-bandwidth memory and GPU chips. Leading international companies have launched products based on 3D-TSV technology, but domestic technology lags behind. Domestic TSVs have large apertures, low aspect ratios, and fewer wiring layers, making it difficult to meet the high-speed, high-density interconnect requirements of high-performance computing units and high-density storage units.

[0003] TSV (Transformer Module) interconnects, acting as an intermediary between chips and substrates, achieve interconnection between multiple chips and between chips and substrates through metal redistribution lines (RDLs). However, domestic mass production processes are immature, and TSV-RDL composite interconnect structures are prone to failures such as open circuits, short circuits, and voids during manufacturing and use, severely impacting device reliability. Therefore, failure analysis of TSVs is crucial, but current failure analysis methods have drawbacks. For example, most methods employ single-point testing or simple parallel structures. Interconnecting TSVs with chips requires pathways such as RDLs, bonding wires, and microbumps. Under thermal and electromigration stress, the RDL layer, with its smaller cross-sectional area and higher current density, is more likely to become a weak point compared to the TSV itself. This makes it difficult to accurately simulate the current path of the TSV and RDL in series in actual packaging, leading to significant deviations between test results and actual failure modes. In addition, TSV electromigration testing is only for a single TSV structure and cannot achieve multi-physics analysis; high-temperature electronic packaging interconnect testing is applicable to traditional interconnects and lacks the ability to detect failure modes at the TSV-RDL interface; large-scale integrated interconnect testing introduces additional processes, but the failure criteria are singular; TSV failure verification relies solely on electrical testing, making it difficult to achieve in-situ monitoring and microscopic analysis; the industry lacks unified failure criteria, data comparability is poor, and analysis is limited to macroscopic resistance monitoring, lacking systematic research on microstructure evolution.

[0004] In summary, current failure analysis still suffers from problems such as insufficient detection of interface defects, difficulty in achieving multi-physics analysis, and lack of standardized evaluation systems, resulting in weak early failure warning capabilities. There is an urgent need to establish a failure analysis system and method for TSV-RDL interconnect structures that can improve early warning capabilities and achieve standardized evaluation. Summary of the Invention

[0005] This invention provides a TSV-RDL interconnect structure failure testing and analysis system and method, which can improve early warning capabilities and achieve standardized evaluation.

[0006] To solve the above-mentioned technical problems, this application provides the following technical solution:

[0007] A failure test and analysis method for TSV-RDL interconnect structures includes the following steps:

[0008] Step 1, Preparation of test sample: The test sample adopts a daisy chain structure. The test sample has a TSV. The TSV has a copper pillar. The upper and lower ends of the copper pillar are electrically connected to the RDL layer. The two ends of the daisy chain structure are provided with pads. The pads are bonded to the test printed circuit board through gold wire bonding to form a closed current path.

[0009] Step 2, Apply multi-physics stress: Apply thermal stress to the test sample according to the preset temperature gradient, time gradient and heating rate and cooling rate, and at the same time apply electromigration stress to the test sample according to the preset temperature gradient, current density gradient and energizing time.

[0010] Step 3, cross-scale data acquisition: Power is applied to the test sample, and the resistance data of the test sample is acquired in real time; imaging data of the test sample is acquired by X-ray computed tomography; microscopic data are acquired by SEM and EBSD.

[0011] Step 4, Multi-parameter fusion analysis and early warning determination: The resistance data, imaging data and microscopic data are fused and processed to establish a multi-parameter hierarchical early warning model. A first-level early warning is triggered based on the resistance data, a second-level early warning is triggered based on the first-level early warning combined with the imaging data, and a third-level early warning is triggered based on the second-level early warning combined with the microscopic data.

[0012] The basic principle and beneficial effects of the solution are as follows: A daisy-chain series structure is used to form a closed current path between the TSV and RDL layers, realistically simulating the current transmission scenario of TSV-RDL series connection in actual packaging. This accurately captures early failure signals in the RDL layer, a weak link with high current density, avoiding misjudgment of the failure source by single-point or parallel test structures. Simultaneously, real-time acquisition of macroscopic resistance captures weak resistance fluctuations, enabling mesoscopic X-ray imaging to locate early defects such as interface microcracks and delamination. Microscopic SEM / EBSD analysis obtains initial failure characteristics such as grain boundary degradation and microvoids, forming a complete macroscopic-mesoscopic-microscopic data chain capable of identifying multi-dimensional weak signals in the early stages of failure. Furthermore, a multi-parameter fusion early warning logic based on resistance change rate, defect density, and microstructure evolution uses the resistance change rate as the primary early warning trigger point to capture early failure precursors before traditional criteria. Combining mesoscopic and microscopic data, the early warning level is gradually upgraded, achieving a leap from post-failure judgment to pre-failure warning, significantly advancing the warning time and improving early warning capabilities.

[0013] This scheme clearly defines the parameter ranges for thermal stress and electromigration stress, ensuring consistency in temperature parameters for both types of stress. It also standardizes the operational steps for sample preparation, data acquisition, and preprocessing to avoid result deviations caused by varying test conditions. A graded and quantitative standard is established for Level 1 warning, Level 2 warning (combined with mesoscopic data), Level 3 warning (combined with microscopic data), and failure determination, replacing the 10%-50% of ambiguous resistance increment criteria used in the industry, enabling horizontal comparability of results under different test scenarios. Characterization techniques such as 2D / 3DX-ray (submicron resolution) and SEM / EBSD (fixed test parameters) are uniformly adopted, and data acquisition accuracy, analysis software, and processing procedures are clearly defined, forming a standardized link for data acquisition, analysis, and determination. This prevents chaotic analysis methods and inconsistent data interpretation, ensuring the scientific validity and reliability of the evaluation results.

[0014] In summary, this solution, through standardized design of the entire process of test structure, data acquisition, and criterion model, combined with technological innovations in cross-scale characterization and multi-parameter early warning, not only achieves accurate capture of early failures in TSV-RDL interconnect structures, but also establishes a unified and comparable evaluation system, providing standardized technical support for process optimization and product reliability improvement.

[0015] Furthermore, in step 3, the test sample is powered on, and the resistance data of the test sample is collected in real time. This includes: setting up a data acquisition system consisting of a digital multimeter, a multiplexer, and a temperature detector, as well as an experimental environment system consisting of an oil bath or an aging furnace, and placing the test sample in the experimental environment system; the digital multimeter is connected to the test sample through the multiplexer, and after the test sample is powered on, the digital multimeter collects the resistance information of the sample in real time, and the ambient temperature information collected by the temperature detector is transmitted in parallel to the computer through the multiplexer.

[0016] The beneficial effects are as follows: by building a dedicated data acquisition system and experimental environment system, the synchronous real-time acquisition of resistance and ambient temperature information can be achieved; the digital multimeter is connected to the test sample through a multiplexer, ensuring the stability and efficiency of data acquisition and accurately capturing weak resistance fluctuations; the synchronous transmission of temperature information can correct for the influence of environmental interference and improve data accuracy.

[0017] Furthermore, in step 3, imaging data of the test sample is acquired by X-ray computed tomography, including: using 2DX-ray and 3DX-ray non-destructive testing equipment that integrates a high-brightness X-ray source and a high-resolution detector, scanning the silicon interposer structure of the test sample by computed tomography CT technology to obtain sub-micron resolution three-dimensional imaging data; the imaging data can present the bonding connection state, the interconnection state of TSV and RDL and the filling state of TSV in a non-destructive manner, forming cross-scale characterization data covering the external morphology of the sample to the internal microstructure.

[0018] The beneficial effects are as follows: by leveraging the synergistic effect of a high-brightness X-ray source and a high-resolution detector, submicron-level stereo imaging can be achieved through 2D / 3DX-ray technology. Its non-destructive nature can fully present the bonded connections, TSV-RDL interconnects, and TSV filling state, avoiding sample damage. At the same time, it forms cross-scale characterization data covering the external morphology to the internal microstructure, accurately capturing early defects such as interface microcracks and delamination, and making up for the blind spots of traditional detection in observing internal structures.

[0019] Furthermore, in step 3, microscopic data is acquired using SEM and EBSD, including: characterizing the cross-section of the test sample using SEM and EBSD; first, adjusting the edge of the test sample to be parallel to the edge of the sample stage; then tilting the cross-section of the test sample to a preset angle; setting the working distance; and applying an accelerating voltage in a vacuum environment to excite the Kikuchi pattern; acquiring microscopic morphology data and void / hill defect data of the test sample using SEM; acquiring Cu grain orientation data using EBSD; and then using Aztec-crystal software to analyze and process the microscopic morphology data, void / hill defect data, and Cu grain orientation data to obtain microscopic data of the TSV structure, including the grain orientation distribution and morphological characteristics.

[0020] The beneficial effects are as follows: by combining SEM and EBSD and setting standardized test parameters, the microstructure, defects and Cu grain orientation data of the samples can be accurately collected; compared with the lack of microstructure evolution analysis, after analysis and processing by Aztec-crystal software, key information such as TSV structure grain orientation distribution and morphological characteristics can be obtained, and early failure micro signals such as grain boundary degradation and microvoids can be captured, which helps to trace the root cause of failure.

[0021] Furthermore, in step 4, a multi-parameter hierarchical early warning model is established, including: using the LSTM time series network in deep learning algorithms, analyzing the resistance time series data, temperature time series data and corresponding failure records in historical tests, autonomously learning the mapping relationship between data features and failure states, and establishing an adaptive optimization failure prediction model.

[0022] The beneficial effects are as follows: by leveraging the LSTM time series network, the correlation between historical resistance and temperature time series data and failure records can be deeply explored; by autonomously learning the mapping relationship between data features and failure states, it can get rid of the dependence on physical failure models and build an adaptive optimization failure prediction model, which can capture early weak failure signals, achieve very early warning, and can dynamically optimize parameters with new data to improve the accuracy of warning.

[0023] Furthermore, in step 2, applying multi-physics stress also includes: integrating a micro temperature sensor and a micro stress sensor in the vicinity of the TSV-RDL structure of the test sample or on a dedicated test pad using MEMS technology; using the micro temperature sensor and micro stress sensor to acquire local temperature data and local stress data inside the device; and synchronously transmitting the acquired local temperature data and local stress data to the data processing unit to assist in the optimization of the multi-parameter hierarchical early warning model and the failure cause tracing analysis.

[0024] The beneficial effects are as follows: By integrating miniature temperature and stress sensors through MEMS technology, local temperature and stress data inside the device can be captured in situ in real time. The micron-level spatial resolution ensures the directness and accuracy of the data. The synchronously transmitted data can accurately quantify the electro-thermal-mechanical multi-physics field effects, make up for the shortcomings of lacking field parameter monitoring in testing, optimize the accuracy of early warning, and help trace the root cause of failure caused by thermomechanical stress.

[0025] Furthermore, in step 3, during the cross-scale data acquisition process, surface acoustic wave (SAW) detection technology or terahertz wave detection technology is also used to assist in the acquisition of imaging data: if SAW detection technology is used, the characteristics of sound waves propagating at the interface of the test sample material are utilized to achieve highly sensitive non-destructive testing of microcracks and delamination defects at the TSV-RDL interface; if terahertz wave detection technology is used, the penetrability of terahertz waves to dielectric materials is utilized to obtain imaging data of the deep internal structure of the sample.

[0026] The beneficial effects are as follows: by supplementing imaging data with surface acoustic wave (SAW) or terahertz wave detection technologies, complementary advantages are formed. The former, with its sensitivity to changes in the propagation characteristics of material interfaces, can accurately capture minute defects such as microcracks and delamination at the TSV-RDL interface, while the latter, relying on its strong penetration of dielectric materials, can clearly present the deep internal structure of the sample. The two technologies, together with X-ray imaging data, corroborate each other, filling the blind spots in interface defect identification and deep structure observation, and improving the accuracy of failure tracing.

[0027] Furthermore, in step 1, after preparing the test sample, before conducting cross-scale data acquisition, the test sample is embedded and solidified using a conductive nickel-based alloy hot-mount material; the test sample is then mechanically polished using diamond sandpaper of a preset mesh size, with the surface state of the sample observed under an optical microscope at preset intervals during the polishing process, and polishing is stopped when the TSV is just exposed and there are no obvious scratches; the test sample is first mechanically polished using Al2O3 polishing slurry of a first preset particle size until there are no obvious scratches under an optical microscope; then, fine polishing is performed using Al2O3 polishing suspension of a second preset particle size in conjunction with DP-Nap polishing cloth to ensure that there are no scratches remaining on the sample surface; finally, the test sample is treated with vibration polishing technology to eliminate residual stress on the surface; the first preset particle size is 3.0 μm, and the second preset particle size is 1.0 μm.

[0028] The beneficial effects are as follows: through standardized inlaying, grinding, polishing and stress relief, the test sample surface is ensured to be flat and free of scratches and internal residual stress; the conductivity of the nickel-based alloy hot-mount material ensures the conductivity of subsequent tests; graded grinding and polishing accurately expose the TSV structure and avoid over-processing that damages the sample; vibratory polishing completely eliminates residual stress on the surface and reduces the interference of stress on the test data.

[0029] Furthermore, in step 1, test samples are prepared by etching and electroplating. Attached Figure Description

[0030] Figure 1 This is a flowchart of an implementation example;

[0031] Figure 2 This is a schematic diagram of the interconnection structure of the TSV adapter board;

[0032] Figure 3a The image shows the appearance of the test sample under 2D-Xray.

[0033] Figure 3b For the appendix Figure 3a A magnified view showing the details of the bonding connection state;

[0034] Figure 3c The image shows the topography of pads and vias under 3D-Xray imaging.

[0035] Figure 3d For the appendix Figure 3c Enlarged view of pads and vias in detail;

[0036] Figure 4a This is a diagram showing the melting of aluminum bonding wires.

[0037] Figure 4b A diagram showing the bulging of the RDL;

[0038] Figure 5a This is a view of the packaged chip.

[0039] Figure 5b This is a micrograph of the bare metal sample.

[0040] Figure 5c SEM of the TSV cross section;

[0041] Figure 5d SEM of a single TSV section;

[0042] Figure 6a For a constant current density of 2.0 × 10 5 A / cm 2 Microscopic morphology of aluminum leads (bonding wires) after power is applied;

[0043] Figure 6b The morphology of TSV-RDL bulging during 300℃ heat storage. Detailed Implementation

[0044] The following detailed description illustrates the specific implementation method:

[0045] Explanation of reference numerals in the attached diagram: 1. Substrate; 2. Insulating layer; 3. Copper pillar; 4. Bump; 5. Microbump; 6. Pad; 7. Bonding wire; 8. Chip; 9. Rewiring layer.

[0046] High-performance computing commonly adopts a "processor + memory" architecture, integrating multiple memories and processors onto the same silicon-based interface board to improve the overall performance of the computing unit, as shown in the attached figure. Figure 2 As shown, a silicon-based adapter board is disposed between chip 8 and substrate 1. The adapter board has three-dimensional through-silicon vias (TSVs), within which copper pillars 3 are located. An insulating layer 2 is located near the copper pillars 3. A bump 4 is located at the lower end of the copper pillar 3, interconnecting with substrate 1. A redistribution layer 9 (RDL) is located at the upper end of the copper pillar 3, and microbumps 5 are located above the redistribution layer, interconnecting with chip 8. Thus, chip 8 is interconnected with the adapter board through microbumps 5, and the adapter board is interconnected with the substrate 1 below through bumps 4. The adapter board acts as an intermediary bridge between chip 8 and substrate 1, enabling interconnection between multiple chips 8 via the redistribution layer 9 (RDL), and also enabling interconnection between chip 8 and substrate 1. For example, a pad 6 is located at the upper end of the copper pillar 3, and bonding wires 7 are connected to the pad 6, which are then connected to the chip. Since the interconnection between TSV and chip 8 requires the use of RDL, bonding wire 7, microbumps 5, etc., under the action of thermal stress and electromigration stress, RDL has a smaller cross-sectional area and higher current density. Compared with TSV, the high current density RDL is more likely to become a weak link. If the focus of TSV is on the reliability of the TSV via itself, the test results are likely to deviate significantly from the actual failure mode.

[0047] This invention provides a failure test and analysis method for TSV-RDL interconnect structures, as shown in the appendix. Figure 1 As shown, the specific implementation process is as follows:

[0048] Step 1, Preparation of test sample: The test sample adopts a daisy chain structure. The test sample has a TSV. The TSV has copper pillars. The upper and lower ends of the copper pillars are electrically connected to the RDL layer. Both ends of the daisy chain structure have pads. The pads are bonded to the test printed circuit board to form a closed current path through gold wire bonding.

[0049] In step 1, test samples are fabricated through etching and electroplating; as shown in the attached document. Figure 5a Appendix Figure 5b Appendix Figure 5c Appendix Figure 5d As shown, attached Figure 5a View of the packaged chip body; attached Figure 5b Microscopic image of the bare slide; attached. Figure 5c SEM image of TSV cross section; attached Figure 5dThe SEM image of a single TSV cross-section shows that the TSV is fully filled, the copper filler is well bonded to the substrate, and there are no obvious voids or cracks. A daisy-chain structure is used to connect the two TSV copper pillars in series, creating a closed current path to improve the efficiency of electromigration testing. The pads at both ends of the daisy chain on the chip with the daisy-chain structure are connected to the test printed circuit board using bonding wires to facilitate subsequent alignment and power-on.

[0050] After preparing the test samples, before conducting cross-scale data acquisition, the test samples were embedded and solidified using a conductive nickel-based alloy hot-mount material. The test samples were then mechanically polished using diamond sandpaper of a preset mesh size. During the polishing process, the surface condition of the samples was observed using an optical microscope at preset intervals. Polishing was stopped when the TSV (Total Vapor Vein) was just exposed and there were no obvious scratches. The test samples were then mechanically polished using an Al2O3 polishing slurry with a first preset particle size of 3.0 μm until no obvious scratches were observed under the optical microscope. Next, a fine polishing was performed using an Al2O3 polishing suspension with a second preset particle size of 1.0 μm in conjunction with a DP-Nap polishing cloth to ensure no scratches remained on the sample surface. Finally, vibration polishing technology was used for the final treatment of the test samples to eliminate residual surface stress. Standardized inlaying, grinding, polishing, and stress relief processes ensure that the test sample surface is smooth and free of scratches and internal residual stress. The conductivity of the nickel-based alloy hot-mount material ensures the conductivity of subsequent tests. Graded grinding and polishing precisely expose the TSV structure, avoiding over-processing that could damage the sample. Vibratory polishing completely eliminates residual surface stress, reducing the interference of stress on test data.

[0051] Step 2, Applying Multiphysics Stress: Thermal stress is applied to the test sample according to preset temperature gradient, time gradient, heating rate, and cooling rate. Temperature gradient: 200℃, 300℃; Time gradient: 48h (short-term), 480h (long-term, simulating 20 days of accelerated aging); Heating rate: 10℃ / min; Cooling method: furnace cooling; Cooling rate: 10℃ / min. Simultaneously, electromigration stress is applied to the test sample according to preset temperature gradient, current density gradient, and energizing time. Thermal aging temperature: 200℃, 300℃; Aging time: 48h (2 days), 480h (20 days); Current density: 2.0×10⁻⁶. 5 A / cm² ~ 4.0 × 10 5 A / cm² (gradient setting), power-on time: 48h (continuous power-on), real-time monitoring: dynamic resistance monitoring, sampling frequency 1Hz. (See attached image) Figure 6a Appendix Figure 6b As shown, attached Figure 6a For a constant current density of 2.0 × 10 5 A / cm 2Microscopic images of the aluminum leads (bonding wires) after power is applied, with attached images. Figure 6b The morphology of TSV-RDL bulging during 300℃ heat storage.

[0052] Step 2, applying multiphysics stress, further includes: integrating micro-temperature sensors and micro-stress sensors using MEMS technology in the vicinity of the TSV-RDL structure of the test sample or on a dedicated test pad. These sensors acquire local temperature and stress data within the device, and the collected data is simultaneously transmitted to a data processing unit to assist in optimizing the multi-parameter hierarchical early warning model and tracing the root causes of failures. Integrating micro-temperature and stress sensors using MEMS technology allows for in-situ, real-time capture of local temperature and stress data within the device. The micrometer-level spatial resolution ensures the directness and accuracy of the data. The synchronously transmitted data accurately quantifies the electro-thermal-mechanical multiphysics effects, compensating for the lack of field parameter monitoring in testing, optimizing early warning accuracy, and assisting in tracing the root causes of failures caused by thermomechanical stress.

[0053] Step 3, cross-scale data acquisition: Power is applied to the test sample to acquire the resistance data of the test sample in real time; imaging data of the test sample is acquired by X-ray computed tomography; microscopic data is acquired by SEM and EBSD.

[0054] The main concerns regarding thermal and electromigration stress are the bonding wire and pad connection status, whether the bonding wire has melted, whether the RDL has bulged, the TSV-RDL interconnection status, and whether the Cu via filler in the TSV has bulged. Since TSVs are composed of multiple materials, temperature changes generate thermomechanical stress inside and around the TSV, leading to various failures such as interface delamination, substrate cracking, and wafer warping. The large current generated by electromigration stress can easily cause bonding wire meltdown and atomic migration along the electron flow direction, resulting in voids and hillocks inside the TSV, causing increased resistance and even open-circuit failure.

[0055] In step 3, the test sample is powered on, and its resistance data is collected in real time. This includes: setting up a data acquisition system consisting of a digital multimeter, a multiplexer, and a temperature detector, and an experimental environment system consisting of an oil bath or aging furnace; placing the test sample in the experimental environment system; connecting the digital multimeter to the test sample via the multiplexer; after powering on the test sample, the digital multimeter collects the sample's resistance information in real time, and the ambient temperature information collected by the temperature detector is transmitted in parallel to the computer via the multiplexer. By setting up a dedicated data acquisition system and experimental environment system, synchronous real-time acquisition of resistance and ambient temperature information is achieved; the connection of the digital multimeter to the test sample via the multiplexer ensures the stability and efficiency of data acquisition, and can accurately capture weak resistance fluctuations; synchronous transmission of temperature information can correct for environmental interference and improve data accuracy.

[0056] In step 3, imaging data of the test sample is acquired via X-ray computed tomography (CT), including: using 2DX-ray and 3DX-ray non-destructive testing equipment integrating a high-brightness X-ray source and a high-resolution detector, scanning the silicon interposer structure of the test sample using computed tomography CT technology to obtain sub-micron resolution three-dimensional imaging data; the imaging data can non-destructively present the bonding connection state, the interconnection state of TSV and RDL, and the TSV filling state, forming cross-scale characterization data covering the sample's external morphology to its internal microstructure. Leveraging the synergistic effect of the high-brightness X-ray source and high-resolution detector, sub-micron level three-dimensional imaging is achieved through 2D / 3DX-ray technology. Its non-destructive nature allows for the complete presentation of bonding connections, TSV-RDL interconnections, and TSV filling states, avoiding sample damage; simultaneously, it forms cross-scale characterization data covering the external morphology to the internal microstructure, accurately capturing early defects such as interface microcracks and delamination, compensating for the blind spots in traditional detection methods regarding internal structures. (See attached image) Figure 3a Appendix Figure 3b Appendix Figure 3c Appendix Figure 3d As shown, attached Figure 3a Appendix Figure 3b The image shows the morphological features of the test sample under 2D-Xray imaging. Figure 3b For the appendix Figure 3a Detailed magnified image of the bonding connection state; attached Figure 3c Appendix Figure 3d The image shows the topography of pads and vias under 3D-Xray imaging. Figure 3d It is attached Figure 3c Enlarged details of the pads and vias are shown; using 2DX-ray and 3DX-ray non-destructive testing techniques, a high-brightness X-ray source and a high-resolution detector, computed tomography (CT) technology is employed to perform sub-micron resolution stereoscopic imaging of the adapter board; (See attached image). Figure 4a Appendix Figure 4b As shown, attached Figure 4a A diagram showing the melting of aluminum bonding wires is attached. Figure 4b The RDL bulge pattern allows for non-destructive observation of the bonding wires to the pads, the interconnection between TSVs and the RDL, and the filling of TSV vias.

[0057] In step 3, microscopic data are collected using SEM and EBSD, including: characterizing the cross-section of the test sample using SEM and EBSD. SEM and EBSD are two types of microscopic characterization techniques for the cross-section of the test sample. By observing the cross-section, the microscopic morphology, defects and grain orientation information inside the TSV structure can be accurately obtained.

[0058] First, the edge of the test sample is aligned parallel to the edge of the sample stage. Then, the cross-section of the test sample is tilted to a preset angle, and the working distance is set. An accelerating voltage is applied in a vacuum environment to excite the Kikuchi pattern. Microscopic morphology data and void / hill defect data of the test sample are acquired using SEM, and Cu grain orientation data are acquired using EBSD. Aztec-crystal software is then used to analyze and process the microscopic morphology data, void / hill defect data, and Cu grain orientation data to obtain microscopic data of the TSV structure, including grain orientation distribution and morphological characteristics. By combining SEM and EBSD and setting standardized test parameters, the microscopic morphology, defects, and Cu grain orientation data of the sample are accurately acquired. Compared to methods lacking microstructural evolution analysis, after analysis and processing by Aztec-crystal software, key information such as TSV structure grain orientation distribution and morphological characteristics can be obtained. This allows for the capture of early failure microscopic signals such as grain boundary degradation and microvoids, helping to trace the root cause of failure.

[0059] In step 3, during the cross-scale data acquisition process, surface acoustic wave (SAW) detection technology or terahertz wave detection technology is also used to assist in acquiring imaging data. If SAW detection technology is used, it utilizes the changes in the propagation characteristics of sound waves at the interface of the test sample material to achieve highly sensitive non-destructive testing of microcracks and delamination defects at the TSV-RDL interface. If terahertz wave detection technology is used, it utilizes the penetrability of terahertz waves through dielectric materials to obtain imaging data of the deep internal structure of the sample. By supplementing imaging data with SAW or terahertz wave detection technologies, complementary advantages are formed. The former, with its sensitivity to changes in the propagation characteristics of the material interface, can accurately capture minute defects such as microcracks and delamination at the TSV-RDL interface, while the latter, relying on its strong penetrability through dielectric materials, clearly presents the deep internal structure of the sample. Both technologies corroborate X-ray imaging data, filling the blind spots in interface defect identification and deep structure observation, and improving the accuracy of failure tracing.

[0060] Step 4, Multi-parameter Fusion Analysis and Early Warning Judgment: Resistance data, imaging data, and microscopic data are fused to establish a multi-parameter hierarchical early warning model. A Level 1 early warning is triggered based on resistance data; a Level 2 early warning is triggered based on the Level 1 early warning combined with imaging data; and a Level 3 early warning is triggered based on the Level 2 early warning combined with microscopic data. For example, Level 1: ΔR / R0 ≥ 10%, where ΔR is the resistance change and R0 is the initial resistance value; Level 2: Macroscopic low-magnification appearance and non-destructive testing analysis; Level 3: Microscopic morphology analysis.

[0061] In step 4, a multi-parameter hierarchical early warning model is established, including: using an LSTM time series network from deep learning algorithms, analyzing resistance time series data, temperature time series data, and corresponding failure records from historical tests, autonomously learning the mapping relationship between data features and failure states, and establishing an adaptively optimized failure prediction model. By leveraging the LSTM time series network, the correlation between historical resistance and temperature time series data and failure records is deeply mined; by autonomously learning the mapping relationship between data features and failure states, it can break free from dependence on physical failure models and construct an adaptively optimized failure prediction model. This model can capture early, weak failure signals, achieve very early warning, and dynamically optimize parameters with new data, improving the accuracy of early warning.

[0062] In summary, this solution, through standardized design of the entire process of test structure, data acquisition, and criterion model, combined with technological innovations in cross-scale characterization and multi-parameter early warning, not only achieves accurate capture of early failures in TSV-RDL interconnect structures, but also establishes a unified and comparable evaluation system, providing standardized technical support for process optimization and product reliability improvement.

[0063] The above are merely embodiments of the present invention. The invention is not limited to the fields covered by these embodiments. Commonly known structures and characteristics in the solutions are not described in detail here. Those skilled in the art are aware of all common technical knowledge in the field prior to the application date or priority date, are able to access all existing technologies in that field, and have the ability to apply conventional experimental methods prior to that date. Those skilled in the art can, under the guidance of this application, improve and implement this solution in combination with their own capabilities. Some typical known structures or methods should not be obstacles for those skilled in the art to implement this application. It should be noted that those skilled in the art can make several modifications and improvements without departing from the structure of the present invention. These should also be considered within the scope of protection of the present invention, and will not affect the effectiveness of the implementation of the present invention or the practicality of the patent. The scope of protection claimed in this application should be determined by the content of its claims, and the specific embodiments described in the specification can be used to interpret the content of the claims.

Claims

1. A method for failure testing and analysis of TSV-RDL interconnect structures, characterized in that, Including the following steps: Step 1, Preparation of test sample: The test sample adopts a daisy chain structure. The test sample has a TSV. The TSV has a copper pillar. The upper and lower ends of the copper pillar are electrically connected to the RDL layer. The two ends of the daisy chain structure are provided with pads. The pads are bonded to the test printed circuit board through gold wire bonding to form a closed current path. Step 2, Apply multi-physics stress: Apply thermal stress to the test sample according to the preset temperature gradient, time gradient and heating rate and cooling rate, and at the same time apply electromigration stress to the test sample according to the preset temperature gradient, current density gradient and energizing time. Step 3, cross-scale data acquisition: Power is applied to the test sample, and the resistance data of the test sample is acquired in real time; imaging data of the test sample is acquired by X-ray computed tomography; microscopic data are acquired by SEM and EBSD. Step 4, Multi-parameter fusion analysis and early warning determination: The resistance data, imaging data and microscopic data are fused and processed to establish a multi-parameter hierarchical early warning model. A first-level early warning is triggered based on the resistance data, a second-level early warning is triggered based on the first-level early warning combined with the imaging data, and a third-level early warning is triggered based on the second-level early warning combined with the microscopic data.

2. The failure test and analysis method for TSV-RDL interconnect structure according to claim 1, characterized in that, In step 3, the test sample is powered on, and the resistance data of the test sample is collected in real time. This includes: setting up a data acquisition system consisting of a digital multimeter, a multiplexer, and a temperature detector, as well as an experimental environment system consisting of an oil bath or an aging furnace, and placing the test sample in the experimental environment system; the digital multimeter is connected to the test sample through the multiplexer, and after the test sample is powered on, the digital multimeter collects the resistance information of the sample in real time, and the ambient temperature information collected by the temperature detector is transmitted to the computer in parallel through the multiplexer.

3. The failure test and analysis method for a TSV-RDL interconnect structure according to claim 2, characterized in that, In step 3, imaging data of the test sample is acquired by X-ray computed tomography (CT), including: using 2DX-ray and 3DX-ray non-destructive testing equipment that integrates a high-brightness X-ray source and a high-resolution detector, scanning the silicon interposer structure of the test sample by computed tomography CT technology to obtain sub-micron resolution three-dimensional imaging data; the imaging data can present the bonding connection state, the interconnection state of TSV and RDL and the filling state of TSV in a non-destructive manner, forming cross-scale characterization data covering the external morphology of the sample to the internal microstructure.

4. The failure test and analysis method for a TSV-RDL interconnect structure according to claim 3, characterized in that, In step 3, microscopic data are acquired using SEM and EBSD, including: characterizing the cross-section of the test sample using SEM and EBSD; first, adjusting the edge of the test sample to be parallel to the edge of the sample stage; then tilting the cross-section of the test sample to a preset angle; setting the working distance; and applying an accelerating voltage in a vacuum environment to excite the Kikuchi pattern; acquiring microscopic morphology data and void / hill defect data of the test sample using SEM; acquiring Cu grain orientation data using EBSD; and then using Aztec-crystal software to analyze and process the microscopic morphology data, void / hill defect data, and Cu grain orientation data to obtain microscopic data of the TSV structure, including the grain orientation distribution and morphological characteristics.

5. The failure test and analysis method for a TSV-RDL interconnect structure according to claim 4, characterized in that, In step 4, a multi-parameter hierarchical early warning model is established, including: using the LSTM time series network in deep learning algorithms, analyzing the resistance time series data, temperature time series data and corresponding failure records in historical tests, autonomously learning the mapping relationship between data features and failure states, and establishing an adaptive optimization failure prediction model.

6. The failure test and analysis method for a TSV-RDL interconnect structure according to claim 5, characterized in that, In step 2, applying multi-physics stress also includes: integrating a micro temperature sensor and a micro stress sensor in the vicinity of the TSV-RDL structure of the test sample or on a dedicated test pad using MEMS technology; using the micro temperature sensor and micro stress sensor to acquire local temperature data and local stress data inside the device; and synchronously transmitting the acquired local temperature data and local stress data to the data processing unit to assist in the optimization of the multi-parameter hierarchical early warning model and the failure cause tracing analysis.

7. The failure test and analysis method for a TSV-RDL interconnect structure according to claim 6, characterized in that, In step 3, during the cross-scale data acquisition process, surface acoustic wave (SAW) detection technology or terahertz wave detection technology is also used to assist in the acquisition of imaging data: if SAW detection technology is used, the characteristics of sound waves propagating at the interface of the test sample material are utilized to achieve highly sensitive non-destructive testing of microcracks and delamination defects at the TSV-RDL interface; if terahertz wave detection technology is used, the penetrability of terahertz waves to dielectric materials is utilized to obtain imaging data of the deep internal structure of the sample.

8. The failure test and analysis method for a TSV-RDL interconnect structure according to claim 7, characterized in that, In step 1, after preparing the test sample, before conducting cross-scale data acquisition, the test sample is embedded and cured using a conductive nickel-based alloy hot-mount material. The test sample is then mechanically polished using diamond sandpaper of a preset mesh size. During polishing, the surface condition of the sample is observed using an optical microscope at preset intervals. Polishing is stopped when the TSV is just exposed and there are no obvious scratches. The test sample is then mechanically polished using an Al2O3 polishing slurry of a first preset particle size until no obvious scratches are visible under the optical microscope. Next, a fine polishing is performed using an Al2O3 polishing suspension of a second preset particle size in conjunction with a DP-Nap polishing cloth to ensure no scratches remain on the sample surface. Finally, a vibration polishing technique is used for the final treatment of the test sample to eliminate residual surface stress. The first preset particle size is 3.0 μm, and the second preset particle size is 1.0 μm.

9. The failure test and analysis method for a TSV-RDL interconnect structure according to claim 8, characterized in that, In step 1, test samples are prepared by etching and electroplating.

10. A failure test and analysis system for TSV-RDL interconnect structures, characterized in that, Used to perform the method according to any one of claims 1-9.

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