Chip test analysis circuit and chip

Abstract

The present disclosure provides a chip test analysis circuit, comprising: an address decoding circuit, configured to generate a first test selection signal and a second test selection signal; an output test circuit, configured to select a corresponding to-be-output test signal from a plurality of to-be-output test signals according to the first test selection signal, and output the selected to-be-output test signal to a test node for output signal test analysis; an input test circuit, configured to select an input test channel corresponding to the second test selection signal from a plurality of input test channels according to the second test selection signal, and input a to-be-input test signal to a corresponding circuit inside a to-be-tested chip through the selected input test channel for internal circuit test analysis; and a test direction selection circuit, configured to generate a test mode selection signal, the test mode selection signal being used to control the output test circuit and the test node to be connected or disconnected, and control the input test circuit and the test node to be disconnected or connected.

Description

Technical Field

[0001] This disclosure relates to the field of integrated circuit technology, and in particular to a chip test and analysis circuit and chip. Background Technology

[0002] Some defects in integrated circuit design can cause malfunctions during factory testing, preventing the chip from achieving its intended functions and performance. In severe cases, it may even prevent the chip from powering on. Therefore, chip developers need to test and analyze the signals inside the chip to locate the fault and subsequently improve the chip.

[0003] In related technologies, signal analysis within chips typically involves direct probing or testing via pads. Probing methods involve removing the chip's package and using pre-existing electrical test points (probePADs) on a probe station. If no pre-existing test points are available, focused ion beam (FIB) methods are used to create test points on the chip surface before testing with a probe station. Regardless of the method used, direct probing requires removing the package and testing on a probe station, resulting in high costs and low efficiency.

[0004] The method of sending signals off-chip or on-chip via test pins (PADs) for testing does not require damaging the chip structure and package. While this method has significant advantages over probe-based methods, it still requires additional resources, such as the number of pins supporting the test. If a large number of signals need to be analyzed, and these signals are categorized as analog or digital, differentiating them via pins would require even more pins. Furthermore, adding signals into the chip requires additional pins. This increases the chip area and raises testing costs. Summary of the Invention

[0005] This disclosure provides a chip test and analysis circuit and a chip.

[0006] This disclosure provides a chip test and analysis circuit, which includes:

[0007] The address decoding circuit is used to generate a first test selection signal. Each first test selection signal is applied to select an output test channel of the chip under test. Each output test channel is used to output a test signal generated internally by the chip under test.

[0008] The address decoding circuit is also used to generate a second test selection signal. Each second test selection signal is applied to select an input test channel of the chip under test. Each input test channel is used to input the test signal to be input into the corresponding circuit inside the chip under test.

[0009] The output test circuit is provided with multiple output test signals generated inside the chip under test as inputs. The output test circuit is used to select the output test signal corresponding to the first test selection signal from the multiple output test signals according to the first test selection signal provided by the address decoding circuit, and output the selected output test signal to the test node for output signal test analysis.

[0010] The input test circuit is provided with a test signal from the chip under test. The input test circuit is used to select an input test channel corresponding to the second test selection signal from multiple input test channels according to the second test selection signal provided by the address decoding circuit, so as to input the test signal to be input to the corresponding circuit inside the chip under test for internal circuit test and analysis through the selected input test channel.

[0011] A test direction selection circuit is used to generate a test mode selection signal, which is used to control the connection or disconnection between the output test circuit and the test node, and to control the disconnection or connection between the input test circuit and the test node.

[0012] In some embodiments, the address decoding circuit includes at least two first decoding circuits and one second decoding circuit, wherein the input of the second decoding circuit is connected to the output of the first decoding circuit.

[0013] The first decoding circuit is used to generate a plurality of decoding signals based on a first external input signal, and the second decoding circuit is used to generate either the first test selection signal or the second test selection signal based on the decoding signals output by the at least two first decoding circuits.

[0014] In some embodiments, the first decoding circuit includes: a first resistor, a second resistor, a third resistor, a first P-type transistor, a second P-type transistor, a third P-type transistor, a first N-type transistor, a second N-type transistor, a third N-type transistor, a fourth N-type transistor, a first inverter, a second inverter, a third inverter, a fourth inverter, a first AND gate, a second AND gate, and a third AND gate.

[0015] Wherein, one end of the first resistor is connected to a first external pin and the other end is connected to a first node. The first external pin is multiplexed from a pin on the chip under test and is used to provide a first external input signal. One end of the second resistor is connected to the first node and the other end is connected to a second node. One end of the third resistor is connected to the second node and the other end is grounded.

[0016] The control electrode of the first N-type transistor is connected to the first node, the first electrode is grounded, and the second electrode is connected to the third node; the control electrode of the second N-type transistor is connected to the second node, the first electrode is grounded, and the second electrode is connected to the fourth node; the control electrode of the third N-type transistor is connected to the first bias current terminal, the first electrode is grounded, and the second electrode is connected to the first bias current terminal; the control electrode of the fourth N-type transistor is connected to the first bias current terminal, the first electrode is grounded, and the second electrode is connected to the fifth node.

[0017] The control electrode of the first P-type transistor is connected to the fifth node, the first electrode is connected to the first constant voltage power supply terminal, and the second electrode is connected to the fifth node; the control electrode of the second P-type transistor is connected to the fifth node, the first electrode is connected to the first constant voltage power supply terminal, and the second electrode is connected to the third node; the control electrode of the third P-type transistor is connected to the fifth node, the first electrode is connected to the first constant voltage power supply terminal, and the second electrode is connected to the fourth node.

[0018] The input terminal of the first inverter is connected to the third node, and its output terminal is connected to the input terminal of the second inverter; the input terminal of the third inverter is connected to the fourth node, and its output terminal is connected to the input terminal of the fourth inverter.

[0019] The output of the fourth inverter is connected to the first input of the first AND gate, and the output of the second inverter is connected to the second input of the first AND gate; the output of the fourth inverter is also connected to the first input of the second AND gate, and the output of the first inverter is also connected to the second input of the second AND gate; the output of the third inverter is also connected to the first input of the third AND gate, and the output of the first inverter is also connected to the second input of the third AND gate.

[0020] The output of the first AND gate is used to generate a decoded signal based on the signal output by the fourth inverter and the signal output by the second inverter; the output of the second AND gate is used to generate a decoded signal based on the signal output by the fourth inverter and the signal output by the first inverter; the output of the third AND gate is used to generate a decoded signal based on the signal output by the third inverter and the signal output by the first inverter.

[0021] In some embodiments, the second decoding circuit includes a 3-8 decoding circuit, a 2-4 decoding circuit, or a 46 decoding circuit.

[0022] In some embodiments, the address decoding circuit includes a third decoding circuit, which is used to generate the first test selection signal or the second test selection signal based on the logic input address signal provided by the digital logic circuit inside the chip under test.

[0023] In some embodiments, the third decoding circuit is implemented using a binary decoder.

[0024] In some embodiments, the test direction selection circuit includes: a first control switch, a fourth resistor, a fifth resistor, a fourth P-type transistor, a fifth P-type transistor, a fifth N-type transistor, a sixth N-type transistor, a seventh N-type transistor, and a fifth inverter;

[0025] Wherein, one end of the first control switch is connected to the second external pin, and the other end is connected to one end of the fourth resistor. The second external pin is multiplexed from a pin on the chip under test and is used to provide a second external input signal. The other end of the fourth resistor is connected to the sixth node. One end of the fifth resistor is connected to the sixth node, and the other end is grounded.

[0026] The control electrode of the fifth N-type transistor is connected to the sixth node, the first electrode is grounded, and the second electrode is connected to the seventh node; the control electrode of the sixth N-type transistor is connected to the second bias current terminal, the first electrode is grounded, and the second electrode is connected to the second bias current terminal; the control electrode of the seventh N-type transistor is connected to the second bias current terminal, the first electrode is grounded, and the second electrode is connected to the eighth node.

[0027] The control electrode and the second electrode of the fourth P-type transistor are both connected to the eighth node, and the first electrode is connected to the second constant voltage power supply terminal; the control electrode of the fifth P-type transistor is connected to the eighth node, the first electrode is connected to the second constant voltage terminal, and the second electrode is connected to the seventh node.

[0028] The input terminal of the fifth inverter is connected to the seventh node, and the fifth inverter is used to output the test mode selection signal according to the signal output by the seventh node.

[0029] In some embodiments, the test signal to be output is an analog signal, and the output test circuit includes an analog signal output test circuit and an analog output buffer.

[0030] The analog signal output test circuit uses an analog data selector. The input of the analog signal output test circuit is a plurality of test signals to be output generated inside the chip under test. The output of the analog signal output test circuit is connected to the input of the analog output buffer. The output of the analog output buffer is connected to the test node through a second control switch.

[0031] In some embodiments, the test signal to be output is a digital signal, and the output test circuit includes a digital signal output test circuit and a digital output buffer;

[0032] The digital signal output test circuit uses a digital data selector. The input of the digital signal output test circuit is a plurality of test signals to be output generated inside the chip under test. The output of the digital signal output test circuit is connected to the input of the digital output buffer. The output of the digital output buffer is connected to the test node through a third control switch.

[0033] In some embodiments, the input test signal is an analog signal, and the input test circuit includes an analog signal input test circuit;

[0034] The analog signal input test circuit uses an analog demultiplexer. The input of the analog signal input test circuit is connected to the test node through a fourth control switch. The output of the analog signal input test circuit consists of multiple input test channels.

[0035] In some embodiments, the input test signal is a digital signal, and the input test circuit includes a digital signal input test circuit;

[0036] The digital signal input test circuit uses a digital demultiplexer. The input of the digital signal input test circuit is connected to the test node through a fifth control switch. The output of the digital signal input test circuit consists of multiple input test channels.

[0037] In some embodiments, the chip test and analysis circuit further includes:

[0038] The test start circuit is used to output a test enable signal to control the chip under test to enter the test mode.

[0039] In some embodiments, the test start-up circuit includes: a sixth resistor, a seventh resistor, an eighth resistor, a ninth resistor, a sixth P-type transistor, a seventh P-type transistor, an eighth N-type transistor, a ninth N-type transistor, a tenth N-type transistor, and a sixth inverter;

[0040] Wherein, one end of the sixth resistor is connected to the third external pin, and the other end is connected to the ninth node; the third external pin is multiplexed from a pin on the chip under test, and the third external pin is used to provide a third external input signal; one end of the seventh resistor is connected to the ninth node, and the other end is grounded; one end of the eighth resistor is connected to the third external pin, and the other end is connected to the second terminal of the eighth N-type transistor; one end of the ninth resistor is connected to the third constant voltage power supply terminal, and the other end is connected to the tenth node;

[0041] The control electrode of the eighth N-type transistor is connected to the second electrode, and the first electrode is grounded; the control electrode of the ninth N-type transistor is connected to the control electrode of the eighth N-type transistor, the first electrode is grounded, and the second electrode is connected to the eleventh node; the control electrode of the tenth N-type transistor is connected to the ninth node, the first electrode is grounded, and the second electrode is connected to the tenth node.

[0042] The control electrode and the second electrode of the sixth P-type transistor are connected to the eleventh node, and the first electrode is connected to the third constant voltage power supply terminal; the control electrode of the seventh P-type transistor is connected to the eleventh node, the first electrode is connected to the third constant voltage power supply terminal, and the second electrode is used to output bias current.

[0043] The input of the sixth inverter is connected to the tenth node, and its output is used to output the test enable signal.

[0044] This disclosure provides a chip that integrates a chip test and analysis circuit, the chip test and analysis circuit including the chip test and analysis circuit described above.

[0045] According to the chip test and analysis circuit and chip provided in this disclosure, on the one hand, different signals generated inside the chip under test can be selected through the output test circuit and tested from an independent test node; on the other hand, the test node can also send signals into the chip under test through the input test circuit to test the internal circuitry of the chip under test. The output and input test circuits can select the test channel based on the test selection signal provided by the address decoding circuit. By setting the address decoding circuit and selecting the test channel through the output and input test circuits, the number of test pins can be effectively reduced, allowing chip test and analysis to be performed with fewer pins. This minimizes the number of pins required for chip test and analysis, reduces chip area, and lowers test costs. Attached Figure Description

[0046] Figure 1 A structural block diagram of a chip test and analysis circuit provided in this embodiment of the present disclosure;

[0047] Figure 2This is a schematic diagram of the structure of an address decoding circuit provided in an embodiment of the present disclosure;

[0048] Figure 3 A schematic diagram of the circuit structure of a first decoding circuit provided in an embodiment of this disclosure;

[0049] Figure 4 A schematic diagram of another address decoding circuit provided in an embodiment of this disclosure;

[0050] Figure 5 A schematic diagram of the circuit structure of a test direction selection circuit provided in an embodiment of this disclosure;

[0051] Figure 6 This is a schematic diagram of the structure of an output test circuit and an input test circuit provided in an embodiment of the present disclosure;

[0052] Figure 7 A structural block diagram of another chip test and analysis circuit provided in this embodiment of the present disclosure;

[0053] Figure 8 This is a schematic diagram of the circuit structure of a test startup circuit provided in an embodiment of the present disclosure. Detailed Implementation

[0054] The chip test and analysis circuit provided in this disclosure will be described in detail below with reference to the accompanying drawings.

[0055] The present disclosure will be described more fully below with reference to the accompanying drawings; however, the embodiments shown may be embodied in different forms and should not be construed as being limited to the embodiments set forth in this disclosure. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will enable those skilled in the art to fully understand the scope of this disclosure.

[0056] This disclosure may be described with reference to plan and / or cross-sectional views using the ideal schematic diagrams of this disclosure. Therefore, the example illustrations may be modified according to manufacturing techniques and / or tolerances.

[0057] Where there is no conflict, the various embodiments of this disclosure and the features thereof in the embodiments may be combined with each other.

[0058] The terminology used in this disclosure is for describing particular embodiments only and is not intended to limit the disclosure. The term "and / or" as used in this disclosure includes any and all combinations of one or more of the associated enumerated entries. The singular forms "a" and "the" as used in this disclosure are also intended to include the plural forms, unless the context clearly indicates otherwise. The term "comprising" as used in this disclosure specifies the presence of the stated feature, integral, step, operation, element, and / or component, but does not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components, and / or groups thereof.

[0059] Unless otherwise specified, all terms used in this disclosure (including technical and scientific terms) have the same meaning as commonly understood by one of ordinary skill in the art. It will also be understood that terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant art and this disclosure, and will not be interpreted as having an idealized or overly formal meaning, unless expressly so defined in this disclosure.

[0060] This disclosure is not limited to the embodiments shown in the accompanying drawings, but includes modifications to the configuration based on the manufacturing process. Therefore, the areas illustrated in the drawings are schematic, and the shapes of the areas shown illustrate specific shapes of the areas of an element, but are not intended to be limiting.

[0061] This disclosure provides a chip test and analysis circuit. Figure 1 An optional implementation of the chip test and analysis circuit provided in this disclosure is illustrated. For example... Figure 1 As shown, the chip test and analysis circuit of this embodiment includes:

[0062] Address decoding circuit 101 is used to generate first test selection signals. Each first test selection signal is applied to select one output test channel of the chip under test. Each output test channel is used to output a test signal generated internally by the chip under test.

[0063] The address decoding circuit 101 is also used to generate a second test selection signal. Each second test selection signal is applied to select an input test channel of the chip under test. Each input test channel is used to input the test signal to be input into the corresponding circuit inside the chip under test.

[0064] The output test circuit 102 receives multiple output test signals generated inside the chip under test as input. The output test circuit 102 is used to select the output test signal corresponding to the first test selection signal from the multiple output test signals according to the first test selection signal provided by the address decoding circuit 101, and output the selected output test signal to the test node 103 for output signal test analysis.

[0065] The input test circuit 104 receives the test signal provided by the chip under test. The input test circuit 104 selects the input test channel corresponding to the second test selection signal from multiple input test channels according to the second test selection signal provided by the address decoding circuit 101, so as to input the test signal to be input to the corresponding circuit inside the chip under test for internal circuit test analysis through the selected input test channel.

[0066] The test direction selection circuit 105 is used to generate a test mode selection signal. The test mode selection signal is used to control the connection or disconnection between the output test circuit 102 and the test node 103, and to control the disconnection or connection between the input test circuit 104 and the test node 103.

[0067] In this embodiment, the test mode is selected by the test direction selection circuit 105, that is, the output test circuit 102 is selected for testing, or the input test circuit is selected for testing. When the test mode selection signal is the first test mode selection signal, the output test circuit 102 is connected to the test node 103, and the input test circuit 104 is disconnected from the test node 103. The chip under test is controlled to output the test signal to the output test circuit 102. When the test mode selection signal is the second test mode selection signal, the output test circuit 102 is disconnected from the test node 103, and the input test circuit 104 is connected to the test node 103. The input test signal is output to the test node 103 through an external device, so that the input test signal is input to the input test circuit 104 through the test node 103.

[0068] For example, the first test mode selects a low-level signal, and the second test mode selects a high-level signal.

[0069] In this embodiment of the disclosure, the output test signal is the signal output from the chip under test and is to be tested. This part of the signal needs to be pulled out from the chip under test to the test node for signal testing and analysis. The input test signal is a signal generated by an external device and used to input into the chip under test for power performance analysis of related circuits. This part of the signal needs to be sent into the chip under test for power performance analysis of related circuits inside the chip under test. Specifically, when it is necessary to test and analyze the signals generated inside the chip under test, the test direction selection circuit 105 generates a first test selection signal to select the output test circuit 102 for testing. The output test circuit 102 selects different output test signals generated inside the chip under test, and outputs the selected output test signal through the test node 103 to an external test device for signal testing and analysis. The external test device is, for example, an oscilloscope. When it is necessary to test and analyze the circuit inside the chip under test, the test direction selection circuit 105 generates a second test selection signal to select the input test circuit 104 for testing. The external device outputs the input test signal to the test node 103, and the test node 103 inputs the input test signal to the input test circuit 104. The input test circuit 104 injects the input test signal into the corresponding circuit inside the chip under test, thereby changing the working state of the corresponding circuit inside the chip under test. This allows for internal circuit testing and analysis of the corresponding circuit inside the chip under test, verifying the relevant functional performance of the corresponding circuit inside the chip under test.

[0070] The chip test and analysis circuit provided in this embodiment can, on the one hand, select different signals generated inside the chip under test through the output test circuit and pull them out for testing from an independent test node; on the other hand, the test node can also send signals into the chip under test through the input test circuit to test the internal circuitry of the chip. The output and input test circuits can select the test channel based on the test selection signal provided by the address decoding circuit. By setting the address decoding circuit and selecting the test channel through the output and input test circuits, the number of test pins can be effectively reduced, allowing chip test and analysis to be performed with fewer pins. This minimizes the number of pins required for chip test and analysis, reduces chip area, and lowers testing costs.

[0071] Figure 2 This illustration shows an optional implementation of the address decoding circuit provided in an embodiment of the present disclosure. In some embodiments, such as... Figure 2 As shown, the address decoding circuit 101 includes at least two first decoding circuits 1011 and one second decoding circuit 1012, with the input of the second decoding circuit 1012 correspondingly connected to the output of the first decoding circuit 1011.

[0072] The first decoding circuit 1011 is used to generate multiple decoding signals A according to the first external input signal, and the second decoding circuit 1012 is used to generate a first test selection signal B1 or a second test selection signal B2 according to at least two decoding signals A output by the first decoding circuit 1011.

[0073] The input of the first decoding circuit 1011 is connected to the first external pin 1010. The first external pin 1010 can reuse a pin on the chip under test. The first external pin 1010 is used to provide a first external input signal, which can be provided to the first external pin 1010 by an external device.

[0074] Figure 3 This illustration shows an optional implementation of the first decoding circuit provided in an embodiment of the present disclosure. In some embodiments, such as... Figure 3 As shown, the first decoding circuit 1011 includes: a first resistor R1, a second resistor R2, a third resistor R3, a first P-type transistor MP1, a second P-type transistor MP2, a third P-type transistor MP3, a first N-type transistor MN1, a second N-type transistor MN2, a third N-type transistor MN3, a fourth N-type transistor MN4, a first inverter INV1, a second inverter INV2, a third inverter INV3, a fourth inverter INV3, a first AND gate 301, a second AND gate 302, and a third AND gate 303.

[0075] In this circuit, one end of the first resistor R1 is connected to the first external pin 1010, and the other end is connected to the first node N1. The first external pin 1010 can reuse a pin on the chip under test, or it can be set as an independent pin on the chip. The first external pin 1010 is used to provide the first external input signal. One end of the second resistor R2 is connected to the first node N1, and the other end is connected to the second node N2. One end of the third resistor R3 is connected to the second node N2, and the other end is grounded to GND.

[0076] The control electrode of the first N-type transistor MN1 is connected to the first node N1, the first electrode is grounded (GND), and the second electrode is connected to the third node N3; the control electrode of the second N-type transistor MN2 is connected to the second node N2, the first electrode is grounded (GND), and the second electrode is connected to the fourth node N4; the control electrode of the third N-type transistor MN3 is connected to the first bias current terminal I1, the first electrode is grounded (GND), and the second electrode is connected to the first bias current terminal I1; the control electrode of the fourth N-type transistor MN4 is connected to the first bias current terminal I1, the first electrode is grounded (GND), and the second electrode is connected to the fifth node N5.

[0077] The control electrode of the first P-type transistor MP1 is connected to the fifth node N5, the first electrode is connected to the first constant voltage power supply terminal VDD1, and the second electrode is connected to the fifth node N5. The first constant voltage power supply terminal VDD1 is used to provide power supply voltage. The control electrode of the second P-type transistor MP2 is connected to the fifth node N5, the first electrode is connected to the first constant voltage power supply terminal VDD1, and the second electrode is connected to the third node N3. The control electrode of the third P-type transistor MP3 is connected to the fifth node N5, the first electrode is connected to the first constant voltage power supply terminal VDD1, and the second electrode is connected to the fourth node N4.

[0078] The input of the first inverter INV1 is connected to the third node N3, and its output is connected to the input of the second inverter INV2; the input of the third inverter INV3 is connected to the fourth node N4, and its output is connected to the input of the fourth inverter INV4.

[0079] The output terminal s1p of the fourth inverter INV4 is connected to the first input terminal of the first AND gate 301, and the output terminal s0p of the second inverter INV2 is connected to the second input terminal of the first AND gate 301. The output terminal s1p of the fourth inverter INV4 is also connected to the first input terminal of the second AND gate 302, and the output terminal s0n of the first inverter INV1 is also connected to the second input terminal of the second AND gate 302. The output terminal s1n of the third inverter INV3 is also connected to the first input terminal of the third AND gate 303, and the output terminal s0n of the first inverter INV1 is also connected to the second input terminal of the third AND gate 303.

[0080] The first AND gate 301 is used to generate a decoded signal vlo based on the signal output from the output terminal s1p of the fourth inverter INV4 and the signal output from the output terminal s0p of the second inverter INV2; the second AND gate 302 is used to generate a decoded signal vmd based on the signal output from the output terminal s1p of the fourth inverter INV4 and the signal output from the output terminal s0n of the first inverter INV1; the third AND gate 303 is used to generate a decoded signal vhi based on the signal output from the output terminal s1n of the third inverter INV3 and the signal output from the output terminal s0n of the first inverter INV1.

[0081] In this embodiment, different voltage values ​​can be set through the first external pin 1010, and different voltage divider signals V1 and V2 can be obtained using the first resistor R1, the second resistor R2, and the third resistor R3. These two voltage divider signals V1 and V2 control transistors MN1 and MN2 respectively. Based on the conduction status of MN1 and MN2, corresponding different level signals V3 and V4 are obtained. These two level signals V3 and V4 are processed by inverters INV1 to INV4 and logic AND gates 301 to 303 to finally obtain three decoded signals, namely vlo, vmd, and vhi. Only one of these three decoded signals vlo, vmd, and vhi is a logic 1, and the rest are logic 0.

[0082] Specifically, when the first external input signal provided by the first external pin 1010 is a low-level signal, the voltage divider signal V1 output by the first node N1 and the voltage divider signal V2 output by the second node N2 are both low-level signals. Transistors MN1 and MN2 are turned off, while transistors MN3 and MN4 are turned on under the action of the bias current output by the first bias current terminal I1. Transistors MP1, MP2, and MP3 are turned on under the action of the voltage at the fifth node N5. The first constant voltage power supply terminal VDD1 writes the power supply voltage to the third node N3 and the fourth node N4 through the turned-on transistors MP2 and MP3. The voltages of the third node N3 and the fourth node N4 are set to high level, that is, at this time, the voltage V3 output by the third node N3 and the voltage V4 output by the fourth node N4 are both high-level signals. The voltage V3 output by the third node N3 is processed by the first inverter INV1 to output a low-level signal. The low-level signal output by the output terminal s0n of the first inverter INV1 is processed by the second inverter INV2 to make the output terminal S0p outputs a high-level signal; similarly, the voltage V4 output by the fourth node N4 is processed by the third inverter INV3 to output a low-level signal. The low-level signal output by the output terminal s1n of the third inverter INV3 is processed by the fourth inverter INV4 to make the output terminal s1p output a high-level signal. The high-level signal output by the output terminal s1p of the fourth inverter INV4 and the high-level signal output by the output terminal s0p of the second inverter INV2 are combined by the first logic AND gate 301 to obtain the decoded signal vlo, which is logic 1. The high-level signal output by the output terminal s1p of the fourth inverter INV4 and the low-level signal output by the output terminal s0n of the first inverter INV1 are combined by the second logic AND gate 302 to obtain the decoded signal vmd, which is logic 0. The low-level signal output by the output terminal s1n of the third inverter INV3 and the low-level signal output by the output terminal s0n of the first inverter INV1 are combined by the third logic AND gate 303 to obtain the decoded signal vhi, which is logic 0.

[0083] When the first external input signal provided by the first external pin 1010 is a high-level signal, the voltage divider signal V1 output by the first node N1 and the voltage divider signal V2 output by the second node N2 are both high-level signals. Transistor MN1 is turned on by the voltage divider signal V1 output by the first node N1, and transistor MN2 is turned on by the voltage divider signal V2 output by the second node N2. The ground voltage (low-level voltage) is written to the third node N3 and the fourth node N4 through the turned-on transistors MN1 and MN2. The voltages of the third node N3 and the fourth node N4 are set to low level, that is, the voltage V3 output by the third node N3 and the voltage V4 output by the fourth node N4 are both low-level signals. The voltage V3 output by the third node N3 is turned on by the first inverter INV1 and outputs a high-level signal. The high-level signal output by the output terminal s0n of the first inverter INV1 is turned on by the second inverter INV2 and outputs a low-level signal by the output terminal s0p. Similarly, The voltage V4 output from the fourth node N4 is processed by the third inverter INV3 to output a high-level signal. The high-level signal output from the output terminal s1n of the third inverter INV3 is processed by the fourth inverter INV4 to output a low-level signal from the output terminal s1p. The low-level signal output from the output terminal s1p of the fourth inverter INV4 and the low-level signal output from the output terminal s0p of the second inverter INV2 are combined by the first logic AND gate 301 to obtain the decoded signal vlo, which is logic 0. The low-level signal output from the output terminal s1p of the fourth inverter INV4 and the high-level signal output from the output terminal s0n of the first inverter INV1 are combined by the second logic AND gate 302 to obtain the decoded signal vmd, which is logic 0. The high-level signal output from the output terminal s1n of the third inverter INV3 and the high-level signal output from the output terminal s0n of the first inverter INV1 are combined by the third logic AND gate 303 to obtain the decoded signal vhi, which is logic 1.

[0084] When the first external input signal provided by the first external pin 1010 is an intermediate level signal, the intermediate level signal is a signal with a level between low level and high level. The voltage divider signal V1 output by the first node N1 is greater than the voltage divider signal V2 output by the second node N2. Transistor MN1 is turned on under the action of the voltage divider signal V1 output by the first node N1, and transistor MN2 is turned off under the action of the voltage divider signal V2 output by the second node N2. The ground voltage (low level voltage) is written to the third node N3 through the turned-on transistor MN1. At the same time, transistors MN3 and MN4 are turned on under the action of the bias current output by the first bias current terminal I1. Transistor MP3 is turned on under the action of the voltage of the fifth node N5. The first constant voltage power supply terminal VDD1 writes the power supply voltage to the fourth node N4 through the turned-on transistor MP3. At this time, the voltage of the third node N3 is set to a low level, and the voltage of the fourth node N4 is set to a high level. That is, the voltage V3 output by the third node N3 is a low-level signal, and the voltage V4 output by the fourth node N4 is a high-level signal. The voltage V3 output by the third node N3 passes through the first inverter INV1 and outputs a high-level signal. The high-level signal output from the output terminal s0n of the first inverter INV1 passes through the second inverter INV2, causing the output terminal s0p to output a low-level signal. Similarly, the voltage V4 output by the fourth node N4 passes through the third inverter INV3 and outputs a low-level signal. The low-level signal output from the output terminal s1n of the third inverter INV3 passes through the fourth inverter INV4, causing... The output terminal s1p outputs a high-level signal; the high-level signal output from the output terminal s1p of the fourth inverter INV4 and the low-level signal output from the output terminal s0p of the second inverter INV2, under the action of the first logic AND gate 301, obtain the decoded signal vlo, which is logic 0; the high-level signal output from the output terminal s1p of the fourth inverter INV4 and the high-level signal output from the output terminal s0n of the first inverter INV1, under the action of the second logic AND gate 302, obtain the decoded signal vmd, which is logic 1; the low-level signal output from the output terminal s1n of the third inverter INV3 and the high-level signal output from the output terminal s0n of the first inverter INV1, under the action of the third logic AND gate 303, obtain the decoded signal vhi, which is logic 0.

[0085] In some embodiments, the number of first decoding circuits 1011 is two. When two first decoding circuits 1011 are used, each of the first decoding circuits 1011 can output three decoding signals. These signals are then combined by the second decoding circuit 1012 to generate three decoded signals. 2 -1 = 8 test selection signals.

[0086] In some embodiments, the number of first decoding circuits 1011 is three. When three first decoding circuits 1011 are used, each of the three first decoding circuits 1011 can output three decoded signals, which are then combined by the second decoding circuits 1012 to generate three decoded signals. 3 -1 = 26 test selection signals.

[0087] It should be noted that the embodiments disclosed herein are for Figure 3 The number of resistors in the circuit shown is not limited; however, this is done to further reduce the number of pins. Figure 3 The circuit shown can also include an additional voltage divider resistor. One end of the new voltage divider resistor is connected in series with the third resistor R3, and the other end is grounded. Simultaneously, a P-type transistor and an N-type transistor are added. The control electrode of the P-type transistor is connected to the fifth node N5, the first electrode of the P-type transistor is connected to the first constant voltage power supply terminal VDD, and the second electrode of the P-type transistor is connected to the new node. The control electrode of the N-type transistor is connected to one end of the voltage divider resistor, the first electrode of the N-type transistor is grounded, and the second electrode of the N-type transistor is connected to the new node. Additionally, two inverters are added. The new node is connected to the input of one of the inverters, and the output of one inverter is connected to the input of the other inverter.

[0088] The voltages output from the third node N3, the fourth node N4, and the newly added node are processed by their respective series-connected inverters. The signals from the different inverters are then combined and controlled by an AND gate to output four decoded signals. These signals are then combined by the second decoding circuit 1012 to generate more selection signals. In this case, if two first decoding circuits 1011 are used, each first decoding circuit 1011 can generate four decoded signals. After being combined and decoded by the second decoding circuit 1012, four... 2 -1 = 15 test selection signals; if three first decoding circuits are used, each first decoding circuit 1011 can generate four decoded signals, which, after being combined and decoded by the second decoding circuit 1012, can generate four... 3 -1 = 63 test selection signals.

[0089] In some embodiments, the second decoding circuit 1012 includes a 3-8 decoding circuit (also known as a 3-line 8-line decoder), a 2-4 decoding circuit (also known as a 2-line 4-line decoder), or a 4-6 decoding circuit (also known as a 4-line 16-line decoder).

[0090] Figure 4 An alternative implementation of the address decoding circuit according to an embodiment of this disclosure is shown. In some embodiments, such as... Figure 4As shown, the address decoding circuit 101 includes a third decoding circuit 1013, which is used to generate a first test selection signal B1 or a second test selection signal B2 based on the logic input address signal C provided by the digital logic circuit inside the chip under test.

[0091] For example, the logic input address signal C sent by the digital logic circuit is a binary address signal. Through the third decoding circuit 1013, a corresponding quadratic number of test selection signals can be obtained. If the logic input address signal C is a 5-bit binary address signal, then 2... 5 = 32 test selection signals.

[0092] In some embodiments, the test selection signal generated by the combination of the first decoding circuit 1011 and the second decoding circuit 1012 can be used to select some signals before the digital logic circuit inside the chip under test can operate normally. The test selection signal is generated using signals provided by external pins, allowing selection of corresponding signals for test analysis even without the digital logic circuit being operational. Conversely, the test selection signal generated by the third decoding circuit 1013 can be used to select some signals after the digital logic circuit is operating normally. It is generated directly using the logic input address signals output by the digital logic circuit, saving significant resources.

[0093] In some embodiments, when the digital logic circuits inside the chip under test are functioning normally, the required test selection signal can be generated by the third decoding circuit 1013, or by a combination of the first decoding circuit 1011 and the second decoding circuit 1012. When the digital logic circuits inside the chip under test malfunction and cannot function normally, the required test selection signal is generated by a combination of the first decoding circuit 1011 and the second decoding circuit 1012. This effectively saves resources and avoids test analysis circuit failure caused by digital logic circuit malfunctions.

[0094] In some embodiments, the third decoding circuit 1013 is implemented using a binary decoder. The specific binary decoder used can be determined according to the number of bits in the input logical address signal, and this disclosure does not impose any special restrictions on this.

[0095] Figure 5 An optional implementation of the test direction selection circuit according to an embodiment of this disclosure is shown. In some embodiments, such as... Figure 5 As shown, the test direction selection circuit 105 includes: a first control switch SW1, a fourth resistor R4, a fifth resistor R5, a fourth P-type transistor MP4, a fifth P-type transistor MP5, a fifth N-type transistor MN5, a sixth N-type transistor MN6, a seventh N-type transistor MN7, and a fifth inverter INV5.

[0096] In this circuit, one end of the first control switch SW1 is connected to the second external pin 1051, and the other end is connected to one end of the fourth resistor R4. The second external pin 1051 can reuse a pin on the chip under test, or it can be set as an independent pin on the chip. The second external pin 1051 is used to provide a second external input signal. The other end of the fourth resistor R4 is connected to the sixth node N6. One end of the fifth resistor R5 is connected to the sixth node N6, and the other end is grounded to GND.

[0097] The control electrode of the fifth N-type transistor MN5 is connected to the sixth node N6, the first electrode is grounded to GND, and the second electrode is connected to the seventh node N7; the control electrode of the sixth N-type transistor MN6 is connected to the second bias current terminal I2, the first electrode is grounded to GND, and the second electrode is connected to the second bias current terminal I2; the control electrode of the seventh N-type transistor MN7 is connected to the second bias current terminal I2, the first electrode is grounded to GND, and the second electrode is connected to the eighth node N8.

[0098] The control electrode and the second electrode of the fourth P-type transistor MP4 are both connected to the eighth node N8, and the first electrode is connected to the second constant voltage power supply terminal VDD2; the control electrode of the fifth P-type transistor MP5 is connected to the eighth node N8, the first electrode is connected to the second constant voltage terminal VDD2, and the second electrode is connected to the seventh node N7.

[0099] The input of the fifth inverter INV5 is connected to the seventh node N7. The fifth inverter INV5 is used to select the output test mode signal D according to the signal output by the seventh node N7.

[0100] In the test direction selection circuit 105, the first control switch SW1 is used to control the connection or disconnection between the second external pin 1051 and the fourth resistor R4. When the first control switch SW1 is closed, the connection between the second external pin 1051 and the fourth resistor R4 is disconnected, the fifth N-type transistor MN5 is turned off, and the seventh N-type transistor MN7 is turned on under the control of the bias current of the second bias current terminal I2. The ground voltage (low level voltage) is written to the eighth node N8 through the turned-on seventh N-type transistor MN7. The fifth P-type transistor MP5 is turned on under the control of the voltage of the eighth node N8. The second constant voltage power supply terminal VDD2 writes the power supply voltage (high level voltage) to the seventh node N7 through the turned-on fifth P-type transistor MP5. The voltage of the seventh node N7 is set to a high level voltage. The voltage of the seventh node N7, through the action of the fifth inverter INV5, obtains the test mode selection signal D. At this time, the test mode selection signal D is a low level signal.

[0101] When the first control switch SW1 is turned on, the second external pin 1051 is connected to the fourth resistor R4. The second external input signal (high-level signal) provided by the second external pin 1051 is written to the sixth node N6 through the fourth resistor R4. The fifth N-type transistor MN5 is turned on under the action of the voltage V5 output by the sixth node N6. The ground voltage (low-level voltage) is written to the seventh node N7 through the turned-on fifth N-type transistor MN5. The voltage of the seventh node N7 is set to a low-level voltage. The voltage of the seventh node N7 is used by the fifth inverter INV5 to obtain the test mode selection signal D. At this time, the test mode selection signal D is a high-level signal.

[0102] When the test mode selection signal D is a low-level signal, the output test circuit 102 is selected for testing. The output test circuit 102 selects different output test signals generated internally by the chip under test, and outputs the selected output test signal through test node 103 to an external test device for signal testing and analysis. When the test mode selection signal D is a high-level signal, the input test circuit 104 is selected for testing. An external device outputs an input test signal to test node 103, which then inputs the input test signal to input test circuit 104. The input test circuit 104 injects the input test signal into the corresponding internal circuit of the chip under test, thereby changing the operating state of the corresponding internal circuit. Internal circuit testing and analysis are then performed on the corresponding internal circuit of the chip under test to verify its performance.

[0103] Figure 6 This illustration shows an optional implementation of the output test circuit and input test circuit according to embodiments of the present disclosure. In some embodiments, the output test signal is an analog signal, such as... Figure 6 As shown, the output test circuit 102 includes an analog signal output test circuit 1021 and an analog output buffer 1022.

[0104] The analog signal output test circuit 1021 uses an analog data selector MUX(A). The input of the analog signal output test circuit 1021 is a plurality of test signals to be output (Asig1, Asig2, Asig3, ..., Asig(m-1), Asig(m)) generated inside the chip under test. The output of the analog signal output test circuit 1021 is connected to the input of the analog output buffer 1022. The output of the analog output buffer 1022 is connected to the test node 103 through the second control switch SW2. The second control switch SW2 is used to control the connection or disconnection between the output of the analog output buffer 1022 and the test node 103. In this embodiment, the plurality of input ports of the analog signal output test circuit 1021 are referred to as output test channels.

[0105] A data selector (Multiplexer, MUX), also known as a multiplexer, modulator, or multiplexer, is a combinational logic circuit that selects a specific input signal from a set of input signals and sends it to the output based on a given input address code.

[0106] In this embodiment of the present disclosure, the analog signal output test circuit 1021 selects the output test signal corresponding to the first test selection signal B1 from a plurality of input output test signals under the action of the given first test selection signal B1, and outputs it to the analog output buffer 1022. The analog output buffer 1022 outputs the selected output test signal to the test node 103 through the second control switch SW2, so as to perform test analysis on the output test signal.

[0107] In some embodiments, the analog output buffer 1022 is implemented using a power amplifier (AMP). The positive terminal of the power amplifier is connected to the output terminal of the analog signal output test circuit 1021, and the negative terminal is connected to the output terminal of the power amplifier. The output terminal of the power amplifier is connected to one end of the second control switch SW2, and the other end of the second control switch SW2 is connected to the test node 103.

[0108] In some embodiments, the test signal to be output is a digital signal, such as... Figure 6 As shown, the output test circuit 102 includes a digital signal output test circuit 1023 and a digital output buffer 1024.

[0109] The digital signal output test circuit 1023 employs a digital data selector MUX(D). The inputs of the digital signal output test circuit 1023 are multiple test signals (Dsig1, Dsig2, Dsig3, ..., Dsig(n-1), Dsig(n)) generated internally by the chip under test. The output of the digital signal output test circuit 1023 is connected to the input of the digital output buffer 1024. The output of the digital output buffer 1024 is connected to the test node 103 via a third control switch SW3. The third control switch SW3 controls the connection or disconnection between the output of the digital output buffer 1024 and the test node 103. In this embodiment, the multiple input ports of the digital signal output test circuit 1023 are referred to as output test channels.

[0110] In this embodiment of the present disclosure, the digital signal output test circuit 1023 selects the output test signal corresponding to the first test selection signal B1 from a plurality of input output test signals under the action of the given first test selection signal B1, and outputs it to the digital output buffer 1024. The digital output buffer 1024 outputs the selected output test signal to the test node 103 through the third control switch SW3, so as to perform test analysis on the output test signal.

[0111] In some embodiments, the digital output buffer 1024 is implemented using two inverters connected in series. The input of one inverter is connected to the output of the digital signal output test circuit 1023, the output of the one inverter is connected to the input of the other inverter, the output of the other inverter is connected to one end of the third control switch SW3, and the other end of the third control switch SW3 is connected to the test node 103.

[0112] In some embodiments, the input test signal is an analog signal, such as... Figure 6 As shown, the input test circuit 104 includes an analog signal input test circuit 1041.

[0113] The analog signal input test circuit 1041 uses an analog demultiplexer DEMUX(A). The input of the analog signal input test circuit 1041 is connected to the test node 103 through the fourth control switch SW4. The output of the analog signal input test circuit 1041 is multiple input test channels (Ain1, Ain2, Ain3, ..., Ain(j-1), Ain(j)). The fourth control switch SW4 is used to control the connection or disconnection between the input of the analog signal input test circuit 1041 and the test node 103. In this embodiment, the multiple output ports of the analog signal input test circuit 1041 are referred to as input test channels.

[0114] The counterpart to the data selector MUX is the demultiplexer (DEMUX), also known as a multiplexer. It is a combinational logic circuit that selects a specified output port from a set of output ports based on a given input address code and sends the input signal out through the selected output port.

[0115] In this embodiment of the disclosure, the analog signal input test circuit 1041 selects the input test channel corresponding to the second test selection signal B2 from multiple input test channels under the action of the given second test selection signal B2, and inputs the input test signal to be input to the corresponding circuit inside the chip under test through the selected input test channel for internal circuit test analysis.

[0116] In some embodiments, the input test signal is a digital signal, such as... Figure 6 As shown, the input test circuit 104 includes a digital signal input test circuit 1042.

[0117] The digital signal input test circuit 1042 uses a digital demultiplexer DEMUX(D). The input of the digital signal input test circuit 1042 is connected to the test node 103 through the fifth control switch SW5. The output of the digital signal input test circuit 1042 is multiple input test channels (Din1, Din2, Din3, ..., Din(k-1), Din(k)). The fifth control switch SW5 is used to control the connection or disconnection between the input of the digital signal input test circuit 1042 and the test node 103. In this embodiment, the multiple output ports of the digital signal input test circuit 1042 are referred to as input test channels.

[0118] In this embodiment of the disclosure, the digital signal input test circuit 1042, under the action of the given second test selection signal B2, selects the input test channel corresponding to the second test selection signal B2 from multiple input test channels, and inputs the input test signal to be input to the corresponding circuit inside the chip under test through the selected input test channel for internal circuit test analysis.

[0119] Figure 7 This illustration shows an optional implementation of the chip test and analysis circuit according to an embodiment of the present disclosure. In some embodiments, such as... Figure 7 As shown, the chip test and analysis circuit also includes a test start circuit 106, which is used to output a test enable signal to control the chip under test to enter the test mode, and can also be used to provide the required bias current to other parts of the chip test and analysis circuit.

[0120] In test mode, the internal circuitry of the chip under test operates, and the chip test and analysis circuit starts operating simultaneously, with each part of the circuit beginning to perform the test.

[0121] Figure 8 An optional implementation of the test startup circuit according to an embodiment of this disclosure is shown. In some embodiments, such as... Figure 8 As shown, the test start-up circuit 106 includes: a sixth resistor R6, a seventh resistor R7, an eighth resistor R8, a ninth resistor R9, a sixth P-type transistor MP6, a seventh P-type transistor MP7, an eighth N-type transistor MN8, a ninth N-type transistor MN9, a tenth N-type transistor MN10, and a sixth inverter INV6.

[0122] Among them, one end of the sixth resistor R6 is connected to the third external pin 1061, and the other end is connected to the ninth node N9; the third external pin 1061 can reuse a pin on the chip under test, or a separate pin can be set on the chip as the third external pin 1061. The third external pin 1061 is used to provide the third external input signal; one end of the seventh resistor R7 is connected to the ninth node N9, and the other end is grounded to GND; one end of the eighth resistor R8 is connected to the third external pin 1061, and the other end is connected to the second terminal of the eighth N-type transistor MN8; one end of the ninth resistor R9 is connected to the third constant voltage power supply terminal VDD3, and the other end is connected to the tenth node N10.

[0123] The control electrode of the eighth N-type transistor MN8 is connected to the second electrode, and the first electrode is grounded to GND; the control electrode of the ninth N-type transistor MN9 is connected to the control electrode of the eighth N-type transistor MN8, the first electrode is grounded to GND, and the second electrode is connected to the eleventh node N11; the control electrode of the tenth N-type transistor MN10 is connected to the ninth node N9, the first electrode is grounded to GND, and the second electrode is connected to the tenth node N10.

[0124] The control electrode and the second electrode of the sixth P-type transistor MP6 are connected to the eleventh node N11, and the first electrode is connected to the third constant voltage power supply terminal VDD3; the control electrode of the seventh P-type transistor MP7 is connected to the eleventh node N11, the first electrode is connected to the third constant voltage power supply terminal VDD3, and the second electrode is used to output the bias current In.

[0125] The input of the sixth inverter INV6 is connected to the tenth node N10, and its output is used to output the test enable signal En.

[0126] In the initial state, the third external pin 1061 is pulled down to a low level by default, the tenth N-type transistor MN10 is cut off, and the third constant voltage power supply terminal VDD3 writes the power supply voltage (high level voltage) to the tenth node N10 through the ninth resistor R9. At this time, the voltage of the tenth node N10 is processed by the sixth inverter INV6 to output a test shutdown signal. The test shutdown signal is a low level signal. At this time, the chip under test and the chip test analysis circuit do not enter the test mode.

[0127] When the third external pin 1061 provides a third external input signal, which is a high-level signal, the signal is written to the ninth node N9 through the sixth resistor R6. The voltage V6 at the ninth node N9 is then high. The tenth N-type transistor MN10 is turned on by the voltage V6 at the ninth node N9. The ground voltage (low-level voltage) is written to the tenth node N10 through the turned-on transistor MN10, setting the voltage at the tenth node N10 to low. At this time, the voltage at the tenth node N10 is then transmitted through the sixth inverter I. The function of NV6 is to output a test enable signal. The test enable signal is a high-level signal, at which time the chip under test and the chip test analysis circuit enter the test mode. At the same time, the third external input signal is written to the control terminal and the second terminal of the eighth N-type transistor MN8 and the control terminal of the ninth N-type transistor MN9 through the eighth resistor R8. The eighth N-type transistor MN8 and the ninth N-type transistor MN9 are turned on, the voltage of the eleventh node N11 is set to a low level, the sixth P-type transistor and the seventh P-type transistor are turned on, and the second terminal of the seventh P-type transistor outputs a bias current.

[0128] This disclosure also provides a chip testing and analysis method, which is applied to the chip testing and analysis circuit provided in this disclosure. The chip testing and analysis method implemented based on the chip testing and analysis circuit provided in the above embodiments is all the content that needs to be protected in this disclosure.

[0129] This disclosure also provides a chip that integrates a chip test and analysis circuit, which includes the chip test and analysis circuit provided in the above embodiments.

[0130] For a detailed description of the chip test and analysis circuit, please refer to the relevant description of the chip test and analysis circuit in the above embodiments, which will not be repeated here.

[0131] Those skilled in the art will understand that all or some of the steps, systems, and devices disclosed above, as functional modules / units, can be implemented as software, firmware, hardware, or suitable combinations thereof.

[0132] In hardware implementations, the division between functional modules / units mentioned in the above description does not necessarily correspond to the division of physical components; for example, a physical component may have multiple functions, or a function or step may be executed by several physical components working together.

[0133] This disclosure has disclosed exemplary embodiments, and although specific terminology has been used, it is for general illustrative purposes only and should not be construed as limiting. In some instances, it will be apparent to those skilled in the art that features, characteristics, and / or elements described in conjunction with particular embodiments may be used alone, or in combination with features, characteristics, and / or elements described in conjunction with other embodiments, unless otherwise expressly indicated. Therefore, those skilled in the art will understand that various changes in form and detail may be made without departing from the scope of this disclosure as set forth by the appended claims.

Claims

1. A chip test analysis circuit, characterized by, The chip test analysis circuit comprises: an address decoding circuit, configured to generate first test selection signals, each of which is used to select an output test channel of the chip to be tested, and each of the output test channels is used to output a to-be-output test signal generated inside the chip to be tested; the address decoding circuit is further configured to generate second test selection signals, each of which is used to select an input test channel of the chip to be tested, and each of the input test channels is used to input a to-be-input test signal into a corresponding circuit inside the chip to be tested; an output test circuit, an input of the output test circuit being a plurality of to-be-output test signals generated inside the chip to be tested, the output test circuit being configured to select a to-be-output test signal corresponding to the first test selection signal from the plurality of to-be-output test signals according to the first test selection signal provided by the address decoding circuit, and output the selected to-be-output test signal to a test node for output signal test analysis; an input test circuit, an input of the input test circuit being a to-be-input test signal provided by the chip to be tested, the input test circuit being configured to select an input test channel corresponding to the second test selection signal from a plurality of input test channels according to the second test selection signal provided by the address decoding circuit, so as to input the to-be-input test signal into a corresponding circuit inside the chip to be tested through the selected input test channel for internal circuit test analysis; a test direction selection circuit, configured to generate a test mode selection signal, the test mode selection signal being used to control the output test circuit and the test node to be connected or disconnected, and control the input test circuit and the test node to be disconnected or connected.

2. The chip test analysis circuit according to claim 1, characterized by The address decoding circuit comprises at least two first decoding circuits and a second decoding circuit, an input of the second decoding circuit being connected to outputs of the first decoding circuits; the first decoding circuits are configured to generate a plurality of decoding signals according to first external input signals, and the second decoding circuit is configured to generate the first test selection signals or the second test selection signals according to the decoding signals output by the at least two first decoding circuits.

3. The chip test analysis circuit of claim 2, wherein, The first decoding circuit comprises a first resistor, a second resistor, a third resistor, a first P-type transistor, a second P-type transistor, a third P-type transistor, a first N-type transistor, a second N-type transistor, a third N-type transistor, a fourth N-type transistor, a first inverter, a second inverter, a third inverter, a fourth inverter, a first logic AND gate, a second logic AND gate, and a third logic AND gate; one end of the first resistor is connected to a first external pin, the other end of the first resistor is connected to a first node, the first external pin is multiplexed with a pin on the chip to be tested, and the first external pin is used to provide a first external input signal; one end of the second resistor is connected to the first node, and the other end of the second resistor is connected to a second node; one end of the third resistor is connected to the second node, and the other end of the third resistor is grounded. The control electrode of the first N-type transistor is connected to the first node, the first electrode is grounded, and the second electrode is connected to the third node; the control electrode of the second N-type transistor is connected to the second node, the first electrode is grounded, and the second electrode is connected to the fourth node; the control electrode of the third N-type transistor is connected to the first bias current terminal, the first electrode is grounded, and the second electrode is connected to the first bias current terminal; the control electrode of the fourth N-type transistor is connected to the first bias current terminal, the first electrode is grounded, and the second electrode is connected to the fifth node; The control electrode of the first P-type transistor is connected to the fifth node, the first electrode is connected to the first constant-voltage power terminal, and the second electrode is connected to the fifth node; the control electrode of the second P-type transistor is connected to the fifth node, the first electrode is connected to the first constant-voltage power terminal, and the second electrode is connected to the third node; the control electrode of the third P-type transistor is connected to the fifth node, the first electrode is connected to the first constant-voltage power terminal, and the second electrode is connected to the fourth node; The input end of the first inverter is connected to the third node, and the output end is connected to the input end of the second inverter; the input end of the third inverter is connected to the fourth node, and the output end is connected to the input end of the fourth inverter; The output end of the fourth inverter is connected to the first input end of the first logic AND gate, and the output end of the second inverter is connected to the second input end of the first logic AND gate; the output end of the fourth inverter is also connected to the first input end of the second logic AND gate, and the output end of the first inverter is also connected to the second input end of the second logic AND gate; the output end of the third inverter is also connected to the first input end of the third logic AND gate, and the output end of the first inverter is also connected to the second input end of the third logic AND gate; The output end of the first logic AND gate is used to generate a decoding signal according to the signals output from the output end of the fourth inverter and the output end of the second inverter; the output end of the second logic AND gate is used to generate a decoding signal according to the signals output from the output end of the fourth inverter and the output end of the first inverter; and the output end of the third logic AND gate is used to generate a decoding signal according to the signals output from the output end of the third inverter and the output end of the first inverter.

4. The chip test analysis circuit of claim 2, wherein, The second decoding circuit includes a three-eight decoding circuit, a two-four decoding circuit, or a four-sixteen decoding circuit.

5. The chip test analysis circuit of claim 1, wherein, The address decoding circuit includes a third decoding circuit, which is used to generate the first test selection signal or the second test selection signal according to a logic input address signal provided by a digital logic circuit inside a chip to be tested.

6. The chip test analysis circuit according to claim 5, characterized by The third decoding circuit is implemented by using a binary decoder.

7. The chip test analysis circuit of claim 1, wherein The test direction selection circuit includes a first control switch, a fourth resistor, a fifth resistor, a fourth P-type transistor, a fifth P-type transistor, a fifth N-type transistor, a sixth N-type transistor, a seventh N-type transistor, and a fifth inverter. One end of the first control switch is connected to a second external pin, and the other end is connected to one end of the fourth resistor, the second external pin is multiplexed with a pin on the chip to be tested, and the second external pin is used to provide a second external input signal; the other end of the fourth resistor is connected to a sixth node; one end of the fifth resistor is connected to the sixth node, and the other end is grounded; The control electrode of the fifth N-type transistor is connected to the sixth node, the first electrode is grounded, and the second electrode is connected to a seventh node; the control electrode of the sixth N-type transistor is connected to a second bias current terminal, the first electrode is grounded, and the second electrode is connected to the second bias current terminal; the control electrode of the seventh N-type transistor is connected to the second bias current terminal, the first electrode is grounded, and the second electrode is connected to an eighth node; The control electrode and the second electrode of the fourth P-type transistor are both connected to the eighth node, and the first electrode is connected to a second constant voltage terminal; the control electrode of the fifth P-type transistor is connected to the eighth node, the first electrode is connected to the second constant voltage terminal, and the second electrode is connected to the seventh node; The input end of the fifth inverter is connected to the seventh node, and the fifth inverter is used to output the test mode selection signal according to the signal output by the seventh node.

8. The chip test analysis circuit of claim 1, wherein, The test signal to be output is an analog signal, and the output test circuit comprises an analog signal output test circuit and an analog output buffer; The analog signal output test circuit adopts an analog data selector, the input of the analog signal output test circuit is a plurality of test signals to be output generated inside the chip to be tested, the output of the analog signal output test circuit is connected to the input of the analog output buffer, and the output of the analog output buffer is connected to the test node through a second control switch.

9. The chip test analysis circuit of claim 1, wherein, The test signal to be output is a digital signal, and the output test circuit comprises a digital signal output test circuit and a digital output buffer; The digital signal output test circuit adopts a digital data selector, the input of the digital signal output test circuit is a plurality of test signals to be output generated inside the chip to be tested, the output of the digital signal output test circuit is connected to the input of the digital output buffer, and the output of the digital output buffer is connected to the test node through a third control switch.

10. The chip test analysis circuit of claim 1, wherein, The test signal to be input is an analog signal, and the input test circuit comprises an analog signal input test circuit; The analog signal input test circuit adopts an analog demultiplexer, the input of the analog signal input test circuit is connected to the test node through a fourth control switch, and the output of the analog signal input test circuit is a plurality of input test channels.

11. The chip test analysis circuit of claim 1, wherein, The test signal to be input is a digital signal, and the input test circuit comprises a digital signal input test circuit; The digital signal input test circuit adopts a digital demultiplexer, the input of the digital signal input test circuit is connected to the test node through a fifth control switch, and the output of the digital signal input test circuit is a plurality of input test channels.

12. The chip test analysis circuit of claim 1, wherein, The chip test analysis circuit further comprises: A test start circuit is configured to output a test enable signal to control the chip to be tested to enter a test mode.

13. The chip test analysis circuit of claim 12, wherein, The test starting circuit comprises a sixth resistor, a seventh resistor, an eighth resistor, a ninth resistor, a sixth P-type transistor, a seventh P-type transistor, an eighth N-type transistor, a ninth N-type transistor, a tenth N-type transistor and a sixth inverter; One end of the sixth resistor is connected to a third external pin, and the other end is connected to a ninth node; the third external pin is multiplexed with a pin on the chip to be tested, and the third external pin is used to provide a third external input signal; one end of the seventh resistor is connected to the ninth node, and the other end is grounded; one end of the eighth resistor is connected to the third external pin, and the other end is connected to the second electrode of the eighth N-type transistor; one end of the ninth resistor is connected to a third constant-voltage power supply end, and the other end is connected to a tenth node; The control electrode and the second electrode of the eighth N-type transistor are connected, and the first electrode is grounded; the control electrode of the ninth N-type transistor is connected to the control electrode of the eighth N-type transistor, the first electrode is grounded, and the second electrode is connected to an eleventh node; the control electrode of the tenth N-type transistor is connected to the ninth node, the first electrode is grounded, and the second electrode is connected to the tenth node; The control electrode and the second electrode of the sixth P-type transistor are connected to the eleventh node, and the first electrode is connected to the third constant-voltage power supply end; the control electrode of the seventh P-type transistor is connected to the eleventh node, the first electrode is connected to the third constant-voltage power supply end, and the second electrode is used to output a bias current; The input end of the sixth inverter is connected to the tenth node, and the output end is used to output the test enable signal.

14. A chip, characterized by The chip is integrated with a chip test analysis circuit, and the chip test analysis circuit comprises the chip test analysis circuit in any one of claims 1-13.

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