On-chip adaptive voltage and frequency scaling for high performance processors

Abstract

The application discloses a kind of on-chip adaptive voltage and frequency regulation device for high-performance processor power supply, including digital low dropout regulator DLDO with time domain voltage comparator, time domain voltage comparator includes three comparison registers and four delay units respectively working in Vcomp, Vhigh, Vref and Vlow four voltage domains, three comparison registers respectively with the voltage level Dout of the output signal of corresponding delay unit in voltage domain Vcomp as clock signal to sample the rest with the voltage level of the output signal of corresponding delay unit in voltage domain Vhigh, Vref and Vlow to obtain three-way voltage comparison result.The application aims to solve the problems of stability, resolution, response speed and power consumption of the voltage comparator built by traditional on-chip analog circuit, realize the synthesis of voltage comparator, with the advantages of strong robustness, high resolution, fast response speed and low power consumption.

Description

Technical Field

[0001] This invention relates to the field of power management technology for processors, and more specifically to an on-chip adaptive voltage and frequency regulation device for powering high-performance processors. Background Technology

[0002] With the increasing complexity of high-performance processors such as GPUs and DSPs, the on-chip power management and voltage drop issues caused by drastic workload fluctuations are becoming increasingly severe. At advanced process nodes, voltage drops can reach 200 millivolts when the workload changes rapidly within 10 nanoseconds. To maintain processor functionality, additional voltage margins must be added, leading to a significant increase in power consumption. To improve energy efficiency, researchers are working to reduce the magnitude of voltage drops. The core challenge lies in response latency—excessive latency degrades performance and causes chip timing issues. On-chip voltage monitors and timing detectors are crucial components of power management systems. Voltage comparators are core circuits widely used in integrated circuits for analog-to-digital conversion, power management, and signal detection. Their function is to compare the magnitudes of two input voltages and output a high or low level digital signal, acting as a key interface between the analog and digital voltage domains. Their main performance parameters include speed, accuracy, and power consumption. Existing voltage comparators typically use a sense amplifier as the preamplifier circuit. However, this structure has significant limitations in practical applications: First, it is extremely sensitive to process variations, power supply voltage fluctuations, and operating temperature changes (PVT variations), resulting in poor cross-condition stability and difficulty in ensuring performance consistency. Second, when the two input voltage values ​​to be compared are very close, the circuit is in a small differential input state, which results in insufficient gain and slow response, significantly increasing the propagation delay and reducing the overall comparison speed. More importantly, this problem of increased delay and insufficient sensitivity is further amplified in low-voltage or precision application scenarios, thus severely limiting the improvement of the voltage comparator's resolution and accuracy, becoming a major technical bottleneck in achieving high-precision, high-reliability comparator designs. Summary of the Invention

[0003] The technical problem to be solved by this invention is to provide an on-chip adaptive voltage and frequency regulation device for powering high-performance processors, addressing the aforementioned problems of the prior art. This invention aims to solve the problems of stability, resolution, response speed, and power consumption of voltage comparators built from analog circuits in traditional on-chip adaptive voltage and frequency regulation circuits, and to achieve synthesizable voltage comparators with the advantages of strong robustness, high resolution, fast response speed, and low power consumption.

[0004] To solve the above-mentioned technical problems, the technical solution adopted by the present invention is as follows:

[0005] An on-chip adaptive voltage and frequency regulation device for powering high-performance processors includes a digital low-dropout regulator (DLDO) with a voltage comparator. The voltage comparator is a time-domain voltage comparator, comprising three comparison registers and four delay units operating in four voltage domains: Vcomp, Vhigh, Vref, and Vlow. Vcomp is the output voltage of the DLDO, Vref is the regulated reference voltage, and Vhigh and Vlow are voltages higher and lower than the reference voltage by a specified amount, respectively. The three comparison registers use the voltage level Dout of the output signal of the delay unit corresponding to voltage domain Vcomp as a clock signal to sample the voltage levels Dhigh, Dref, and Dlow of the output signals of the delay units corresponding to voltage domains Vhigh, Vref, and Vlow to obtain three voltage comparison results Qhigh, Qref, and Qlow.

[0006] Optionally, when the three comparison registers use the voltage level Dout of the output signal of the delay unit corresponding to the voltage domain Vcomp as a clock signal to sample the voltage levels Dhigh, Dref, and Dlow of the output signals of the delay units corresponding to the voltage domains Vhigh, Vref, and Vlow to obtain the three-way voltage comparison results Qhigh, Qref, and Qlow, if the voltage value of the output signal of the voltage domain Vcomp is between the voltage values ​​of the output signals of the voltage domains Vhigh and Vlow, then the voltage comparison result Qhigh is fixed at 1 and the voltage comparison result Qlow is fixed at 0, and the value of the voltage comparison result Qref is determined by the voltage value of the output signal of the voltage domain Vcomp and the voltage value of the output signal of the voltage domain Vref; if the voltage value of the output signal of the voltage domain Vcomp is greater than the voltage value of the output signal of the voltage domain Vhigh, then the voltage comparison result Qhigh is output as 0; if the voltage value of the output signal of the voltage domain Vcomp is less than the voltage value of the output signal of the voltage domain Vlow, then the voltage comparison result Qlow is output as 1.

[0007] Optionally, each of the four delay units is connected to a flip-flop, and the clock signal terminal and reset signal terminal of the flip-flop are both connected to the sampling clock CKs input to the clock signal input terminal.

[0008] Optionally, the voltage value of the voltage domain Vhigh output signal is 20 mV higher than the voltage value of the voltage domain Vref output signal, and the voltage value of the voltage domain Vlow output signal is 20 mV lower than the voltage value of the voltage domain Vref output signal.

[0009] Optionally, the digital low dropout regulator (DLDO) includes an adaptive sampling clock circuit, a coarse adjustment bidirectional shift register, a fine adjustment bidirectional shift register, a coarse adjustment power supply gate, a fine adjustment power supply gate, and the time-domain voltage comparator. The adaptive sampling clock circuit generates a sampling clock CKs, a coarse adjustment clock CKs_c, and a fine adjustment clock CKs_f. The sampling clock CKs is connected to the clock signal input of the time-domain voltage comparator. The coarse adjustment bidirectional shift register generates a control signal for the coarse adjustment power supply gate based on the coarse adjustment clock CKs_c to control the state of each switching unit in the coarse adjustment power supply gate. The fine adjustment bidirectional shift register generates a control signal for the fine adjustment power supply gate based on the fine adjustment clock CKs_f to control the state of each switching unit in the fine adjustment power supply gate. The coarse adjustment power supply gate and the switching units in the fine adjustment power supply gate are connected in parallel to form the output voltage Vcomp of the digital low dropout regulator (DLDO).

[0010] Optionally, the adaptive sampling clock circuit includes an input section, an intermediate section, and an output section. The intermediate section includes a pair of PMOS transistors, a ring oscillator, and a pair of NMOS transistors arranged in series between the power supply VDD and ground GND. The input section includes a NAND gate and an inverter. The voltage comparison results Qhigh and Qlow are used as the inputs of the NAND gate. The output signal boost of the NAND gate is connected to the gate of one PMOS transistor after passing through the inverter. The gate of the other PMOS transistor is connected to the reference ground VSS. The output signal boost of the NAND gate is connected to the gate of an NMOS transistor. Another NMOS transistor has its gate connected to power supply VDD. The ring oscillator is a ring structure formed by multiple inverters connected in series. The output signal from the ring structure is connected to the output section. The output section includes a latch LS, an AND gate, and a NAND gate. The output signal from the ring structure generates a sampling clock CKs after passing through the latch LS. The sampling clock CKs and the output signal boost of the NAND gate generate a coarse adjustment clock CKs_c through the AND gate. The sampling clock CKs and the output signal boost of the NAND gate generate a fine adjustment clock CKs_f through the NAND gate.

[0011] Optionally, both the coarse-adjustment bidirectional shift register and the fine-adjustment bidirectional shift register are composed of multiple sets of multiplexers and cascaded registers, and the coarse-adjustment bidirectional shift register uses the voltage comparison result Qlow as the enable signal, while the fine-adjustment bidirectional shift register uses the voltage comparison result Qref as the enable signal.

[0012] Optionally, the on-chip adaptive voltage and frequency regulation device includes multiple digital low dropout regulators (DLDOs), and the multiple DLDOs share the same input voltage and output voltage.

[0013] Optionally, the on-chip adaptive voltage and frequency regulation device further includes a self-calibrating adjustable ring oscillator SC-TRO, which is connected to the voltage output terminal of a digital low dropout regulator DLDO to generate the clock signal CLK required by the processor based on the output voltage Vout of the voltage output terminal.

[0014] Optionally, the self-calibrating adjustable ring oscillator SC-TRO includes an encoder and an adjustable ring oscillator. The processor includes an in-situ critical path timing detector, which includes a pulse generator circuit and a simplified time-to-digital converter (TDC). The pulse generator circuit is inserted at the midpoint of a specified critical path and is connected to the input of the encoder via the TDC. The pulse generator circuit generates a short pulse signal labeled "half_cp_pulse" as the clock signal for the TDC each time a detection node flips. The time interval between the short pulse signal and the rising edge of the processor's clock reflects the half-critical path delay at the midpoint of the critical path. The TDC generates a delay value encoding based on the clock signal and inputs it to the encoder. The encoder encodes the delay value into a one-hot encoding to control the adjustable ring oscillator to generate the clock signal CLK required by the processor.

[0015] Compared with existing technologies, this invention mainly achieves the following beneficial effects: The invention uses digital standard logic units to build a synthesizable voltage comparator circuit. By converting the voltage magnitude into the delay of a delay unit and comparing the delay differences under different voltage domains, the voltage comparison result is obtained. This circuit has the following advantages: 1) Synthesizable: The circuit is composed of standard logic units, compatible with fully digital EDA tool flows, reducing design costs. 2) Robust: The circuit contains no analog components, making it far less sensitive to PVT changes than analog circuits. 3) High resolution: The circuit can compare subtle differences in delay, with a resolution up to 1mV. 4) Fast response: The circuit uses a high-frequency sampling clock, outputting the result once per clock rising edge, regardless of the magnitude and proximity of the voltage value. 5) Low power consumption: The circuit has no current feedthrough path, resulting in lower power consumption than analog voltage comparators. Attached Figure Description

[0016] Figure 1 This is a schematic diagram of the circuit principle of the time-domain voltage comparator in an embodiment of the present invention.

[0017] Figure 2This is the output waveform diagram of the time-domain voltage comparator in the embodiment of the present invention. Among them, (a) is the output waveform when Qhigh = 1 and Qlow = 0; (b) is the output waveform when Vcomp > Vhigh, Qhigh = 0, Qlow = 0, and Qref = 0; (c) is the output waveform when Vcomp < Vlow, Qlow = 1, Qhigh = 1, and Qref = 1.

[0018] Figure 3 This is the schematic circuit diagram of the on-chip adaptive voltage and frequency regulation device in the embodiment of the present invention.

[0019] Figure 4 This is the schematic circuit diagram and the output waveform diagram of the adaptive sampling clock circuit in the embodiment of the present invention. Among them, (a) is the schematic circuit diagram, and (b) is the output waveform diagram.

[0020] Figure 5 This is the schematic circuit diagram of the coarse-tuning bidirectional shift register and the fine-tuning bidirectional shift register in the embodiment of the present invention.

[0021] Figure 6 This is the schematic circuit diagram of the self-calibrating adjustable ring oscillator SC-TRO in the embodiment of the present invention.

[0022] Figure 7 This is the voltage resolution and power consumption test results of the time-domain voltage comparator in the embodiment of the present invention.

[0023] Figure 8 This is the simulation results of the load transient response, the adaptive sampling clock circuit, and the self-calibrating adjustable ring oscillator SC-TRO in the embodiment of the present invention. Among them, (a) is the simulation result of the load transient response, (b) is the simulation result of the adaptive sampling clock circuit, and (c) is the simulation result of the self-calibrating adjustable ring oscillator SC-TRO. Specific implementation manners

[0024] In order to enable those skilled in the art to better understand the technical solutions of the present invention, the technical solutions of the present invention will be further described in detail below in conjunction with the accompanying drawings in the embodiments of the present invention.

[0025] The on-chip adaptive voltage and frequency regulation device for high-performance processor power supply in this embodiment includes a digital low-dropout regulator DLDO with a voltage comparator. The voltage comparator is a time-domain voltage comparator, such as Figure 1As shown, the time-domain voltage comparator in this embodiment includes three comparison registers and four delay units respectively operating in four voltage domains of Vcomp, Vhigh, Vref, and Vlow. Among them, Vcomp is the output voltage of the digital low-dropout regulator (DLDO), Vref is the regulated reference voltage, Vhigh and Vlow are voltages that are higher and lower than the reference voltage by a specified voltage magnitude respectively. The three comparison registers respectively use the voltage level Dout of the output signal of the delay unit corresponding to the voltage domain Vcomp as the clock signal to sample the voltage levels Dhigh, Dref, and Dlow of the output signals of the delay units corresponding to the voltage domains Vhigh, Vref, and Vlow, so as to obtain three voltage comparison results Qhigh, Qref, and Qlow. The time-domain voltage comparator in this embodiment generates a voltage resolution result through the delay difference between the four delay units, provided that the delay difference meets the setup / hold time requirements for comparison triggering. To improve the resolution of the voltage comparator, the total delay of each voltage domain needs to be as long as possible, but must be shorter than the sampling clock period.

[0026] In this embodiment, when the three comparison registers respectively use the voltage level Dout of the output signal of the delay unit corresponding to the voltage domain Vcomp as the clock signal to sample the voltage levels Dhigh, Dref, and Dlow of the output signals of the delay units corresponding to the voltage domains Vhigh, Vref, and Vlow to obtain three voltage comparison results Qhigh, Qref, and Qlow, if the voltage value of the output signal of the voltage domain Vcomp is between the voltage values of the output signals of the voltage domains Vhigh and Vlow, then the voltage comparison result Qhigh is fixed to 1, the voltage comparison result Qlow is fixed to 0, and the value of the voltage comparison result Qref is determined to be 1 or 0 by the voltage value of the output signal of the voltage domain Vcomp and the voltage value of the output signal of the voltage domain Vref; if the voltage value of the output signal of the voltage domain Vcomp is greater than the voltage value of the output signal of the voltage domain Vhigh, then the voltage comparison result Qhigh outputs 0; if the voltage value of the output signal of the voltage domain Vcomp is less than the voltage value of the output signal of the voltage domain Vlow, then the voltage comparison result Qlow outputs 1. Figure 2 The waveform diagrams of the time-domain voltage comparator in this embodiment under different conditions are shown. Among them, (a) is the output waveform when Qhigh = 1 and Qlow = 0. At this time, if Vcomp > Vref, then Qref = 0, otherwise Qref = 1; (b) is the output waveform when Vcomp > Vhigh, Qhigh = 0, Qlow = 0, and Qref = 0; (c) is the output waveform when Vcomp < Vlow, Qlow = 1, Qhigh = 1, and Qref = 1.

[0027] The time-domain voltage comparator in this embodiment is started at the rising edge of the sampling clock CKs, propagates the logic "1" to the delay unit, and is reset to logic 0 at the falling edge of the sampling clock CKs (the reset pin is also connected to CKs). The comparison flip-flop samples the voltage levels of the delayed output signals with the Dout clock: Dhigh, Dref, and Dlow. When the voltage value of the output voltage Vout is between Vhigh and Vlow, Qhigh and Qlow are fixed to 1 and 0 respectively, and Qref outputs the corresponding result according to the magnitude relationship between Vout and Vref. When Vout > Vhigh, Qhigh outputs 0. When Vout < Vhigh, Qlow outputs 1.

[0028] As Figure 1 shown, in this embodiment, a flip-flop is connected to the input end of each of the four delay units, and the clock signal terminal (denoted as Clk in the figure) and the reset signal terminal (denoted as Reset in the figure) of the flip-flop are both connected to the sampling clock CKs input at the clock signal input end.

[0029] Voltages Vhigh and Vlow that are higher and lower than the reference voltage by a specified voltage magnitude can be provided by a reference voltage supply circuit according to the required reference voltage selected in actuality. For example, as an optional implementation manner, in this embodiment, the voltage value of the output signal of the voltage domain Vhigh is 20 mV higher than the voltage value of the output signal of the voltage domain Vref, and the voltage value of the output signal of the voltage domain Vlow is 20 mV lower than the voltage value of the output signal of the voltage domain Vref.

[0030] As Figure 3 shown, in the on-chip adaptive voltage and frequency regulation device for powering a high-performance processor in this embodiment, the digital low-dropout regulator DLDO includes an adaptive sampling clock circuit, a coarse-tuning bidirectional shift register, a fine-tuning bidirectional shift register, a coarse-tuning power gate, a fine-tuning power gate, and the time-domain voltage comparator. The adaptive sampling clock circuit is used to generate the sampling clock CKs, the coarse-tuning clock CKs_c, and the fine-tuning clock CKs_f. The sampling clock CKs is connected to the clock signal input end of the time-domain voltage comparator. The coarse-tuning bidirectional shift register is used to generate a control signal for the coarse-tuning power gate based on the coarse-tuning clock CKs_c to control the states of the switch units in the coarse-tuning power gate. The fine-tuning bidirectional shift register is used to generate a control signal for the fine-tuning power gate based on the fine-tuning clock CKs_f to control the states of the switch units in the fine-tuning power gate. The switch units in the coarse-tuning power gate and the fine-tuning power gate are connected in parallel to form the output voltage Vcomp of the digital low-dropout regulator DLDO.

[0031] In this embodiment, the adaptive sampling clock circuit is a current-starved clock generation circuit. Its core design principle lies in controlling the supply current of the ring oscillator, using a pair of constantly conducting PMOS / NMOS transistors to enable the circuit to generate a basic output at a lower sampling frequency. For example... Figure 4 As shown in (a), the adaptive sampling clock circuit in this embodiment includes an input section, an intermediate section, and an output section. The intermediate section includes a pair of PMOS transistors, a ring oscillator, and a pair of NMOS transistors arranged in series between the power supply VDD and ground GND. The input section includes a NAND gate and an inverter. The voltage comparison results Qhigh and Qlow are used as the inputs of the NAND gate. The output signal boost of the NAND gate is connected to the gate of one PMOS transistor after passing through the inverter. The gate of the other PMOS transistor is connected to the reference ground VSS. The output signal boost of the NAND gate is connected to the gate of an NMOS transistor. The gates of two NMOS transistors are connected, and the gate of another NMOS transistor is connected to the power supply VDD. The ring oscillator is a ring structure formed by six inverters connected end to end, and the output signal from the ring structure is connected to the output section. The output section includes a latch LS, an AND gate, and a NAND gate. The output signal from the ring structure generates a sampling clock CKs after passing through the latch LS. The sampling clock CKs and the output signal boost of the NAND gate generate a coarse clock CKs_c through the AND gate, and the sampling clock CKs and the output signal boost of the NAND gate generate a fine clock CKs_f through the NAND gate. When the output voltage of the digital low dropout regulator (DLDO) exceeds the Vlow–Vhigh range, the 'boost' signal will flip to 1, allowing more current to flow into the oscillator to generate a higher sampling clock. The adaptive sampling clock circuit also splits the CK signal into a high-frequency coarse clock CKs_c and a low-frequency fine clock CKs_f. When the voltage is stable, the low-frequency fine-tuning clock CKs_f can be used for fine adjustment; while when the voltage fluctuates significantly, the high-frequency coarse-tuning clock CKs_c can achieve rapid coarse adjustment. In this embodiment, the waveforms of the sampling clock CKs, the NAND gate output signal boost, the coarse-tuning clock CKs_c, and the fine-tuning clock CKs_f are respectively as follows: Figure 4 As shown in (b) of the diagram.

[0032] In this embodiment, coarse-adjustment bidirectional shift registers and fine-adjustment bidirectional shift registers, along with two sets of power gates, are used to implement coarse and fine voltage adjustments, corresponding to the coarse and fine sampling clocks, respectively. For example... Figure 5As shown, in this embodiment, both the coarse-adjustment bidirectional shift register and the fine-adjustment bidirectional shift register are composed of multiple cascaded multiplexers and registers. The coarse-adjustment bidirectional shift register uses the voltage comparison result Qlow as the enable signal, while the fine-adjustment bidirectional shift register uses the voltage comparison result Qref as the enable signal. During coarse voltage adjustment, the coarse-adjustment bidirectional shift register operates with the CKs_c clock. If the output voltage Vcomp of the digital low-dropout regulator (DLDO) is lower than Vlow, Qlow flips to 1, and the coarse-adjustment bidirectional shift register shifts to the right to enable more PMOS power gates. Note that when Vcomp > Vlow, Qlow = 0, but CKs_c is only effective when Vcomp > Vhigh. Therefore, when Vcomp is in the Vlow–Vhigh range, the coarse-adjustment bidirectional shift register does not operate, thus achieving fast response and high-efficiency voltage regulation.

[0033] like Figure 3 As shown, in this embodiment, the on-chip adaptive voltage and frequency regulation device includes multiple digital low-dropout regulators (DLDOs), and the multiple DLDOs share the same input voltage and output voltage. For example, as an optional implementation, this embodiment of the on-chip adaptive voltage and frequency regulation device includes three DLDOs (DLDO×3), and the three DLDOs share the same input voltage and output voltage.

[0034] like Figure 3 As shown, the on-chip adaptive voltage and frequency regulation device in this embodiment also includes a self-calibrating adjustable ring oscillator SC-TRO. The self-calibrating adjustable ring oscillator SC-TRO is connected to the voltage output terminal of a digital low dropout regulator DLDO to generate the clock signal CLK required by the processor based on the output voltage Vout of the voltage output terminal. Figure 3 and Figure 6As shown, in this embodiment, the self-calibrating adjustable ring oscillator SC-TRO includes an encoder and an adjustable ring oscillator. The processor includes an in-situ critical path timing detector, which includes a pulse generator circuit and a simplified time-to-digital converter (TDC). The pulse generator circuit is inserted at the midpoint of a specified critical path and is connected to the input of the encoder via the TDC. The pulse generator circuit generates a short pulse signal labeled "half_cp_pulse" as the clock signal for the TDC each time a detection node flips. The time interval between the short pulse signal and the rising edge of the processor's clock reflects the half-critical path delay at the midpoint of the critical path. The TDC generates a delay value encoding based on this clock signal and inputs it to the encoder. The encoder encodes the delay value into a one-hot encoding (Tuning) to control the adjustable ring oscillator to generate the clock signal CLK required by the processor. The short pulse signal "half_cp_pulse" serves as the clock signal for the TDC trigger. The time interval between the rising edge of the clock and the rising edge of "half_cp_pulse" reflects the half-critical path delay, which is converted into the simplified time-to-digital converter (TDC) output code based on the actual propagation timing of the delay unit. The TDC output code is then sent to the encoding module to generate a one-hot code for the transmission gate selection, while the oscillator generates a clock signal CLK with a flexible clock cycle based on the delay unit (whose characteristics vary with the processor voltage).

[0035] like Figure 6 As shown, the pulse generator circuit includes a delay unit, an XOR gate, and an AND gate. After the signal flips at the midpoint of the critical path, the signal along the edge and the XOR gate of the delayed signal obtained by the delay unit generate a short pulse signal. Then, the short pulse signal passes through the AND gate controlled by the control signal SE to generate a short pulse signal labeled "half_cp_pulse". The AND gate is used to ensure that the short pulse signal is effective only during the high level of the control signal SE.

[0036] like Figure 6 As shown, the simplified time-to-digital converter (TDC) includes a start-point flip-flop, a delay chain, and a register set. The delay chain consists of an input flip-flop, a basic delay unit, and a calibration delay unit connected in sequence. The delay chain propagates logic levels at each rising edge of the clock, which is represented as a temperature code on the delay chain. This temperature code is output at the rising edge of the short pulse signal "half_cp_pulse," and it reflects the time interval between the rising edge of the clock and the rising edge of the pulse. Therefore, this circuit realizes the signal conversion from delay information to the digital domain.

[0037] like Figure 6 As shown, the adjustable ring oscillator is a ring structure consisting of multiple basic delay units, multiple self-calibrating delay units, and logic gates and inverters connected end to end. One input of the logic gate is the output of multiple self-calibrating delay units, and the other input is the reset signal RST. Each self-calibrating delay unit is connected in parallel with a transmission gate unit compared to the basic delay units. The temperature code output by the simplified time-to-digital converter (TDC) is encoded by an encoder to output a unique thermal code, which is then selected by the transmission gate unit to select the corresponding delay length, thereby realizing the self-calibration function of the delay chain.

[0038] In this embodiment, the on-chip adaptive voltage and frequency regulation device for powering high-performance processors is implemented and simulated in a 28-nanometer CMOS process, occupying an area of ​​only 0.025 mm². Figure 7 The voltage resolution and power consumption characteristics of the time-domain voltage comparator in this embodiment are illustrated. As the number of delay unit stages increases, the resolution decreases, but the power consumption increases. For better performance, a two- or three-stage structure is recommended. When using five delay unit stages, the voltage resolution accuracy reaches 1mV. Figure 8 The following are the simulation results of the load transient response, the adaptive sampling clock circuit, and the self-calibrating adjustable ring oscillator SC-TRO in this embodiment, where (a) is the simulation result of the load transient response, (b) is the simulation result of the adaptive sampling clock circuit, and (c) is the simulation result of the self-calibrating adjustable ring oscillator SC-TRO. Figure 8 (a) shows the voltage drop during a 90mA load transition with an input voltage Vin of 0.8V. The three curves correspond to sampling clocks CKs of 500MHz, 356MHz, and the adaptive sampling clock provided by the adaptive sampling clock circuit, respectively. In this embodiment, the adaptive sampling clock circuit achieves the minimum drop (88mV) and the fastest setup time (15ns). Figure 8 Figure (b) illustrates the adaptive clock frequency characteristics: when the NAND gate's output signal boost is high, the frequency linearly increases from 356 MHz to 900 MHz. This frequency can also be adjusted by changing the PMOS / NMOS size; Vout in the figure represents the output voltage. Adaptive system clock regulation effect. Figure 8As shown in (c), the clock cycle is compressed or stretched depending on the output voltage Vout. Thanks to the adaptive sampling clock circuit and the high-resolution, low-power time-domain voltage comparator, the performance parameters of the digital low-dropout regulator (DLDO) in this embodiment are as follows: input voltage 0.5~0.9V, output voltage 0.4~0.8V, frequency 200~1000MHz, maximum load current 120mA, quiescent current 138~250μA, output capacitance 60pF, output voltage transient fluctuation amplitude of 88mV when the load current jumps, load current step corresponding to the above output voltage transient fluctuation 90mA, edge time 10ns, settling time: 15ns, quality factor: 0.14ps, demonstrating highly competitive performance in the field of energy-saving processors.

[0039] This embodiment presents a digital low-dropout regulator (DLDO) in an on-chip adaptive voltage and frequency regulation device for powering high-performance processors. The DLDO includes a fully synthesizable low-power voltage comparator and an adaptive sampling clock generator, enabling both coarse and fine voltage adjustment. The overall architecture is implemented using a 28nm CMOS process and simulation results have been completed. Post-layout simulation results show that the time-domain voltage comparator in this embodiment solves the problems of stability, resolution, response speed, and power consumption inherent in traditional on-chip analog circuit-built voltage comparators. It achieves synthesizable voltage comparators and possesses advantages such as strong robustness, high resolution, fast response speed, and low power consumption. This embodiment's on-chip adaptive voltage and frequency regulation device for powering high-performance processors achieves fast transient response and minimal voltage drop, with a 53% reduction in voltage drop and a 30% improvement in transient response speed compared to the baseline design. The proposed DLDO in this embodiment surpasses existing technical solutions in terms of performance indicators.

[0040] The above description is merely a preferred embodiment of the present invention, and the scope of protection of the present invention is not limited to the above embodiments. All technical solutions falling within the scope of the present invention's concept are within the scope of protection of the present invention. It should be noted that for those skilled in the art, any improvements and modifications made without departing from the principle of the present invention should also be considered within the scope of protection of the present invention.

Claims

1. A self-adapting voltage and frequency scaling device for high performance processor power supply on chip, comprising a digital low-dropout regulator (DLDO) with a voltage comparator, characterized in that, The voltage comparator is a time domain voltage comparator, which comprises three comparison registers and four delay units working in voltage domains Vcomp, Vhigh, Vref and Vlow respectively, wherein Vcomp is the output voltage of a digital low-dropout regulator (DLDO), Vref is a stable reference voltage, Vhigh and Vlow are voltages higher and lower than the reference voltage by specified voltage values respectively, the three comparison registers sample the voltage level Dout of the output signal of the delay unit corresponding to the voltage domain Vcomp as a clock signal and obtain three voltage comparison results Qhigh, Qref and Qlow by sampling the voltage levels Dhigh, Dref and Dlow of the output signals of the delay units corresponding to the voltage domains Vhigh, Vref and Vlow respectively; when the three comparison registers sample the voltage level Dout of the output signal of the delay unit corresponding to the voltage domain Vcomp as a clock signal and obtain three voltage comparison results Qhigh, Qref and Qlow, if the voltage value of the output signal of the voltage domain Vcomp is between the voltage values of the output signals of the voltage domains Vhigh and Vlow, the voltage comparison result Qhigh is fixed as 1, the voltage comparison result Qlow is fixed as 0, and the voltage comparison result Qref is determined by the voltage value of the output signal of the voltage domain Vcomp and the voltage value of the output signal of the voltage domain Vref, and is 1 or 0; if the voltage value of the output signal of the voltage domain Vcomp is greater than the voltage value of the output signal of the voltage domain Vhigh, the voltage comparison result Qhigh is 0; if the voltage value of the output signal of the voltage domain Vcomp is less than the voltage value of the output signal of the voltage domain Vlow, the voltage comparison result Qlow is 1; the input end of each of the four delay units is connected with a flip-flop, and the clock signal end and the reset signal end of the flip-flop are connected with the sampling clock CKs input by the clock signal input end.

2. The on-chip adaptive voltage and frequency scaling device for high performance processor powered supply according to claim 1, wherein, The voltage value of the output signal of the voltage domain Vhigh is 20 mV higher than the voltage value of the output signal of the voltage domain Vref, and the voltage value of the output signal of the voltage domain Vlow is 20 mV lower than the voltage value of the output signal of the voltage domain Vref.

3. The on-chip adaptive voltage and frequency scaling device for high performance processor power supply of claim 1 or 2, wherein, The digital low-dropout regulator DLDO comprises an adaptive sampling clock circuit, a coarse adjustment bidirectional shift register, a fine adjustment bidirectional shift register, a coarse adjustment power gate, a fine adjustment power gate and the time-domain voltage comparator, the adaptive sampling clock circuit is used to generate a sampling clock CKs, a coarse adjustment clock CKs_c and a fine adjustment clock CKs_f, the sampling clock CKs is connected with a clock signal input end of the time-domain voltage comparator, the coarse adjustment bidirectional shift register is used to generate a control signal of the coarse adjustment power gate based on the coarse adjustment clock CKs_c to control states of each switch unit in the coarse adjustment power gate, the fine adjustment bidirectional shift register is used to generate a control signal of the fine adjustment power gate based on the fine adjustment clock CKs_f to control states of each switch unit in the fine adjustment power gate, and each switch unit in the coarse adjustment power gate and the fine adjustment power gate is connected in parallel to form an output voltage Vcomp of the digital low-dropout regulator DLDO.

4. The on-chip adaptive voltage and frequency scaling device for high performance processor power supply of claim 3, wherein, The adaptive sampling clock circuit comprises an input part, an intermediate part and an output part, the intermediate part comprises a pair of PMOS transistors, a ring oscillator and a pair of NMOS transistors arranged in series between a power supply VDD and a ground GND, the input part comprises an OR gate and an inverter, a voltage comparison result Qhigh after inversion and Qlow are taken as inputs of the OR gate, an output signal boost of the OR gate is connected with a gate of a PMOS transistor after inversion, a gate of another PMOS transistor is connected with a reference ground VSS, the output signal boost of the OR gate is connected with a gate of an NMOS transistor, a gate of another NMOS transistor is connected with the power supply VDD, the ring oscillator is a ring structure formed by a plurality of inverters connected in series, and an output signal led out of the ring structure is connected with the output part, the output part comprises a latch LS and two AND gates, the output signal led out of the ring structure generates a sampling clock CKs after the latch LS, the sampling clock CKs and the output signal boost of the OR gate generate a coarse adjustment clock CKs_c through a first AND gate of the two AND gates, and the sampling clock CKs and a signal obtained by inversion of the output signal boost of the OR gate generate a fine adjustment clock CKs_f through a second AND gate of the two AND gates.

5. The on-chip adaptive voltage and frequency scaling device for high performance processor power supply of claim 3, wherein, The coarse adjustment bidirectional shift register and the fine adjustment bidirectional shift register are both composed of a plurality of groups of multiplexers and registers connected in series, and the coarse adjustment bidirectional shift register adopts the voltage comparison result Qlow as an enable signal, and the fine adjustment bidirectional shift register adopts the voltage comparison result Qref as an enable signal.

6. The on-chip adaptive voltage and frequency scaling device for high performance processor power supply of claim 3, wherein, The on-chip adaptive voltage and frequency adjustment device comprises a plurality of digital low-dropout regulators DLDOs, and the plurality of digital low-dropout regulators DLDOs share the same input voltage and output voltage.

7. The on-chip adaptive voltage and frequency scaling device for high performance processor power supply facing of claim 1, wherein, The on-chip adaptive voltage and frequency scaling device further comprises a self-calibrating tunable ring oscillator (SC-TRO) connected to a voltage output of a digital low-dropout regulator (DLDO) for generating a clock signal (CLK) required by the processor according to an output voltage (Vout) of the voltage output.

8. The on-chip adaptive voltage and frequency scaling device for high performance processor power supply facing of claim 7, wherein, The self-calibrating tunable ring oscillator (SC-TRO) comprises an encoder and a tunable ring oscillator, the processor comprises an in-situ critical path timing detector comprising a pulse generator circuit inserted at a midpoint of a specified critical path and a simple time-to-digital converter (TDC), the pulse generator circuit is connected to an input of the encoder through the simple time-to-digital converter (TDC), the pulse generator circuit generates a short pulse signal marked as "half_cp_pulse" as an input clock signal of the simple time-to-digital converter (TDC) at each time of detecting a node flip, a time interval between the short pulse signal and a clock rising edge of the processor reflects a half critical path delay of the midpoint of the critical path, the simple time-to-digital converter (TDC) generates a delay value encoding according to the input clock signal and inputs the delay value encoding into the encoder, the encoder encodes the delay value into a one-hot encoding to control the tunable ring oscillator to generate the clock signal (CLK) required by the processor.

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