Power consumption control system and method and electronic equipment

Abstract

The invention relates to a power consumption control system and method and electronic equipment. The system comprises an enhanced decoding unit, a plurality of functional modules and power gating units respectively corresponding to the functional modules, wherein the enhanced decoding unit is used for receiving a to-be-executed instruction, decoding the to-be-executed instruction, determining a list of functional modules needing to be activated, generating a power consumption control vector based on the list of the functional modules needing to be activated, and sending the power consumption control vector to a power gating unit corresponding to each functional module; and the power gating unit is used for determining the enabling state of the functional module corresponding to the power gating unit in the power consumption control vector, and controlling the power state of the functional module based on the enabling state. By adopting the system, the power supply state of each functional module can be accurately and timely controlled in a fine-grained manner based on the functional module needing to be activated of each module, power is supplied in a targeted manner according to the requirement of a to-be-executed instruction, the system is tightly combined with an instruction execution assembly line, and the effectiveness of power consumption control is ensured.

Description

Technical Field

[0001] This application relates to the field of integrated circuit technology, and in particular to a power consumption control system, method and electronic device. Background Technology

[0002] With the rapid development of electronic circuit technology, electronic devices are being used in increasingly diverse and frequent applications. Every electronic device contains a controller, which may include a central processing unit (CPU) or a graphics processing unit (GPU). The controller is used to control the electronic device to perform multiple functions. Therefore, the controller's uptime is crucial to the performance of the electronic device, and power consumption control is necessary to extend its uptime.

[0003] In related technologies, the power supply to the entire controller is usually completely turned off. However, the wake-up time from power-off to power-on is relatively long, and the controller is used frequently. Frequent overall power-on and power-off will affect the lifespan of the controller. Therefore, there is an urgent need for a more effective power consumption control method for the controller. Summary of the Invention

[0004] Therefore, it is necessary to provide a precise and effective power consumption control system, method, and electronic device to address the aforementioned technical problems.

[0005] In a first aspect, this application provides a power consumption control system, which includes an enhanced decoding unit, multiple functional modules, and power gating units corresponding to each of the functional modules; wherein:

[0006] The enhanced decoding unit is used to receive the instruction to be executed, decode the instruction to be executed, determine the list of functional modules to be activated, generate a power consumption control vector based on the list of functional modules to be activated, and send the power consumption control vector to the power gating unit corresponding to each functional module.

[0007] The power gating unit is used to determine the enable state of the functional module corresponding to the power gating unit in the power consumption control vector, and control the power state of the functional module based on the enable state.

[0008] In some embodiments, the enhanced decoding unit is specifically used to query a list of functional modules to be activated corresponding to the instruction to be executed in a preset control lookup table, wherein the control lookup table includes the correspondence between instructions and modules to be activated.

[0009] In some embodiments, the initial control vector includes multiple elements, each element corresponding one-to-one with a functional module; each element represents a valid or invalid state; wherein:

[0010] The enhanced decoding unit is further specifically used to update the elements corresponding to each functional module to be activated in the list of functional modules to be activated to an active state, and to update other elements to an inactive state in the initial control vector, so as to obtain a power consumption control vector.

[0011] In some embodiments, the power gating unit is specifically used to determine the enable state of a corresponding element based on the functional module corresponding to the power control unit in the power consumption control vector; when the enable state is valid, control the power supply of the functional module to be in an on state, or when the enable state is invalid, control the power supply of the functional module to be in an off / cut-off state.

[0012] In some embodiments, the power gating unit is further configured to, during the instruction phase of the instruction to be executed, control the power supply of the functional module to be turned off / cut off if it is determined that the functional module whose power supply is on is not being used.

[0013] In some embodiments, the system further includes an instruction fetch unit; wherein:

[0014] The instruction fetching unit is used to fetch one instruction to be executed or multiple instructions to be executed in parallel from a preset memory system.

[0015] In some embodiments, the instruction fetch unit is further configured to obtain the decoding results of a target number of prefetched instructions following the instruction to be executed;

[0016] The enhanced decoding unit is specifically used to receive the decoding results of the instruction to be executed and the prefetch instruction, decode the instruction to be executed to obtain the decoding result, and determine the list of functional modules to be activated based on the decoding result and the decoding result of the prefetch instruction.

[0017] In some embodiments, each of the functional modules includes, but is not limited to, one or more of the following: arithmetic logic unit, floating-point operation unit, storage unit, vector unit, register file port, encryption processor, decryption processor, and artificial intelligence operator.

[0018] Secondly, this application also provides a power consumption control method applied to a power consumption control system, the power consumption control system including an enhanced decoding unit, multiple functional modules, and power gating units corresponding to each of the functional modules; the method includes:

[0019] The enhanced decoding unit receives the instruction to be executed, decodes the instruction to be executed, determines the list of functional modules to be activated, generates a power control vector based on the list of functional modules to be activated, and sends the power control vector to the power gating unit corresponding to each functional module.

[0020] Each power gating unit determines the enable state of the functional module corresponding to the power gating unit in the power consumption control vector, and controls the power state of the functional module based on the enable state.

[0021] Thirdly, this application also provides an electronic device, including a memory and a processor, wherein the memory stores a computer program, and the processor executes the computer program to implement the steps in the embodiments of this application.

[0022] Fourthly, this application also provides a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the steps in the embodiments of this application.

[0023] Fifthly, this application also provides a computer program product, including a computer program, which, when executed by a processor, represents the steps in the embodiments of this application.

[0024] Sixthly, this application also provides a chip including programmable logic circuitry and / or program instructions, which, when running, can execute the steps in the above-described method embodiments.

[0025] The aforementioned power consumption control system, method, and electronic device include an enhancement decoding unit, multiple functional modules, and power gating units corresponding to each functional module. The enhancement decoding unit receives and decodes instructions to be executed, determines a list of functional modules to be activated, generates a power consumption control vector based on the list, and sends the power consumption control vector to the power gating unit corresponding to each functional module. The power gating unit determines the enable state of the functional module corresponding to the power gating unit within the power consumption control vector and controls the power state of the functional module based on the enable state. By employing this system, the power state of each functional module can be controlled precisely and promptly with fine granularity based on the functional modules that need to be activated. This enables targeted power supply according to the needs of the instructions to be executed, allowing for close integration with the instruction execution pipeline. Timely control of the power state of each functional module reduces control latency and ensures effective power consumption control. Attached Figure Description

[0026] To more clearly illustrate the technical solutions in the embodiments of this application or related technologies, the drawings used in the description of the embodiments of this application or related technologies will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0027] Figure 1 This is a schematic diagram of a power consumption control system in one embodiment;

[0028] Figure 2 This is a schematic diagram of the enhanced decoding unit and decoding pipeline in a power consumption control system in one embodiment;

[0029] Figure 3 This is a schematic diagram of a power consumption control system in another embodiment;

[0030] Figure 4 This is a flowchart illustrating a power consumption control method in one embodiment;

[0031] Figure 5 This is a structural block diagram of a power consumption control device in one embodiment;

[0032] Figure 6 This is a diagram of the internal structure of an electronic device in one embodiment. Detailed Implementation

[0033] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application.

[0034] It should be noted that the terms "first," "second," etc., used in this application can be used to describe various elements, but these elements are not limited by these terms. These terms are only used to distinguish the first element from the second element. The terms "comprising" and "having," and any variations thereof, used in this application, are intended to cover non-exclusive inclusion. The term "multiple" used in this application refers to two or more. The term "and / or" used in this application refers to one of the embodiments, or any combination of multiple embodiments.

[0035] The power consumption control system 10 provided in this application embodiment can be a controller in an electronic device, such as a central processing unit (CPU) or a graphics processing unit (GPU); the structural schematic diagram of the power consumption control system 10 can be as shown below. Figure 1As shown, it includes at least an enhanced decoding unit 100, multiple functional modules, and power gating units 200 corresponding to each functional module. The multiple functional modules may include functional module 1, functional module 2, ..., functional module n. There is a one-to-one correspondence between the functional modules and the power gating units 200, meaning that each functional unit is equipped with a power gating unit 200 to control the power state of that functional unit, such as whether it is in an on or off state. This provides a communication basis for subsequent fine-grained control of the on or off states of each functional module.

[0036] This application provides a power consumption control system, which includes an enhanced decoding unit, multiple functional modules, and power gating units corresponding to each functional module; wherein:

[0037] The enhanced decoding unit is used to receive the instruction to be executed, decode the instruction, determine the list of functional modules to be activated, generate a power control vector based on the list of functional modules to be activated, and send the power control vector to the power gating unit corresponding to each functional module.

[0038] The instruction to be executed can be an instruction about to be executed, or an instruction currently stored in the memory of the power control system. The instruction to be executed is the instruction that the controller will execute. The list of functional modules to be activated includes multiple functional modules that the controller needs to use when executing the instruction to be executed. The power control vector can be a vector representing the power state of each functional module within the controller. This power control vector contains multiple elements, each corresponding to a specific functional module. That is, there is a one-to-one correspondence between elements and functional modules within the controller. Elements can have active and inactive states, representing whether the power state of the corresponding functional module is on or off.

[0039] Specifically, the enhanced decoding unit can receive the current instruction to be executed, decode the instruction, determine the type of the instruction, and determine the list of functional modules to be activated for that type. Based on each functional module in the list, a power control vector is generated. The enhanced decoding unit can then send the generated power control vector to each functional module within the power control system. Optionally, the enhanced decoding unit can send the power control vector to the power gating unit in each functional module via a communication connection or an electrical connection.

[0040] Optionally, the power control vector can be a power control enable signal, which may include flag bits corresponding to each functional module. Each flag bit is an element, and each flag bit may have a valid state or an invalid state. The functional module corresponding to the flag bit may have a power-on state or a power-off state.

[0041] The power gating unit is used to determine the enable state of the functional module corresponding to the power gating unit in the power consumption control vector, and control the power state of the functional module based on the enable state.

[0042] Each functional module in the power consumption control system is equipped with a power gating unit, which controls the power supply VDD of the module. Optionally, the power gating unit can be a head switch or a tail switch. For example, a PMOS transistor can be connected in series between the functional module's VDD and the global VDD as a head switch, thus serving as the power gating unit for that functional module. The power consumption control vector generated by the enhancement decoding unit is also directly sent to the PMOS transistor / switch in that functional module.

[0043] Specifically, the enhanced decoding unit can send the generated power control vector to the power gating units in each functional module of the power control system. Upon receiving the power control vector, the power gating unit can determine the state of the corresponding functional module indicated by the power control vector. Based on this state, the power gating unit can control its gate. For example, if the power control vector indicates an active state, the gate is turned on to put the functional module into an active state; or, if the power control vector indicates an inactive state, the gate is turned off to put the functional module into an inactive / off state, severing the connection between the global VDD and the functional module's VDD, thus disconnecting the power supply to the functional module and placing it in a cut-off power supply state.

[0044] In the aforementioned power consumption control system, the enhanced decoding unit receives and decodes the instructions to be executed, determines the list of functional modules to be activated, generates a power consumption control vector based on the list, and sends the power consumption control vector to the power gating unit corresponding to each functional module. The power gating unit determines the enable state of the functional module corresponding to the power gating unit in the power consumption control vector and controls the power state of the functional module based on the enable state. By adopting this system, the power state of each functional module can be controlled in a fine-grained, precise, and timely manner based on the functional modules that need to be activated, achieving targeted power supply according to the needs of the instructions to be executed. It can be closely integrated with the instruction execution pipeline to control the power state of each functional module in a timely manner, thereby reducing control latency and ensuring the effectiveness of power consumption control.

[0045] In one embodiment, the enhanced decoding unit is specifically used to query a list of functional modules to be activated corresponding to the instruction to be executed in a preset control lookup table.

[0046] The control lookup table includes the correspondence between instructions and modules to be activated. For example, the control lookup table can store the mapping between the opcodes corresponding to each instruction and the modules to be activated; alternatively, it can store the mapping between the indexes corresponding to each instruction and the modules to be activated; or it can store the mapping between the types corresponding to each instruction and the modules to be activated, and so on. The correspondence between instructions and opcodes, instructions and indexes, and instructions and types can be one-to-one or many-to-one based on the actual application scenario. Optionally, the control lookup table can be a read-only memory (ROM) or a power decoder. The functional modules to be activated corresponding to the instruction to be executed are the modules that the controller needs to use when executing the instruction. Based on the combination of these functional modules, a list of functional modules to be activated corresponding to the instruction to be executed is generated.

[0047] Specifically, after receiving the instruction to be executed, the enhanced decoding unit can determine the opcode corresponding to the instruction, and then use the opcode as an index to search for the corresponding functional module to be activated in the control lookup table that stores the correspondence between opcodes and functional modules to be activated. The enhanced decoding unit can then combine the found functional modules to be activated to generate a list of functional modules to be activated.

[0048] Optionally, when the instruction to be executed is an integer addition instruction, the lookup result of the control lookup table, i.e., the generated list of functional modules to be activated, can be the instruction register, the integer ALU, and the read / write ports of the general-purpose register file. When the instruction to be executed is a floating-point multiply-accumulate instruction (e.g., FMADD), the lookup result of the control lookup table, i.e., the generated list of functional modules to be activated, can be the instruction register, the floating-point register file, the floating-point multiplier, and the floating-point adder. The opcodes corresponding to each instruction to be executed can be pre-configured or configured based on the requirements of the actual application scenario. The opcodes and the functional modules to be activated can be configured based on the actual application scenario after determining the electronic device where the controller is located, the electronic device controlled by the controller, or the scenario / task currently applied by the controller.

[0049] In this embodiment, using the opcode of the instruction as intermediate data for querying the various functional modules required to execute the instruction can enhance the query efficiency and accuracy of the functional modules. By storing the opcode instead of the actual instruction, the utilization rate of storage space can be improved.

[0050] In one embodiment, the initial control vector includes multiple elements, each corresponding one-to-one with a functional module; each element is either active or inactive. Specifically, the initial control vector can be an initialized vector or a power control vector generated in the previous time step. Each element in the initial control vector can be a flag bit, and each element corresponds to a functional module in the controller. The correspondence between functional modules and elements can be pre-configured. When an element in the power control vector is active, the corresponding indicator function module's power state is ON; when an element in the power control vector is inactive, the corresponding indicator function module's power state is OFF.

[0051] The enhanced decoding unit is also specifically used to update the elements corresponding to each functional module to be activated in the list of functional modules to be activated to an active state, and to update other elements to an inactive state in the initial control vector, so as to obtain the power consumption control vector.

[0052] Specifically, after determining the multiple functional modules that need to be activated when the instruction to be executed is executed, the enhanced decoding unit can identify the elements in the initial control vector corresponding to these multiple functional modules. Specifically, it identifies multiple first elements in the initial control vector that indicate the power state of the multiple functional modules to be activated, and second elements that do not indicate the aforementioned functional modules. The state of the multiple first elements is updated to a valid state (e.g., updating the element to a first target value), and the state of each of the other second elements that do not indicate the power state of the aforementioned functional modules is updated to an invalid state (e.g., updating the element to a second target value). The initial control vector after this update process is then determined as the power consumption control vector corresponding to the module to be executed, generated by the enhanced decoding unit. Each functional module can be the smallest independently controllable unit within the controller. The first target value can be 1, the second target value can be 0, etc.

[0053] In this embodiment, by precisely determining the functional modules in the controller that the instruction to be executed needs during execution, targeted and fine-grained control of the instruction to be executed can be achieved. This enables real-time and timely on-demand power supply to each functional module, reducing or even eliminating the static power consumption / leakage power consumption of each functional module in the controller, reducing the power supply time of each functional module in the controller when it is not in use, and completely cutting off the power supply when the functional module is not working through the power gating unit, thereby extending the service life of each functional module in the controller.

[0054] In one embodiment, the power gating unit is specifically used to determine the enable state of the corresponding element in the power consumption control vector based on the functional module corresponding to the power gating unit; when the enable state is valid, the power supply of the control functional module is in the on state, or when the enable state is invalid, the power supply of the control functional module is in the off / cut-off state.

[0055] Specifically, the execution process of each power gating unit in the power consumption control system is similar. Here, we take the power gating unit corresponding to any one of the functional modules as an example for illustration; the power gating unit is a switch set inside the functional module. After receiving the power consumption control vector sent by the enhancement decoding unit, the power gating unit first determines the functional module corresponding to the power gating unit, and based on the identification information of the functional module, queries the power consumption control vector for the element corresponding to the identification information, and extracts the current enable state of the element, that is, the current state of the element.

[0056] In this way, the power gating unit can control the power supply of the corresponding functional module based on the enable state of the element. When the enable state is determined to be valid, the power gating unit can control the gate of the power gating unit to be turned on, so that the power supply state of the functional module is on, that is, the global VDD can be connected to the VDD of the functional module. Alternatively, when the enable state is determined to be invalid, the power gating unit can control the gate of the power gating unit to be turned off, so that the power supply state of the functional module is off, that is, the global VDD can be disconnected from the VDD of the functional module.

[0057] In this embodiment, the power consumption control vector is determined by the functional modules required by the instruction to be executed itself, and the power consumption control vector is sent to the power gating unit so that the power gating unit can achieve sensitive and fine-grained control of the power status of each functional module in the controller. The power status control can also be tightly coupled with the instruction execution pipeline, that is, the power switching action can be performed synchronously with the instruction execution, and the delay of power on and off is extremely low.

[0058] In one embodiment, the power gating unit is further configured to, during the instruction phase of the instruction to be executed, control the power supply of the functional module to be turned off / cut off if it is determined that the functional module whose power supply is on is not being used.

[0059] Specifically, during the execution phase of the instruction to be executed, the power gating unit will also detect whether the functional module corresponding to the power gating unit is used or called during the execution phase. If the power gating unit determines that the functional module is not used during the execution phase, the power gating unit can control the power supply of the functional module to be in a disconnected state in real time, that is, it can control the gate of the current power gating unit to be disconnected, so that the power supply state of the functional module is in a disconnected state, which means that the global VDD and the VDD of the functional module are disconnected.

[0060] In this embodiment, the power supply gating unit can cut off the power to each unused functional module in a timely manner, further reducing power consumption and enabling more flexible and comprehensive multi-stage monitoring and updating of power status.

[0061] In one embodiment, the power consumption control system further includes an instruction fetch unit; wherein:

[0062] The instruction fetch unit is used to fetch one instruction to be executed or multiple instructions to be executed in parallel from a preset memory system.

[0063] The preset memory system can be the controller's memory subsystem, which can cache multiple instructions to be executed serially or multiple instructions to be executed in parallel, etc.

[0064] Specifically, the instruction fetch unit can acquire an instruction to be executed from a preset memory system. Optionally, the power control system can be a system that supports parallel execution. In this case, when multiple instructions to be executed in parallel are cached in the preset memory system, the instruction fetch unit can acquire these multiple instructions. The enhanced decoding unit can then determine these multiple instructions as the instructions to be executed, and further determine the list of functional modules to be activated for each instruction through multiple parallel threads, thereby generating a power control vector, or generating a corresponding power control vector for each instruction. The number of instructions to be executed in parallel can be determined based on the actual model of the controller, etc., and this embodiment does not limit this.

[0065] In this embodiment, multiple instructions to be executed are processed in parallel, thereby improving the efficiency of instruction processing and the efficiency of updating the power status of each functional module.

[0066] In one embodiment, the instruction fetching unit is further configured to obtain the decoding results of a target number of prefetched instructions following the instruction to be executed; the enhanced decoding unit is specifically configured to receive the decoding results of the instruction to be executed and the prefetched instructions, decode the instruction to be executed to obtain the decoding results, and determine the list of functional modules to be activated based on the decoding results and the decoding results of the prefetched instructions.

[0067] The target number can be the highest threshold for the number of instructions that can be pre-decoded, or the number of instructions that have already been pre-decoded. This embodiment does not limit the specific value of the target number. The prefetch instruction can be the instruction following or several instructions of the instruction to be executed that have been obtained in advance. The decoding result of the prefetch instruction is the opcode of the prefetch instruction determined after pre-decoding, or the specific requirements of the prefetch instruction for various functional modules, such as functional modules that need to be woken up in advance.

[0068] Specifically, the enhanced decoding unit can decode the instruction to be executed to determine the list of functional modules to be activated corresponding to that instruction, as well as the opcodes represented by the decoding results of each prefetched instruction. It can then query the list of functional modules to be activated for each prefetched instruction from a preset mapping between opcodes and functional modules to be activated, and determine the list of functional modules to be activated based on each specific requirement. Based on this, the enhanced decoding unit can generate a power control vector for unified power control of the functional modules, based on the list of functional modules to be activated corresponding to the instruction to be executed, the list of functional modules to be activated corresponding to each prefetched instruction, and the list of functional modules to be activated corresponding to each specific requirement.

[0069] In this embodiment, parallel processing or pre-decoding is used to improve instruction processing efficiency and enable early wake-up of functional modules, avoiding power wake-up delay and ensuring timely and accurate execution of each instruction.

[0070] In one embodiment, each functional module includes, but is not limited to, one or more of the following: arithmetic logic unit, floating-point operation unit, storage unit, vector unit, register file port, encryption processor, decryption processor, and artificial intelligence operator.

[0071] Specifically, the functional modules may include an integer arithmetic logic unit (ALU), a loading unit, a storage unit, a vector / SIMD processing unit, a specific register file port, etc.; the floating point unit (FPU) may include one or more of a multiplier, adder, and divider; the encryption processor may be an encryption coprocessor, and the decryption processor may be a decryption coprocessor.

[0072] The following describes a specific embodiment, such as... Figure 2 As shown, the specific execution flow and architecture diagram of the aforementioned power consumption control system are described in detail. This power consumption control system includes an instruction fetch unit (IFU), an enhanced decoding unit, and various functional modules. Each functional module may contain a power switch / power gating unit. Optionally, the enhanced decoding unit can be located within the IFU. The location of the enhanced decoding unit is optional, meaning it is sufficient to ensure that the enhanced decoding unit can communicate with the IFU and the various functional modules. The functional modules may include an ALU, FPU, VSU, and artificial intelligence operators, etc. The execution steps may include:

[0073] Step 1, Instruction Fetch. Specifically, this involves retrieving the instruction to be executed from the instruction cache. For example, a power control system may include an IFU (Instruction Cache) that can be used to retrieve the instruction to be executed from the memory subsystem of the power control system.

[0074] Step 2: Instruction Decoding and Power Consumption Information Extraction. Specifically, the enhanced decoding unit decodes the instruction to be executed. In this stage, in addition to generating micro-operations (μOPs) or control signals, it also queries a preset power consumption control lookup table to obtain the list of target functional modules that need to be activated to execute the instruction, thus obtaining the list of functional modules that need to be activated corresponding to the instruction to be executed.

[0075] Optionally, for integer addition instructions (such as ADD R1, R2, R3), the lookup control table indicates that the modules to be activated are: the instruction register, the integer ALU, and the read / write ports of the general-purpose register file. For floating-point multiply-accumulate instructions (such as FMADD), the following need to be activated: the instruction register, the floating-point register file, the floating-point multiplier, and the floating-point adder.

[0076] In other words, during the instruction decoding stage, it is necessary to parse out the operation type and operands of the instruction to be executed, as well as the CPU / GPU internal hardware modules that need to be activated to execute the instruction. Based on this information, corresponding module enable signals / power control vectors are generated, and the power switching circuits of the corresponding functional modules are directly controlled through these power control vectors.

[0077] Step 3: Generate module enable signals / power control vectors. Specifically, based on the list of functional modules to be activated, a set of module enable signals (power control vectors) is generated. Each signal corresponds to multiple fine-grained functional modules.

[0078] Step 4: Dynamic power control. The power consumption control vector is sent to the power gating unit corresponding to each module. When the enable signal is valid, the power supply to the corresponding module is turned on; when the enable signal is invalid, the power supply to that module is turned off.

[0079] Additionally, to conceal the power-on delay of modules, the pipeline characteristics can be utilized during the current instruction decoding stage to wake up modules that will be used soon, based on the decoding results of the next or several prefetched instructions, early in the pipeline. For example... Figure 3 As shown, the decoding pipeline can be ID1, ID2, ID3, and ID4, and the current instruction can be ID0. The decoding pipeline can send the opcode of the current instruction and the pre-decode result of the next instruction to the enhanced decoding unit. The enhanced decoding unit uses a power control lookup table (ROM) or a power decoder to perform decoding, generating a power control vector. This generated power control vector is then sent to the power gating units corresponding to each functional module. In other words, the decoding result from the decoding pipeline is used to send the pre-decode result (instruction opcode or special power requirements) to the enhanced decoding unit in advance. The enhanced decoding unit generates a "merged" module enable signal based on the modules required by the current instruction and subsequent instructions, enabling all modules that will be used in advance, just in time for the instruction execution phase.

[0080] The enhanced decoding unit (IFU) integrates power control logic. This logic includes a power control lookup table and a module enable signal generator. The power control lookup table stores the mapping relationship between instruction types and required functional modules. The module enable signal generator generates specific control signals, i.e., generates a power control vector, based on the output of the lookup table.

[0081] Optionally, the power control system includes multiple fine-grained functional modules (depending on the chip product's functionality): these are the objects being controlled; the power control system also includes a distributed power gating network: each (or group of) fine-grained functional module is connected to a power gating unit. This unit receives a module enable signal from the decoding unit and controls the power (VDD) flowing to that module.

[0082] The power control lookup table can be a read-only memory (ROM) or a simple power decoder. The index of the power control lookup table / control lookup table is the opcode of the instruction, and the corresponding output is a vector containing multiple bits / elements. Each bit of the vector represents a specific functional module. For example, bit 0 = integer ALU, bit 1 = floating-point multiplier, bit 2 = load unit, and so on.

[0083] Correspondingly, when decoding an instruction, the lookup table is indexed using its opcode, and the output bit vector directly indicates which modules need to be activated.

[0084] The power gating unit can be implemented using either a head switch or a tail switch. For example, a PMOS transistor can be connected in series as a head switch between the functional module's VDD and the global VDD. The power control vector directly controls the gate of this switch.

[0085] The power control system provided in this embodiment achieves fine-grained control, zero-latency power-on, significantly reduced static power consumption, minimal performance impact, and low hardware overhead. The power state control granularity of the functional modules is refined to the individual functional module level (such as a specific ALU or multiplier), enabling power supply based on the needs of the instruction to be executed. The control signal originates from the instruction stream itself and is tightly coupled with the instruction execution pipeline; switching actions can be performed synchronously with instruction execution, resulting in extremely low latency. Through power gating, power is completely cut off when a module is not in operation, eliminating leakage power consumption (static power consumption) of that module, which is particularly effective at advanced process nodes. Mechanisms such as "early wake-up" ensure that functional modules are ready when needed, avoiding pipeline stalls caused by waiting for power-on. The only additional hardware required is a power control lookup table and distributed power gating units; the area overhead is small compared to the entire CPU, but the benefits are significant.

[0086] In other words, the power consumption control system provided in this embodiment specifically relates to a power consumption management system / method for a central processing unit (CPU) or GPU. It enables fine-grained power consumption control at the instruction execution level, allowing for rapid and dynamic control of the power supply of minute functional modules within the CPU at the granularity of a single instruction execution. This achieves extreme power consumption optimization while minimizing the impact on performance. It meets the demands for reduced power consumption resulting from improved CPU / GPU performance and increased integration, and also satisfies the energy efficiency requirements of mobile devices, data centers, and other scenarios.

[0087] In one exemplary embodiment, such as Figure 4 As shown, a power consumption control method is also provided, applied to a power consumption control system. The power consumption control system includes an enhanced decoding unit, multiple functional modules, and power gating units corresponding to each functional module. Taking the application of this power consumption control method to a power consumption control system as an example, the method includes:

[0088] Step 402: The enhanced decoding unit receives the instruction to be executed, decodes the instruction to be executed, determines the list of functional modules to be activated, generates a power control vector based on the list of functional modules to be activated, and sends the power control vector to the power gating unit corresponding to each functional module.

[0089] Step 404: Through each power gating unit, determine the enable state of the functional module corresponding to the power gating unit in the power consumption control vector, and control the power state of the functional module based on the enable state.

[0090] The execution process of each step is similar to that of each unit and module in the system embodiment, and will not be described again here.

[0091] In the aforementioned power consumption control method, the enhanced decoding unit in the power consumption control system receives the instruction to be executed, decodes it, determines the list of functional modules to be activated, generates a power consumption control vector based on the list, and sends the power consumption control vector to the power gating unit corresponding to each functional module. The power gating unit then determines the enable state of the corresponding functional module within the power consumption control vector and controls the power state of the functional module based on the enable state. By employing this method, the power state of each functional module can be controlled in a fine-grained, precise, and timely manner based on the functional modules that need to be activated. This allows for targeted power supply according to the requirements of the instruction to be executed, enabling close integration with the instruction execution pipeline. Timely control of the power state of each functional module reduces control latency and ensures effective power consumption control.

[0092] It should be understood that although the steps in the flowcharts of the embodiments described above are shown sequentially according to the arrows, these steps are not necessarily executed in the order indicated by the arrows. Unless explicitly stated herein, there is no strict order restriction on the execution of these steps, and they can be executed in other orders. Moreover, at least some steps in the flowcharts of the embodiments described above may include multiple steps or multiple stages. These steps or stages are not necessarily completed at the same time, but can be executed at different times. The execution order of these steps or stages is not necessarily sequential, but can be performed alternately or in turn with other steps or at least some of the steps or stages in other steps. It is understood that the steps in different embodiments can be freely combined as needed, and all non-contradictory solutions formed by such combinations are within the scope of protection of this application.

[0093] Based on the same inventive concept, this application also provides a power control device for implementing the power control method described above. The solution provided by this device is similar to the implementation described in the above method; therefore, the specific limitations in one or more power control device embodiments provided below can be found in the limitations of the power control method described above, and will not be repeated here.

[0094] In one exemplary embodiment, such as Figure 5 As shown, a power consumption control device 500 is provided, applied to a power consumption control system. The power consumption control system includes an enhanced decoding unit, multiple functional modules, and power gating units corresponding to each functional module. The device includes:

[0095] The receiving module 502 is used to receive the instruction to be executed through the enhanced decoding unit, decode the instruction to be executed, determine the list of functional modules to be activated, generate a power consumption control vector based on the list of functional modules to be activated, and send the power consumption control vector to the power gating unit corresponding to each functional module.

[0096] The determination module 504 is used to determine the enable state of the functional module corresponding to each power gating unit in the power consumption control vector through each power gating unit, and control the power state of the functional module based on the enable state.

[0097] Each module in the aforementioned power consumption control device can be implemented entirely or partially through software, hardware, or a combination thereof. These modules can be embedded in the processor of the electronic device in hardware form or independent of it, or stored in the memory of the electronic device in software form, so that the processor can call and execute the operations corresponding to each module.

[0098] In one exemplary embodiment, an electronic device is provided, which may be a server, and its internal structure diagram may be as follows: Figure 6 As shown, this electronic device includes a processor, memory, input / output (I / O) interfaces, and a communication interface. The processor, memory, and I / O interfaces are connected via a system bus, and the communication interface is also connected to the system bus via the I / O interfaces. The processor provides computing and control capabilities. The memory includes non-volatile storage media and internal memory. The non-volatile storage media stores the operating system, computer programs, and a database. The internal memory provides the environment for the operation of the operating system and computer programs stored in the non-volatile storage media. The database stores data for instructions to be executed. The I / O interfaces are used for exchanging information between the processor and external devices. The communication interface is used for communicating with external terminals via a network connection. When the computer program is executed by the processor, it implements a power consumption control method.

[0099] Those skilled in the art will understand that Figure 6 The structure shown is merely a block diagram of a portion of the structure related to the present application and does not constitute a limitation on the electronic device to which the present application is applied. The specific electronic device may include more or fewer components than shown in the figure, or combine certain components, or have different component arrangements.

[0100] In one embodiment, a computer-readable storage medium is provided having a computer program stored thereon that, when executed by a processor, implements the steps in the above method embodiments.

[0101] In one embodiment, a computer program product is provided, including a computer program that, when executed by a processor, implements the steps in the above method embodiments.

[0102] This application also provides a chip that includes programmable logic circuits and / or program instructions, which can execute the steps in the above-described method embodiments when the chip is running.

[0103] In one embodiment, the task-orchestration-based instruction processing method can also be executed by a chip or a chip module; the data processing device may be, for example, a chip or a chip module.

[0104] Regarding the modules / units included in the various devices and products described in the above embodiments, they can be software modules / units, hardware modules / units, or a combination of both. For example, for various devices and products applied to or integrated into a chip, all of their modules / units can be implemented using hardware methods such as circuits, or at least some modules / units can be implemented using software programs that run on a processor integrated within the chip, while the remaining (if any) modules / units can be implemented using hardware methods such as circuits; for various devices and products applied to or integrated into a chip module, all of their modules / units can be implemented using hardware methods such as circuits, and different modules / units can be located in the same component (e.g., chip, circuit module, etc.) or different components of the chip module, or at least some modules / units can be implemented using hardware methods such as circuits. The components can be implemented using software programs that run on the processor integrated within the chip module. The remaining (if any) modules / units can be implemented using hardware methods such as circuits. For various devices and products applied to or integrated into the terminal, each of its components / units can be implemented using hardware methods such as circuits. Different modules / units can be located in the same component (e.g., chip, circuit module, etc.) or in different components within the terminal. Alternatively, at least some modules / units can be implemented using software programs that run on the processor integrated within the terminal, while the remaining (if any) modules / units can be implemented using hardware methods such as circuits.

[0105] Those skilled in the art will understand that all or part of the processes in the methods of the above embodiments can be implemented by a computer program instructing related hardware. The computer program can be stored in a non-volatile computer-readable storage medium, and when executed, it can include the processes of the embodiments of the above methods. Any references to memory, databases, or other media used in the embodiments provided in this application can include at least one of non-volatile memory and volatile memory. Non-volatile memory can include read-only memory (ROM), magnetic tape, floppy disk, flash memory, optical memory, high-density embedded non-volatile memory, resistive random access memory (ReRAM), magnetic random access memory (MRAM), ferroelectric random access memory (FRAM), phase change memory (PCM), graphene memory, etc. Volatile memory can include random access memory (RAM) or external cache memory, etc. By way of illustration and not limitation, RAM can take many forms, such as Static Random Access Memory (SRAM) or Dynamic Random Access Memory (DRAM). The databases involved in the embodiments provided in this application may include at least one type of relational database and non-relational database. Non-relational databases may include, but are not limited to, blockchain-based distributed databases. The processors involved in the embodiments provided in this application may be general-purpose processors, central processing units, graphics processing units, digital signal processors, programmable logic devices, quantum computing-based data processing logic devices, artificial intelligence (AI) processors, etc., and are not limited to these.

[0106] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this application.

[0107] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are specific and detailed, they should not be construed as limiting the scope of this patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this application should be determined by the appended claims.

Claims

1. A power consumption control system, characterized in that, The power consumption control system includes an enhanced decoding unit, multiple functional modules, and power gating units corresponding to each of the functional modules; wherein: The enhanced decoding unit is used to receive the instruction to be executed, decode the instruction to be executed, determine the list of functional modules to be activated, generate a power consumption control vector based on the list of functional modules to be activated, and send the power consumption control vector to the power gating unit corresponding to each functional module. The power gating unit is used to determine the enable state of the functional module corresponding to the power gating unit in the power consumption control vector, and control the power state of the functional module based on the enable state.

2. The system according to claim 1, characterized in that, The enhanced decoding unit is specifically used to query a list of functional modules to be activated corresponding to the instruction to be executed in a preset control lookup table. The control lookup table includes the correspondence between instructions and modules to be activated.

3. The system according to claim 2, characterized in that, The initial control vector includes multiple elements, each corresponding one-to-one with a functional module; each element represents a valid or invalid state; wherein: The enhanced decoding unit is further specifically used to update the elements corresponding to each functional module to be activated in the list of functional modules to be activated to an active state, and to update other elements to an inactive state in the initial control vector, so as to obtain a power consumption control vector.

4. The system according to claim 3, characterized in that, The power gating unit is specifically used to determine the enable state of the corresponding element in the power consumption control vector based on the functional module corresponding to the power gating unit; when the enable state is valid, control the power supply of the functional module to be in the on state, or when the enable state is invalid, control the power supply of the functional module to be in the off / cut-off state.

5. The system according to claim 4, characterized in that, The power gating unit is further configured to, during the instruction phase of the instruction to be executed, if it is determined that the power supply of the functional module is not in use, control the power supply of the functional module to be turned off / cut off.

6. The system according to claim 1, characterized in that, The system further includes an instruction fetch unit; wherein: The instruction fetching unit is used to fetch one instruction to be executed or multiple instructions to be executed in parallel from a preset memory system.

7. The system according to claim 6, characterized in that, The instruction fetching unit is also used to obtain the decoding results of the target number of prefetched instructions following the instruction to be executed; The enhanced decoding unit is specifically used to receive the decoding results of the instruction to be executed and the prefetch instruction, decode the instruction to be executed to obtain the decoding result, and determine the list of functional modules to be activated based on the decoding result and the decoding result of the prefetch instruction.

8. The system according to any one of claims 1 to 7, characterized in that, Each of the functional modules includes, but is not limited to, one or more of the following: arithmetic logic unit, floating-point operation unit, storage unit, vector unit, register file port, encryption processor, decryption processor, and artificial intelligence operator.

9. A power consumption control method, characterized in that, The method is applied to a power consumption control system, which includes an enhanced decoding unit, multiple functional modules, and power gating units corresponding to each of the functional modules; the method includes: The enhanced decoding unit receives the instruction to be executed, decodes the instruction to be executed, determines the list of functional modules to be activated, generates a power control vector based on the list of functional modules to be activated, and sends the power control vector to the power gating unit corresponding to each functional module. Each power gating unit determines the enable state of the functional module corresponding to the power gating unit in the power consumption control vector, and controls the power state of the functional module based on the enable state.

10. An electronic device comprising a memory and a processor, wherein the memory stores a computer program, characterized in that, When the processor executes the computer program, it implements the steps of the method described in claim 9.

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