Instruction dispatch method, apparatus, processor core, and computer device

Abstract

The application provides an instruction dispatching method, device, processor core and computer device. The method comprises the following steps: obtaining instruction types of a plurality of to-be-dispatched instructions in a current period; determining whether the plurality of to-be-dispatched instructions comprise instructions of a first instruction type according to the instruction types of the plurality of to-be-dispatched instructions; if the plurality of to-be-dispatched instructions comprise instructions of the first instruction type, dispatching the instructions of the first instruction type to a first launch queue; if the plurality of to-be-dispatched instructions comprise instructions of a next instruction type, dispatching the instructions of the next instruction type to a corresponding launch queue according to a dispatching rule corresponding to the next instruction type, wherein the next instruction type comprises an instruction type that can be dispatched to a specified type of launch queue or a plurality of types of launch queue. According to the scheme, the instructions are divided according to priority, the instructions with high priority are preferentially allocated, and then the instructions with low priority are dispatched according to a certain dispatching rule, so that the instruction dispatching efficiency is improved.

Description

Technical Field

[0001] This application relates to the field of computer technology, and more specifically, to an instruction dispatch method, apparatus, processor core, and computer device. Background Technology

[0002] Instruction dispatch primarily involves sending renamed instructions to the issue queue and ensuring that dispatch is completed without causing congestion. Here, "renamed instruction" refers to an instruction in which the architectural register name has been replaced with a unique physical register identifier within the processor.

[0003] In related technologies, the system typically checks if there is an empty slot in the corresponding launch queue based on the type of instruction. If there is an empty slot, the instruction is assigned to the corresponding launch queue. However, this instruction assignment method is inefficient. Summary of the Invention

[0004] In view of this, embodiments of this application provide an instruction dispatch method, apparatus, processor core, and computer device to solve the problem of low instruction dispatch efficiency.

[0005] In a first aspect, embodiments of this application provide an instruction dispatch method, including: Get the instruction types of multiple pending instructions within the current cycle; Based on the instruction type of the plurality of instructions to be assigned, determine whether the plurality of instructions to be assigned include instructions of the first-level instruction type, wherein instructions of the first-level instruction type are instructions that are assigned only to a specified launch queue; If the plurality of instructions to be assigned includes instructions of the first level instruction type, then the instructions of the first level instruction type are assigned to the first launch queue. If the plurality of instructions to be dispatched includes instructions of a lower-level instruction type, the instructions of the lower-level instruction type are dispatched to the corresponding launch queue according to the dispatch rules corresponding to the lower-level instruction type. The lower-level instruction type includes instruction types that can be dispatched to one or more designated launch queues.

[0006] In an optional implementation, if the plurality of instructions to be dispatched include instructions of a lower-level instruction type, dispatching the instructions of the lower-level instruction type to the corresponding launch queue according to the dispatch rules corresponding to the lower-level instruction type includes: Based on the dispatch rules corresponding to the next-level instruction type and the current occupancy status of each launch queue, the instructions of the next-level instruction type are dispatched to the corresponding launch queue, and so on, until all the instructions to be dispatched are dispatched. The current occupancy status of each launch queue is used to indicate the current number of instructions occupied by each launch queue.

[0007] In an optional implementation, the type of launch queue includes at least: a first launch queue and a second launch queue; the step of assigning the instruction of the next-level instruction type to the corresponding launch queue according to the dispatch rule corresponding to the next-level instruction type and the current occupancy status of each launch queue includes: If the plurality of instructions to be dispatched include instructions of the second-level instruction type, then the remaining instruction dispatch quantity of the first launch queue is obtained according to the preset number of dispatched instructions in the first launch queue in the current period and the current number of instructions occupied in the first launch queue. Based on the remaining number of instructions to be dispatched in the first launch queue, a first dispatch queue is determined from the first launch queue and the second launch queue; Dispatch instructions of the second-level instruction type to the first dispatch queue.

[0008] In an optional implementation, determining the first dispatch queue from the first and second launch queues based on the remaining instruction dispatch quantity of the first launch queue includes: If the number of remaining instruction assignments in the first transmission queue is 0, then the second transmission queue is determined to be the first queue to be assigned. If the number of remaining dispatched instructions in the first launch queue is greater than 0 and less than the preset number of dispatched instructions, then according to the preset polling rules between the first launch queue and the second launch queue, the launch queue currently polled is determined as the first dispatch queue.

[0009] In an optional implementation, determining the first dispatch queue from the first and second launch queues based on the remaining instruction dispatch quantity of the first launch queue includes: If the remaining number of instructions to be dispatched in the first launch queue is equal to the preset number of dispatched instructions, then the difference between the number of instructions occupied in the first launch queue and the number of instructions occupied in the second launch queue is obtained based on the current number of instructions occupied in the first launch queue and the current number of instructions occupied in the second launch queue. The first dispatch queue is determined from the first and second launch queues based on the difference between the remaining number of dispatched instructions in the first launch queue and the number of instructions occupied.

[0010] In an optional implementation, determining the first dispatch queue from the first and second launch queues based on the difference between the remaining instruction dispatch quantity and the instruction occupancy quantity in the first launch queue includes: Obtain the first assignment result of the previous cycle, the first assignment result being used to indicate the launch queue assigned to the last second-level instruction type instruction of the previous cycle; The first queue to be assigned is determined from the first and second launch queues based on the remaining number of instructions to be assigned in the first launch queue, the difference in the number of instructions occupied, and the first assignment result.

[0011] In an optional implementation, each of the multiple types of launch queues includes at least the first launch queue and the second launch queue; The step of assigning instructions of the next-level instruction type to the corresponding launch queue according to the dispatch rules corresponding to the next-level instruction type and the current occupancy status of each launch queue includes: If the plurality of instructions to be dispatched include instructions of the third-level instruction type, the remaining instruction dispatch quantity of each transmission queue is obtained according to the current instruction occupancy quantity of each transmission queue and the preset dispatch instruction quantity of each transmission queue in the current period. A preset balanced allocation algorithm is adopted to determine the second allocation queue from all the launch queues based on the number of remaining instructions allocated to each launch queue. The instructions of the third-level instruction type are assigned to the second assignment queue.

[0012] In an optional implementation, the step of employing a preset balanced allocation algorithm to determine the second allocation queue from all launch queues based on the remaining instruction allocation quantity of each launch queue includes: Using the preset balanced allocation algorithm, a preset polling rule is determined among all launch queues based on the second allocation result of the previous cycle. The second allocation result is used to indicate the launch queue assigned to the last instruction of the third-level instruction type in the previous cycle. Based on the preset polling rules among all the launch queues and the remaining instruction allocation quantity of each launch queue, the second allocation queue is determined from all the launch queues.

[0013] In an optional implementation, the method further includes: Based on the current occupancy status of each launch queue, it is determined whether there is a target launch queue in each launch queue. The current occupancy status of each launch queue is used to indicate the current number of instructions occupied by each launch queue. The current number of instructions occupied by the target launch queue and the current number of instructions occupied by other launch queues in each launch queue satisfy a preset number distribution condition. If the target launch queue exists, the remaining instruction dispatch quantity of the target launch queue is set to 0.

[0014] Secondly, embodiments of this application also provide an instruction dispatching apparatus, comprising: The acquisition module is used to acquire the instruction types of multiple instructions to be dispatched within the current cycle; The determining module is used to determine whether the plurality of instructions to be assigned include instructions of the first-level instruction type based on the instruction type of the plurality of instructions to be assigned. The instructions of the first-level instruction type are instructions that are only assigned to a specified launch queue. The dispatch module is used to dispatch instructions of the first level instruction type to the first launch queue if the plurality of instructions to be dispatched include instructions of the first level instruction type. The dispatch module is further configured to, if among the plurality of instructions to be dispatched are instructions of a next-level instruction type, dispatch the instructions of the next-level instruction type to the corresponding launch queue according to the dispatch rules corresponding to the next-level instruction type. The next-level instruction type includes instruction types that can be dispatched to one or more designated launch queues.

[0015] Thirdly, embodiments of this application also provide a processor core for performing the method described in any of the first aspects.

[0016] Fourthly, embodiments of this application also provide a computer device, including: a processor, a memory, and a bus, wherein the memory stores machine-readable instructions executable by the processor, and when the computer device is running, the processor communicates with the memory via the bus, and the processor executes the machine-readable instructions to perform the method described in any of the first aspects.

[0017] This application provides an instruction dispatch method, apparatus, processor core, and computer device. The method includes: obtaining the instruction types of multiple instructions to be dispatched in the current cycle; determining, based on the instruction types of the multiple instructions to be dispatched, whether the multiple instructions to be dispatched include instructions of a first-level instruction type; if the multiple instructions to be dispatched include instructions of a first-level instruction type, dispatching the instructions of the first-level instruction type to a first issue queue; if the multiple instructions to be dispatched include instructions of a next-level instruction type, dispatching the instructions of the next-level instruction type to the corresponding issue queue according to the dispatch rules corresponding to the next-level instruction type, wherein the next-level instruction type includes instruction types that can be dispatched to one or more specified issue queues. This solution improves instruction dispatch efficiency by dividing instructions according to priority, prioritizing the allocation of high-priority instructions, and then dispatching low-priority instructions according to certain dispatch rules. Attached Figure Description

[0018] To more clearly illustrate the technical solutions of the embodiments of this application, the accompanying drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of this application and should not be regarded as a limitation of the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0019] Figure 1 A flowchart illustrating the instruction dispatch method provided in this application embodiment. Figure 1 ; Figure 2 A flowchart illustrating the instruction dispatch method provided in this application embodiment. Figure 2 ; Figure 3 A flowchart illustrating the instruction dispatch method provided in this application embodiment. Figure 3 ; Figure 4 A flowchart illustrating the instruction dispatch method provided in this application embodiment. Figure 4 ; Figure 5 A flowchart illustrating the instruction dispatch method provided in this application embodiment. Figure 5 ; Figure 6 A flowchart illustrating the instruction dispatch method provided in this application embodiment. Figure 6 ; Figure 7 This is a schematic diagram of the structure of the instruction dispatching device provided in the embodiments of this application; Figure 8 A schematic diagram of the structure of a computer device provided in an embodiment of this application. Detailed Implementation

[0020] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. The components of the embodiments of this application described and shown in the accompanying drawings can generally be arranged and designed in various different configurations. Therefore, the following detailed description of the embodiments of this application provided in the accompanying drawings is not intended to limit the scope of the claimed application, but merely represents selected embodiments of this application. All other embodiments obtained by those skilled in the art based on the embodiments of this application without inventive effort are within the scope of protection of this application.

[0021] To address the issue of low efficiency in current instruction dispatch methods for processor issue queues, this application improves instruction dispatch efficiency by dividing instructions according to priority, prioritizing the allocation of high-priority instructions, and then dispatching low-priority instructions according to certain dispatch rules.

[0022] Figure 1 A flowchart illustrating the instruction dispatch method provided in this application embodiment. Figure 1 In this embodiment, the execution entity can be a processor, such as a superscalar processor.

[0023] like Figure 1 As shown, the method may include: S101. Obtain the instruction types of multiple instructions to be dispatched within the current cycle.

[0024] In this embodiment of the application, the instruction may refer to the micro-operation instruction mop (Micro-Operation or Micro-Op), which is the processor decomposing complex instructions into smaller, lower-level micro-operations.

[0025] Among them, multiple pending instructions in the current cycle can be multiple instructions that are expected to be assigned to the launch queue in the current cycle.

[0026] The instruction type to be assigned may include an instruction type that can be assigned to only one specified launch queue, an instruction type that can be assigned to a specified type of launch queue, or an instruction type that can be assigned to multiple types of launch queues, wherein a type of launch queue may include at least two launch queues.

[0027] Taking a single-class launch queue (class A or class B) comprising two launch queues (A0 and A1, or B0 and B1), and multiple-class launch queues comprising two launch queues (class A and class B) as an example, Table 1 is a schematic table of instruction types. As shown in Table 1, there are 5 instruction types: Mop1, Mop2, Mop3, Mop4, and Mop5. Among them, Mop1 can only be assigned to A0, Mop2 can only be assigned to B0, Mop3 can be assigned to both A0 and A1, Mop4 can be assigned to both B0 and B1, and Mop5 can be assigned to A0, A1, B0, and B1.

[0028] In this embodiment of the application, Mop1 and Mop2 are denoted as A0_only and B0_only, Mop3 and Mop4 are denoted as A_any and B_any, and Mop5 is denoted as AB_any.

[0029] Table 1

[0030] S102. Based on the instruction types of multiple instructions to be dispatched, determine whether the multiple instructions to be dispatched include instructions of the first-level instruction type.

[0031] S103. If multiple instructions to be assigned include instructions of the first-level instruction type, then the instructions of the first-level instruction type shall be assigned to the first launch queue.

[0032] Determine whether the multiple pending instructions include instructions of the first-level instruction type. Instructions of the first-level instruction type are those that are only assigned to a specified launch queue. See Table 1. The first-level instruction type can be A0_only or B0_only.

[0033] If multiple instructions to be dispatched include instructions of the first-level instruction type, then the instructions of the first-level instruction type are dispatched to the first dispatch queue, where the first dispatch queue is the dispatch queue to which instructions of the first-level instruction type are dispatched only, for example, A0 or B0.

[0034] In some embodiments, each queue can only dispatch 2 instructions per cycle, and the upstream can provide the processor with a maximum of 6 instructions per cycle.

[0035] For example, if Class A launch queue includes A0 and A1, and Class B launch queue includes B0 and B1, then Class A launch queue and Class B launch queue can dispatch 4 instructions in one cycle.

[0036] Taking the first launch queue as A0 and the first level instruction type as Mop1 as an example, Table 2 is a schematic table of Mop1 assignment. As shown in Table 2, Mop1_num is the number of instructions for Mop1, and St1_A0_remain is the remaining item of A0.

[0037] Table 2

[0038] As shown in Table 2, if Mop1_num is 0, it means that there is no Mop1 instruction in the current cycle, and the remaining term of A0 is 2, that is, no position is reserved for Mop1. If Mop1_num is 1, it means that there is 1 Mop1 instruction in the current cycle, and the remaining term of A0 is 1, that is, 1 position is reserved for Mop1. If Mop1_num is 2, it means that there are 2 Mop1 instructions in the current cycle, and the remaining term of A0 is 0, that is, 2 positions are reserved for Mop1.

[0039] Taking the first launch queue as B0 and the first-level instruction type as Mop2 as an example, Table 3 is a schematic table of Mop2 assignment. As shown in Table 3, Mop2_num is the number of instructions for Mop2, and St1_B0_remain is the remaining item of B0.

[0040] Table 3

[0041] As shown in Table 2, if Mop2_num is 0, it means that there is no Mop2 instruction in the current cycle, and the remaining number of B0 is 2, that is, no position is reserved for Mop2. If Mop2_num is 1, it means that there is 1 Mop2 instruction in the current cycle, and the remaining number of B0 is 1, that is, 1 position is reserved for Mop2. If Mop2_num is 2, it means that there are 2 Mop2 instructions in the current cycle, and the remaining number of B0 is 0, that is, 2 positions are reserved for Mop2.

[0042] S104. If multiple instructions to be dispatched include instructions of the next-level instruction type, dispatch the instructions of the next-level instruction type to the corresponding launch queue according to the dispatch rules corresponding to the next-level instruction type.

[0043] Determine whether the multiple pending instructions include a next-level instruction type, wherein the next-level instruction type includes instruction types that can be assigned to a specified type of launch queue (including the first launch queue) or multiple types of launch queues (including the specified type of launch queue).

[0044] The next level of instruction types includes the next level of instruction types after the first level (i.e., the second level instruction type) and the next level of instruction types after the second level (i.e., the third level instruction type). Among them, the second level instruction type is the instruction type that can be assigned to a specified type of launch queue, and the third level instruction type is the instruction type that can be assigned to multiple specified types of launch queues.

[0045] Referring to Table 1, the second-level instruction type can be A_any or B_any, and the third-level instruction type can be AB_any.

[0046] After the first-level instruction type is assigned, if the multiple instructions to be assigned include instructions of the second-level instruction type, then according to the assignment rules corresponding to the second-level instruction type, the corresponding transmission queue for the second-level instruction type is determined from each transmission queue, and the instructions of the second-level instruction type are assigned to the corresponding transmission queue.

[0047] After the second-level instruction type is assigned, if the multiple instructions to be assigned include instructions of the third-level instruction type, then according to the assignment rules corresponding to the third-level instruction type, the corresponding transmission queue for the instruction of the third-level instruction type is determined from each transmission queue, and the instruction of the third-level instruction type is assigned to the corresponding transmission queue.

[0048] In this embodiment, instructions are prioritized, with the first-level instruction type having the highest priority. Priority is given to reserving space for the first-level instruction type to ensure that the first-level instruction type can be dispatched. Then, instructions of the next-level instruction type are dispatched according to certain rules, thereby improving dispatch efficiency.

[0049] In an optional implementation, step S104 above, if the multiple instructions to be dispatched include instructions of a lower-level instruction type, dispatching the instructions of the lower-level instruction type to the corresponding launch queue according to the dispatch rules corresponding to the lower-level instruction type, may include: Based on the dispatch rules corresponding to the next level instruction type and the current occupancy status of each launch queue, the instructions of the next level instruction type are dispatched to the corresponding launch queue, and so on, until all the instructions to be dispatched have been dispatched.

[0050] Each launch queue includes a first launch queue. The current occupancy status of each launch queue is obtained. The current occupancy status of each launch queue is used to indicate the current number of instructions occupied by each launch queue, that is, the number of instructions currently available in each launch queue.

[0051] The next level of instruction types includes second-level instruction types and third-level instruction types. Second-level instruction types are those that can be assigned to a single type of launch queue, while third-level instruction types are those that can be assigned to multiple types of launch queues.

[0052] Based on the dispatch rules corresponding to the second-level instruction type and the current occupancy status of each launch queue, the launch queue corresponding to the second-level instruction type is determined from each launch queue, and the second-level instruction type is dispatched to the corresponding launch queue.

[0053] After the second-level instruction type is dispatched, if the multiple pending instructions include third-level instruction type instructions, the current occupancy status of each launch queue is retrieved again. Based on the dispatch rules corresponding to the third-level instruction type and the current occupancy status of each launch queue is retrieved again, the launch queue corresponding to the third-level instruction type instruction is determined from each launch queue, and the third-level instruction type instruction is dispatched to the corresponding launch queue. At this point, the multiple pending instructions are dispatched, and the number of instructions in each launch queue remains balanced after the dispatch is completed.

[0054] In this embodiment, a polling algorithm based on reserved items is adopted. During the dispatching process, the instructions are divided into priorities. According to the priority, priority is given to high-priority instructions (instructions of the first-level instruction type) to ensure that they can be dispatched. Then, low-priority instructions (instructions of the next-level instruction type) and the current occupancy status of each launch queue are dispatched according to certain rules. This improves dispatching efficiency while ensuring balance.

[0055] One type of launch queue includes at least a first launch queue and a second launch queue. For example, if the launch queue is of type A, then the first launch queue is A0 and the second launch queue is A1; or, if the launch queue is of type B, then the first launch queue is B0 and the second launch queue is B1.

[0056] Figure 2 A flowchart illustrating the instruction dispatch method provided in this application embodiment. Figure 2 ,like Figure 2 As shown, in an optional implementation, the instruction of the next-level instruction type is assigned to the corresponding launch queue according to the dispatch rule corresponding to the next-level instruction type and the current occupancy status of each launch queue, including: S201. If multiple instructions to be dispatched include instructions of the second-level instruction type, then the remaining instruction dispatch quantity of the first launch queue is obtained based on the preset number of dispatched instructions in the first launch queue in the current period and the current instruction occupancy quantity of the first launch queue.

[0057] The next level instruction type is the second level instruction type, which is an instruction type that can be assigned to a specified type of launch queue. The preset number of assignment instructions for the first launch queue in the current cycle is the maximum number of assignment instructions for the first launch queue in one cycle, for example, 2.

[0058] The current instruction occupancy count of the first launch queue refers to the number of instructions currently in the first launch queue. This count includes the number of instructions of the first-level instruction type. The current instruction occupancy count of the first launch queue can be determined based on the assignment results of the first-level instruction types.

[0059] If multiple pending instructions include instructions of the second-level instruction type, the difference between the preset number of dispatched instructions in the first launch queue and the current number of instructions occupied in the first launch queue in the current period is calculated as the remaining number of dispatched instructions in the first launch queue. The remaining number of dispatched instructions is used to indicate the number of instructions that the first launch queue can still dispatch after dispatching instructions of the first-level instruction type to the first launch queue in the current period, which is St1_A0_remain and St1_B0_remain in Tables 2 and 3.

[0060] S202. Based on the remaining number of instructions to be assigned in the first launch queue, determine the first queue to be assigned from the first launch queue and the second launch queue.

[0061] The first queue to be assigned is either the first launch queue or the second launch queue.

[0062] In an optional implementation, step S202, which involves determining a first dispatch queue from the first and second launch queues based on the remaining number of instruction dispatches in the first launch queue, includes: If the number of remaining instruction assignments in the first launch queue is 0, then the second launch queue is determined to be the first queue to be assigned. If the number of remaining dispatched instructions in the first launch queue is greater than 0 and less than the preset number of dispatched instructions, then according to the preset polling rules between the first launch queue and the second launch queue, the launch queue currently polled is determined as the first queue to be dispatched.

[0063] If the remaining number of instructions to be dispatched in the first launch queue is 0, it means that the number of instructions of the first level instruction type in the current cycle has reached the preset number of dispatched instructions. Taking the A-type launch queue as an example, if there are 2 A0_only instructions in the current cycle, then it is impossible to dispatch instructions to the first launch queue. Therefore, the second launch queue is determined to be the first queue to be dispatched.

[0064] If the number of remaining instructions to be dispatched in the first launch queue is greater than 0 and less than the preset number of dispatched instructions, taking the Class A launch queue as an example, the number of remaining instructions to be dispatched in the first launch queue is 1, there are 2 A0_only instructions in the current cycle, and instructions can still be dispatched to the first launch queue. Then, according to the preset polling rules between the first launch queue and the second launch queue, polling is performed in the first launch queue and the second launch queue, and the launch queue currently polled is determined as the first queue to be dispatched.

[0065] Taking a Class A transmission queue as an example, the preset polling rule can be, for example, A1->A0->A1. The polling rule can be flexibly set according to the actual situation, and this embodiment does not impose any special limitations on it.

[0066] In some embodiments, the number of instructions of the second-level instruction type includes, but is not limited to, one. In this case, the first dispatch queue corresponding to each second-level instruction type can be determined from the first and second dispatch queues according to the preset polling order between the first and second dispatch queues.

[0067] S203. Assign instructions of the second-level instruction type to the first queue to be assigned.

[0068] The first queue to be dispatched is used as the dispatch queue for instructions of the second-level instruction type, so that instructions of the second-level instruction type can be dispatched to the first queue to be dispatched.

[0069] Figure 3 A flowchart illustrating the instruction dispatch method provided in this application embodiment. Figure 3 ,like Figure 3As shown, in an optional implementation, step S202, determining the first dispatch queue from the first and second launch queues based on the remaining instruction dispatch quantity in the first launch queue, may include: S301. If the remaining number of instructions to be dispatched in the first launch queue is equal to the preset number of dispatched instructions, then the difference between the number of instructions occupied in the first launch queue and the number of instructions occupied in the second launch queue is obtained based on the current number of instructions occupied in the first launch queue and the current number of instructions occupied in the second launch queue.

[0070] The current instruction occupancy count of the first launch queue refers to the number of instructions currently in the first launch queue, and the current instruction occupancy count of the second launch queue refers to the number of instructions currently in the second launch queue.

[0071] If the remaining number of instructions to be dispatched in the first launch queue is equal to the preset number of dispatched instructions, it means that there are no instructions of the first level instruction type in the current period. Taking the A-class launch queue as an example, there are no instructions of A0_only in the current period. Then, the difference between the current number of instructions occupied in the first launch queue and the current number of instructions occupied in the second launch queue is calculated as the difference between the number of instructions occupied in the first launch queue and the second launch queue, which is represented as A0-A1.

[0072] S302. Based on the difference between the remaining number of instructions to be assigned and the number of instructions occupied in the first launch queue, determine the first queue to be assigned from the first launch queue and the second launch queue.

[0073] The remaining number of instructions to be assigned in the first launch queue and the difference in the number of instructions occupied are used as a reference for balancing the number of queues. A preset matching rule is used to determine the first queue to be assigned from the first launch queue and the second launch queue, so that instructions of the second level instruction type can be assigned to the first queue to be assigned, and the number of launch queues is balanced after assignment.

[0074] For example, if the preset number of dispatched instructions is 2, the remaining number of dispatched instructions in the first launch queue is 2, the difference in the number of instructions occupied is 0, and the number of instructions of the second-level instruction type is 1, it means that the number of instructions already in the first launch queue and the second launch queue is the same. However, since the number of remaining dispatched instructions in the first launch queue is large, the first launch queue can be used as the first queue to be dispatched.

[0075] In some embodiments, the number of instructions of the second-level instruction type includes, but is not limited to, one. In this case, the first dispatch queue corresponding to each instruction of the second-level instruction type can be determined from the first and second launch queues by using a preset matching rule based on the difference between the remaining instruction dispatch quantity and the instruction occupancy quantity in the first launch queue.

[0076] For example, if the preset number of dispatched instructions is 2, the remaining number of dispatched instructions in the first launch queue is 2, the difference in the number of instructions occupied is 1, and the number of instructions of the second-level instruction type is 2, it means that the number of existing instructions in the first launch queue is 1 more than that in the second launch queue. However, since the number of remaining dispatched instructions in the first launch queue is larger, the first launch queue can be used as the first queue to be dispatched for instructions of the second-level instruction type, and the second launch queue can be used as the first queue to be dispatched for instructions of another second-level instruction type.

[0077] In an optional implementation, step S302 above, determining the first dispatch queue from the first and second launch queues based on the difference between the remaining instruction dispatch quantity and the instruction occupancy quantity in the first launch queue, may include: Get the first dispatch result of the previous cycle. The first dispatch result is used to indicate the launch queue to which the last second-level instruction type instruction of the previous cycle was dispatched. Based on the remaining number of instructions to be assigned in the first launch queue, the difference in the number of instructions occupied, and the first assignment result, the first queue to be assigned is determined from the first launch queue and the second launch queue.

[0078] The previous cycle refers to the cycle preceding the current cycle. The first dispatch result is used to indicate the launch queue assigned to the last second-level instruction type instruction of the previous cycle, such as A0 or A1.

[0079] Based on the remaining number of instructions to be assigned in the first launch queue, the difference in the number of instructions occupied, and the first assignment result, the first queue to be assigned is determined from the first launch queue and the second launch queue.

[0080] To further ensure the balance of the number of queues, the remaining number of instructions to be assigned in the first launch queue, the difference in the number of instructions occupied, and the first assignment result can be used as a reference for the balance of the number of queues. A preset matching rule is adopted to determine the first queue to be assigned from the first launch queue and the second launch queue, so that the instructions of the second level instruction type can be assigned to the first queue to be assigned, and the number of launch queues is balanced after assignment.

[0081] Taking the second-level instruction type Mop3 as an example, Table 4 is a dispatch diagram of Mop3. As shown in Table 4, Mop3_num is the number of Mop3 instructions, St1_A0_remain is the remaining item of A0 (the remaining number of dispatched instructions), Last_mop is the first dispatch result of the previous cycle, resolve is the dispatch result of the second-level instruction type, St2_A0_remain is the remaining item of A0 after the dispatch of the second-level instruction type, and St2_A1_remain is the remaining item of A1 after the dispatch of the second-level instruction type.

[0082] Table 4

[0083] As shown in Table 4, when Mop3_num is 1 and St1_A0_remain is 0 or 1, the first dispatch result Last_mop and the instruction occupancy difference A0-A1 are not considered. When St1_A0_remain is 0, the first queue to be dispatched is A1, then St2_A0_remain is 0 and St2_A1_remain is 1; when St1_A0_remain is 1, the first queue to be dispatched is A1, then St2_A0_remain is 1 and St2_A1_remain is 1; when St1_A0_remain is 2, Last_mop is A0, and A0-A1 is 1, the first queue to be dispatched is A1, St2_A0_remain is 2 and St2_A1_remain is 1; when St1_A0_remain is 2, Last_mop is A1, and A0-A1 is 1, the first queue to be dispatched is A1, and St2_A0_remain is 1. When St2_A1_remain is 1 and St2_A0_remain is 2, Last_mop is A0 and A0-A1 is 0, the first queue to be dispatched is A1, St2_A0_remain is 2 and St2_A1_remain is 1; when St2_A0_remain is 2, Last_mop is A1 and A0-A1 is 0, the first queue to be dispatched is A0, St2_A0_remain is 1 and St2_A1_remain is 2.

[0084] When Mop3_num is 2 and St1_A0_remain is 0 or 1, the first dispatch result Last_mop and the instruction usage difference A0-A1 are not considered. When St1_A0_remain is 0, the first dispatch queue is A1 and A1 (dispatching the two Mop3_num instructions to A1), then St2_A0_remain is 0 and St2_A1_remain is 0; when St1_A0_remain is 1, the first dispatch queue is A1 and A0 (dispatching the two Mop3_num instructions to A0 and A1 respectively), then St2_A0_remain is 0 and St2_A1_remain is 1; when St1_A0_remain is 2, Last_mop is A0, and A0-A1 is 1, the first dispatch queue is A0 and A1 (dispatching the two Mop3_num instructions to A0 and A1 respectively), then St2_A0_remain is 1 and St2_A1_remain is 1. The same logic applies to the others. It should be noted that A1->A0->A1 means that the three Mop3_num instructions are assigned to A1, A0, and A1 respectively, and A1->A0->A1->A0 means that the four Mop3_num instructions are assigned to A1, A0, A1, and A0 respectively.

[0085] Each of the multiple types of launch queues includes at least a first launch queue and a second launch queue. For example, the multiple types of launch queues include launch queue A and launch queue B. For launch queue A, the first launch queue is A0 and the second launch queue is A1. For launch queue B, the first launch queue is B0 and the second launch queue is B1.

[0086] Figure 4 A flowchart illustrating the instruction dispatch method provided in this application embodiment. Figure 4 ,like Figure 4 As shown, in an optional implementation, step S104 above, which assigns instructions of the next-level instruction type to the corresponding launch queue according to the dispatch rules corresponding to the next-level instruction type and the current occupancy status of each launch queue, may include: S401. If multiple instructions to be dispatched include instructions of the third-level instruction type, obtain the remaining instruction dispatch quantity for each transmission queue based on the current instruction occupancy quantity of each transmission queue and the preset dispatch instruction quantity of each transmission queue in the current period.

[0087] The next level instruction type is the third level instruction type, which is an instruction type that can be assigned to multiple types of launch queues.

[0088] After allocating instructions of the first-level instruction type and instructions of the second-level instruction type, obtain the current instruction occupancy count of each launch queue. The current instruction occupancy count refers to the number of instructions currently available in each launch queue after allocating instructions of the first-level instruction type and instructions of the second-level instruction type.

[0089] The difference between the preset number of dispatched instructions and the current number of instructions occupied by each launch queue is calculated as the remaining number of dispatched instructions for each launch queue. The remaining number of dispatched instructions here is used to indicate the number of instructions that each launch queue can still dispatch after dispatching the first-level instruction type and the second-level instruction type instructions in the current cycle, such as St2_A0_remain and St2_A1_remain in Table 4.

[0090] S402. Using a preset balanced dispatch algorithm, the second dispatch queue is determined from all dispatch queues based on the number of remaining instructions to be dispatched in each dispatch queue.

[0091] The number of instructions of the third-level instruction type includes, but is not limited to, one. A preset balanced dispatch algorithm is used to indicate the queue polling order of instructions of the third-level instruction type. For example, the first instruction of the third-level instruction type is polled to A0, the second instruction of the third-level instruction type is polled to A1, the third instruction of the third-level instruction type is polled to B0, the fourth instruction of the third-level instruction type is polled to B1, the fifth instruction of the third-level instruction type is polled to A0, and so on. The queue polling order is A0, A1, B0, B1, A0...

[0092] A pre-defined balanced dispatch algorithm is used to determine the issue queue to which the third-level instruction type is polled. If the remaining number of dispatchable instructions in the issue queue is not zero, then the issue queue is determined as the second queue to be dispatched. If the remaining number of dispatchable instructions in the issue queue is zero, then the next issue queue to be dispatched is determined as the second queue to be dispatched based on the polling order. For example, if the first third-level instruction type is polled to A0, but the remaining number of dispatchable instructions in A0 is zero, then A1 is determined as the second queue to be dispatched corresponding to the first third-level instruction type. The second queues to be dispatched corresponding to the second and third third-level instruction types are shifted to B0 and B1 respectively.

[0093] S403: Dispatch the instruction of the third-level instruction type to the second dispatch queue.

[0094] The second queue to be dispatched is used as the dispatch queue for instructions of the third-level instruction type, so that instructions of the third-level instruction type can be dispatched to the second queue to be dispatched.

[0095] Figure 5A flowchart illustrating the instruction dispatch method provided in this application embodiment. Figure 5 ,like Figure 5 As shown, in an optional implementation, step S402 above, which employs a preset balanced allocation algorithm to determine the second allocation queue from all launch queues based on the remaining instruction allocation quantity of each launch queue, may include: S501. A preset balanced allocation algorithm is adopted to determine the preset polling rules among all launch queues based on the second allocation result of the previous cycle.

[0096] The second dispatch result is used to indicate the launch queue to which the last instruction of the third-level instruction type in the previous cycle was dispatched.

[0097] The second allocation result corresponds to the preset polling rules between all launch queues. Table 5 is a schematic table of the allocation rules of the equalization algorithm. As shown in Table 5, Last_mop is the second allocation result, 1st is the first instruction of the third level instruction type, 2nd is the second instruction of the third level instruction type, 3rd is the third instruction of the third level instruction type, 4th is the fourth instruction of the third level instruction type, 5th is the fifth instruction of the third level instruction type, and 6th is the sixth instruction of the third level instruction type.

[0098] Table 5

[0099] As shown in Table 5, when Last_mop is B0, the default polling rule is B1->A0->A1->B0->B1->A0, which means that the first to sixth third-level instruction types are assigned to B1, A0, A1, B0, B1, and A0 respectively.

[0100] S502. Based on the preset polling rules among all launch queues and the remaining instruction allocation quantity of each launch queue, determine the second allocation queue from all launch queues.

[0101] Table 6 is a schematic table of the remaining instruction assignments in the launch queue. As shown in Table 6, ST2_A0_remain, ST2_A1_remain, ST2_B0_remain, and ST2_B1_remain represent the remaining instruction assignments for A0, A1, B0, and B1, respectively.

[0102] Table 6

[0103] Based on the preset polling rules among all launch queues, the launch queue corresponding to the instruction of the third-level instruction type is determined. If the remaining number of instruction assignments in the launch queue is not 0, then the launch queue is the second queue to be assigned for the instruction of the third-level instruction type. If the remaining number of instruction assignments in the launch queue is 0, then the next launch queue of the launch queue is the second queue to be assigned. The second queues to be assigned for the instructions of other third-level instruction types are moved to the next queue in turn.

[0104] For example, if there are 4 instructions of the third-level instruction type, i.e., 4 Mop5 instructions, and last_mop is B0, then the default polling rule is B1->A0->A1->B0->B1->A0. The first Mop5 instruction should be assigned to B1 according to the default polling rule. At this time, the remaining amount of ST2_B1_remain is 2, so it can be assigned to B1. The second Mop5 instruction should be assigned to A0 according to the default polling rule. At this time, ST2_A0_remain has no remaining amount. So, following the order B1->A0->A1->B0->B1->A0, A0 is skipped, so the second Mop5 instruction is assigned to A1. The third Mop5 instruction is assigned to B0. Since ST2_B1_remain has 2 remaining amount, and only the first Mop5 instruction was assigned to B1 previously, there is one remaining. Therefore, the fourth Mop5 instruction is assigned to B1. The final actual assignment result is: B1->A1->B0->B1.

[0105] In this embodiment, for instructions of the third-level instruction type, the equalization algorithm is used to allocate instructions of the third-level instruction type according to the remaining number of instructions allocated to each transmission queue. This allocation of instructions improves allocation efficiency while ensuring balance.

[0106] Figure 6 A flowchart illustrating the instruction dispatch method provided in this application embodiment. Figure 6 ,like Figure 6 As shown, in an optional implementation, the method may further include: S601. Based on the current occupancy status of each launch queue, determine whether there is a target launch queue in each launch queue.

[0107] S602. If a target launch queue exists, set the remaining instruction dispatch quantity of the target launch queue to 0.

[0108] The current occupancy status of each launch queue is used to indicate the current number of commands occupied by each launch queue.

[0109] The current number of instructions occupied by the target launch queue and the current number of instructions occupied by other launch queues in each launch queue meet the preset number distribution conditions. Among them, other launch queues are launch queues other than the target launch queue in each launch queue. The preset number distribution conditions may include, for example, the difference between the current number of instructions occupied by the target launch queue and the current number of instructions occupied by other launch queues exceeds a preset number, such as 4, which means that the target launch queue has 4 more instructions than the other launch queues.

[0110] If a target launch queue exists, the remaining instruction allocation quantity of the target launch queue is set to 0. In other words, if the target launch queue already has a large number of instructions and the distribution of instructions between the target launch queue and other launch queues is unbalanced, the bias algorithm is used to force the remaining instruction allocation quantity of the target launch queue to be set to 0, thereby achieving the purpose of not allocating instructions to the target launch queue.

[0111] Table 7 is a schematic table of the remaining command assignments for each launch queue. As shown in Table 7, Bias_not_A represents the bias of launch queue A, Bias_not_A0 represents the bias of A0, Bias_not_A1 represents the bias of A1, Bias_not_B0 represents the bias of B0, Bias_not_B1 represents the bias of B1, St2_A0_remain represents the remaining command assignments for A0, St2_A1_remain represents the remaining command assignments for A1, St2_B0_remain represents the remaining command assignments for B0, and St2_B1_remain represents the remaining command assignments for B1.

[0112] Table 7

[0113] As shown in Table 7, assuming that A0 currently occupies the most instructions and exceeds the other queues by 4, then Bias_not_A0 is effective, and St2_A0_remain is forcibly set to 0. The remaining instruction dispatch quantity of the other emit queues is 2. Assuming Last_mop is B1, the default polling rule is A0->A1->B0->B1->A0->A1. However, since St2_A0_remain is forcibly set to 0, the polling order at this time is A1->B0->B1->A1->A0->A0.

[0114] In this embodiment, when the distribution of the launch queues is uneven, an equalization algorithm is used to force the values ​​to be 0 in order to ensure that the distribution of each launch queue is balanced.

[0115] Figure 7 This is a schematic diagram of the instruction dispatch device provided in an embodiment of this application. The device can be integrated into a processor.

[0116] like Figure 7 As shown, the device may include: The acquisition module 701 is used to acquire the instruction types of multiple instructions to be dispatched within the current cycle; The determination module 702 is used to determine whether the multiple instructions to be assigned include instructions of the first-level instruction type based on the instruction type of the multiple instructions to be assigned. Instructions of the first-level instruction type are instructions that are only assigned to a specified launch queue. The dispatch module 703 is used to dispatch instructions of the first level instruction type to the first launch queue if there are instructions of the first level instruction type among multiple instructions to be dispatched. The dispatch module 703 is also used to dispatch instructions of the next level instruction type to the corresponding dispatch queue according to the dispatch rules corresponding to the next level instruction type and the current occupancy status of each dispatch queue, and so on, until multiple instructions to be dispatched are dispatched. The current occupancy status of each dispatch queue is used to indicate the current number of instructions occupied by each dispatch queue.

[0117] In an optional implementation, the dispatch module 703 is specifically used for: Based on the dispatch rules corresponding to the next level instruction type and the current occupancy status of each launch queue, the instructions of the next level instruction type are dispatched to the corresponding launch queues, and so on, until multiple instructions to be dispatched are dispatched. The current occupancy status of each launch queue is used to indicate the number of instructions currently occupied in each launch queue.

[0118] In an optional implementation, a type of launch queue includes at least: a first launch queue and a second launch queue; the dispatch module 703 is specifically used for: If multiple pending instructions include instructions of the second-level instruction type, then the remaining instruction allocation quantity of the first launch queue is obtained based on the preset allocation quantity of the first launch queue in the current period and the current instruction occupancy quantity of the first launch queue. Based on the remaining number of instructions to be assigned in the first launch queue, determine the first queue to be assigned from the first launch queue and the second launch queue; Dispatch instructions of the second-level instruction type to the first dispatch queue.

[0119] In an optional implementation, the dispatch module 703 is specifically used for: If the number of remaining instruction assignments in the first launch queue is 0, then the second launch queue is determined to be the first queue to be assigned. If the number of remaining dispatched instructions in the first launch queue is greater than 0 and less than the preset number of dispatched instructions, then according to the preset polling rules between the first launch queue and the second launch queue, the launch queue currently polled is determined as the first queue to be dispatched.

[0120] In an optional implementation, the dispatch module 703 is specifically used for: If the remaining number of instructions to be dispatched in the first launch queue is equal to the preset number of dispatched instructions, then the difference between the number of instructions occupied in the first launch queue and the number of instructions occupied in the second launch queue is obtained based on the current number of instructions occupied in the first launch queue and the current number of instructions occupied in the second launch queue. Based on the difference between the remaining number of instructions to be dispatched and the number of instructions occupied in the first launch queue, the first queue to be dispatched is determined from the first launch queue and the second launch queue.

[0121] In an optional implementation, the dispatch module 703 is specifically used for: Get the first dispatch result of the previous cycle. The first dispatch result is used to indicate the launch queue to which the last second-level instruction type instruction of the previous cycle was dispatched. Based on the remaining number of instructions to be assigned in the first launch queue, the difference in the number of instructions occupied, and the first assignment result, the first queue to be assigned is determined from the first launch queue and the second launch queue.

[0122] In an optional implementation, each type of launch queue in the multiple launch queues includes at least a first launch queue and a second launch queue; the dispatch module 703 is specifically used for: If multiple pending instructions include instructions of the third-level instruction type, the remaining instruction allocation quantity of each launch queue is obtained based on the current instruction occupancy quantity of each launch queue and the preset allocation quantity of each launch queue in the current period. A preset balanced allocation algorithm is adopted to determine the second allocation queue from all launch queues based on the number of remaining instructions allocated to each launch queue. Dispatch instructions of the third-level instruction type to the second dispatch queue.

[0123] In an optional implementation, the dispatch module 703 is specifically used for: A preset balanced allocation algorithm is adopted. Based on the second allocation result of the previous cycle, the preset polling rules among all launch queues are determined. The second allocation result is used to indicate the launch queue to which the last third-level instruction type instruction of the previous cycle is allocated. Based on the preset polling rules among all launch queues and the remaining number of instructions to be dispatched in each launch queue, the second queue to be dispatched is determined from all launch queues.

[0124] In an optional embodiment, the device further includes: The judgment module 704 is used to determine whether there is a target launch queue in each launch queue based on the current occupancy status of each launch queue. The current occupancy status of each launch queue is used to indicate the current number of instructions occupied in each launch queue. The current number of instructions occupied in the target launch queue and the current number of instructions occupied in other launch queues in each launch queue meet a preset quantity distribution condition. The setting module 705 is used to set the remaining instruction dispatch quantity of the target launch queue to 0 if a target launch queue exists.

[0125] The processing flow of each module in the device and the interaction flow between each module can be referred to the relevant descriptions in the above method embodiments, and will not be detailed here.

[0126] This application also provides a processor core, which is integrated into the processor described above and is used to execute the methods described above.

[0127] Figure 8 A schematic diagram of the structure of the computer device provided in the embodiments of this application, such as... Figure 8 As shown, the computer device may include a processor 801, a memory 802, and a bus 803. The memory 802 stores machine-readable instructions that can be executed by the processor 801. When the computer device is running, the processor 801 communicates with the memory 802 through the bus 803, and the processor 801 executes the machine-readable instructions to perform the above-described method embodiments.

[0128] The processor 801 includes one or more processor cores.

[0129] In the embodiments provided in this application, it should be understood that the disclosed apparatus and methods can be implemented in other ways. The apparatus embodiments described above are merely illustrative. For example, the division of units is only a logical functional division, and in actual implementation, there may be other division methods. Furthermore, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Additionally, the displayed or discussed mutual couplings, direct couplings, or communication connections may be through some communication interfaces; indirect couplings or communication connections between devices or units may be electrical, mechanical, or other forms.

[0130] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0131] In addition, the functional units in the embodiments provided in this application can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit.

[0132] If the aforementioned functions are implemented as software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or a portion of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0133] It should be noted that similar labels and letters in the following figures indicate similar items. Therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures. In addition, the terms "first", "second", "third", etc. are used only to distinguish descriptions and should not be construed as indicating or implying relative importance.

[0134] Finally, it should be noted that the above-described embodiments are merely specific implementations of this application, used to illustrate the technical solutions of this application, and not to limit them. The protection scope of this application is not limited thereto. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that any person skilled in the art can still modify or easily conceive of changes to the technical solutions described in the foregoing embodiments, or make equivalent substitutions for some of the technical features, within the scope of the technology disclosed in this application; and these modifications, changes, or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application. All should be covered within the protection scope of this application. Therefore, the protection scope of this application should be determined by the protection scope of the claims.

Claims

1. An instruction dispatch method, characterized in that, include: Get the instruction types of multiple pending instructions within the current cycle; Based on the instruction type of the plurality of instructions to be assigned, determine whether the plurality of instructions to be assigned include instructions of the first-level instruction type, wherein instructions of the first-level instruction type are instructions that are assigned only to a specified launch queue; If the plurality of instructions to be assigned includes instructions of the first level instruction type, then the instructions of the first level instruction type are assigned to the first launch queue. After the first-level instruction type is dispatched, if the plurality of instructions to be dispatched includes instructions of the next-level instruction type, the instructions of the next-level instruction type are dispatched to the corresponding launch queue according to the dispatch rules corresponding to the next-level instruction type. The next-level instruction type includes instruction types that can be dispatched to one or more designated launch queues. If the plurality of instructions to be dispatched includes instructions of the second-level instruction type, the instructions of the second-level instruction type are dispatched to the designated launch queue according to the dispatch rules corresponding to the second-level instruction type. After the second-level instruction type is dispatched, if the plurality of instructions to be dispatched includes instructions of the third-level instruction type, the instructions of the third-level instruction type are dispatched to the designated launch queues according to the dispatch rules corresponding to the third-level instruction type. If the plurality of instructions to be dispatched includes instructions of a lower-level instruction type, the instructions of the lower-level instruction type are dispatched to the corresponding launch queue according to the dispatch rules corresponding to the lower-level instruction type, including: According to the dispatch rules corresponding to the next level instruction type and the current occupancy status of each launch queue, the instruction of the next level instruction type is dispatched to the corresponding launch queue, and so on, until all the multiple instructions to be dispatched are dispatched. The current occupancy status of each launch queue is used to indicate the current number of instructions occupied by each launch queue.

2. The method according to claim 1, characterized in that, The type of launch queue includes at least: a first launch queue and a second launch queue; the step of assigning the instruction of the next-level instruction type to the corresponding launch queue according to the dispatch rule corresponding to the next-level instruction type and the current occupancy status of each launch queue includes: If the plurality of instructions to be dispatched include instructions of the second-level instruction type, then the remaining instruction dispatch quantity of the first launch queue is obtained according to the preset number of dispatched instructions in the first launch queue in the current period and the current number of instructions occupied in the first launch queue. Based on the remaining number of instructions to be dispatched in the first launch queue, a first dispatch queue is determined from the first launch queue and the second launch queue; Dispatch instructions of the second-level instruction type to the first dispatch queue.

3. The method according to claim 2, characterized in that, The step of determining the first dispatch queue from the first and second launch queues based on the remaining instruction dispatch quantity of the first launch queue includes: If the number of remaining instruction assignments in the first transmission queue is 0, then the second transmission queue is determined to be the first queue to be assigned. If the number of remaining dispatched instructions in the first launch queue is greater than 0 and less than the preset number of dispatched instructions, then according to the preset polling rules between the first launch queue and the second launch queue, the launch queue currently polled is determined as the first dispatch queue.

4. The method according to claim 2, characterized in that, The step of determining the first dispatch queue from the first and second launch queues based on the remaining instruction dispatch quantity of the first launch queue includes: If the remaining number of instructions to be dispatched in the first launch queue is equal to the preset number of dispatched instructions, then the difference between the number of instructions occupied in the first launch queue and the number of instructions occupied in the second launch queue is obtained based on the current number of instructions occupied in the first launch queue and the current number of instructions occupied in the second launch queue. The first dispatch queue is determined from the first and second launch queues based on the difference between the remaining number of dispatched instructions in the first launch queue and the number of instructions occupied.

5. The method according to claim 4, characterized in that, The step of determining the first dispatch queue from the first and second launch queues based on the difference between the remaining dispatch quantity and the number of instructions occupied in the first launch queue includes: Obtain the first assignment result of the previous cycle, the first assignment result being used to indicate the launch queue assigned to the last second-level instruction type instruction of the previous cycle; The first queue to be assigned is determined from the first and second launch queues based on the remaining number of instructions to be assigned in the first launch queue, the difference in the number of instructions occupied, and the first assignment result.

6. The method according to claim 1, characterized in that, Each of the multiple types of launch queues includes at least the first launch queue and the second launch queue; The step of assigning instructions of the next-level instruction type to the corresponding launch queue according to the dispatch rules corresponding to the next-level instruction type and the current occupancy status of each launch queue includes: If the plurality of instructions to be dispatched include instructions of the third-level instruction type, the remaining instruction dispatch quantity of each transmission queue is obtained according to the current instruction occupancy quantity of each transmission queue and the preset dispatch instruction quantity of each transmission queue in the current period. A preset balanced allocation algorithm is adopted to determine the second allocation queue from all the launch queues based on the number of remaining instructions allocated to each launch queue. The instructions of the third-level instruction type are assigned to the second assignment queue.

7. The method according to claim 6, characterized in that, The method employs a preset balanced allocation algorithm to determine the second allocation queue from all launch queues based on the remaining instruction allocation quantity of each launch queue, including: Using the preset balanced allocation algorithm, a preset polling rule is determined among all launch queues based on the second allocation result of the previous cycle. The second allocation result is used to indicate the launch queue assigned to the last instruction of the third-level instruction type in the previous cycle. Based on the preset polling rules among all the launch queues and the remaining instruction allocation quantity of each launch queue, the second allocation queue is determined from all the launch queues.

8. The method according to any one of claims 1-7, characterized in that, The method further includes: Based on the current occupancy status of each launch queue, it is determined whether there is a target launch queue in each launch queue. The current occupancy status of each launch queue is used to indicate the current number of instructions occupied by each launch queue. The current number of instructions occupied by the target launch queue and the current number of instructions occupied by other launch queues in each launch queue satisfy a preset number distribution condition. If the target launch queue exists, the remaining instruction dispatch quantity of the target launch queue is set to 0.

9. An instruction dispatching device, characterized in that, include: The acquisition module is used to acquire the instruction types of multiple instructions to be dispatched within the current cycle; The determining module is used to determine whether the plurality of instructions to be assigned include instructions of the first-level instruction type based on the instruction type of the plurality of instructions to be assigned. The instructions of the first-level instruction type are instructions that are only assigned to a specified launch queue. The dispatch module is used to dispatch instructions of the first level instruction type to the first launch queue if the plurality of instructions to be dispatched include instructions of the first level instruction type. The dispatch module is further configured to, after the dispatch of instructions of the first-level instruction type is completed, if the plurality of instructions to be dispatched include instructions of the next-level instruction type, dispatch the instructions of the next-level instruction type to the corresponding launch queue according to the dispatch rules corresponding to the next-level instruction type. The next-level instruction type includes instruction types that can be dispatched to a specified type of launch queue or multiple types of launch queues. If the plurality of instructions to be dispatched include instructions of the second-level instruction type, then dispatch the instructions of the second-level instruction type to the type of launch queue according to the dispatch rules corresponding to the second-level instruction type. After the dispatch of instructions of the second-level instruction type is completed, if the plurality of instructions to be dispatched include instructions of the third-level instruction type, then dispatch the instructions of the third-level instruction type to the multiple types of launch queues according to the dispatch rules corresponding to the third-level instruction type. The dispatch module is specifically used for: According to the dispatch rules corresponding to the next level instruction type and the current occupancy status of each launch queue, the instruction of the next level instruction type is dispatched to the corresponding launch queue, and so on, until all the multiple instructions to be dispatched are dispatched. The current occupancy status of each launch queue is used to indicate the current number of instructions occupied by each launch queue.

10. A processor core, characterized in that, The processor core is used to execute the method according to any one of claims 1-8.

11. A computer device, characterized in that, include: A processor, a memory, and a bus, wherein the memory stores machine-readable instructions executable by the processor, and when the computer sub-device is running, the processor communicates with the memory via the bus, and the processor executes the machine-readable instructions to perform the method according to any one of claims 1 to 8.

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