Semiconductor equipment-oriented software and hardware co-simulation method, device, equipment and medium
By constructing a software-hardware co-simulation framework, the semantic gap between the simulation environment and the real environment in semiconductor device development is solved, realizing efficient and low-cost software-hardware co-verification and improving simulation efficiency and accuracy.
Patent Information
- Application Number
- CN202511742880.4
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-11-25
- Publication Date
- 2026-02-24
AI Technical Summary
In semiconductor equipment development, existing technologies have limitations. Pure physical testing is costly and not repeatable, while pure software simulation fails to accurately reflect hardware characteristics, resulting in a semantic gap between the simulation environment and the real environment, making it difficult to achieve efficient and low-cost software-hardware co-verification.
A hardware and software co-simulation framework is constructed. By initializing the software runtime environment simulation module, configuring the dynamic interface simulation module and the co-communication module, and combining the timestamp synchronization mechanism, a hybrid scheduling strategy is adopted to manage multiple tasks, forming a closed-loop simulation process to ensure high fidelity and efficiency of the simulation process.
It improves simulation efficiency, solves pain points such as development efficiency, simulation accuracy and cost control, provides strong technical support for the research and development of complex semiconductor equipment, and realizes low-cost and high-efficiency software and hardware co-simulation.
Smart Images
Figure CN121560754A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of semiconductor simulation technology, and in particular to a software and hardware co-simulation method, apparatus, equipment and medium for semiconductor devices. Background Technology
[0002] With the rapid development of semiconductor technology, the functional complexity, integration, and real-time requirements of semiconductor equipment are constantly increasing. From early simple transistor circuits to today's large-scale integrated circuits containing billions of transistors, modern semiconductor equipment (such as high-end chip manufacturing equipment and advanced packaging platforms) has evolved into complex systems integrating high-precision control, high-speed data processing, and complex logic operations. These devices place extremely high demands on the stability of the hardware architecture, the accuracy of the software algorithms, and the efficiency of hardware-software collaboration. During the development process, how to achieve comprehensive verification of the hardware and software systems at low cost and low risk has become a key bottleneck restricting the speed and quality of product iteration.
[0003] Existing technologies primarily rely on two types of simulation methods: one is pure physical testing, which involves comprehensive functional verification based on real prototypes. While offering high realism, this method is limited by cost, security, and repeatability, making it difficult to support high-frequency, multi-scenario testing needs. The other is pure software simulation, which simulates device behavior by constructing fully virtualized digital models. Although this approach reduces hardware dependence and improves testing flexibility, it fails to fully consider the actual characteristics of physical hardware (such as communication latency, interrupt response time, memory access timing, and power consumption fluctuations), resulting in a "semantic gap" between the simulation environment and the real operating environment. Especially in scenarios involving real-time control and high-performance computing, software performs well in simulation, but requires repeated debugging after being ported to actual hardware, weakening the predictive value of the simulation. Therefore, a new simulation mechanism that can integrate the real characteristics of hardware with the advantages of flexible software verification is urgently needed. Summary of the Invention
[0004] In view of this, the purpose of this application is to provide a software and hardware co-simulation method, apparatus, equipment and medium for semiconductor devices, and to build a software and hardware co-simulation framework that integrates high-fidelity simulation, efficient scheduling, flexible configuration and reliable communication. This comprehensively solves the pain points of existing technologies in terms of development efficiency, simulation accuracy, test coverage and cost control, and provides strong technical support for the research and development of complex semiconductor devices, thereby improving simulation efficiency.
[0005] This application provides a software-hardware co-simulation method for semiconductor devices, the software-hardware co-simulation method including: Initialize the software runtime environment simulation module of the software under test, and build a virtual simulation module based on the obtained hardware design parameters of the target semiconductor device; Configure the dynamically configurable interface simulation module, start the collaborative communication module and timestamp synchronization mechanism; When scheduling multiple concurrent tasks, a simulation algorithm is used to abstract instruction execution, data transmission, and interrupt response into tasks with time attributes, and a hybrid scheduling strategy of priority queue and time slice round-robin is combined for task management. When the software under test initiates a hardware access request, the access request is forwarded by the virtual simulation module to the dynamically configurable interface simulation module for processing. The processed response data is returned to the software runtime environment simulation module through the collaborative communication module, forming a closed-loop simulation process.
[0006] In one possible implementation, the hardware design parameters include: Register mapping relationships, bus structure, memory resource configuration, and peripheral interface types.
[0007] In one possible implementation, the initiation of the collaborative communication module and the timestamp synchronization mechanism includes: The collaborative communication module enables data interaction between the software runtime environment simulation module and the virtual simulation module, employing a message queue-based communication mechanism and ensuring reliable data transmission via the TCP protocol. During the simulation, the hardware and software simulation clocks are synchronized through both timestamp synchronization and task trigger synchronization mechanisms to ensure time consistency during the simulation.
[0008] In one possible implementation, when the software under test initiates a hardware access request, the access request is forwarded via the virtual simulation module to the dynamically configurable interface simulation module for processing. The processed response data is then returned to the software runtime environment simulation module via the cooperative communication module, forming a closed-loop simulation process, including: Receive a hardware access request from the software runtime environment simulation module; wherein, the access request is used to simulate the operation call of the software under test to a physical interface in the target semiconductor device; The access request is passed to a dynamically configurable interface simulation module, which models the interface behavior according to preset interface configuration parameters. The interface configuration parameters include at least communication latency, signal jitter range, data packet error rate, and power fluctuation threshold. The dynamically configurable interface simulation module performs timing adjustment and exception injection processing on the received access requests based on the interface configuration parameters, generating simulated requests that conform to the actual hardware characteristics. The simulation request is passed to the virtual simulation module, which executes the corresponding functional logic based on the physical hardware design parameters and generates response data. The response data is transmitted back to the software runtime environment simulation module via the collaborative communication module through a message queue-based message passing mechanism, so that the software under test can receive it and perform subsequent logical judgments.
[0009] In one possible implementation, a simulation algorithm monitors the concurrent state of multiple tasks, a priority queue is used to manage high-priority tasks, execution windows are allocated for tasks of the same priority using a time-slice round-robin method, and task scheduling information throughout the simulation process is recorded to generate a visual debugging report, including: It receives physical drive tasks from the virtual simulation module and periodic task requests from the software runtime environment simulation module; wherein, the physical drive tasks include interrupt signals, GPIO state changes, or timer overflows; The received tasks are classified according to preset priorities and inserted into the corresponding scheduling queues; high-priority tasks are entered into the priority queue, and tasks of the same priority are stored in the time slice round-robin queue in the order of arrival. Throughout the simulation, tasks are executed based on priority, and data on context switching time, interrupt response latency, CPU utilization, and memory usage changes are continuously collected to form a complete task scheduling trajectory log.
[0010] In one possible implementation, the step of performing task execution based on priority tasks throughout the simulation process includes: Within each simulation time step, check if there are any expired high-priority tasks at the head of the priority queue; If it exists, immediately preempt the currently executing task and schedule its corresponding processing program; If no task exists, the next task is selected from the time-slice round-robin queue, a fixed-length execution window is assigned to it, and after execution, the task is switched to the next task in the queue.
[0011] This application embodiment also provides a software and hardware co-simulation device for semiconductor devices, the software and hardware co-simulation device comprising: The module is used to initialize the software runtime environment simulation module of the software under test, and to build a virtual simulation module based on the obtained hardware design parameters of the target semiconductor device; The configuration module is used to configure the dynamically configurable interface simulation module, start the cooperative communication module, and the timestamp synchronization mechanism. The simulation scheduling module is used to schedule multiple concurrent tasks. It employs simulation algorithms to abstract instruction execution, data transmission, and interrupt response into tasks with time attributes, and combines a hybrid scheduling strategy of priority queues and time slice round-robin for task management. The processing module is used to forward the hardware access request to the dynamically configurable interface simulation module via the virtual simulation module when the software under test initiates a hardware access request. The processed response data is then returned to the software runtime environment simulation module via the cooperative communication module, forming a closed-loop simulation process.
[0012] In one possible implementation, when the configuration module is used for launching the collaborative communication module and the timestamp synchronization mechanism, the configuration module is specifically used for: The collaborative communication module enables data interaction between the software runtime environment simulation module and the virtual simulation module, employing a message queue-based communication mechanism and ensuring reliable data transmission via the TCP protocol. During the simulation, the hardware and software simulation clocks are synchronized through both timestamp synchronization and task trigger synchronization mechanisms to ensure time consistency during the simulation.
[0013] This application also provides an electronic device, including: a processor, a memory, and a bus. The memory stores machine-readable instructions executable by the processor. When the electronic device is running, the processor communicates with the memory via the bus. When the machine-readable instructions are executed by the processor, the steps of the software and hardware co-simulation method for complex semiconductor devices described above are performed.
[0014] This application also provides a computer-readable storage medium storing a computer program, which, when run by a processor, executes the steps of the above-described hardware-software co-simulation method for complex semiconductor devices.
[0015] This application provides a software-hardware co-simulation method, apparatus, device, and medium for semiconductor devices. The software-hardware co-simulation method includes: initializing a software runtime environment simulation module for the software under test; constructing a virtual simulation module based on the hardware design parameters of the target semiconductor device; configuring a dynamically configurable interface simulation module; starting a cooperative communication module and a timestamp synchronization mechanism; when scheduling multiple concurrent tasks, using a simulation algorithm to abstract instruction execution, data transmission, and interrupt response into time-attributed tasks, and combining a hybrid scheduling strategy of priority queues and time-slice round-robin for task management; when the software under test initiates a hardware access request, the access request is forwarded via the virtual simulation module to the dynamically configurable interface simulation module for processing, and the processed response data is returned to the software runtime environment simulation module via the cooperative communication module, forming a closed-loop simulation process. This constructs a software-hardware co-simulation framework integrating high-fidelity simulation, efficient scheduling, flexible configuration, and reliable communication, comprehensively solving the pain points of existing technologies in terms of development efficiency, simulation accuracy, test coverage, and cost control, providing strong technical support for the research and development of complex semiconductor devices, and improving simulation efficiency.
[0016] To make the above-mentioned objectives, features and advantages of this application more apparent and understandable, preferred embodiments are described below in detail with reference to the accompanying drawings. Attached Figure Description
[0017] To more clearly illustrate the technical solutions of the embodiments of this application, the accompanying drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of this application and should not be regarded as a limitation of the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.
[0018] Figure 1 A flowchart illustrating a hardware / software co-simulation method for semiconductor devices provided in an embodiment of this application; Figure 2 This is a schematic diagram of a hardware and software co-simulation method for semiconductor devices provided in an embodiment of this application; Figure 3 This is a schematic diagram of the structure of a hardware and software co-simulation device for semiconductor devices provided in an embodiment of this application; Figure 4 This is a schematic diagram of the structure of an electronic device provided in an embodiment of this application. Detailed Implementation
[0019] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. The components of the embodiments of this application described and shown in the accompanying drawings can generally be arranged and designed in various different configurations. Therefore, the following detailed description of the embodiments of this application provided in the accompanying drawings is not intended to limit the scope of the claimed application, but merely represents selected embodiments of this application. Based on the embodiments of this application, every other embodiment obtained by those skilled in the art without inventive effort falls within the scope of protection of this application.
[0020] First, the applicable scenarios for this application will be introduced. This application can be applied to the field of semiconductor simulation technology.
[0021] With the rapid development of semiconductor technology, the functional complexity, integration, and real-time requirements of semiconductor equipment are constantly increasing. From early simple transistor circuits to today's large-scale integrated circuits containing billions of transistors, modern semiconductor equipment (such as high-end chip manufacturing equipment and advanced packaging platforms) has evolved into complex systems integrating high-precision control, high-speed data processing, and complex logic operations. These devices place extremely high demands on the stability of the hardware architecture, the accuracy of the software algorithms, and the efficiency of hardware-software collaboration. During the development process, how to achieve comprehensive verification of the hardware and software systems at low cost and low risk has become a key bottleneck restricting the speed and quality of product iteration.
[0022] Existing technologies primarily rely on two types of simulation methods: one is pure physical testing, which involves comprehensive functional verification based on real prototypes. While offering high realism, this method is limited by cost, security, and repeatability, making it difficult to support high-frequency, multi-scenario testing needs. The other is pure software simulation, which simulates device behavior by constructing fully virtualized digital models. Although this approach reduces hardware dependence and improves testing flexibility, it fails to fully consider the actual characteristics of physical hardware (such as communication latency, interrupt response time, memory access timing, and power consumption fluctuations), resulting in a "semantic gap" between the simulation environment and the real operating environment. Especially in scenarios involving real-time control and high-performance computing, software performs well in simulation, but requires repeated debugging after being ported to actual hardware, weakening the predictive value of the simulation. Therefore, a new simulation mechanism that can integrate the real characteristics of hardware with the advantages of flexible software verification is urgently needed.
[0023] Based on this, the embodiments of this application provide a software and hardware co-simulation method for semiconductor devices, which constructs a software and hardware co-simulation framework that integrates high-fidelity simulation, efficient scheduling, flexible configuration and reliable communication. It comprehensively solves the pain points of existing technologies in terms of development efficiency, simulation accuracy, test coverage and cost control, provides strong technical support for the research and development of complex semiconductor devices and improves simulation efficiency.
[0024] Please see Figure 1 , Figure 1 This is a flowchart illustrating a hardware-software co-simulation method for semiconductor devices provided in an embodiment of this application. Figure 1 As shown in the embodiments of this application, the hardware and software co-simulation method includes: S101: Initialize the software runtime environment simulation module of the software under test, and build a virtual simulation module based on the hardware design parameters of the target semiconductor device.
[0025] In this step, the software runtime environment simulation module of the software to be tested is initialized, and a virtual simulation module is constructed based on the obtained hardware design parameters of the target semiconductor device.
[0026] Here, the hardware design parameters include: register mapping relationship, bus structure, memory resource configuration and peripheral interface type.
[0027] It should be noted that the software runtime environment simulation module supports the simulation of various business scenarios. For different business scenarios, this module provides a complete runtime environment for the software by simulating the processing logic and system call interfaces of the business scenario. For embedded real-time operating systems, this module focuses on simulating their task scheduling mechanism, interrupt handling mechanism, and implementation guarantee mechanism to ensure that the software can be accurately simulated and verified even in scenarios with high real-time requirements.
[0028] Here, the virtual simulation module is the core processing unit of the simulation environment, building a hardware-software integrated simulation environment based on the design parameters of the physical hardware. The virtual simulation module not only pushes code blocks down to the lower level for execution, accelerating code loading and execution speed, but also reduces the overhead of memory allocation and deallocation through optimized memory management mechanisms. Simultaneously, to accurately evaluate the software's performance under different hardware resource conditions, the virtual simulation module also implements system resource simulation functions, ensuring that the software's operating logic in the virtual environment remains consistent with the physical hardware. This invention can simulate different memory capacities and memory usage during operation, allowing developers to optimize performance during the software design phase and avoid resource bottlenecks on actual hardware platforms. For example, by simulating different sizes of buffer memory and observing the software's runtime under different processing capabilities, targeted optimization of the software algorithm can be achieved, further improving operating efficiency.
[0029] S102: Configure the dynamically configurable interface simulation module, start the cooperative communication module and timestamp synchronization mechanism.
[0030] To meet the hardware interface requirements of different semiconductor devices, the hardware interface simulation layer supports dynamically configurable interface simulation. Developers can flexibly adjust hardware interface model parameters, such as interface call parameters and interface latency thresholds, according to specific design requirements via configuration files or a graphical interface. For example, when testing software handling scenarios with long interface latency, time thresholds can be manually injected by configuring the interface model to observe the software's response and processing. This dynamically configurable feature enables the interface simulation layer to adapt to various complex business scenarios, improving the flexibility and practicality of software simulation.
[0031] In one possible implementation, the initiation of the collaborative communication module and the timestamp synchronization mechanism includes: A: The collaborative communication module facilitates data interaction between the software runtime environment simulation module and the virtual simulation module, employing a message queue-based communication mechanism and ensuring reliable data transmission via the TCP protocol.
[0032] Here, the collaborative communication module is responsible for achieving high-speed, reliable communication between the software simulation module and the hardware simulation module. It employs a message queue-based communication mechanism, combining the advantages of the TCP (Transmission Control Protocol) protocol to achieve fast data transmission and reliable delivery. During communication, the data to be transmitted is encapsulated into messages and sent to the message queue. The receiver reads the messages from the message queue and parses and processes them. In this way, the collaborative communication module can establish a stable and efficient communication bridge between the software and hardware simulation modules, ensuring the smooth operation of software-hardware co-simulation.
[0033] B: During the simulation process, the hardware and software simulation clocks are synchronized through both timestamp synchronization and task trigger synchronization mechanisms to ensure time consistency during the simulation.
[0034] Here, the collaborative communication module adopts two mechanisms: timestamp synchronization and task trigger synchronization, to ensure that the virtual simulation and physical hardware run at the same time, thus solving the problem of "software and hardware not synchronizing and model not being accurate" in existing solutions.
[0035] S103: When scheduling multiple concurrent tasks, a simulation algorithm is used to abstract instruction execution, data transmission, and interrupt response into tasks with time attributes, and a hybrid scheduling strategy of priority queue and time slice round-robin is combined for task management.
[0036] In this step, when scheduling multiple concurrent tasks, a simulation algorithm is used to abstract instruction execution, data transmission, and interrupt response into tasks with time attributes, and a hybrid scheduling strategy of priority queue and time slice round-robin is combined for task management.
[0037] In one possible implementation, when scheduling multiple concurrent tasks, a simulation algorithm is used to abstract instruction execution, data transmission, and interrupt response into tasks with time attributes, and a hybrid scheduling strategy combining priority queues and time-slice round-robin is used for task management, including: (1): Receive physical drive task requests from the virtual simulation module and periodic task requests from the software runtime environment simulation module; wherein, the physical drive task requests include interrupt signals, GPIO state changes or timer overflows.
[0038] Here, we receive physics-driven tasks from the virtual simulation module and periodic task requests from the software runtime environment simulation module.
[0039] (2): Classify the received tasks according to the preset priority and insert them into the corresponding scheduling queue; among them, high priority tasks enter the priority queue, and tasks of the same priority are stored in the time slice round-robin queue in the order of arrival.
[0040] Here, the received tasks are classified according to preset priorities and inserted into the corresponding scheduling queues; high-priority tasks enter the priority queue, while tasks of the same priority are stored in the time slice round-robin queue in the order of arrival.
[0041] (3): Throughout the simulation process, tasks are executed in order of priority, and the context switching time, interrupt response delay, CPU utilization and memory usage change data of the tasks are continuously collected to form a complete task scheduling trajectory log.
[0042] Here, throughout the simulation process, tasks are executed according to priority, and data on context switching time, interrupt response latency, CPU utilization, and memory usage changes are continuously collected to form a complete task scheduling trajectory log.
[0043] In one possible implementation, the step of executing tasks based on priority order throughout the simulation includes: Within each simulation time step, check if there is a high-priority task that has expired at the head of the priority queue; if so, immediately preempt the currently executing task and schedule its corresponding handler; if not, select the next task from the time slice round-robin queue, allocate it a fixed-length execution window, and switch to the next task in the queue after execution.
[0044] Here, within each simulation time step, it checks whether there is a high-priority task that has expired at the head of the priority queue; if there is, it immediately preempts the currently executing task and schedules its corresponding handler; if there is no such task, it selects the next task from the time slice round-robin queue, assigns it a fixed-length execution window, and switches to the next task in the queue after execution.
[0045] In particular, considering the concurrent tasks that occur during the operation of highly complex semiconductor devices, the virtual simulation module adopts a physical-driven simulation algorithm, combined with a priority queue and time-slice round-robin scheduling mechanism, to achieve efficient management of multiple concurrent tasks, such as... Figure 2 As shown, in time-driven simulation algorithms, various operations in semiconductor device software are abstracted as time, such as data transmission, instruction execution, and interrupt triggering. When a task occurs, the scheduling algorithm quickly schedules the corresponding handler based on the task type and priority. The priority queue mechanism stores tasks to be processed in a queue, sorting them according to their priority to ensure that high-priority tasks are processed promptly. The time-slice round-robin scheduling mechanism is used to handle multiple tasks with the same priority, allocating a certain time slice to each task to ensure that each task has a fair opportunity to execute. In this way, virtual simulation can significantly improve simulation speed while ensuring simulation accuracy, effectively improving simulation efficiency compared to traditional sequential execution simulation methods.
[0046] S104: When the software under test initiates a hardware access request, the access request is forwarded to the dynamically configurable interface simulation module via the virtual simulation module for processing. The processed response data is returned to the software runtime environment simulation module via the cooperative communication module, forming a closed-loop simulation process.
[0047] In this step, when the software under test initiates a hardware access request, the access request is forwarded by the virtual simulation module to the dynamically configurable interface simulation module for processing. The processed response data is then returned to the software runtime environment simulation module through the collaborative communication module, forming a closed-loop simulation process.
[0048] In one possible implementation, when the software under test initiates a hardware access request, the access request is forwarded via the virtual simulation module to the dynamically configurable interface simulation module for processing. The processed response data is then returned to the software runtime environment simulation module via the cooperative communication module, forming a closed-loop simulation process, including: (1): Receive a hardware access request from the software runtime environment simulation module; wherein the access request is used to simulate the operation call of the software under test to a physical interface in the target semiconductor device.
[0049] (2): The access request is passed to a dynamically configurable interface simulation module, which models the interface behavior according to preset interface configuration parameters; the interface configuration parameters include at least communication delay, signal jitter range, data packet error rate and power fluctuation threshold.
[0050] Here, the access request is passed to the dynamically configurable interface simulation module, which models the interface behavior according to the preset interface configuration parameters.
[0051] (3): The dynamically configurable interface simulation module performs timing adjustment and exception injection processing on the received access requests based on the interface configuration parameters, and generates simulated requests that conform to the actual hardware characteristics.
[0052] Here, the dynamically configurable interface simulation module performs timing adjustments and exception injection processing on the received access requests based on the interface configuration parameters, generating simulated requests that conform to the actual hardware characteristics.
[0053] (4) The simulation request is passed to the virtual simulation module, which executes the corresponding functional logic and generates response data based on the physical hardware design parameters; the response data is transmitted back to the software runtime environment simulation module via the collaborative communication module through a message passing mechanism based on a message queue, so that the software under test can receive it and make subsequent logic judgments.
[0054] Here, the simulation request is passed to the virtual simulation module, which executes the corresponding functional logic and generates response data according to the physical hardware design parameters. The response data is transmitted back to the software runtime environment simulation module via the message passing mechanism of the message queue through the collaborative communication module, so that the software under test can receive it and perform subsequent logic judgments.
[0055] To meet the hardware interface requirements of different semiconductor devices, the hardware interface simulation layer supports dynamically configurable interface simulation. Developers can flexibly adjust hardware interface model parameters, such as interface call parameters and interface latency thresholds, according to specific design requirements through configuration files or a graphical interface. For example, when testing software handling scenarios with long interface latency, time thresholds can be manually injected by configuring the interface model to observe the software's response and processing. This dynamically configurable function enables the interface simulation layer to adapt to various complex business scenarios, improving the flexibility and practicality of software simulation. The hardware interface simulation layer constructs a rich hardware interface library, storing the hardware interfaces of different device models and scenarios. Subsequently, through the interfaces stored in the library, the software can realistically interact with the simulated hardware interfaces in the simulation environment, just as if running on an actual hardware platform.
[0056] For further details, please refer to Figure 2 , Figure 2 This is a schematic diagram illustrating a hardware-software co-simulation method for semiconductor devices provided in an embodiment of this application. Figure 2 As shown, the software runtime environment simulation module sends different business scenarios to the virtual simulation module. The virtual simulation module provides the software program runtime environment. The simulation algorithm and scheduling module process the runtime environment and send out interfaces according to the scheduling algorithm. The dynamically configurable interface simulation module sets dynamic parameters according to the sent interfaces and sends the dynamic parameter settings to the hardware interface library module for invocation through the collaborative communication module.
[0057] This application provides a software-hardware co-simulation method for semiconductor devices. The method includes: initializing a software runtime environment simulation module for the software under test; constructing a virtual simulation module based on the hardware design parameters of the target semiconductor device; configuring a dynamically configurable interface simulation module; starting a collaborative communication module and a timestamp synchronization mechanism; when scheduling multiple concurrent tasks, using simulation algorithms to abstract instruction execution, data transmission, and interrupt responses into time-attributed tasks, and combining a hybrid scheduling strategy of priority queues and time-slice round-robin for task management; when the software under test initiates a hardware access request, the access request is forwarded via the virtual simulation module to the dynamically configurable interface simulation module for processing, and the processed response data is returned to the software runtime environment simulation module via the collaborative communication module, forming a closed-loop simulation process. This constructs a software-hardware co-simulation framework integrating high-fidelity simulation, efficient scheduling, flexible configuration, and reliable communication, comprehensively solving the pain points of existing technologies in terms of development efficiency, simulation accuracy, test coverage, and cost control, providing strong technical support for the research and development of complex semiconductor devices, and improving simulation efficiency.
[0058] Please see Figure 3 , Figure 3 This is a schematic diagram of the structure of a hardware and software co-simulation device for semiconductor devices provided in an embodiment of this application. Figure 3 As shown, the hardware / software co-simulation device 300 includes: Module 301 is used to initialize the software runtime environment simulation module of the software to be tested and to build a virtual simulation module based on the hardware design parameters of the target semiconductor device. Configuration module 302 is used to configure the dynamically configurable interface simulation module, start the cooperative communication module, and the timestamp synchronization mechanism; The simulation scheduling module 303 is used to schedule multiple concurrent tasks. It adopts a simulation algorithm to abstract instruction execution, data transmission and interrupt response into tasks with time attributes, and combines a hybrid scheduling strategy of priority queue and time slice round-robin for task management. The processing module 304 is used to forward the hardware access request to the dynamically configurable interface simulation module via the virtual simulation module for processing when the software under test initiates a hardware access request. The processed response data is then returned to the software runtime environment simulation module via the cooperative communication module, forming a closed-loop simulation process.
[0059] Furthermore, when the configuration module 302 is used to start the collaborative communication module and the timestamp synchronization mechanism, the configuration module 302 is specifically used for: The collaborative communication module enables data interaction between the software runtime environment simulation module and the virtual simulation module, employing a message queue-based communication mechanism and ensuring reliable data transmission via the TCP protocol. During the simulation, the hardware and software simulation clocks are synchronized through both timestamp synchronization and task trigger synchronization mechanisms to ensure time consistency during the simulation.
[0060] Furthermore, the hardware design parameters include: Register mapping relationships, bus structure, memory resource configuration, and peripheral interface types.
[0061] Furthermore, when the simulation scheduling module 303 is used to schedule multiple concurrent tasks, it uses a simulation algorithm to abstract instruction execution, data transmission, and interrupt response into tasks with time attributes, and combines a hybrid scheduling strategy of priority queues and time-slice round-robin for task management. The simulation scheduling module 303 is also used for: It receives physical drive task requests from the virtual simulation module and periodic task requests from the software runtime environment simulation module; wherein, the physical drive task requests include interrupt signals, GPIO state changes or timer overflows; The received tasks are classified according to preset priorities and inserted into the corresponding scheduling queues; high-priority tasks are entered into the priority queue, and tasks of the same priority are stored in the time slice round-robin queue in the order of arrival. Throughout the simulation, tasks are executed in order of priority, and data on context switching time, interrupt response latency, CPU utilization, and memory usage changes are continuously collected to form a complete task scheduling trajectory log.
[0062] Furthermore, when the simulation scheduling module 303 is used to execute tasks based on the order of priority tasks throughout the simulation process, the simulation scheduling module 303 is also used to: Within each simulation time step, check if there are any expired high-priority tasks at the head of the priority queue; If it exists, immediately preempt the currently executing task and schedule its corresponding processing program; If no task exists, the next task is selected from the time-slice round-robin queue, a fixed-length execution window is assigned to it, and after execution, the task is switched to the next task in the queue.
[0063] Furthermore, when the software under test initiates a hardware access request, and the access request is forwarded via the virtual simulation module to the dynamically configurable interface simulation module for processing, and the processed response data is returned to the software runtime environment simulation module via the cooperative communication module to form a closed-loop simulation process, the processing module 304 is also used for: Receive a hardware access request from the software runtime environment simulation module; wherein, the access request is used to simulate the operation call of the software under test to a physical interface in the target semiconductor device; The access request is passed to a dynamically configurable interface simulation module, which models the interface behavior according to preset interface configuration parameters. The interface configuration parameters include at least communication latency, signal jitter range, data packet error rate, and power fluctuation threshold. The dynamically configurable interface simulation module performs timing adjustment and exception injection processing on the received access requests based on the interface configuration parameters, generating simulated requests that conform to the actual hardware characteristics. The simulation request is passed to the virtual simulation module, which executes the corresponding functional logic based on the physical hardware design parameters and generates response data. The response data is transmitted back to the software runtime environment simulation module via the collaborative communication module through a message queue-based message passing mechanism, so that the software under test can receive it and perform subsequent logical judgments.
[0064] Please see Figure 4 , Figure 4 This is a schematic diagram of the structure of an electronic device provided in an embodiment of this application. Figure 4 As shown, the electronic device 400 includes a processor 410, a memory 420, and a bus 430.
[0065] The memory 420 stores machine-readable instructions executable by the processor 410. When the electronic device 400 is running, the processor 410 communicates with the memory 420 via the bus 430. When the machine-readable instructions are executed by the processor 410, they can perform the operations described above. Figure 1The specific implementation of the hardware and software co-simulation method for semiconductor devices in the illustrated method embodiment can be found in the method embodiment, and will not be repeated here.
[0066] This application also provides a computer-readable storage medium storing a computer program, which, when executed by a processor, can perform the above-described actions. Figure 1 The specific implementation of the hardware and software co-simulation method for semiconductor devices in the illustrated method embodiment can be found in the method embodiment, and will not be repeated here.
[0067] Those skilled in the art will understand that, for the sake of convenience and brevity, the specific working processes of the systems, devices, and units described above can be referred to the corresponding processes in the foregoing method embodiments, and will not be repeated here.
[0068] In the several embodiments provided in this application, it should be understood that the disclosed systems, apparatuses, and methods can be implemented in other ways. The apparatus embodiments described above are merely illustrative. For example, the division of units is only a logical functional division, and in actual implementation, there may be other division methods. Furthermore, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Additionally, the shown or discussed mutual couplings, direct couplings, or communication connections may be through some communication interfaces; indirect couplings or communication connections between devices or units may be electrical, mechanical, or other forms.
[0069] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.
[0070] In addition, the functional units in the various embodiments of this application can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit.
[0071] If the aforementioned functions are implemented as software functional units and sold or used as independent products, they can be stored in a processor-executable, non-volatile, computer-readable storage medium. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or a portion of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.
[0072] Finally, it should be noted that the above-described embodiments are merely specific implementations of this application, used to illustrate the technical solutions of this application, and not to limit them. The scope of protection of this application is not limited thereto. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that any person skilled in the art can still modify or easily conceive of changes to the technical solutions described in the foregoing embodiments, or make equivalent substitutions for some of the technical features, within the scope of the technology disclosed in this application. Such modifications, changes, or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application, and should all be covered within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.
Claims
1. A hardware and software co-simulation method for semiconductor devices, characterized in that, The hardware / software co-simulation method includes: Initialize the software runtime environment simulation module of the software under test, and build a virtual simulation module based on the obtained hardware design parameters of the target semiconductor device; Configure the dynamically configurable interface simulation module, start the collaborative communication module and timestamp synchronization mechanism; When scheduling multiple concurrent tasks, a simulation algorithm is used to abstract instruction execution, data transmission, and interrupt response into tasks with time attributes, and a hybrid scheduling strategy of priority queue and time slice round-robin is combined for task management. When the software under test initiates a hardware access request, the access request is forwarded by the virtual simulation module to the dynamically configurable interface simulation module for processing. The processed response data is returned to the software runtime environment simulation module through the collaborative communication module, forming a closed-loop simulation process.
2. The hardware / software co-simulation method according to claim 1, characterized in that, The hardware design parameters include: Register mapping relationships, bus structure, memory resource configuration, and peripheral interface types.
3. The hardware / software co-simulation method according to claim 1, characterized in that, The startup of the collaborative communication module and the timestamp synchronization mechanism include: The collaborative communication module enables data interaction between the software runtime environment simulation module and the virtual simulation module, employing a message queue-based communication mechanism and ensuring reliable data transmission via the TCP protocol. During the simulation, the hardware and software simulation clocks are synchronized through both timestamp synchronization and task trigger synchronization mechanisms to ensure time consistency during the simulation.
4. The hardware / software co-simulation method according to claim 1, characterized in that, When scheduling multiple concurrent tasks, a simulation algorithm is used to abstract instruction execution, data transmission, and interrupt response into tasks with time attributes. A hybrid scheduling strategy combining priority queues and time-slice round-robin is then used for task management, including: It receives physical drive task requests from the virtual simulation module and periodic task requests from the software runtime environment simulation module; wherein, the physical drive task requests include interrupt signals, GPIO state changes or timer overflows; The received tasks are classified according to preset priorities and inserted into the corresponding scheduling queues; high-priority tasks are entered into the priority queue, and tasks of the same priority are stored in the time slice round-robin queue in the order of arrival. Throughout the simulation, tasks are executed in order of priority, and data on context switching time, interrupt response latency, CPU utilization, and memory usage changes are continuously collected to form a complete task scheduling trajectory log.
5. The hardware / software co-simulation method according to claim 4, characterized in that, Throughout the simulation process, tasks are executed sequentially based on their priority, including: Within each simulation time step, check if there are any expired high-priority tasks at the head of the priority queue; If it exists, immediately preempt the currently executing task and schedule its corresponding processing program; If no task exists, the next task is selected from the time-slice round-robin queue, a fixed-length execution window is assigned to it, and after execution, the task is switched to the next task in the queue.
6. The hardware / software co-simulation method according to claim 1, characterized in that, When the software under test initiates a hardware access request, the access request is forwarded via the virtual simulation module to the dynamically configurable interface simulation module for processing. The processed response data is then returned to the software runtime environment simulation module via the cooperative communication module, forming a closed-loop simulation process, including: Receive a hardware access request from the software runtime environment simulation module; wherein, the access request is used to simulate the operation call of the software under test to a physical interface in the target semiconductor device; The access request is passed to a dynamically configurable interface simulation module, which models the interface behavior according to preset interface configuration parameters. The interface configuration parameters include at least communication latency, signal jitter range, data packet error rate, and power fluctuation threshold. The dynamically configurable interface simulation module performs timing adjustment and exception injection processing on the received access requests based on the interface configuration parameters, generating simulated requests that conform to the actual hardware characteristics. The simulation request is passed to the virtual simulation module, which executes the corresponding functional logic based on the physical hardware design parameters and generates response data. The response data is transmitted back to the software runtime environment simulation module via the collaborative communication module through a message queue-based message passing mechanism, so that the software under test can receive it and perform subsequent logical judgments.
7. A hardware and software co-simulation device for semiconductor devices, characterized in that, The hardware / software co-simulation device includes: The module is used to initialize the software runtime environment simulation module of the software under test, and to build a virtual simulation module based on the obtained hardware design parameters of the target semiconductor device; The configuration module is used to configure the dynamically configurable interface simulation module, start the cooperative communication module, and the timestamp synchronization mechanism. The simulation scheduling module is used to schedule multiple concurrent tasks. It employs simulation algorithms to abstract instruction execution, data transmission, and interrupt response into tasks with time attributes, and combines a hybrid scheduling strategy of priority queues and time slice round-robin for task management. The processing module is used to forward the hardware access request to the dynamically configurable interface simulation module via the virtual simulation module when the software under test initiates a hardware access request. The processed response data is then returned to the software runtime environment simulation module via the cooperative communication module, forming a closed-loop simulation process.
8. The hardware and software co-simulation device according to claim 7, characterized in that, When the configuration module is used for starting the collaborative communication module and the timestamp synchronization mechanism, the configuration module is specifically used for: The collaborative communication module enables data interaction between the software runtime environment simulation module and the virtual simulation module, employing a message queue-based communication mechanism and ensuring reliable data transmission via the TCP protocol. During the simulation, the hardware and software simulation clocks are synchronized through both timestamp synchronization and task trigger synchronization mechanisms to ensure time consistency during the simulation.
9. An electronic device, characterized in that, include: The device includes a processor, a memory, and a bus. The memory stores machine-readable instructions executable by the processor. When the electronic device is running, the processor communicates with the memory via the bus. The machine-readable instructions are executed by the processor to perform the steps of the hardware-software co-simulation method for complex semiconductor devices as described in any one of claims 1 to 6.
10. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a computer program that, when executed by a processor, performs the steps of the software-hardware co-simulation method for complex semiconductor devices as described in any one of claims 1 to 6.