Data processing method, content addressable memory and electronic equipment
By introducing a caching module into CAM and segmenting the data path, the challenges of querying and writing data in CAM at high clock frequencies are solved, achieving efficient and stable data processing.
Patent Information
- Application Number
- CN202511783491.6
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-11-28
- Publication Date
- 2026-02-24
AI Technical Summary
Existing CAM systems struggle to complete querying, hit/miss determination, and data writing operations within a single clock cycle at high clock frequencies, leading to reduced stability and reliability.
By adding a cache module, queries are performed on the storage array and cache module within the same clock cycle. The hit result is determined within the same clock cycle, and the data that was not hit is written in the next clock cycle, thus splitting the data path and reducing the amount of operation in each clock cycle.
It improves data query efficiency and accuracy, reduces timing pressure, meets the requirements of real-time data storage and retrieval under high-frequency clock cycles, and enhances the stability and reliability of CAM.
Smart Images
Figure CN121560775A_ABST
Abstract
Description
Technical Field
[0001] This disclosure relates to, but is not limited to, the field of integrated circuit technology, and particularly to a data processing method, a content-addressable memory, and an electronic device. Background Technology
[0002] Content-Addressable Memory (CAM) is a storage structure that allows direct data retrieval based on content. It is widely used in high-speed route lookup, pattern recognition, and cache management. Unlike traditional addressing methods, CAM allows users to retrieve the location of data within the memory by inputting the data content, thus enabling fast matching operations.
[0003] In related technologies, as clock frequencies increase, CAM structures built on registers struggle to complete operations such as querying, hit / miss judgment, and data writing within a single clock cycle (i.e., one clock cycle). This results in problems such as slower processing speed, timing conflicts, and data writing errors, thereby reducing the stability and reliability of the CAM. Summary of the Invention
[0004] This disclosure provides a data processing method, a content-addressable memory, and an electronic device.
[0005] The technical solution of this disclosure embodiment is implemented as follows: This disclosure provides a content-addressable memory, including a storage array with at least one first storage unit, a judgment module, a processing module, a cache module with a second storage unit, and an address generation module, wherein the bit width of the second storage unit is greater than the bit width of the first storage unit, wherein: The judgment module is used to determine the hit result of the first query data within the first cycle, based on the first query data and the data in at least one target storage unit; wherein, the target storage unit includes one of the following: a non-empty first storage unit and a non-empty second storage unit; The processing module is used to update the second storage unit within the first frame based on the first query data and the address corresponding to the first query data; wherein the address corresponding to the first query data is the address of an empty first storage unit in the storage array, and the address corresponding to the first query data is determined based on the second storage unit and the address generation module; The processing module is further configured to, within the second cycle, write the first query data to the address corresponding to the first query data if the hit result of the first query data indicates a miss; wherein the second cycle is the cycle following the first cycle.
[0006] This disclosure provides a data processing method applied to a content-addressable memory (CNTM). The CNTM includes a storage array having at least one first storage unit, a judgment module, a processing module, a cache module having a second storage unit, and an address generation module. The bit width of the second storage unit is greater than the bit width of the first storage unit. The data processing method includes: Within the first cycle, the judgment module determines the hit result of the first query data based on the first query data and the data in at least one target storage unit; wherein, the target storage unit includes one of the following: a non-empty first storage unit and a non-empty second storage unit; Within the first frame, the processing module updates the second storage unit based on the first query data and the address corresponding to the first query data; wherein, the address corresponding to the first query data is the address of an empty first storage unit in the storage array, and the address corresponding to the first query data is determined based on the second storage unit and the address generation module; In the second cycle, if the hit result of the first query data indicates a miss, the processing module writes the first query data to the address corresponding to the first query data; wherein, the second cycle is the cycle following the first cycle.
[0007] This disclosure provides an electronic device including the above-described addressable memory.
[0008] In this embodiment, on the one hand, by adding a cache module to cache query data and the address corresponding to the query data, queries are performed on both the storage array and the cache module within the same clock cycle, improving the efficiency and accuracy of data query and compensating for the data write latency caused by the newly added cache module. On the other hand, by writing the missing query data into the storage array in the next clock cycle, the data path of the relevant CAM is effectively segmented. That is, the query and hit result judgment of the data in the storage array are realized within the same clock cycle, and the missing data in the cache module is written into the storage array in the next clock cycle, shortening the critical path length, effectively reducing the amount of operations that need to be completed in each clock cycle, reducing timing pressure and speeding up processing speed. This can meet the stringent requirements for real-time data storage and retrieval under high-frequency clock cycles, thereby improving the stability and reliability of the CAM.
[0009] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and are not intended to limit this disclosure. Attached Figure Description
[0010] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this disclosure and, together with the specification, serve to illustrate the technical solutions of this disclosure.
[0011] Figure 1 A schematic diagram of the composition structure of a content-addressable memory provided in an embodiment of this disclosure; Figure 2 A schematic diagram illustrating the implementation flow of a data processing method provided in an embodiment of this disclosure; Figure 3 This is a schematic diagram of a content-addressable memory in related technologies; Figure 4 This is a schematic diagram of a content-addressable memory provided in an embodiment of the present disclosure. Detailed Implementation
[0012] To make the objectives, technical solutions, and advantages of this disclosure clearer, the disclosure will be further described in detail below with reference to the accompanying drawings. The described embodiments should not be regarded as limitations on this disclosure. All other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this disclosure.
[0013] In the following description, references are made to “some embodiments,” which describe a subset of all possible embodiments. However, it is understood that “some embodiments” may be the same subset or different subsets of all possible embodiments and may be combined with each other without conflict.
[0014] In the following description, the terms “first, second, third” are used merely to distinguish similar objects and do not represent a specific ordering of objects. It is understood that “first, second, third” may be interchanged in a specific order or sequence where permitted, so that the embodiments of this disclosure described herein can be implemented in an order other than that illustrated or described herein.
[0015] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. The terminology used herein is for the purpose of describing embodiments of this disclosure only and is not intended to be limiting of this disclosure.
[0016] The technical solutions in the embodiments of this disclosure will now be clearly and completely described with reference to the accompanying drawings.
[0017] like Figure 1 As shown, the content-addressable memory 10 includes a memory array 11 with at least one first memory cell 111, a judgment module 12, a processing module 13, a cache module 14 with a second memory cell 141, and an address generation module 15. The bit width of the second memory cell 141 is greater than the bit width of the first memory cell 111, wherein: The judgment module 12 is used to determine the hit result of the first query data within the first cycle, based on the first query data and the data in at least one target storage unit; wherein the target storage unit includes one of the following: a non-empty first storage unit and a non-empty second storage unit; Processing module 13 is used to update the second storage unit within the first cycle based on the first query data and the address corresponding to the first query data; wherein, the address corresponding to the first query data is the address of an empty first storage unit in the storage array, and the address corresponding to the first query data is determined based on the second storage unit and the address generation module; The processing module 13 is also used to write the first query data to the address corresponding to the first query data in the second phase if the hit result of the first query data indicates that the first query data has not been hit; wherein the second phase is the phase following the first phase.
[0018] Here, the storage array 11 can be any suitable hardware module capable of implementing storage functions, such as registers, memory, etc. The storage array 11 may include one first storage unit 111, or two or more first storage units 111. The first storage unit 111 is the basic storage structure of the CAM, and is used to store data and its corresponding address; that is, the first storage unit 111 includes at least a data portion and an address portion. In some embodiments, the first storage unit 111 may be a register group, which includes registers for storing data and registers for storing addresses.
[0019] In digital circuit design, a "cycle" refers to a processing phase within a clock cycle. Operations in different phases can be completed within different cycles. In implementation, the entire data processing flow is divided into multiple consecutive cycles (such as the first cycle, the second cycle, etc.), with each cycle executing a portion of the task. This achieves pipelined processing, reduces overall processing latency, and improves overall processing efficiency. It can be understood that the first cycle can be the i-th cycle, and the second cycle can be the (i+1)-th cycle.
[0020] The query data (including the initial query data and other query data mentioned below) can be any suitable data that needs to be queried. This query data is the data received by CAM for retrieval or matching.
[0021] The cache module 14 can be any suitable hardware module capable of implementing storage functions, such as registers or memory. The cache module 14 may include one second storage unit 141. In some embodiments, the cache module 14 may also include at least two second storage units 141; the number of second storage units 141 can be set according to actual needs during implementation.
[0022] The second storage unit 141 is the basic storage structure of the cache module. The second storage unit 141 is at least used to store a hit flag, data, and the address corresponding to the data; that is, the second storage unit 141 includes at least a hit flag portion, a data portion, and an address portion. In some embodiments, the second storage unit 141 can be a register group, which includes a register for storing data, a register for storing addresses, and a register for storing hit flags.
[0023] In some implementations, the bit width of the address portion of the second storage cell 141 is the same as the bit width of the address portion of the first storage cell 111, the bit width of the content portion of the second storage cell 141 is the same as the bit width of the content portion of the first storage cell 111, and the bit width of the hit flag portion of the second storage cell 141 is not less than one bit.
[0024] Here, the address width can be any suitable number of bits, such as 8 bits, 16 bits, 32 bits, etc. The address portion refers to the field used to locate the data position in the storage unit, usually represented in binary form. The width of the address portion determines the size of the addressable storage space. In implementation, by setting the address width of the second storage unit to the same width as the first storage unit, it ensures that the same address format and mapping mechanism are used when accessing both storage units, thereby simplifying the address resolution and translation process in the system. Furthermore, maintaining consistent address widths for both storage units helps improve system compatibility and stability, reducing errors or performance degradation caused by inconsistent address formats. Simultaneously, it unifies the address processing flow, thereby reducing hardware complexity and improving overall operating efficiency.
[0025] The bit width of the content portion can be any suitable number of bits, such as 32 bits, 64 bits, etc. It is understood that the bit width of the address portion can be the same as or different from the bit width of the data portion. In implementation, the bit width of the address portion and the bit width of the content portion can be set according to actual needs. The content portion refers to the actual data field stored in the storage unit, and the bit width of the content portion determines the amount of data transferred in each read / write operation. In implementation, by maintaining the same bit width between the content portion of the second storage unit 141 and the content portion of the first storage unit, it helps to ensure the matching of the two storage units in terms of data width. This eliminates the need for additional conversion or expansion operations during data exchange or copying, improving data transmission efficiency, reducing errors or delays that may be caused by inconsistent data widths, and avoiding the overhead of data format conversion, thereby improving data processing speed and enhancing responsiveness.
[0026] The hit flag can be at least one bit wide. For example, the hit flag can be 1 bit wide, using 1 bit to store the hit result (i.e., hit or miss). Understandably, the hit result can be in any suitable format. For example, "1" indicates a hit, and "0" indicates a miss.
[0027] In this embodiment, on the one hand, by maintaining the consistency design of the address and content portions of the storage units in the storage array, the second storage unit is compatible with the operating format of the first storage unit, avoiding the conversion overhead caused by structural differences and improving the integration of CAM; on the other hand, by storing the hit result through the hit identifier portion, more accurate support is provided for subsequent data querying and data writing.
[0028] The target storage unit can be either a non-empty first storage unit 111 or a non-empty second storage unit 141. It is understood that when the storage array is empty and the second storage unit 141 is empty, the number of target storage units can be 0; when the storage array is not empty and / or the second storage unit 141 is not empty, the number of target storage units can be at least one. For example, the target storage unit may include at least one non-empty first storage unit 111 and / or at least one non-empty second storage unit 141.
[0029] The judgment module 12 is mainly used to perform data querying, comparison, and hit / miss determination. The judgment module 12 can be any suitable hardware circuit capable of implementing this function.
[0030] In some implementations, the determination module 12 may first determine the target storage unit, then read data from the data portion of the target storage unit, then compare the first query data with the read data, and finally determine the hit result of the first query data.
[0031] In some implementations, if the second storage unit 141 is not empty, it is used as the target storage unit.
[0032] In some implementations, the determination module 12 can directly traverse the storage array 11, and when a certain first storage cell 111 is not empty, it is taken as the target storage cell. In some implementations, since the first storage cells 111 of the storage array 11 can be stored sequentially, the non-empty first storage cells 111 in the storage array can be determined based on the address in the second storage cell 141. Therefore, only these non-empty first storage cells 111 need to be queried in parallel. For example, if the storage array 11 includes 1024 first storage cells 111, and if the second storage cell 141 stores the address of the 10th first storage cell 111, then the first to 9th first storage cells 111 can be non-empty first storage cells 111, so only the first 9 first storage cells 111 need to be queried.
[0033] In some implementations, the judgment module 12 includes a comparison module and a hit judgment module. The comparison module is used to compare the first query data and the data in each target storage unit in parallel within the first cycle to obtain the comparison result of each target storage unit. The hit judgment module is used to determine the hit result of the first query data based on the comparison result of each target storage unit within the first cycle.
[0034] Here, the comparison module is mainly used for data querying and comparison. This comparison module can be any suitable hardware circuit capable of implementing this function. In implementation, the comparison module performs parallel comparisons of the input first query data and the data in each target storage unit within the same clock cycle. Compared to serial comparison, this reduces latency and improves query efficiency.
[0035] Parallel comparisons can be implemented through hardware acceleration or multithreading / multiprocessing at the software level. For example, in a hardware implementation, the comparison module may consist of multiple independent comparators, each corresponding to a target memory unit. Parallel comparisons can complete all comparison tasks within one clock cycle. This allows for the matching of large amounts of data in a short time, significantly reducing query response time and improving real-time performance and concurrent processing capabilities.
[0036] The comparison result of the target storage unit indicates whether the data in the target storage unit is the same as the query data. The comparison result may include, but is not limited to, a first comparison result and a second comparison result. A first comparison result indicates that the data in the target storage unit is the same as the query data, and a second comparison result indicates that the data in the target storage unit is different from the query data. It is understood that the number of first comparison results can be zero, one, or more. In implementation, if the data in all target storage units is different from the first query data, the number of first comparison results can be zero; if the data in multiple target storage units is the same as the first query data, the number of first comparison results can be multiple.
[0037] In some implementations, the comparison module is further configured to use a first comparison result as the comparison result of the target storage unit if the data in the target storage unit is the same as the first query data; and to use a second comparison result as the comparison result of the target storage unit if the data in the target storage unit is different from the first query data. In practice, the comparison module performs parallel comparison operations between the data in the content portions of multiple target storage units and the first query data within the first iteration to obtain the comparison result for each target storage unit. This ensures the accuracy of the hit determination by performing precise content comparison on each target storage unit, enhances robustness, and achieves efficient, low-latency processing capabilities at the hardware level, making it suitable for applications requiring rapid retrieval and response.
[0038] The hit determination module is mainly used to determine whether the input query data is a hit. The hit determination module can be any suitable hardware circuit capable of implementing this function. In implementation, this hit determination module can be connected to the determination module 12.
[0039] The hit detection module can complete the final judgment logic within the same clock cycle. This operation mode allows the entire judgment process to be completed within a complete clock cycle, thereby further improving response speed and processing efficiency.
[0040] The hit result can include, but is not limited to, a first hit result indicating a hit, a second hit result indicating a miss, etc. The form of the hit result can be any suitable form, such as a Boolean value, a status code, or an identifier. For example, "1" indicates a hit, and "0" indicates a miss. Or, for example, "TRUE" indicates a hit, and "FALSE" indicates a miss.
[0041] In some implementations, the hit determination module is further configured to: if the comparison result of any target storage unit is a first comparison result, use the first hit result as the hit result of the first query data; and if the comparison result of each target storage unit is a second comparison result, use the second hit result as the hit result of the first query data. Specifically, when a target storage unit returns a first comparison result, it indicates that the target storage unit contains content matching the first query data, and the first query data is considered to have hit. When all target storage units return second comparison results, it indicates that no storage unit contains content matching the first query data, and the first query data is considered to have missed. Thus, by introducing a mechanism to distinguish between the first and second comparison results in the hit determination module, and outputting the first and second hit results accordingly, the existence of a matching item in the first query data can be determined more accurately, thereby improving the accuracy of the determination, optimizing overall query performance, and improving resource utilization efficiency.
[0042] In this embodiment, on the one hand, by setting up a comparison module to achieve parallel comparison and setting up a hit judgment module to quickly obtain the hit result, the high-speed hit judgment task can be completed through division of labor and cooperation, which can effectively improve the processing efficiency of the judgment module, thereby shortening the query response time and further improving the overall operating performance and user experience.
[0043] The processing module 13 can be any suitable hardware module capable of implementing this function.
[0044] Understandably, cache module 14 is a new addition, used to temporarily store information about the input query data.
[0045] The update of the second storage unit 141 may include, but is not limited to, updating the content portion of the second storage unit 141, updating the hit flag portion of the second storage unit 141, and updating the address portion of the second storage unit 141. In implementation, before updating, the hit flag portion of the second storage unit 141 can be read first, and the second storage unit 141 can be updated according to the hit flag portion.
[0046] The address corresponding to the first queried data can be an address within the address portion of the second storage unit 141, or the address following the address within the address portion of the second storage unit 141. It is understood that the address within the address portion of the second storage unit 141 can be the address of an empty first storage unit 111.
[0047] In some implementations, if the hit flag of the second storage unit 141 indicates a miss, the data in the content portion of the second storage unit 141 is written to the address in the address portion of the second storage unit 141. That is, the data in the content portion of the second storage unit 141 is written into the storage array 11. After the writing is completed, the content portion and the address portion of the second storage unit 141 are updated. That is, the first query data is saved to the content portion of the second storage unit 141, and the address corresponding to the first query data is saved to the address portion of the second storage unit 141. At this time, the address corresponding to the first query data can be the address of the next empty first storage unit 111.
[0048] In some implementations, if the hit flag portion of the second storage unit 141 indicates a hit, the address portion of the second storage unit 141 can remain unchanged, but the content portion of the second storage unit 141 needs to be updated, that is, the first query data is updated to the content portion of the second storage unit 141. In this case, the address corresponding to the first query data can be an address in the address portion of the second storage unit 141.
[0049] In some implementations, after the judgment module 12 determines the hit result of the first query data, the hit result of the first query data can be updated to the hit identifier portion of the second storage unit 141. It is understood that the hit identifier portion of the second storage unit 141 can be updated at the same time as writing the data of the second storage unit 141 into the storage array, or after the data of the second storage unit 141 is written into the storage array 11.
[0050] In practice, the processing module 13 can complete the update operation of the cache module 14 within one clock cycle, and the preparation of key data is completed before entering the next clock cycle, thereby shortening the overall processing delay.
[0051] In some implementations, writing the data from the second storage unit 141 to the storage array 11 and determining the hit result of the first query data can be performed simultaneously, so that reading and writing of the storage array 11 can be achieved within the same timeframe.
[0052] In some implementations, the processing module 13 is further configured to update the content portion of the second storage unit 141 with the first query data and update the hit result of the first query data with the hit flag portion of the second storage unit 141. Specifically, updating the hit flag portion and content portion of the second storage unit 141 to the content of the current query data within one clock cycle allows the caching module to reflect the current query status in real time, providing more accurate data support for subsequent queries and improving cache utilization.
[0053] The address generation module 15 is primarily used to allocate an available address, which is the address of a first storage cell 111 of the storage array 11. The address generation module 15 can be any suitable hardware module capable of implementing this function, such as a register. In some embodiments, the address generation module 15 can maintain all addresses of the entire storage array 11 and record the state (i.e., empty or not empty) of the first storage cell 111 corresponding to each address. In some embodiments, the address generation module 15 can record only the address of the first empty first storage cell 111 or the addresses of all empty first storage cells 111 in the storage array 11. In some embodiments, the address generation module 15 can record the addresses of each non-empty first storage cell 111.
[0054] In some implementations, if the first query data hit result indicates a hit, it means that the first query data already exists in the storage array 11. Therefore, in the second cycle, it is not necessary to write the first query data into the storage array 11. At this time, the address generation module 15 does not need to be updated.
[0055] In some implementations, if the first query result indicates a miss, it means that the first query data does not exist in the storage array 11. Then, in the second cycle, the address portion of the second storage unit 141 can be obtained, and the first query data can be stored in the first storage unit 111 pointed to by that free address. This allows the write operation of the miss data to be completed within the second cycle, enabling the entire query-write process to be completed within two consecutive cycles, thus improving the system's throughput. At this point, the address generation module needs to be updated.
[0056] For example, if the address generation module 15 records the addresses of all empty first storage units 111, then the address corresponding to the first query data needs to be deleted from the address generation module 15.
[0057] For example, the address generation module 15 only records the address of the first empty first storage cell 111 in the storage array. At this time, the address recorded by the address generation module 15 is updated to the address of the next first empty first storage cell 111.
[0058] For example, the address generation module 15 records the addresses of each non-empty first storage unit 111. In this case, the address of the first query data can be added to the address generation module 15.
[0059] For example, the address generation module 15 maintains all addresses of the entire storage array 11. In this case, the state of the first storage unit 111 corresponding to the address of the first query data can be updated to non-empty.
[0060] In digital chips, the timing path consists of a start point, interconnect delay, cell delay, and end point. The start point is the time when data is loaded by the clock edge, while the end point is the time when data is loaded by another clock edge after passing through combinational logic. The path from the start point to the end point is called the data path (or critical path). In implementation, this disclosure divides the original data path in the CAM into two segments by adding a cache module. One segment starts from the input of the first query data, passes through the judgment module to determine the hit result, and finally reaches the cache module. The other segment starts from the cache module, flows to the address generation module, and finally reaches the memory array. This greatly reduces the amount of operations that need to be completed in each clock cycle, enabling the CAM to better adapt to high clock frequency operating environments.
[0061] In this embodiment, on the one hand, by adding a cache module to cache query data and the address corresponding to the query data, queries are performed on both the storage array and the cache module within the same clock cycle, improving the efficiency and accuracy of data query and compensating for the data write latency caused by the newly added cache module. On the other hand, by writing the missing query data into the storage array in the next clock cycle, the data path of the relevant CAM is effectively segmented. That is, the query and hit result judgment of the data in the storage array are realized within the same clock cycle, and the missing data in the cache module is written into the storage array in the next clock cycle, shortening the critical path length, effectively reducing the amount of operations that need to be completed in each clock cycle, reducing timing pressure and speeding up processing speed. This can meet the stringent requirements for real-time data storage and retrieval under high-frequency clock cycles, thereby improving the stability and reliability of the CAM.
[0062] In some embodiments, the second storage unit 141 includes a hit identifier portion, an address portion, and a content portion. The processing module 13 is further configured to, within the first cycle, obtain the hit result of the second query data from the hit identifier portion of the second storage unit 141, and if the hit result of the second query data indicates a miss, write the second query data in the content portion of the second storage unit 141 to the address in the address portion of the second storage unit 141; wherein the second query data is data received in the third cycle, and the third cycle is the cycle preceding the first cycle.
[0063] Here, in the clock cycle before receiving the first query data, CAM also receives the second query data. It's understandable that if the first clock cycle could be the i-th cycle, then the third clock cycle could be the (i-1)-th cycle.
[0064] This hit flag is used to record the hit result of the query data, that is, whether the query data exists in the storage array. In implementation, the hit result stored in this hit flag can be used to determine whether to perform the subsequent write operation of writing the second query data to the storage array 11.
[0065] The address portion is used to store the address of an empty first storage unit 111. In implementation, if the hit result of the second query data indicates a hit, it means that the storage array 11 already contains the second query data, and therefore, no further write operation is required; if the hit result of the second query data indicates a miss, it means that the storage array 11 does not contain the second query data, and therefore, the address stored in the address portion will be extracted to perform the subsequent write operation.
[0066] The content section is used to store query data. In implementation, if the hit result of the second query data indicates a match, the data stored in the content section will not be retrieved; conversely, if the hit result of the second query data indicates a miss, the second query data stored in the content section will be retrieved and written to the storage array to complete the data update.
[0067] During implementation, within the same time frame, before updating the second storage unit 141, it can be determined whether the second query data stored in the second storage unit 141 needs to be stored in the storage array 11.
[0068] In this embodiment, on the one hand, by introducing a hit flag, it is possible to quickly determine whether the second query data has a hit within the first cycle, avoiding unnecessary data read or write operations, further reducing resource waste and improving system response speed. On the other hand, by introducing an address flag, in the event of a data miss, the stored address can be used directly without needing to obtain the address from the address generation module, thus improving data processing efficiency. Furthermore, before updating the second storage unit, a hit flag check and write operation are performed, forming a closed-loop data processing chain, namely: data is received in the third cycle, and a hit check and data writing are performed in the first cycle. The precise timing between each cycle ensures the timeliness and consistency of the data, thereby improving operating performance, stability, and responsiveness.
[0069] In some implementations, the processing module 13 is further configured to determine the address corresponding to the first query data from at least one address in the address generation module 15; and update the address corresponding to the first query data to the address portion of the second storage unit 141.
[0070] Here, the address generation module 15 can maintain all addresses of the entire storage array 11, and can also record the addresses of all empty first storage units 111. In some embodiments, the address of the first empty first storage unit 111 can be used as the address corresponding to the first query data. In practice, within the first cycle, the address corresponding to the first query data is updated to the address portion of the second storage unit 141 in a timely manner to ensure the continuity and consistency of subsequent data access.
[0071] In the disclosed implementation, the address generation module assists in selecting a free address and updates the address portion of the second storage unit in a timely manner, ensuring the accuracy of subsequent write operations, avoiding address conflicts, and improving the stability and reliability of the system.
[0072] In some implementations, when the hit result of the second query data indicates a hit, the processing module 13 is further configured to use the address in the address portion of the second storage unit 141 as the address corresponding to the first query data.
[0073] Here, when the hit result of the second query data indicates a hit, it means that the second query data already exists in the storage array 11. At this time, there is no need to regenerate a new address, but the address in the second storage unit 141 can be directly reused, that is: the address part of the address of the second storage unit 141 is directly used as the address corresponding to the first query data.
[0074] In the disclosed implementation, when the second query data is matched, there is no need to generate a new address; the existing address can be reused directly, saving the computational overhead of address generation, speeding up the processing flow, and thus improving the overall system response efficiency and resource utilization.
[0075] In some embodiments, the content-addressable memory 10 further includes an output module, which is used to output the hit result of the first query data; and when the hit result of the first query data indicates a hit, it outputs the address corresponding to the first query data.
[0076] Here, the output module is mainly used to provide feedback on the query results. These results can include, but are not limited to, hit results and addresses. The output module can be any suitable hardware circuit or interface capable of implementing this function. In implementation, the output module determines whether the first query data hits the CAM, and if it does, returns the address corresponding to the first query data to speed up data reading. It is understood that if the first query data does not hit the CAM, only the second hit result is output.
[0077] This output module may include a hit result output interface and an address output interface. The hit result output interface is used to output the hit result. The address output interface is used to output the address corresponding to the first query data when the hit result indicates a hit.
[0078] As a crucial component of the CAM (Computer-Aided Query), the output module enables efficient communication between the CAM and external systems by promptly providing feedback on the hit results and address information of the query data. In practical implementation, the output module plays a pivotal role in the entire query process. Upon receiving the hit result of the first query, the output module outputs the address corresponding to the hit query data within the first cycle, providing a basis for subsequent data access requests and other processing logic.
[0079] In the disclosed implementation, an external interface is implemented through an output module, which facilitates external devices to obtain query results and address information, thereby improving the availability and scalability of the system.
[0080] Based on the above embodiments, this disclosure also provides a data processing method. The method provided by this disclosure can be executed by an electronic device, which can be a laptop, tablet, desktop computer, set-top box, mobile device (e.g., mobile phone, portable music player, personal digital assistant, dedicated messaging device, portable gaming device), or other types of terminal. It can also be implemented as a server. The server can be an independent physical server, a server cluster or distributed system composed of multiple physical servers, or a cloud server providing basic cloud computing services such as cloud services, cloud databases, cloud computing, cloud functions, cloud storage, network services, cloud communication, middleware services, domain name services, security services, content delivery networks (CDN), and big data and artificial intelligence platforms. The electronic device includes at least any of the foregoing CAM components. Figure 2 As shown, the data processing method includes steps S21 and S23, wherein: Step S21: Within the first frame, the judgment module determines the hit result of the first query data based on the first query data and the data in at least one target storage unit; wherein, the target storage unit includes one of the following: a non-empty first storage unit, a non-empty second storage unit; Step S22: Within the first frame, the processing module updates the second storage unit based on the first query data and the address corresponding to the first query data; wherein, the address corresponding to the first query data is the address of an empty first storage unit in the storage array, and the address corresponding to the first query data is determined based on the second storage unit and the address generation module; Step S23: In the second cycle, if the hit result of the first query data indicates a miss, the processing module writes the first query data to the address corresponding to the first query data; wherein, the second cycle is the cycle following the first cycle.
[0081] In some implementations, the determination module includes a comparison module and a hit determination module; step S11 includes steps S211 and S212, wherein: Step S211: In the first cycle, the comparison module compares the first query data and the data in each target storage unit in parallel to obtain the comparison result of each target storage unit. Step S212: Within the first frame, the hit determination module determines the hit result of the first query data based on the comparison result of each target storage unit.
[0082] In some embodiments, step S211 includes step S2111, wherein: Step S2111: For each target storage unit, the comparison module compares the data in the content portion of the target storage unit with the first query data to obtain the comparison result of the target storage unit.
[0083] In some embodiments, step S2111 includes steps S21111 and S21112, wherein: Step S21111: If the data in the content portion of the target storage unit is the same as the first query data, the comparison module uses the first comparison result as the comparison result of the target storage unit.
[0084] Step S21112: If the data in the content portion of the target storage unit is different from the first query data, the comparison module uses the second comparison result as the comparison result of the target storage unit.
[0085] In some embodiments, step S212 includes steps S2121 and S2122, wherein: Step S2121: If the comparison result of any target storage unit is the first comparison result, the hit determination module takes the first hit result as the hit result of the first query data; wherein, the first hit result represents a hit. Step S2122: When the comparison result of each target storage unit is the second comparison result, the hit judgment module uses the second hit result as the hit result of the first query data; wherein, the second hit result indicates a miss.
[0086] In some implementations, the second storage unit includes a hit identifier portion, an address portion, and a content portion. Before updating the second storage unit, the data processing method further includes step S241, wherein: Step S241: In the first cycle of the processing module, the hit result of the second query data is obtained from the hit identifier part of the second storage unit, and if the hit result of the second query data indicates a miss, the second query data in the content part of the second storage unit is written to the address in the address part of the second storage unit; wherein, the second query data is the data received in the third cycle, and the third cycle is the cycle before the first cycle.
[0087] In some implementations, when the hit result of the second query data indicates a hit, the data processing method further includes step S242, wherein: Step S242: The processing module uses the address in the address portion of the second storage unit as the address corresponding to the first query data.
[0088] In some implementations, after writing the second query data, the data processing method further includes steps S251 and S252, wherein: Step S251: The processing module determines the address corresponding to the first query data from at least one address in the address generation module; Step S252: The processing module updates the address corresponding to the first query data to the address portion of the second storage unit.
[0089] In some embodiments, the data processing method further includes step S253, wherein: Step S253: The processing module updates the first query data to the content part of the second storage unit and stores the hit result of the first query data in the hit identifier part of the second storage unit.
[0090] In some embodiments, the content-addressable memory further includes an output module, and the data processing method further includes steps S261 and S262, wherein: Step S261: The output module outputs the hit results of the first query data; Step S262: If the hit result of the first query data indicates a hit, the output module outputs the address corresponding to the first query data.
[0091] The description of the above method embodiments is similar to that of the above memory embodiments, and has similar beneficial effects. For technical details not disclosed in the method embodiments of this disclosure, please refer to the description of the memory embodiments of this disclosure for understanding.
[0092] The technical solutions provided in the embodiments of this disclosure are described in detail below.
[0093] In the current environment of ever-increasing chip clock frequencies, CAM design in related technologies has revealed significant limitations. As clock frequencies rise, the timing requirements within the chip become more stringent, and related CAM designs struggle to meet these stringent requirements. Specifically, related CAMs face increasing difficulties in performing operations such as polling, hit / miss checks, new write address calculations, and data writing.
[0094] From the perspective of query operations, due to the increase in clock frequency, data matching and searching need to be completed in a shorter time. The matching speed and efficiency of the related design are difficult to adapt to this change, which may lead to the query results not being output in a timely manner, affecting the overall system speed.
[0095] In terms of hit / miss judgment, the relevant design may lack efficient logic circuits to quickly determine whether the queried data exists in the CAM, which increases the time consumption of the judgment process and cannot meet the real-time requirements under high-frequency clock.
[0096] For new write address calculation and data write operations, the complexity of address calculation and the timing requirements of data write increase significantly with the increase of clock frequency. Related designs may fail to accurately calculate the new write address within the specified clock cycle, and timing conflicts may easily occur during data write, leading to data write failure or errors.
[0097] This disclosure aims to address the aforementioned challenges faced by CAM designs at high clock frequencies. Specifically, the goal is to design a novel CAM architecture that avoids timing conflicts and data write errors, thereby improving the stability and reliability of the entire CAM system under high-frequency conditions. Against the backdrop of continuously increasing digital chip frequencies, this disclosure overcomes the shortcomings of existing REG-based CAMs, such as timing delays and insufficient logic processing speed, by achieving high-speed and synchronized implementation of the following key functions: High-speed query address mapping: Within a high-frequency clock cycle, it accurately and quickly completes the mapping and matching between query data and storage address, realizing real-time location of target data address; Real-time existence determination: Synchronously complete the logical determination of whether the query data is stored in the CAM, and ensure that the existence signal is output within the same time frame of obtaining the query result; Dynamic blank address writing: If it is determined that the query data is not stored in the CAM, based on the blank address information detected in real time, the query data is written to the target blank address in a timely and accurate manner under high frequency timing, so as to avoid data writing failure or address conflict caused by processing delay.
[0098] This disclosure aims to improve the data processing efficiency and response speed of CAM in high-frequency scenarios, realize the full-process pipeline of query, judgment and write operations, and meet the stringent requirements of high-speed digital systems for real-time data storage and retrieval.
[0099] like Figure 3 As shown, in the field of modern integrated circuit design, the increase in clock frequency places higher demands on circuit performance. The CAM structure in related technologies faces severe challenges in this context. The data path (credit path) in the related CAM structure is marked by curve 30. From the starting point of this path, data must sequentially flow through the polling comparison circuit, the hit / miss judgment circuit, and the data writing circuit. These three critical paths constitute a complete operation flow. However, as the circuit clock frequency continues to increase, completing all the above operations within a single clock cycle becomes increasingly difficult. This is because high clock frequencies shorten the available time for each operation step, and the inherent delays and complexity of these critical paths in the related CAM structure make it difficult for them to complete all tasks in such a short time, thus limiting the performance and efficiency of the entire CAM in high-frequency environments. This limitation not only affects the speed of data processing but may also lead to timing errors in the system, thereby reducing the stability and reliability of the system.
[0100] This disclosure provides an innovative CAM structure designed to address the problem that existing CAM structures struggle to complete operations such as polling, hit / miss judgment, and data writing within a single clock cycle at high clock frequencies. The complete technical solution of this disclosure is as follows: exist Figure 3 Based on the relevant CAM structure shown, such as Figure 4 As shown, this disclosure adds a register group 44 (corresponding to the aforementioned cache module). The bit width of register group 44 is designed to be the sum of the address and data bit widths of memory array 11 plus 1 bit. Its main function is to cache the output of hit / miss lookup results. In this way, the length of the original data path (credit path) is effectively shortened, dividing the current data path within the CAM into two segments: The first critical path 401: Starting from the beginning of the data path, the data flows sequentially through the query comparison circuit (corresponding to the aforementioned comparison module) and finally reaches the answer store 44 (corresponding to the aforementioned cache module).
[0101] The second critical path 402: Starting from the answer store 44 (corresponding to the aforementioned cache module), the data continues to flow to the hit / miss judgment circuit (corresponding to the aforementioned hit judgment module) and the data writing circuit 45 (corresponding to the aforementioned address generation module).
[0102] Therefore, the data processing workflow needs to be adjusted: Because a new register has been added, data cannot be directly written to the memory array within a single clock cycle, preventing the original circuit from completing all its functions within that cycle. To address this issue, this disclosure employs the following improved data query and processing method: Joint query mechanism The addresses and data stored in the answer store are queried together with the existing storage array. Specifically, different processing strategies are used for the storage array and the answer store during the query process: Querying the storage array: When querying the storage array, the corresponding address information can be obtained by using the registers of the storage array, thereby achieving accurate location and query of data in the storage array.
[0103] Querying the answer store: When querying the answer store, if a DATA miss occurs, the value at the address where the answer store is also stored can be used directly. This simplifies the query process and improves data processing efficiency.
[0104] Through the above structural improvements and adjustments to the data processing flow, the CAM structure disclosed herein has the following advantages at high clock frequencies: Path splitting optimizes timing: The original data path is split into two segments, which effectively reduces the amount of operations that need to be completed in each clock cycle, reduces timing pressure, and enables the circuit to better adapt to high clock frequency operating environments.
[0105] Joint queries improve efficiency: By employing a joint query mechanism, queries are performed simultaneously on the storage array and the answer store, and differentiated query strategies are used for different storage areas. This improves the efficiency and accuracy of data queries, compensates for the data write latency caused by the addition of registers, and ensures that the entire CAM can still operate stably and efficiently at high frequencies.
[0106] It should be noted that, in the embodiments of this disclosure, if the above methods are implemented as software functional modules and sold or used as independent products, they can also be stored in a computer-readable storage medium. Based on this understanding, the technical solutions of the embodiments of this disclosure, or the parts that contribute to related technologies, can be embodied in the form of a software product. This software product is stored in a storage medium and includes several instructions to cause an electronic device (which may be a personal computer, server, or network device, etc.) to execute all or part of the methods described in the various embodiments of this disclosure. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), magnetic disks, or optical disks. Thus, the embodiments of this disclosure are not limited to any specific hardware and software combination.
[0107] This disclosure provides an electronic device including any of the above-described CAMs.
[0108] It should be noted that the description of the above device embodiments is similar to the description of the above memory embodiments, and has similar beneficial effects. For technical details not disclosed in the device embodiments of this disclosure, please refer to the description of the memory embodiments of this disclosure for understanding.
[0109] It should be understood that the phrase "an embodiment" or "one embodiment" throughout the specification means that a specific feature, structure, or characteristic related to the embodiment is included in at least one embodiment of this disclosure. Therefore, "in one embodiment" or "one embodiment" appearing throughout the specification does not necessarily refer to the same embodiment. Furthermore, these specific features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. It should be understood that in the various embodiments of this disclosure, the sequence numbers of the above-described processes do not imply a sequential order of execution; the execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this disclosure. The sequence numbers of the above-described embodiments are for descriptive purposes only and do not represent the superiority or inferiority of the embodiments.
[0110] It should be noted that, in this document, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Unless otherwise specified, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element.
[0111] In the several embodiments provided in this disclosure, it should be understood that the disclosed devices and methods can be implemented in other ways. The device embodiments described above are merely illustrative. For example, the division of units is only a logical functional division, and in actual implementation, there may be other division methods, such as: multiple units or components may be combined, or integrated into another system, or some features may be ignored or not executed. In addition, the coupling, direct coupling, or communication connection between the various components shown or discussed may be through some ports, and the indirect coupling or communication connection between devices or units may be electrical, mechanical, or other forms.
[0112] The units described above as separate components may or may not be physically separate. The components shown as units may or may not be physical units. They may be located in one place or distributed across multiple network units. Some or all of the units may be selected to achieve the purpose of this embodiment according to actual needs.
[0113] In addition, each functional unit in the embodiments of this disclosure can be integrated into one processing unit, or each unit can be a separate unit, or two or more units can be integrated into one unit; the integrated unit can be implemented in hardware or in the form of hardware plus software functional units.
[0114] Those skilled in the art will understand that all or part of the steps of the above method embodiments can be implemented by hardware related to program instructions. The aforementioned program can be stored in a computer-readable storage medium. When the program is executed, it performs the steps of the above method embodiments. The aforementioned storage medium includes various media that can store program code, such as mobile storage devices, read-only memory (ROM), magnetic disks, or optical disks.
[0115] Alternatively, if the integrated units described above are implemented as software functional modules and sold or used as independent products, they can also be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this disclosure, in essence or the part that contributes to related technologies, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause an electronic device (which may be a personal computer, server, or network device, etc.) to execute all or part of the methods described in the various embodiments of this disclosure. The aforementioned storage medium includes various media capable of storing program code, such as mobile storage devices, ROM, magnetic disks, or optical disks.
[0116] The above description is merely an embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any changes or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure.
Claims
1. A content-addressable memory, characterized in that, It includes a storage array having at least one first storage unit, a judgment module, a processing module, a cache module having a second storage unit, and an address generation module, wherein the bit width of the second storage unit is greater than the bit width of the first storage unit, wherein: The judgment module is used to determine the hit result of the first query data within the first cycle, based on the first query data and the data in at least one target storage unit; wherein, the target storage unit includes one of the following: a non-empty first storage unit and a non-empty second storage unit; The processing module is used to update the second storage unit within the first frame based on the first query data and the address corresponding to the first query data; wherein the address corresponding to the first query data is the address of an empty first storage unit in the storage array, and the address corresponding to the first query data is determined based on the second storage unit and the address generation module; The processing module is further configured to, within the second cycle, write the first query data to the address corresponding to the first query data if the hit result of the first query data indicates a miss; wherein the second cycle is the cycle following the first cycle.
2. The content-addressable memory according to claim 1, characterized in that, The second storage unit includes a hit identifier portion, an address portion, and a content portion. The processing module is further configured to, within the first phase, obtain the hit result of the second query data from the hit identifier portion of the second storage unit, and if the hit result of the second query data indicates a miss, write the second query data in the content portion of the second storage unit to the address in the address portion of the second storage unit; wherein the second query data is data received in the third phase, and the third phase is the phase preceding the first phase.
3. The content-addressable memory according to claim 2, characterized in that, The processing module is further configured to determine the address corresponding to the first query data from at least one address in the address generation module; and update the address corresponding to the first query data to the address portion of the second storage unit.
4. The content-addressable memory according to claim 2 or 3, characterized in that, In the case where the hit result of the second query data indicates a hit, The processing module is further configured to use the address in the address portion of the second storage unit as the address corresponding to the first query data.
5. The content-addressable memory according to any one of claims 2 to 4, characterized in that, The processing module is further configured to update the first query data to the content portion of the second storage unit, and update the hit result of the first query data to the hit identifier portion of the second storage unit.
6. The content-addressable memory according to any one of claims 1 to 5, characterized in that, The judgment module includes a comparison module and a hit judgment module; The comparison module is used to compare the first query data and the data in each of the target storage units in parallel within the first phase, and obtain the comparison result of each target storage unit. The hit determination module is used to determine the hit result of the first query data based on the comparison result of each target storage unit within the first frame.
7. The content-addressable memory according to claim 6, characterized in that, The comparison module is further configured to, when the data in the target storage unit is the same as the first query data, use the first comparison result as the comparison result of the target storage unit; If the data in the target storage unit is different from the first query data, the second comparison result shall be used as the comparison result of the target storage unit.
8. The content-addressable memory according to claim 6 or 7, characterized in that, The hit determination module is further configured to, when the comparison result of any of the target storage units is a first comparison result, use the first hit result as the hit result of the first query data; wherein, the first hit result indicates a hit; and when the comparison result of each of the target storage units is a second comparison result, use the second hit result as the hit result of the first query data; wherein, the second hit result indicates a miss.
9. The content-addressable memory according to any one of claims 1 to 8, characterized in that, The address portion of the second storage cell has the same bit width as the address portion of the first storage cell, the content portion of the second storage cell has the same bit width as the content portion of the first storage cell, and the hit flag portion of the second storage cell has a bit width of not less than one bit.
10. The content-addressable memory according to any one of claims 1 to 9, characterized in that, The content-addressable memory also includes an output module; The output module is used to output the hit result of the first query data; if the hit result of the first query data indicates a hit, it outputs the address corresponding to the first query data.
11. A data processing method, characterized in that, The method is applied to a content-addressable memory (CNTM), which includes a storage array with at least one first storage unit, a judgment module, a processing module, a cache module with a second storage unit, and an address generation module. The bit width of the second storage unit is greater than the bit width of the first storage unit. The data processing method includes: Within the first cycle, the judgment module determines the hit result of the first query data based on the first query data and the data in at least one target storage unit; wherein, the target storage unit includes one of the following: a non-empty first storage unit and a non-empty second storage unit; Within the first frame, the processing module updates the second storage unit based on the first query data and the address corresponding to the first query data; wherein, the address corresponding to the first query data is the address of an empty first storage unit in the storage array, and the address corresponding to the first query data is determined based on the second storage unit and the address generation module; In the second cycle, if the hit result of the first query data indicates a miss, the processing module writes the first query data to the address corresponding to the first query data; wherein, the second cycle is the cycle following the first cycle.
12. An electronic device, characterized in that, Includes the content-addressable memory according to any one of claims 1 to 10.