Training method and device of fixed step length prefetcher based on instruction address

Abstract

The invention relates to a training method and device for a fixed-step-length prefetcher based on an instruction address, and the method comprises the steps: judging whether a memory access operation request hits a storage entry in the fixed-step-length prefetcher based on the instruction address or not according to a tag array after the memory access operation request is received, the tag array stores tags and states of storage entries; if the memory access operation request hits the storage entry, reading load information of the hit storage entry in the state from a load array according to the state of the hit storage entry; when the state of the hit storage entry is a prefetching state, generating a prefetching request according to the load information and executing the prefetching request on an assembly line; when the state of the hit storage entry is a training state, updating the state of the storage entry and the load information; and when the state of the hit storage entry is a non-fixed step length state, directly skipping. According to the method, invalid training of the fixed step size prefetcher based on the instruction address can be reduced.

Description

Technical Field

[0001] This application relates to the branch prediction computation domain, and more particularly to a training method and apparatus for a fixed step size prefetcher based on instruction address. Background Technology

[0002] To improve CPU (Central Processing Unit) efficiency, the Load Store Unit (LSU) (the CPU's internal execution unit responsible for processing stored instructions, typically including an L1 cache) usually implements a hardware prefetch module. This module pre-fetches the data needed by the currently executing program flow into the data cache, thereby improving memory access speed. To achieve this, the hardware prefetch module needs to predict future access addresses based on the current address sequence. A common type of hardware prefetcher is called a RIP-based stride prefetcher. By tracking the memory access patterns corresponding to instruction addresses (RIPs), when it is found that memory is read and written sequentially in an increasing or decreasing order with fixed address increments, the fixed-step prefetcher based on RIPs enters the "prefetch" state after recognizing such access sequences during the "training" phase: it sends the next access request to the downstream in advance according to the increasing or decreasing sequence. Traditional solutions continuously train all RIPs, but the memory access sequences of many RIPs cannot naturally form a fixed-step pattern, resulting in invalid training and wasting power consumption and computing power.

[0003] Therefore, there is an urgent need for a solution to reduce the invalid training of RIP-based fixed-step prefetchers without increasing additional storage. Summary of the Invention

[0004] To address the problems existing in the prior art, this application provides a training method and apparatus for a fixed-step prefetcher based on instruction address, which dynamically identifies and marks non-fixed-step pattern RIPs without increasing additional storage, thereby reducing invalid training of RIP-based fixed-step prefetchers.

[0005] The specific technical solutions of this application embodiment are as follows: On one hand, embodiments of this application provide a training method for a fixed-step prefetcher based on instruction addresses, the method comprising: Upon receiving a memory access request, the system determines whether the memory access request hits a memory entry in the fixed-step prefetcher based on the instruction address, according to the tag array. The tag array stores the tag and status of the memory entry. If the memory access operation request hits a storage entry, the load information of the hit storage entry in that state is read from the load array according to the state of the hit storage entry; When the hit storage entry is in the prefetch state, a prefetch request is generated based on the payload information and executed in the pipeline; when the hit storage entry is in the training state, the state and payload information of the storage entry are updated; when the hit storage entry is in the non-fixed step state, it is skipped directly.

[0006] In one embodiment, the payload array corresponds one-to-one with the storage entries involved in the tag array, and the payload array stores the payload information of the storage entries. The payload information of each storage entry only includes the payload domain that needs to be considered in the state of the storage entry in the tag data.

[0007] In one embodiment, the payload field of the prefetch state's stored entry includes step size, confidence level, base address, and access vector; The payload field of the storage entry in the training state includes address difference, address difference valid identifier, previous address, same difference counter and different difference counter.

[0008] In one embodiment, when the state of a hit stored entry is in a prefetch state, a prefetch request is generated based on the payload information and executed on the pipeline, including: The payload information of the hit storage entry is decoded according to the prefetch state to obtain the payload field of the hit storage entry; Find the bit in the access vector corresponding to the address in the current memory access request and set that bit to 1; Update the confidence level based on the access vector; Update the base address and access vector based on the offset between the address and the base address in the current memory access request; Generate prefetch address and prefetch request: Calculate the prefetch address based on the address, step size, and confidence level in the current memory access operation request, and generate a prefetch request after filtering the prefetch address based on the access vector. The pipeline loads the prefetch request onto the storage unit; The prefetch request is executed in the pipeline.

[0009] In one embodiment, updating the confidence level based on the access vector includes: Count the number of bits that are 1 in the access vector; If the number is greater than the first threshold, increment the confidence level by 1; if the confidence level exceeds the maximum confidence level, set the confidence level to the maximum confidence level. If the quantity is less than the second threshold, the confidence level is reduced by 1; if the confidence level is less than or equal to 0, the confidence level is set to 0. Otherwise, keep the confidence level unchanged.

[0010] In one embodiment, the method further includes: When the state of the hit storage entry is in the prefetch state, the number of bits with a confidence level of 1 and a value of 1 in the access vector is less than the second threshold, and the state of the storage entry is changed to the training state.

[0011] In one embodiment, determining the address window width includes: Set the address window width to a fixed value, or determine the address window width based on the confidence level, or determine the address window width based on the step size.

[0012] In one embodiment, updating the base address and access vector based on the offset between the address in the current memory access request and the base address includes: If the offset is greater than or equal to a preset multiple of the step size, it is determined that the storage entry needs to be refreshed, the access vector is cleared to zero, and the base address is updated according to the following formula: BaseAddr + W × Stride, where BaseAddr is the base address, W is the address window width, and Stride is the step size; If the offset is less than a preset multiple of the step size, the base address and access vector remain unchanged.

[0013] In one embodiment, generating a prefetch request after filtering prefetch addresses based on access vectors includes: If the bit value of the access vector corresponding to the prefetch address is 1, skip the prefetch address, obtain the address of the next step offset of the prefetch address, and generate a prefetch request; Alternatively, instead of filtering by access vector, a prefetch request can be generated directly using the prefetch address; Alternatively, a prefetch request can be generated after filtering the prefetch addresses using the access vector.

[0014] In one embodiment, the pipeline that loads the prefetch request onto the storage unit includes: If the pipeline of the load storage unit is idle, the prefetch request will be directly pipelined through arbitration; If the pipeline of the load storage unit is busy, the prefetch request is stored in the prefetch request queue, and the pipeline is selected from the prefetch request queue when the load storage unit is idle.

[0015] In one embodiment, when the state of the hit storage entry is in the training state, the state and payload information of the storage entry are updated, including: The payload information of the hit storage entry is decoded according to the training state to obtain the payload domain of the hit storage entry; Calculate the difference between the address in the current memory access request and the address in the previous request, and use it as the current address difference; If the address difference valid flag is 0, update the previous address to the address in the current memory access operation request, update the address difference to the current address difference, and set the address difference valid flag to 1; If the address difference is marked as valid (1), the status and load information of the storage entry are updated based on the current address difference and the load field of the hit storage entry.

[0016] In one embodiment, updating the status and load information of a storage entry based on the current address difference and the load field of the hit storage entry includes: If the current address difference is equal to the address difference, increment the same difference counter by 1, update the different difference counter, and check if the same difference counter has reached the first counter threshold. If the first calculator threshold is reached, it is determined that a fixed step size has been identified, the state of the hit stored entry is updated from the training state to the prefetch state, and the payload domain of the prefetch state is initialized. If the first calculator threshold is not reached, update the load information of the hit storage entry.

[0017] In one embodiment, updating the status and load information of a storage entry based on the current address difference and the load field of the hit storage entry includes: If the current address difference is not equal to the address difference, determine whether the current address difference meets the step size training requirements; If satisfied, update the address difference to the current address difference, update the previous address to the address in the current memory access operation request, increment the difference counter by 1, clear the difference counter to zero, and check if the difference counter has reached the second counter threshold. If the second calculator threshold is reached, it is determined that the address sequence corresponding to the RIP has no fixed step size, and the status of the hit storage entry is updated to the non-fixed step size state. If the second calculator threshold is not reached, update the load information of the hit storage entry; If the conditions are not met, update the load domain of the matched storage entry to the initial value of the training state.

[0018] In one embodiment, the method further includes: If the memory access request does not match a storage entry in the tag array, a new storage entry is allocated for the memory access request in the tag array; If the tag array is full, replace an existing tag array with a new tag array entry; If the label array is not full, initialize the state of the new storage entry to the training state, and initialize the payload information of the new storage entry in the training state.

[0019] In one embodiment, the method further includes: If the memory access request triggers a request in the missing status handling register, a new storage entry is allocated for the memory access request in the tag array.

[0020] In one embodiment, replacing an existing storage entry in the tag array with a new storage entry includes: The storage entries to be replaced are selected based on a round-robin algorithm, a least recently used algorithm, or a pseudo least recently used algorithm. Alternatively, select the storage entry with low confidence as the storage entry to be replaced; Alternatively, select one of the stored entries that is in the training state or the non-fixed step state as the stored entry to be replaced.

[0021] In one embodiment, the method further includes: When the state of the hit storage entry is a non-fixed step state, the number of times the storage entry in the tag array is hit is recorded by a global counter. Once the number of times a stored entry is hit reaches a threshold, the state of the stored entry is changed to training state.

[0022] On the other hand, embodiments of this application also provide a training apparatus for a fixed-step prefetcher based on instruction addresses, comprising: The hit determination module is used to determine, after receiving a memory access operation request, whether the memory access operation request hits a memory entry in the fixed step prefetcher based on the instruction address according to the tag array. The tag array stores the tag and status of the memory entry. The load reading module is used to read the load information of the hit storage entry in the state from the load array if the memory access operation request hits a storage entry, based on the state of the hit storage entry. The processing module is used to generate a prefetch request based on the payload information and execute it on the pipeline when the state of the hit storage entry is in the prefetch state; to update the state and payload information of the storage entry when the state of the hit storage entry is in the training state; and to skip directly when the state of the hit storage entry is in the non-fixed step size state.

[0023] On the other hand, embodiments of this application also provide a computer-readable storage medium storing a computer program that, when executed by a processor, implements the above-described method.

[0024] On the other hand, embodiments of this application also provide a computer program product, which includes a computer program that, when executed by a processor, implements the above-described method.

[0025] On the other hand, embodiments of this application also provide a computer program product, which includes a computer program that, when executed by a processor, implements the above-described method.

[0026] The proposed solution in this invention reduces invalid prefetching training, lowers power consumption and computational waste. In existing technologies, all RIPs (instruction addresses) are continuously trained, and the memory access sequences of a large number of RIPs naturally cannot form a fixed step size pattern, leading to invalid training and wasted resources. In this solution, when a memory access request hits a storage entry in a "non-fixed step size state," the training process is skipped directly, eliminating the need to repeatedly train RIPs that have been confirmed to have no fixed step size. This avoids unnecessary payload information reading, counter updates, and other operations, significantly reducing the invalid computational consumption of the prefetcher and lowering the dynamic power consumption of the hardware module, achieving the goal of reducing invalid training without increasing additional storage. This solution can accurately trigger prefetching and state management, improving prefetching efficiency and cache hit rate. When a storage entry in the prefetch state is hit, a prefetch request is generated based on the payload information, and the prefetch request must be executed through a pipeline. This prefetching based on a fixed step size after training can pre-fill data that has not been cached into the L1 cache, reducing cache miss latency in subsequent memory access operations and improving data access speed. When a storage entry in the training state is hit, the payload information is continuously updated to determine whether the RIP has formed a fixed step size. This ensures that prefetching is triggered only for regular memory access sequences, avoiding blind prefetching that reduces prefetch accuracy and further optimizing cache resource utilization. This solution optimizes hardware storage and pipeline resource utilization and reduces additional overhead. Traditional solutions, if additional storage is added to record non-fixed step size RIPs, will bring hardware storage and maintenance power consumption. This solution, through the design of a tag array and a payload array, where the tag array only stores entry tags and states, and the payload array only stores payload information, realizes on-demand allocation of storage resources without the need for additional storage. At the same time, through the logic of hit judgment-state branch processing, invalid requests are avoided from occupying pipeline resources, improving the overall operating efficiency of the LSU pipeline. Attached Figure Description

[0027] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the embodiments of this application. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0028] Figure 1 This is a flowchart illustrating a training method for a fixed-step prefetcher based on instruction address, as described in an embodiment of this application. Figure 2 This is a schematic diagram of the LSU structure in an embodiment of the present invention; Figure 3 This is a schematic diagram of the fixed step size data prefetcher based on RIP in an embodiment of the present invention; Figure 4 This is a schematic diagram of the tag array in an embodiment of the present invention; Figure 5 This is a schematic diagram of the load domain under different storage entry states in an embodiment of the present invention; Figure 6 This is a switching diagram of the three state transitions of the storage entry in an embodiment of the present invention; Figure 7 This is a schematic diagram of the training device for a fixed-step prefetcher based on instruction address in an embodiment of this application; Figure 8 The diagram shown is a structural schematic of a computer device in an embodiment of this application.

[0029] [Explanation of Figure Markers]: 701. Hit Detection Module; 702. Load reading module; 703. Processing module. Detailed Implementation

[0030] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the protection scope of the embodiments of this application.

[0031] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of the embodiments of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that embodiments of the present application described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion; for example, a process, method, apparatus, product, or device that includes a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or devices.

[0032] It should be noted that the acquisition, storage, use, and processing of data in the technical solutions of this application all comply with the relevant provisions of national laws and regulations.

[0033] It should be noted that in the embodiments of this application, certain software, components, models and other existing solutions in the industry may be mentioned. These should be regarded as exemplary and are only intended to illustrate the feasibility of implementing the technical solution of this application. However, it does not mean that the applicant has used or necessarily used the solution.

[0034] like Figure 1 This is a flowchart illustrating a training method for a fixed-step prefetcher based on instruction address, as described in an embodiment of this application. The method includes: S101, after receiving a memory access operation request, determine whether the memory access operation request hits a storage entry in the fixed step prefetcher based on the instruction address according to the tag array, wherein the tag array stores the tag and status of the storage entry; S102, if the memory access operation request hits a storage entry, the load information of the hit storage entry in the state is read from the load array according to the state of the hit storage entry; S103: When the state of the hit storage entry is the prefetch state, generate a prefetch request based on the payload information and execute it on the pipeline; when the state of the hit storage entry is the training state, update the state and payload information of the storage entry; when the state of the hit storage entry is the non-fixed step state, skip it directly.

[0035] The solution proposed in this application can reduce invalid training of the prefetcher, reduce power consumption and computing power waste. In the prior art, all RIPs (instruction addresses) are continuously trained, and the memory access sequences of a large number of RIPs cannot naturally form a fixed step size pattern, resulting in invalid training and wasted resources. In this solution, when a memory access request hits a storage entry in a "non-fixed step size state", the training process is skipped directly, and there is no need to repeat training on RIPs that have been confirmed to have no fixed step size. This avoids unnecessary operations such as load information reading and counter updates, significantly reducing the invalid computing power consumption of the prefetcher, and reducing the dynamic power consumption of the hardware module. This achieves the goal of reducing invalid training without increasing additional storage. This solution can accurately trigger prefetching and state management, improve prefetching efficiency and cache hit rate. When a storage entry in the prefetch state is hit, a prefetch request is generated based on the load information, and the prefetch request needs to be executed through the pipeline. This prefetching based on a fixed step size after training can fill the cache-missed data back into the L1 cache in advance, reduce the cache miss latency of subsequent memory access operations, and improve data access speed. When a storage entry in the training state is hit, the payload information is continuously updated to determine whether the RIP has formed a fixed step size. This ensures that prefetching is triggered only for regular memory access sequences, avoiding blind prefetching that reduces prefetch accuracy and further optimizing cache resource utilization. This solution optimizes hardware storage and pipeline resource utilization and reduces additional overhead. Traditional solutions, if additional storage is added to record non-fixed step size RIPs, will bring hardware storage and maintenance power consumption. This solution, through the design of a tag array and a payload array, where the tag array only stores entry tags and states, and the payload array only stores payload information, realizes on-demand allocation of storage resources without the need for additional storage. At the same time, through the logic of hit judgment-state branch processing, invalid requests are avoided from occupying pipeline resources, improving the overall operating efficiency of the LSU pipeline.

[0036] The method proposed in this embodiment of the invention is applied to a RIP-based fixed-step prefetcher in the load-store unit (LSU) of a CPU. Figure 2 This is a schematic diagram of the LSU structure in an embodiment of the present invention. See also... Figure 2 The structure of a conventional load-store unit (LSU) involves the following process for handling memory access instructions: First, the memory access operation instruction sent by the requester is stored in the read-write queue. The memory access operation instruction includes the memory access operation and the corresponding address. The memory access operation includes download operation and storage operation. In this embodiment of the invention, the load storage unit can be represented as LSU (Load-Store Unit), and the read-write queue (LSQ, Load-Store Queue) is used to temporarily store all the information required for the memory access operation.

[0037] Then, these memory access instructions are executed through the arbitration pipeline. The pipeline execution steps include: accessing the TLB (Translation Lookaside Buffer) to translate the address corresponding to the memory access operation to a physical address; accessing the tag array to determine whether the memory access operation hits the L1 cache; and executing the memory access operation based on the type of the memory access operation and the L1 cache hit result. Here, the TLB can be represented as a Translation Lookaside Buffer (TLB), the tag array as a Tag Array, and the address corresponding to the memory access operation as a virtual address. The TLB is essentially a high-speed cache that stores the mapping relationship between virtual address fragments and physical address fragments. When the LSU performs address translation, it first extracts the virtual address corresponding to the current memory access operation and uses its key fragment (such as the virtual page number) as a query condition to match all storage entries stored in the TLB. Only when a matching TLB storage entry is found through this virtual address fragment can the corresponding physical address fragment (such as the physical page number) be read from the storage entry, providing the basis for subsequently concatenating the complete physical address.

[0038] In specific implementation, the memory access operation is executed according to the type of memory access operation and the L1 cache hit result, including: If the type of memory access operation is a download operation and the first-level cache hit result is a hit, read the corresponding data of the memory access operation from the data cache and return it to the requester; If the type of memory access operation is a download operation and the result of the first-level cache hit is a miss, a read request is sent to the second-level cache, and the download operation is stored in the Miss Status Handling Register (MSHR). After the second-level cache returns data and the first-level cache is filled, the download operation is woken up from the Miss Status Handling Register and re-executed. If the type of memory access operation is a storage operation, and the first-level cache hit result is a hit, and the first-level cache is in an exclusive state, the data corresponding to the storage operation is directly written to the data cache. If the type of memory access operation is a storage operation, and the result of the L1 cache hit is a miss or the L1 cache does not meet the exclusive state, a read request is sent to the L2 cache, and the storage operation is stored in the missing state handling register. After waiting for the L2 cache to return data and fill the L1 cache, the storage operation is woken up from the missing state handling register and re-executed.

[0039] To improve cache hit rate, an HWPF (Hardware Prefetching) submodule can be integrated into the LSU module. This module takes memory access operation instructions from the pipeline as input, and its core objective is to identify regular sequences of memory access addresses. The streaming data prefetcher in the HWPF submodule is responsible for identifying streaming data sequences in memory accesses. Once the streaming data prefetcher has confirmed the identification of a streaming data sequence through "training," it enters the "prefetch" state and begins sending prefetch requests. Assuming the address in the prefetch request is a virtual address, the prefetch request, like the memory access operation request, also goes through arbitration before being piped. It accesses the TLB for address translation and checks the tag array to see if it hits the L1 cache. If it hits the L1 cache, no prefetching is needed; otherwise, a read request needs to be sent to the downstream L2 cache and stored in the MSHR. The prefetch request is completed when the downstream data returns and fills the L1 cache. Pipelining prefetch requests with the same address results in wasted power consumption and pipeline bandwidth.

[0040] To address the aforementioned issues, this invention proposes the following RIP-based fixed-step data prefetcher (which improves upon the execution flow of existing RIP-based fixed-step data prefetchers). Figure 3 This is a schematic diagram of the structure of a fixed-step data prefetcher based on RIP in an embodiment of the present invention. The core components include: a tag array, a payload array, an update logic unit, and a prefetch request logic unit. Figure 4This is a schematic diagram of the tag array in an embodiment of the present invention. The tag array stores the tags of storage entries and the status of storage entries. Its function is to determine whether a memory access operation request hits a storage entry and to obtain the current status of a storage entry. A storage entry is an independent storage unit in a fixed-step prefetcher based on a RIP. It corresponds to the tag array and the payload array and is the core carrier for the prefetcher to track the memory access pattern of a single instruction address (RIP) and implement the "training-prefetch-skip training" logic. The storage entry is strongly bound to the tag array and the payload array. The tag array stores the tags and status of each storage entry generated based on the RIP, and the corresponding storage entry in the payload array stores the exclusive payload information under that status. Together, they constitute a complete record of the memory access pattern of a single RIP. Tags are generated based on RIPs and can have different implementations: in some implementations, the tag is the complete RIP; in others, the tag is a partial RIP; and in still others, the tag is obtained from the hash value of the complete / partial RIP. Storage entry states include at least: training, trained, and non-stride. The training state indicates that the current storage entry is in the training phase and has not yet been trained to a fixed stride, or that the current address stream has not been confirmed to have a fixed stride. The prefetch state indicates that the current storage entry has completed training, has been trained to a fixed stride, and can begin generating prefetch requests. The non-stride state indicates that the current storage entry has been confirmed to have no fixed stride, and the training process is skipped upon a hit. Payload array: Corresponds one-to-one with the storage entries in the tag array. It is used to store the payload information of storage entries in different states. When storing, only the payload fields that need to be considered in the current storage entry state are retained (to save storage resources).

[0041] Update logic unit: responsible for completing step size training in training state and updating load information of stored items in each state.

[0042] Prefetch Request Logic Unit: Responsible for generating prefetch addresses and prefetch requests in the prefetch state, and managing the request sending process.

[0043] The tag array and payload array can be organized in either fully associative or multi-way group associative (depending on hardware resources and performance requirements).

[0044] Based on the above design, the specific steps for training a fixed-step prefetcher based on instruction addresses are given below: In step 101, after receiving a memory access operation request, it is determined whether the memory access operation request hits a memory entry in the fixed step prefetcher based on the instruction address according to the tag array. The tag array stores the tag and status of the memory entry. In practice, the prefetcher first generates a temporary tag based on the RIP in the request, according to the tag array generation rules (such as full RIP, partial RIP, or hash). Then, it compares this temporary tag with the tags stored in all storage entries in the tag array one by one. If they match, the storage entry is considered a hit, and its status is further confirmed. If they do not match, it is considered a miss, and a new storage entry needs to be allocated or the old one replaced according to the rules. Essentially, this process uses the tags associated with the RIP for comparison, rather than the request directly carrying pre-existing tags.

[0045] In step 102, if the memory access operation request hits a memory entry, the load information of the hit memory entry in that state is read from the load array according to the state of the hit memory entry; In one embodiment, the payload array corresponds one-to-one with the storage entries involved in the tag array, and the payload array stores the payload information of the storage entries. The payload information of each storage entry only includes the payload domain that needs to be considered in the state of the storage entry in the tag data.

[0046] In this embodiment of the invention, the load information of each state's storage entry only includes the load fields that the storage entry of that state needs to focus on, which can save storage. When storing, only the load field values ​​that need to focus on each state are saved, and the load field values ​​that do not need to be saved are removed. When reading the load of the storage entry, the load is decoded according to the different storage entry states to obtain each field value.

[0047] Through the above embodiments, when a memory access operation request hits a storage entry, the load information of the corresponding state can be directly read from the load array based on the state of the hit storage entry. This avoids unnecessary data lookup and processing, reduces data reading time, and improves memory access efficiency. The load array corresponds one-to-one with the storage entries in the tag array, and the load information of each storage entry only contains the load fields that the storage entry's state in the tag data needs to focus on. This design avoids storing unnecessary information and reduces storage resource consumption. Compared to storing complete load information, more effective data can be stored in the same storage space, improving the utilization rate of storage resources. This mechanism of reading specific load information based on the storage entry state allows the reader to flexibly adapt to different memory access modes and data processing needs. When new memory access operations or data processing logic need to be supported, only the load information of the corresponding state in the load array needs to be expanded or adjusted, without large-scale modifications to the entire storage structure, enhancing the system's scalability. Reducing unnecessary data reading and storage lowers the reader's power consumption. In hardware implementation, both data reading and storage operations consume energy; optimizing data reading and storage methods can effectively reduce system energy consumption.

[0048] In step 103, when the state of the hit storage entry is in the prefetch state, a prefetch request is generated based on the payload information and executed on the pipeline; when the state of the hit storage entry is in the training state, the state and payload information of the storage entry are updated; when the state of the hit storage entry is in the non-fixed step size state, it is skipped directly.

[0049] Figure 5 This is a schematic diagram of the load domain under different storage entry states in an embodiment of the present invention. See also... Figure 3 In one embodiment, the payload field of the prefetch state storage entry includes step size, confidence level, base address, and access vector; The payload field of the storage entry in the training state includes address difference, address difference valid identifier, previous address, same difference counter and different difference counter.

[0050] In this embodiment of the invention, the stride is a fixed stride trained on the storage entries, which is a fixed-length symbol number. Positive numbers correspond to sequentially increasing address access sequences, and negative numbers correspond to sequentially decreasing address access sequences. The address access sequence is a time series of addresses in consecutive memory access requests corresponding to the same RIP.

[0051] The confidence level (Conf) ranges from 0 to a maximum value (e.g., 3). When training is complete, Conf is set from 0 to 1. A higher confidence level indicates a greater number of hits in the address access sequence, thus leading to higher expected prefetch accuracy and allowing for larger prefetch address offsets. During prefetching, an address window with a step size of n times the confidence level exists, and this window can increase with the confidence level. When the address requested by the current memory access operation differs from the base address by more than or equal to n times the step size, the memory entry needs to be refreshed. If the number of accessed blocks recorded in the access vector (AccVec) exceeds the first threshold T... high If the number of accessed blocks recorded in AccVec is lower than the second threshold T, then increase the confidence level; low If the confidence level is lowered, then the confidence level is lowered; otherwise, the confidence level remains unchanged. BaseAddr is the base address, used to indicate the starting address of the step sequence; it is updated to the starting address of the next address window when training is completed and storage entries are refreshed, BaseAddr + W × Stride; here the address window width is W; Stride is the step size, W has three cases: (1) W can be a fixed value; (2) W can change with Conf, the larger Conf is, the larger W is; (3) W changes with Stride, the larger Stride is, the smaller W is. In order to reduce storage, the base address can only save the low-order address, and the high-order address can be padded to form a complete address by requesting the high-order address.

[0052] AccVec is the access vector, which is a bit vector with an effective width equal to the address window width W in the current state. AccVec is used to track whether a certain CL (cache line, i.e., the smallest granularity of data storage in the data cache) address has been accessed by request. Bit n corresponds to the address BaseAddr+(n+1)×Stride. When a corresponding address request occurs, the corresponding bit is set to 1, indicating that the address has been accessed. It is cleared when training is completed and storage entries are refreshed, and recording starts again. In this embodiment of the invention, the payload field of the storage entry in the prefetch state may also be increased with other payload fields, such as access pointers and prefetch pointers, to record the CL offset of the previous address or the prefetch address relative to the base address, depending on specific needs.

[0053] LastAddr is the address of the previous entry; when a storage entry is newly allocated or the load information is updated, LastAddr is updated to the address in the current memory access request; in order to reduce storage, LastAddr only stores the low-order bits of the address, so when Delta is calculated later, only the difference between the low-order bits of the address in the current memory access request and LastAddr is calculated. Delta is the address difference; that is, the difference between the address in the current memory access request and the address LastAddr of the previous access operation. DeltaVld is a valid identifier for address differences. When a storage entry is first allocated, DeltaVld = 0, and there is no valid Delta at this time. In addition, due to the limited width of Delta, when the difference between the address in the current memory access request and the address in the previous memory access request exceeds the range represented by the Delta width, DeltaVld is also 0; otherwise, DeltaVld is set to 1. The Delta width range refers to the range of address differences that can be represented by the binary number corresponding to the Delta width.

[0054] StrdHitCnt is a counter for identical differences; when DeltaVld is 1 and the difference between the address in the current memory access request and LastAddr is equal to Delta, StrdHitCnt = StrdHitCnt + 1; conversely, when the difference between the address in the current memory access request and LastAddr is not equal to Delta, StrdHitCnt is cleared to 0; when consecutive identical Deltas occur, causing StrdHitCnt to reach a certain threshold, it is considered that a fixed-step address access flow has been identified, and the storage entry status is updated to prefetch state; the confidence level is initialized to 1. StrdMisMchCnt is a difference counter; when DeltaVld is 1 and the difference between the address in the current memory access request and LastAddr is not equal to Delta, if the difference meets the step size training requirements, Delta is updated to the new difference; at the same time, StrdMisMchCnt is updated = StrdMisMchCnt + 1; otherwise, when the difference between the address in the current memory access request and LastAddr is equal to Delta, StrdMisMchCnt is cleared to 0; when consecutive differences occur... When the difference (lta) causes StrdMisMchCnt to reach a certain threshold, it is considered that the address access flow corresponding to the current RIP is not a fixed-stride address sequence, and the storage entry status is updated to non-stride. When the difference is equal to Delta, StrdMisMchCnt remains unchanged. When different differences accumulate to the point that StrdMisMchCnt reaches a certain threshold, it is considered that a fixed-stride address access flow has been identified, and the storage entry status is updated to non-stride. In this embodiment of the invention, a counter for different differences is stored in the idle bits of the reader, realizing the determination of non-stride patterns without increasing storage overhead.

[0055] In one embodiment, when the state of a hit stored entry is in a prefetch state, a prefetch request is generated based on the payload information and executed on the pipeline, including: The payload information of the hit storage entry is decoded according to the prefetch state to obtain the payload field of the hit storage entry; Find the bit in the access vector corresponding to the address in the current memory access request and set that bit to 1; Update the confidence level based on the access vector; Update the base address and access vector based on the offset between the address and the base address in the current memory access request; Generate prefetch address and prefetch request: Calculate the prefetch address based on the address, step size, and confidence level in the current memory access operation request, and generate a prefetch request after filtering the prefetch address based on the access vector. The pipeline loads the prefetch request onto the storage unit; The prefetch request is executed in the pipeline.

[0056] In the above embodiments, the mechanism of filtering prefetch addresses through access vectors generates prefetch requests only for addresses that have not been accessed. Simultaneously, the prefetch strategy is dynamically adjusted based on confidence levels, significantly reducing the proportion of invalid prefetches. This design avoids problems such as cache pollution and bus bandwidth consumption caused by blind prefetching, ensuring a high degree of match between prefetched data and actual needs. The prefetch address is calculated based on the current memory access address, step size, and confidence level, and the prefetch address is always aligned with the latest memory access pattern through dynamic updates of the base address and offset. Furthermore, prefetch requests directly enter the Loaded Storage Unit (LSU) pipeline for execution, reducing additional hardware overhead, ensuring rapid response of prefetch operations, and preloading data into the cache to reduce latency for subsequent access needs. The introduction of dynamic optimization mechanisms such as access vector updates, confidence adjustments, and base address calibration allows the prefetcher to track changes in memory access behavior in real time: when the memory access pattern is stable, the confidence level increases, and prefetching becomes more aggressive; when the pattern fluctuates, the confidence level decreases, and the prefetch strategy automatically converges. This adaptive characteristic allows the prefetcher to remain efficient in complex memory access scenarios, enhancing the versatility of the hardware prefetch engine. Prefetch requests reuse the existing pipeline of the payload storage unit, eliminating the need to design a dedicated execution chain for prefetching and reducing hardware area and power consumption. Simultaneously, operations such as payload information decoding and vector updates are implemented based on the existing interaction logic between the tag array and payload array, avoiding the introduction of additional storage or computation modules. This improves prefetch performance while maintaining hardware implementation economy.

[0057] In one embodiment, updating the confidence level based on the access vector includes: Count the number of bits that are 1 in the access vector; If the number is greater than the first threshold, increment the confidence level by 1; if the confidence level exceeds the maximum confidence level, set the confidence level to the maximum confidence level. If the quantity is less than the second threshold, the confidence level is reduced by 1; if the confidence level is less than or equal to 0, the confidence level is set to 0. Otherwise, keep the confidence level unchanged.

[0058] In the above embodiment, the number of "1" bits in the access vector is used as a quantitative indicator of the regularity of memory access patterns (the higher the number, the denser the effective access under the fixed step size pattern). The confidence level is dynamically adjusted by comparing it with a first threshold and a second threshold: when the pattern is stable (the number of "1" bits exceeds the first threshold), the confidence level is increased to enhance prefetching initiative; when the pattern is disordered (the number of "1" bits is lower than the second threshold), the confidence level is decreased to suppress invalid prefetching. This quantitative logic enables the confidence level to objectively reflect the stability of memory access patterns, avoids traditional empirical prefetching decisions, and significantly improves the reliability of the prefetching strategy. The increase or decrease of confidence and boundary constraints (not exceeding the maximum value, not lower than 0) enable the prefetcher to respond in real time to dynamic changes in memory access patterns: when the program enters a stable loop access (such as array traversal), the number of "1" bits continuously reaches the target, the confidence rises to the highest level, and the prefetcher actively prefetches with maximum intensity, fully leveraging the advantages of fixed-step prefetching; when the program exits the loop or the memory access pattern changes abruptly, the number of "1" bits drops sharply, the confidence drops rapidly to 0, and the prefetcher automatically stops invalid prefetching, avoiding cache pollution and bandwidth waste. This "adaptive switching" characteristic ensures that the prefetcher remains highly efficient in complex program scenarios, adapting to different memory access patterns without manual intervention. Through dynamic adjustment of confidence, blind prefetching of low-stability memory access patterns is avoided: when the confidence drops to 0, the prefetcher stops generating prefetch requests, reducing the invalid occupation of resources such as cache ports and bus bandwidth; while active prefetching under high confidence concentrates resources to serve high-regularity memory access, improving the "return on investment" of prefetch requests. Meanwhile, the threshold comparison and addition / subtraction operations are logically simple and have low hardware implementation costs, enabling efficient prefetch control with almost no additional power consumption. Gradual changes in confidence (gradual increases and decreases rather than abrupt changes) avoid drastic fluctuations in the prefetch strategy: for example, when the memory access pattern fluctuates briefly (the number of "1" bits is within the threshold), the confidence remains constant, ensuring the continuity of prefetching and preventing prefetch interruptions due to momentary fluctuations; while sustained stable or disordered patterns trigger confidence adjustments to ensure that the prefetch strength matches actual needs. This balancing mechanism ensures the timeliness of prefetching under high-regularity patterns (preloading data) while reducing the risk of cache misses by suppressing low-confidence prefetching, ultimately reducing overall memory access latency.

[0059] In one embodiment, the method further includes: When the state of the hit storage entry is in the prefetch state, the number of bits with a confidence level of 1 and a value of 1 in the access vector is less than the second threshold, and the state of the storage entry is changed to the training state.

[0060] In the above embodiments, when a memory entry is in the prefetch state but meets the conditions of a confidence level of 1 and the number of 1 bits in the access vector being less than the second threshold, it indicates that the stability of the current memory access pattern has dropped to a critical value (low confidence level + low effective access density), and continuing prefetching is likely to generate invalid requests. Switching the state to the training state at this time immediately stops the prefetching operation based on that memory entry, preventing resources such as cache ports and bus bandwidth from being continuously occupied by inefficient prefetching, and reducing power consumption and performance loss caused by invalid prefetching. After switching back from the prefetch state to the training state, the prefetcher will restart learning the memory access pattern of that memory entry (e.g., recalculating the address difference Delta, updating the last access address, etc.), rather than directly discarding the memory entry. This mechanism allows the prefetcher to recapture memory access patterns that may recover their regularity after a brief deviation from a fixed step size (e.g., the return to regularity after inserting a small number of irregular accesses in the program loop), enhancing the prefetcher's fault tolerance and adaptability to complex memory access patterns, and avoiding permanently abandoning effective prefetching opportunities due to a single pattern fluctuation. The state switch is triggered by a dual condition—confidence level = 1 (minimum effective prefetch threshold) and the number of bits in the access vector < the second threshold (low effective access density)—rather than a single metric, ensuring more accurate state switch decisions. This avoids misjudging mode failure due to instantaneous fluctuations (both low confidence level and low effective access must be met simultaneously) and allows for timely intervention when the mode is indeed unstable. This multi-condition constraint design makes the prefetcher's state management more flexible and adaptable to the memory access characteristics of different programs (such as scenarios with different tolerances to fluctuations). After switching to the training state, the prefetcher stops actively prefetching but retains the basic information of the stored entries (such as RIP tags, historical addresses, etc.). Compared to directly discarding stored entries, some historical data can be reused during retraining, shortening the preparation time for re-entering the prefetch state. This pause-learn-restart logic avoids invalid prefetching while ensuring a rapid response to potential recovery patterns, balancing prefetch continuity and resource efficiency, and ultimately reducing memory access latency fluctuations caused by mode changes.

[0061] In one embodiment, determining the address window width includes: Set the address window width to a fixed value, or determine the address window width based on the confidence level, or determine the address window width based on the step size.

[0062] In the above embodiments, by providing three determination methods—fixed value, confidence-based, and step-based—the address window width can be precisely matched to different memory access scenarios: Fixed value mode: suitable for scenarios with stable memory access patterns and fixed step size and access density (such as simple array traversal), which can meet prefetching requirements without dynamic adjustment and reduce hardware control complexity; Confidence-based mode: when the confidence level is high (stable memory access pattern), the window width can be expanded to prefetch more subsequent data at once, improving prefetching efficiency; when the confidence level is low (pattern fluctuation), the window is narrowed to avoid excessive prefetching leading to cache pollution; Step-based mode: when large step size memory access (such as cross-block data reading), a wide window is matched to reduce the number of prefetch requests; when small step size memory access (such as continuous byte reading), a narrow window is used to avoid prefetching redundant data.

[0063] This multi-mode design breaks the limitation of a single window width adapting to all scenarios, allowing the prefetch strategy to flexibly cope with complex and ever-changing program memory access behaviors. When dynamically adjusted based on confidence, the window width is strongly bound to the stability of the memory access mode, avoiding invalid prefetching with a wide window in high-fluctuation scenarios and insufficient prefetching with a narrow window in high-stability scenarios, ensuring a balance between the accuracy and coverage of prefetch requests. When adjusted based on step size, the window width matches the data access interval. For example, when the step size is 8 bytes, setting the window width to 4 (covering 32 bytes) allows for the prefetching of 4 consecutive step sizes of data at once, reducing the frequency of prefetch request generation in the pipeline and reducing the pressure on bus bandwidth and LSU pipeline. The fixed-value mode provides a lightweight solution for simple scenarios, enabling stable prefetching without additional computational overhead, balancing efficiency and hardware cost. All three determination methods have simple and controllable logic, without the need to introduce complex calculation modules: the fixed value mode only requires hardware registers to store preset values, without dynamic calculation overhead; the confidence level and step size are both payload information already stored in the prefetcher (such as the step size in the Stride payload Array and the confidence level in the label array), and the window width is determined based on these existing parameters, without the need for additional data collection or additional storage units; The hardware can switch between three modes through a simple multiplexer to adapt to different scenarios, avoiding the need to design dedicated hardware circuits for a single complex strategy. While improving prefetch performance, it controls chip area and power consumption, balancing technological advancement with the economics of engineering implementation.

[0064] In one embodiment, updating the base address and access vector based on the offset between the address in the current memory access request and the base address includes: If the offset is greater than or equal to a preset multiple of the step size, it is determined that the storage entry needs to be refreshed, the access vector is cleared to zero, and the base address is updated according to the following formula: BaseAddr + W × Stride, where BaseAddr is the base address, W is the address window width, and Stride is the step size; If the offset is less than a preset multiple of the step size, the base address and access vector remain unchanged.

[0065] In the above embodiments, when the offset reaches a preset multiple of the step size (e.g., exceeding the total number of steps corresponding to the address window width), the base address is updated using the formula BaseAddr + W×Stride, causing the prefetch window to actively slide backward, always focusing on address ranges that may be accessed in the future (rather than remaining in historically covered ranges). Simultaneously, after the access vector is cleared, the access status within the new window is re-recorded, ensuring that prefetch requests are only generated for addresses not yet accessed in the new window. This avoids redundant prefetching of already accessed ranges, significantly improving the matching degree between prefetched data and actual needs, and reducing cache miss latency for subsequent accesses. On-demand updates of the base address are achieved through offset threshold judgment: updates are triggered only when the offset exceeds a preset multiple of the step size (indicating that the current memory access has exceeded the original prefetch window range); otherwise, the base address and access vector remain unchanged. This design ensures that the prefetcher can stably track continuous fixed-step memory access patterns (e.g., continuous address access during array looping), avoiding accidental updates due to small address fluctuations that could cause the prefetch window to become disconnected from the actual memory access rhythm. For example, in fixed-step access within a loop, the base address is only updated after the window is exhausted, ensuring that prefetching always keeps pace with the current memory access progress and enhancing the consistency of the prefetching strategy. Base address calculation and access vector clearing are only performed when necessary (offset thresholds are met), avoiding meaningless update operations for scenarios where the offset has not exceeded the threshold. On the one hand, this reduces the number of dynamic calculations in the hardware circuitry (such as base address addition and vector clearing logic operations), lowering power consumption. On the other hand, it avoids the loss of historical access information caused by frequent access vector resets, reducing the time cost of re-accumulating access states due to information resets. Simultaneously, the update logic is implemented based on existing parameters (offset, step size, window width), requiring no additional data acquisition or storage units. This optimizes performance while controlling hardware area and implementation complexity, balancing technological advancement and engineering economy.

[0066] In one embodiment, generating a prefetch request after filtering prefetch addresses based on access vectors includes: If the bit value of the access vector corresponding to the prefetch address is 1, skip the prefetch address, obtain the address of the next step offset of the prefetch address, and generate a prefetch request; Alternatively, instead of filtering by access vector, a prefetch request can be generated directly using the prefetch address; Alternatively, a prefetch request can be generated after filtering the prefetch addresses using the access vector.

[0067] In the above embodiments, the core logic of access vector filtering can directly exclude addresses that have already been accessed (skipping when the corresponding bit of the prefetch address is 1), and only generate prefetch requests for unaccessed addresses, thus avoiding problems caused by repeated prefetching from the source: preventing cached data from being repeatedly prefetched and occupying cache space, reducing the risk of cache pollution; reducing the occupation of bus bandwidth and LSU pipeline by invalid prefetch requests, avoiding resource waste; ensuring that prefetch resources are concentrated on serving future real needs, improving the return on investment of prefetching, and indirectly reducing cache miss latency for subsequent access needs. The three filtering modes can flexibly match the characteristics of different memory access scenarios, breaking the limitation of a single strategy adapting to all scenarios: Access vector filtering mode: suitable for scenarios with stable memory access patterns and high risk of repeated address access (such as looping through an array), maximizing prefetch benefits through precise filtering; No-filter direct generation mode: suitable for scenarios with strong randomness of memory access addresses and low probability of repeated access (such as reading discrete data), saving the computational overhead of filtering, quickly generating prefetch requests, and prioritizing the timeliness of prefetching; Selectable filtering switch: the hardware can dynamically switch according to the memory access mode (such as combining confidence level judgment: high confidence level uses the filtering mode, low confidence level uses the no-filter mode), so that the prefetching strategy can adapt to changes in program memory access behavior, balancing accuracy and flexibility. The logic design of the three modes is simple and can be flexibly switched without the need for additional complex hardware modules: the unfiltered mode eliminates operations such as access vector query and bit value judgment, minimizing computational overhead and making it suitable for latency-sensitive scenarios; the access vector filtering mode reuses existing access vector storage resources (without adding storage units), requiring only simple bit comparison logic, resulting in low hardware implementation costs; multi-mode switching can be achieved through basic multiplexer circuits, eliminating the need to design independent hardware links for different strategies, improving prefetch performance while controlling chip area and power consumption, thus balancing technological advancement and engineering economy.

[0068] In one embodiment, the pipeline that loads the prefetch request onto the storage unit includes: If the pipeline of the load storage unit is idle, the prefetch request will be directly pipelined through arbitration; If the pipeline of the load storage unit is busy, the prefetch request is stored in the prefetch request queue, and the pipeline is selected from the prefetch request queue when the load storage unit is idle.

[0069] In the above embodiments, prefetch requests do not rely on dedicated execution chains but reuse the existing pipeline of the Load Storage Unit (LSU), avoiding the cost of designing separate hardware circuits for prefetching. Simultaneously, by directly pipelined during idle periods, prefetch operations are fully utilized during idle time slots (such as demand access intervals), avoiding resource idleness. Meanwhile, the design of storing requests in a queue during busy periods ensures that prefetch requests are not discarded and continue execution after resources are released. This achieves efficient scheduling of the LSU pipeline between demand access and prefetch requests, significantly improving the overall utilization of hardware resources. This mechanism, through arbitration scheduling + queue caching logic, ensures both the timeliness of prefetching and avoids interfering with high-priority demand access: when the pipeline is idle, prefetch requests directly enter the pipeline through arbitration, quickly executing prefetch operations and loading data into the cache in advance, shortening latency for subsequent demand access; when the pipeline is busy (e.g., processing demand access), prefetch requests are temporarily stored in a queue, avoiding contention for resources with demand access and preventing increased latency for the latter. This demand-first, prefetch-filling scheduling strategy ensures both the response speed of core business (demand access) and the availability of prefetching opportunities, balancing the benefits of prefetching with the efficiency of core access. The introduction of a prefetch request queue solves the problem of "prefetch requests having nowhere to go when the pipeline is busy": it prevents prefetch requests from being directly discarded due to pipeline busyness, thus avoiding prefetch interruptions and increased cache miss rates for subsequent demand accesses; the queue acts as a buffer layer, isolating prefetch requests from direct competition with the pipeline, preventing a large influx of prefetch requests from causing pipeline congestion (such as address conflicts and resource contention), and ensuring the stable operation of the LSU pipeline; when the pipeline is idle, requests are selected from the queue for pipeline execution, further reducing the probability of operational conflicts through ordered scheduling, and improving the overall stability and reliability of the system.

[0070] In this embodiment of the invention, the step of executing the prefetch request in the pipeline is the same as the aforementioned pipeline execution step, that is, determining whether the L1 cache is hit, and executing the memory access operation according to the type of memory access operation and the L1 cache hit result.

[0071] In summary, when the hit storage entry is in a prefetch state, the steps of generating a prefetch request based on the payload information and executing it on the pipeline can be specifically represented as follows: Read the payload fields of the prefetch state corresponding to the hit storage entry from the payload array: Stride (fixed step size, positive numbers increase, negative numbers decrease), Conf (confidence level, 0 to maximum value such as 3), BaseAddr (base address), AccVec (access vector, bit width = address window width W), and decode the payload information according to the prefetch state rules.

[0072] Update AccVec: Based on the address in the current memory access request, find the corresponding bit in AccVec (current address = BaseAddr + (n + 1) × Stride, corresponding to bit n), and set that bit to 1 (marking that the address has been requested).

[0073] Update Confidence Conf: Count the number of bits that are 1 in AccVec (i.e., the number of blocks accessed): If the number of accessed blocks is greater than the first threshold Thigh: Conf increment by 1 (not exceeding the maximum value).

[0074] If the number of accessed blocks is less than the second threshold Tlow: Conf minus 1 (not less than 0).

[0075] If it is between Thigh and Tlow: Conf remains unchanged.

[0076] Determine the address window width W (select according to preset rules): Rule 1: W is a fixed value (e.g., 8).

[0077] Rule 2: The larger Conf is, the larger W is (a higher confidence level expands the prefetch range).

[0078] Rule 3: The larger the absolute value of the stride, the smaller W (a larger stride will result in a larger address span, so narrowing the range avoids invalid prefetching).

[0079] Check the offset between the address in the current memory access request and BaseAddr: If the offset is greater than or equal to n × Stride (n is the step size multiple, such as 2): it is determined that the storage entry needs to be refreshed, BaseAddr is updated to BaseAddr + W × Stride, and AccVec is cleared (prefetching of the new address window is enabled).

[0080] If the offset is less than n×Stride: keep BaseAddr and AccVec unchanged.

[0081] Generate prefetch address and prefetch request: The prefetch address is calculated based on the address, Stride, and Conf in the current memory access request (e.g., current address + Stride, current address + 2 × Stride, etc., with the offset increasing as Conf increases).

[0082] Filter prefetch addresses and generate prefetch requests according to rules (based on AccVec): Rule 1: If the bit corresponding to AccVec at the prefetch address is 1 (already visited), skip the prefetch address, calculate the next step offset address, and generate a prefetch request.

[0083] Rule 2: Generate a prefetch request directly using the calculated prefetch address without going through AccVec filtering.

[0084] Rule 3: Generate a prefetch request after filtering the prefetch addresses through AccVec, but do not update the prefetch addresses immediately; only mark invalid addresses.

[0085] Send a prefetch request: Rule 1: If the LSU pipeline is idle, the prefetch request is directly pipelined through arbitration; if the LSU pipeline is busy, the request is stored in the prefetch request queue, and is selected from the queue to pipeline when the LSU pipeline becomes idle.

[0086] After the prefetch request is piped up, the TLB address translation and tag array hit detection process is repeated: If the L1 cache is hit: no prefetching is needed, and the prefetch request ends.

[0087] If the L1 cache is not hit: a read request is sent to the downstream L2 cache and stored in MSHR; after the L2 cache returns data to fill the L1 cache, the prefetch request is completed.

[0088] In one embodiment, when the state of the hit storage entry is in the training state, the state and payload information of the storage entry are updated, including: The payload information of the hit storage entry is decoded according to the training state to obtain the payload domain of the hit storage entry; Calculate the difference between the address in the current memory access request and the address in the previous request, and use it as the current address difference; If the address difference valid flag is 0, update the previous address to the address in the current memory access operation request, update the address difference to the current address difference, and set the address difference valid flag to 1; If the address difference is marked as valid (1), the status and load information of the storage entry are updated based on the current address difference and the load field of the hit storage entry.

[0089] In the above embodiments, a two-stage control based on the effective identification of address differences ensures that pattern training is based solely on valid data, avoiding interference from invalid information: During the initial training (identified as 0), only the current address and initial difference are recorded and the identifier is activated to complete data initialization, without blindly judging patterns; during subsequent training (identified as 1), the state and load are updated based on the comparative analysis of historical differences and current differences (such as verifying the consistency of fixed step size), ensuring that training is based on continuous and complete memory access data, rather than isolated addresses. This design significantly reduces pattern misjudgment caused by a single abnormal address access (such as accidental discrete addresses), allowing the prefetcher to more accurately identify true patterns such as fixed step size, laying the foundation for efficient prefetching. The conditional triggering mechanism in the training process avoids redundant calculations and invalid updates, allowing the prefetcher to quickly transition from the training state to the prefetching state: When the identifier is 0, only basic data recording is performed, which is simple, time-saving, and quickly completes training preparation; when the identifier is 1, pattern verification is performed directly based on existing historical data (the previous address, historical difference), without the need to re-collect or initialize information, shortening the pattern confirmation cycle. The lightweight design of the training logic reduces hardware resource consumption while ensuring accuracy: the training phase is controlled solely by an address difference valid identifier (achieved with just one bit of register), eliminating the need for complex state machines or additional storage units; when the identifier is 0, only the address and difference are updated, without performing complex pattern analysis calculations, thus reducing dynamic power consumption; all update operations are implemented based on the prefetcher's existing payload domains (such as historical addresses and difference storage areas), eliminating the need for additional data acquisition or computation modules and controlling chip area overhead. This precise triggering + lightweight computation design allows the prefetcher to maintain efficient training capabilities despite low-cost hardware implementation, balancing technological advancement with engineering practicality.

[0090] In one embodiment, updating the status and load information of a storage entry based on the current address difference and the load field of the hit storage entry includes: If the current address difference is equal to the address difference, increment the same difference counter by 1, update the different difference counter, and check if the same difference counter has reached the first counter threshold. If the first calculator threshold is reached, it is determined that a fixed step size has been identified, the state of the hit stored entry is updated from the training state to the prefetch state, and the payload domain of the prefetch state is initialized. If the first calculator threshold is not reached, update the load information of the hit storage entry.

[0091] In the above embodiments, a dual verification mechanism of comparing the current address difference with the historical address difference and accumulating the difference counter ensures that the fixed step size is only determined when the memory access pattern is stable: the fixed step size is only confirmed when the address difference of multiple consecutive memory accesses is consistent (the counter accumulates to the first threshold), avoiding misjudgment of the pattern due to 1-2 occasional consistent differences, and significantly reducing invalid prefetching caused by false step sizes; the different difference counters are updated synchronously to record the pattern fluctuation in real time, providing a basis for subsequent confidence adjustment or state rollback, further enhancing the reliability of step size identification, and ensuring that the prefetcher starts prefetching only based on the real and stable pattern. The combination of a counter with identical differences and a first threshold provides a quantitative standard for the state switching from training to prefetching, avoiding arbitrariness or delay in state switching: when the counter reaches the threshold, the state switching is immediately triggered and the prefetch state payload domain (such as step size, base address, access vector) is initialized, allowing the prefetcher to quickly enter an effective working state without the need for additional rounds of sampling verification, shortening the cycle from pattern recognition to generating a prefetch request; when the threshold is not reached, only the payload information (such as cumulative difference records) is updated to continuously accumulate pattern data, ensuring that sufficient stable pattern information is obtained before switching, balancing rapid effectiveness and accurate switching, and avoiding prefetching chaos caused by premature switching. The entire update logic is based on lightweight numerical comparison and counter operations, with controllable hardware resource consumption: address difference comparison is based on basic subtraction and equality judgment, and the counter only needs to be simply accumulated and compared with the threshold, without complex algorithm calculations, reducing dynamic power consumption of hardware; state switching and load initialization are only performed when the counter reaches the threshold, avoiding frequent storage operations (such as repeatedly rewriting prefetched state parameters) and reducing access pressure on the load array; counters with the same / different differences can reuse the existing storage bits of the load field, without adding a new dedicated storage unit, controlling chip area overhead, and achieving low-cost and high-precision pattern recognition.

[0092] In one embodiment, updating the status and load information of a storage entry based on the current address difference and the load field of the hit storage entry includes: If the current address difference is not equal to the address difference, determine whether the current address difference meets the step size training requirements; If satisfied, update the address difference to the current address difference, update the previous address to the address in the current memory access operation request, increment the difference counter by 1, clear the difference counter to zero, and check if the difference counter has reached the second counter threshold. If the second calculator threshold is reached, it is determined that the address sequence corresponding to the RIP has no fixed step size, and the status of the hit storage entry is updated to the non-fixed step size state. If the second calculator threshold is not reached, update the load information of the hit storage entry; If the conditions are not met, update the load domain of the matched storage entry to the initial value of the training state.

[0093] In this embodiment of the invention, an innovative difference counter is proposed to identify non-fixed step size patterns during training and mark them as non-stride states. If a non-stride state storage entry is hit in subsequent accesses, training is skipped directly, saving power consumption from invalid training. Idle bits in the training state are reused to store the difference counter, enabling the judgment of non-fixed step size states without increasing storage overhead. Through a dual screening process of comparing the current difference with historical differences and verifying step size training requirements, tolerable pattern fluctuations and invalid patterns without fixed step sizes are strictly distinguished: only when the differences are unequal but meet the step size training requirements (e.g., the difference is within a reasonable fluctuation range) is the difference updated and training continued, avoiding misjudging pattern failure due to small, accidental fluctuations. If the difference does not meet the training requirements (e.g., the difference changes too drastically), the state is directly switched to non-fixed step size, completely terminating training for invalid patterns and preventing subsequent prefetch requests based on erroneous patterns. This hierarchical judgment mechanism significantly reduces the probability of false prefetch triggers in non-fixed step size scenarios, ensuring that the prefetcher only focuses on truly valid regular memory accesses. By using a difference counter plus a second threshold for quantization control, timely identification and processing of non-fixed step size modes are achieved: when the differences are continuously unequal (the counter accumulates to the second threshold), it is determined to be a non-fixed step size mode and the state is switched, stopping subsequent training and prefetching preparation for that storage entry, avoiding continuous consumption of payload array storage and computing resources (such as repeatedly updating the difference and counter); after the state switches to non-fixed step size, the prefetcher no longer generates prefetch requests for that storage entry, further avoiding the invalid prefetching of cache ports and bus bandwidth, releasing hardware resources to other valid memory access entries, and improving resource utilization efficiency. This mechanism allows the prefetcher to dynamically adapt to changes in memory access patterns through flexible state switching logic: for scenarios that recover from short-term fluctuations (such as inserting a small number of discrete accesses in a loop), if the difference counter has not reached the threshold, the training state is retained and the payload information is updated. After the pattern recovers, fixed step size recognition can be quickly restarted, avoiding a one-size-fits-all state elimination; for completely irregular scenarios (such as random address access), the counter threshold or step size training requirements are checked, and the system quickly switches to a non-fixed step size state to avoid ineffective investment. This adaptive logic of keeping what can be kept and stopping what should be stopped allows the prefetcher to remain efficient in complex program memory access scenarios (such as mixed loops and random access), and optimize the running strategy without manual intervention.

[0094] When the state of the hit storage entry is in the training state, the steps for updating the state and payload information of the storage entry can be specifically represented as follows: The payload information of the hit storage entry is decoded according to the training state to obtain the payload field of the hit storage entry, including: address difference Delta, address difference valid identifier DeltaVld, previous address LastAddr, same difference counter StrdHitCnt and different difference counter StrdMisMchCnt.

[0095] Calculate the difference between the address in the current memory access request and LastAddr, denoted as CurrentDelta, and combine it with DeltaVld to determine the processing logic: If DeltaVld=0 (no valid difference or the difference exceeds the Delta bit width): Update LastAddr to the address in the current memory access request, set Delta to CurrentDelta, set DeltaVld to 1 (to mark the difference as valid), keep StrdHitCnt and StrdMisMchCnt at their current values ​​(initially 0), and wait for the next request after completing the payload update.

[0096] If DeltaVld=1 (difference is valid): Compare whether CurrentDelta is equal to Delta: If they are equal: Increment StrdHitCnt by 1, clear StrdMisMchCnt to 0 or leave it unchanged, and check if StrdHitCnt has reached the first calculator threshold: If the first calculator threshold is reached: if a fixed step size is identified, update the status of the hit storage entry from training to trained; initialize the payload field of the trained storage entry (Conf=1, Stride=Delta, BaseAddr = address in the current memory access request, AccVec cleared).

[0097] If the first calculator threshold is not reached: update the load information of the hit storage entry, which means only updating LastAddr to the address in the current memory access operation request.

[0098] If they are not equal: Check if CurrentDelta meets the step size training requirements (e.g., the difference is within a reasonable range): If the following conditions are met: Update Delta to CurrentDelta, and LastAddr to the address in the current memory access request.

[0099] Increment StrdMisMchCnt by 1, clear StdHitCnt to 0; Check if StrdMisMchCnt has reached the second calculator threshold: If the second calculator threshold is reached: it is determined that the address sequence corresponding to the RIP has no fixed stride, and the storage entry status is updated to non-stride; If the second calculator threshold is not reached: After completing the load information update, wait for the next request.

[0100] If not satisfied: directly update the payload field of the hit memory entry to the initial value of the training state: LastAddr = address in the current memory access request, DeltaVld = 0, StrdHitCnt = 0.

[0101] In one embodiment, the method further includes: If the memory access request does not match a storage entry in the tag array, a new storage entry is allocated for the memory access request in the tag array; If the tag array is full, replace an existing tag array with a new tag array entry; If the label array is not full, initialize the state of the new storage entry to the training state, and initialize the payload information of the new storage entry in the training state.

[0102] In the above embodiment, the payload information of the new storage entry for initializing the training state is (Delta=0, DeltaVld=0, LastAddr = current memory access operation request address, StrdHitCnt=0, StrdMisMchCnt=0).

[0103] When a memory access request misses the tag array, a mechanism for allocating new storage entries ensures that the memory access behavior corresponding to each new instruction address (RIP) is captured and incorporated into the training, preventing new memory access patterns from being missed due to a lack of available storage entries. Even if the tag array is full, the access of new patterns is guaranteed by replacing existing storage entries (such as replacing inefficient storage entries that have not been updated for a long time or have irregular patterns), ensuring that the prefetcher can continuously track new memory access scenarios that emerge during program execution (such as new loop accesses after program branch switching), significantly broadening the applicability of the prefetcher and reducing cache misses caused by not covering new patterns. By employing a dynamic management strategy that allocates new storage entries when the array is not full and replaces old ones when it is full, the limited tag array storage resources are always used to serve effective memory access patterns. When a storage entry is not full, it avoids blindly occupying extra space and allocates resources only for new memory access patterns, preventing storage units from being idle. When a storage entry is full, a replacement mechanism (implicitly eliminating inefficient storage entries, such as prioritizing the replacement of non-fixed step size states and storage entries that have not been updated for a long time) ensures that new storage entries can replace older storage entries with lower value, preventing valuable resources from being occupied by ineffective patterns for a long time. This design achieves efficient circulation under fixed storage resources, increases the unit storage value of the tag array, and balances storage costs with prefetch coverage effects. When a new storage entry is initialized, it is directly set to the training state and the training state payload information (such as initial address, difference validity identifier, etc.) is initialized simultaneously, without the need for an additional idle state → training state switching process, allowing new memory access patterns to enter the training process from their first appearance. For example, when the program executes a new loop for the first time, it immediately starts recording address differences and accumulating counters after new storage entries are allocated. Compared to mechanisms that require multiple rounds of triggering to enter training, this significantly shortens the fixed step size recognition and prefetching startup cycle, provides prefetching support for new memory access patterns earlier, and reduces cache miss latency for subsequent access needs.

[0104] In one embodiment, the method further includes: If the memory access request triggers a request in the missing status handling register, a new storage entry is allocated for the memory access request in the tag array.

[0105] In this embodiment of the invention, the memory access operation request triggers a request in the missing status handling register, which means that an access needs to be initiated to the downstream cache. The missing status handling register specifically records requests that trigger memory access misses (such as cache misses). Based on this register, new storage entry allocation is triggered, ensuring that the new storage entry is directly associated with memory access behavior that has already occurred and has a clear data requirement, rather than indiscriminately allocating resources to all miss requests. This on-demand allocation logic allows the tag array resources to prioritize serving high-value memory accesses (i.e., accesses that have already occurred and require subsequent optimization), avoiding wasting storage entries on low-value miss requests (such as one-time discrete accesses), and improving the accuracy of missing data handling and the return on investment of resources. Memory access misses often mean that there is no target data in the current cache, and such missing requests may hide unidentified memory access patterns (such as the first occurrence of a fixed-step access). By allocating new storage entries to requests in the missing state handling register and initiating training (combined with the logic of previously initializing the training state), pattern learning for this memory access behavior can be performed quickly. If a fixed step size is subsequently identified, prefetching can be initiated in a timely manner, loading potentially accessed data into the cache in advance, fundamentally reducing repeated missing data of the same type of memory access, significantly reducing the overall missing rate, and optimizing system memory access performance. The missing state handling register acts as a bridge connecting memory access missing detection and tag array management, avoiding the complex process of missing requests needing to be passed across modules multiple times to trigger storage entry allocation. Once a missing request is recorded in the register, it can directly trigger the allocation of a new storage entry without additional signal interaction or judgment logic, shortening the link latency from missing detection to initiating pattern training. Simultaneously, this modular collaborative design allows for seamless integration of missing handling and prefetching preparation, reducing redundant operations between hardware modules and improving the overall system operating efficiency.

[0106] In one embodiment, replacing an existing storage entry in the tag array with a new storage entry includes: The storage entries to be replaced are selected based on a round-robin algorithm, a least recently used algorithm, or a pseudo least recently used algorithm. Alternatively, select the storage entry with low confidence as the storage entry to be replaced; Alternatively, select one of the stored entries that is in the training state or the non-fixed step state as the stored entry to be replaced.

[0107] In this embodiment of the invention, only storage entries in the prefetch state have confidence levels. By selectively filtering storage entries to be replaced, the limited tag array space is designed to prioritize high-value storage entries that contribute significantly to prefetching: Storage entries with low confidence levels are selected for replacement: low confidence levels mean that the memory access pattern corresponding to the storage entry is unstable and has low prefetching benefits, so replacing it has little impact on the overall prefetching effect; Storage entries in the training state or non-fixed step state are prioritized for replacement: training state storage entries have not yet formed effective prefetch patterns, and non-fixed step state storage entries have no prefetching value. Replacing these storage entries can prevent high-value prefetch state storage entries (which can stably generate effective prefetch requests) from being eliminated, allowing resources to be tilted towards storage entries that can generate actual prefetching benefits, significantly improving the unit space value of the tag array. It offers multiple replacement schemes using classic algorithms and policy filtering, allowing for flexible selection based on hardware implementation cost and performance goals: Round-robin, LRU (Least Recently Used), and pseudo-LRU algorithms are all mature cache replacement strategies. Round-robin has the simplest hardware implementation (requiring only a counter), making it suitable for low-cost scenarios. LRU / pseudo-LRU algorithms can filter based on access frequency, suitable for scenarios with high performance requirements. Confidence-based filtering and state-based filtering combine the prefetcher's own load information (confidence, storage entry status) for replacement, eliminating the need for additional access frequency data collection, balancing performance and hardware complexity. This multi-solution design allows the technology to adapt to the needs of different chips (such as low-power embedded chips and high-performance CPUs), enhancing the versatility and practicality of the patented solution. By avoiding the replacement logic of high-value state storage entries, prefetching interruptions caused by improper replacements are prevented: explicitly do not prioritize replacing prefetching state storage entries, ensuring that storage entries that can stably generate valid prefetch requests continue to work, avoiding prefetching interruptions and a sharp increase in cache miss rate due to replacement; even if training state storage entries are replaced, since these storage entries have not yet generated prefetching benefits, they have no direct impact on current prefetching performance. At the same time, new training can be quickly started after the new storage entries are connected, balancing the elimination of old storage entries and the cultivation of new storage entries, reducing short-term fluctuations in reader performance caused by replacement operations.

[0108] In one embodiment, the method further includes: When the state of the hit storage entry is a non-fixed step state, the number of times the storage entry in the tag array is hit is recorded by a global counter. Once the number of times a stored entry is hit reaches a threshold, the state of the stored entry is changed to training state.

[0109] In the above embodiments, the non-fixed step size state storage entries are not permanently random. Some storage entries may regain fixed step size characteristics due to changes in program logic (such as switching from random access to cyclic access). A global counter records the number of hits for this type of storage entry. When the number reaches a threshold (indicating that the memory access behavior corresponding to this storage entry is frequent and has pattern mining value), the state is switched back to the training state, and the step size recognition process can be restarted. This avoids permanently abandoning a storage entry due to a single non-fixed step size determination, missing subsequent prefetching opportunities brought by pattern changes. Prioritizing retraining for frequently accessed non-fixed step size storage entries ensures that the prefetcher can dynamically follow the evolution of memory access patterns, covering more potential effective memory access scenarios and reducing cache misses caused by missed pattern detection. If non-fixed step size state storage entries lack a retraining mechanism for a long period, they will occupy label array space without generating prefetching benefits, leading to resource idleness. The design of triggering retraining through hit counting allows frequently hit non-fixed-step storage entries to re-enter the training process, potentially transforming them into prefetch state storage entries capable of generating effective prefetches, thus activating the value of idle resources. Retraining is triggered only for frequently hit storage entries, avoiding meaningless repetitive training of low-frequency non-fixed-step storage entries, reducing hardware computational overhead (such as address difference calculation and counter updates), and achieving a balance between resource reuse and overhead control. This mechanism requires no additional hardware modules or manual configuration; state switching is automatically achieved through a global counter and threshold judgment. The threshold setting can be flexibly adjusted according to system needs (e.g., lowering the threshold in high-frequency access scenarios to accelerate retraining; raising the threshold in low-frequency scenarios to reduce invalid operations), adapting to the memory access characteristics of different programs. The retraining process is implemented based on existing training state logic, without the need for new control links, ensuring that the prefetcher can stably handle known patterns while autonomously responding to pattern changes, reducing the cost of prefetch strategy adjustments due to program iterations, and improving the system's automated operation capabilities.

[0110] As can be seen from the above embodiments, when a non-stride storage entry is hit, it is considered that the address sequence corresponding to the current label does not have a fixed step size pattern. Therefore, the corresponding payload storage entry content will not be read subsequently, and training will not be performed. The methods for processing the training state in the embodiments of the present invention include replacing the storage entry with one that is naturally overwritten, modifying it through the principle of a global counter, and in other embodiments, the non-stride state can also be cleared by other means (such as periodic refresh) to restore the training state. This is not a limitation.

[0111] Figure 6This is a switching diagram of the three state transitions of the storage entry in this embodiment of the invention. When the extractor is initialized, it enters the training state. In the training state, if the same difference counter reaches the first calculator threshold, the state of the storage entry is the prefetch state. If the different difference counter reaches the second calculator threshold, the state of the storage entry is the non-fixed step size state. In the prefetch state, if the confidence level is 1 and the number of 1 bits in the access vector is less than the second threshold, the state of the storage entry is changed to the training state. In the non-fixed step size state, the state of the storage entry is changed to the training state according to the aforementioned storage entry replacement being naturally overwritten, through the principle of global counters, etc.

[0112] This application also proposes a training device for a fixed-step prefetcher based on instruction address. Its principle is similar to that of the training method for a fixed-step prefetcher based on instruction address, and will not be described in detail here.

[0113] Figure 7 This is a schematic diagram of the training device for a fixed-step prefetcher based on instruction address in an embodiment of this application. The device includes: The hit determination module 701 is used to determine, after receiving a memory access operation request, whether the memory access operation request hits a storage entry in the fixed step prefetcher based on the instruction address according to the tag array. The tag array stores the tag and status of the storage entry. The load reading module 702 is used to read the load information of the hit storage entry in the state from the load array if the memory access operation request hits a storage entry, based on the state of the hit storage entry. The processing module 703 is used to generate a prefetch request based on the payload information and execute it on the pipeline when the state of the hit storage entry is in the prefetch state; to update the state and payload information of the storage entry when the state of the hit storage entry is in the training state; and to skip directly when the state of the hit storage entry is in the non-fixed step size state.

[0114] In one embodiment, the payload array corresponds one-to-one with the storage entries involved in the tag array, and the payload array stores the payload information of the storage entries. The payload information of each storage entry only includes the payload domain that needs to be considered in the state of the storage entry in the tag data.

[0115] In one embodiment, the payload field of the prefetch state's stored entry includes step size, confidence level, base address, and access vector; The payload field of the storage entry in the training state includes address difference, address difference valid identifier, previous address, same difference counter and different difference counter.

[0116] In one embodiment, the processing module is used to: The payload information of the hit storage entry is decoded according to the prefetch state to obtain the payload field of the hit storage entry; Find the bit in the access vector corresponding to the address in the current memory access request and set that bit to 1; Update the confidence level based on the access vector; Update the base address and access vector based on the offset between the address and the base address in the current memory access request; Generate prefetch address and prefetch request: Calculate the prefetch address based on the address, step size, and confidence level in the current memory access operation request, and generate a prefetch request after filtering the prefetch address based on the access vector. The pipeline loads the prefetch request onto the storage unit; The prefetch request is executed in the pipeline.

[0117] In one embodiment, the processing module is used to: Count the number of bits that are 1 in the access vector; If the number is greater than the first threshold, increment the confidence level by 1; if the confidence level exceeds the maximum confidence level, set the confidence level to the maximum confidence level. If the quantity is less than the second threshold, the confidence level is reduced by 1; if the confidence level is less than or equal to 0, the confidence level is set to 0. Otherwise, keep the confidence level unchanged.

[0118] In one embodiment, the processing module is used to: When the state of the hit storage entry is in the prefetch state, the number of bits with a confidence level of 1 and a value of 1 in the access vector is less than the second threshold, and the state of the storage entry is changed to the training state.

[0119] In one embodiment, the processing module is used to: Set the address window width to a fixed value, or determine the address window width based on the confidence level, or determine the address window width based on the step size.

[0120] In one embodiment, the processing module is used to: If the offset is greater than or equal to a preset multiple of the step size, it is determined that the storage entry needs to be refreshed, the access vector is cleared to zero, and the base address is updated according to the following formula: BaseAddr + W × Stride, where BaseAddr is the base address, W is the address window width, and Stride is the step size; If the offset is less than a preset multiple of the step size, the base address and access vector remain unchanged.

[0121] In one embodiment, the processing module is used to: If the bit value of the access vector corresponding to the prefetch address is 1, skip the prefetch address, obtain the address of the next step offset of the prefetch address, and generate a prefetch request; Alternatively, instead of filtering by access vector, a prefetch request can be generated directly using the prefetch address; Alternatively, a prefetch request can be generated after filtering the prefetch addresses using the access vector.

[0122] In one embodiment, the processing module is used to: If the pipeline of the load storage unit is idle, the prefetch request will be directly pipelined through arbitration; If the pipeline of the load storage unit is busy, the prefetch request is stored in the prefetch request queue, and the pipeline is selected from the prefetch request queue when the load storage unit is idle.

[0123] In one embodiment, the processing module is used to: The payload information of the hit storage entry is decoded according to the training state to obtain the payload domain of the hit storage entry; Calculate the difference between the address in the current memory access request and the address in the previous request, and use it as the current address difference; If the address difference valid flag is 0, update the previous address to the address in the current memory access operation request, update the address difference to the current address difference, and set the address difference valid flag to 1; If the address difference is marked as valid (1), the status and load information of the storage entry are updated based on the current address difference and the load field of the hit storage entry.

[0124] In one embodiment, the processing module is used to: And the payload field of the hit storage entry, perform update processing on the status and payload information of the storage entry, including: If the current address difference is equal to the address difference, increment the same difference counter by 1, update the different difference counter, and check if the same difference counter has reached the first counter threshold. If the first calculator threshold is reached, it is determined that a fixed step size has been identified, the state of the hit stored entry is updated from the training state to the prefetch state, and the payload domain of the prefetch state is initialized. If the first calculator threshold is not reached, update the load information of the hit storage entry.

[0125] In one embodiment, the processing module is used to: If the current address difference is not equal to the address difference, determine whether the current address difference meets the step size training requirements; If satisfied, update the address difference to the current address difference, update the previous address to the address in the current memory access operation request, increment the difference counter by 1, clear the difference counter to zero, and check if the difference counter has reached the second counter threshold. If the second calculator threshold is reached, it is determined that the address sequence corresponding to the RIP has no fixed step size, and the status of the hit storage entry is updated to the non-fixed step size state. If the second calculator threshold is not reached, update the load information of the hit storage entry; If the conditions are not met, update the load domain of the matched storage entry to the initial value of the training state.

[0126] In one embodiment, the processing module is used to: If the memory access request does not match a storage entry in the tag array, a new storage entry is allocated for the memory access request in the tag array; If the tag array is full, replace an existing tag array with a new tag array entry; If the label array is not full, initialize the state of the new storage entry to the training state, and initialize the payload information of the new storage entry in the training state.

[0127] In one embodiment, the processing module is used to: If the memory access request triggers a request in the missing status handling register, a new storage entry is allocated for the memory access request in the tag array.

[0128] In one embodiment, the processing module is used to: Replace an existing storage entry in the tag array with the new storage entry, including: The storage entries to be replaced are selected based on a round-robin algorithm, a least recently used algorithm, or a pseudo least recently used algorithm. Alternatively, select the storage entry with low confidence as the storage entry to be replaced; Alternatively, select one of the stored entries that is in the training state or the non-fixed step state as the stored entry to be replaced.

[0129] In one embodiment, the processing module is used to: When the state of the hit storage entry is a non-fixed step state, the number of times the storage entry in the tag array is hit is recorded by a global counter. Once the number of times a stored entry is hit reaches a threshold, the state of the stored entry is changed to training state.

[0130] The solution proposed in this application can reduce invalid training of the prefetcher, reduce power consumption and computing power waste. In the prior art, all RIPs (instruction addresses) are continuously trained, and the memory access sequences of a large number of RIPs cannot naturally form a fixed step size pattern, resulting in invalid training and wasted resources. In this solution, when a memory access request hits a storage entry in a "non-fixed step size state", the training process is skipped directly, and there is no need to repeat training on RIPs that have been confirmed to have no fixed step size. This avoids unnecessary operations such as load information reading and counter updates, significantly reducing the invalid computing power consumption of the prefetcher, and reducing the dynamic power consumption of the hardware module. This achieves the goal of reducing invalid training without increasing additional storage. This solution can accurately trigger prefetching and state management, improve prefetching efficiency and cache hit rate. When a storage entry in the prefetch state is hit, a prefetch request is generated based on the load information, and the prefetch request needs to be executed through the pipeline. This prefetching based on a fixed step size after training can fill the cache-missed data back into the L1 cache in advance, reduce the cache miss latency of subsequent memory access operations, and improve data access speed. When a storage entry in the training state is hit, the payload information is continuously updated to determine whether the RIP has formed a fixed step size. This ensures that prefetching is triggered only for regular memory access sequences, avoiding blind prefetching that reduces prefetch accuracy and further optimizing cache resource utilization. This solution optimizes hardware storage and pipeline resource utilization and reduces additional overhead. Traditional solutions, if additional storage is added to record non-fixed step size RIPs, will bring hardware storage and maintenance power consumption. This solution, through the design of a tag array and a payload array, where the tag array only stores entry tags and states, and the payload array only stores payload information, realizes on-demand allocation of storage resources without the need for additional storage. At the same time, through the logic of hit judgment-state branch processing, invalid requests are avoided from occupying pipeline resources, improving the overall operating efficiency of the LSU pipeline.

[0131] Based on the aforementioned inventive concept, such as Figure 8 As shown, the present invention also proposes a computer device 800, including a memory 810, a processor 820, and a computer program 830 stored in the memory 810 and executable on the processor 820. When the processor 820 executes the computer program 830, it implements the aforementioned method.

[0132] This application also provides a computer-readable storage medium storing a computer program that, when executed by a processor, implements the above-described method.

[0133] This application also provides a computer program product, which includes a computer program that, when executed by a processor, implements the above-described method.

[0134] Those skilled in the art will understand that embodiments of the present invention can be provided as methods, systems, or computer program products. Therefore, the present invention can take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, the present invention can take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0135] This invention is described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the invention. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, generate instructions for implementing the flowchart illustrations and / or block diagrams. Figure 1 One or more processes and / or boxes Figure 1 A device that provides the functions specified in one or more boxes.

[0136] These computer program instructions may also be stored in a computer-readable storage medium that can direct a computer or other programmable data processing device to function in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means, which are implemented in a process Figure 1 One or more processes and / or boxes Figure 1 The function specified in one or more boxes.

[0137] These computer program instructions may also be loaded onto a computer or other programmable data processing equipment to cause a series of operational steps to be performed on the computer or other programmable equipment to produce a computer-implemented process, thereby providing instructions that execute on the computer or other programmable equipment for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 The steps of the function specified in one or more boxes.

[0138] The specific embodiments described above further illustrate the purpose, technical solution, and beneficial effects of the present invention. It should be understood that the above descriptions are merely specific embodiments of the present invention and are not intended to limit the scope of protection of the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. A training method for a fixed-step prefetcher based on instruction address, characterized in that, include: Upon receiving a memory access request, the system determines whether the memory access request hits a memory entry in the fixed-step prefetcher based on the instruction address, according to the tag array. The tag array stores the tag and status of the memory entry. If the memory access operation request hits a storage entry, the load information of the hit storage entry in that state is read from the load array according to the state of the hit storage entry; When the hit storage entry is in the prefetch state, a prefetch request is generated based on the payload information and executed in the pipeline; when the hit storage entry is in the training state, the state and payload information of the storage entry are updated; when the hit storage entry is in the non-fixed step state, it is skipped directly.

2. The method according to claim 1, characterized in that, The payload array corresponds one-to-one with the storage entries involved in the tag array, and the payload array stores the payload information of the storage entries. The payload information of each storage entry only includes the payload fields that need to be considered in the state of the storage entry in the tag data.

3. The method according to claim 1, characterized in that, The payload field of a prefetch state storage entry includes step size, confidence level, base address, and access vector; The payload field of the storage entry in the training state includes address difference, address difference valid identifier, previous address, same difference counter and different difference counter.

4. The method according to claim 3, characterized in that, When the hit stored entry is in the prefetch state, a prefetch request is generated based on the payload information and executed on the pipeline, including: The payload information of the hit storage entry is decoded according to the prefetch state to obtain the payload field of the hit storage entry; Find the bit in the access vector corresponding to the address in the current memory access request and set that bit to 1; Update the confidence level based on the access vector; Update the base address and access vector based on the offset between the address and the base address in the current memory access request; Generate prefetch address and prefetch request: Calculate the prefetch address based on the address, step size, and confidence level in the current memory access operation request, and generate a prefetch request after filtering the prefetch address based on the access vector. The pipeline loads the prefetch request onto the storage unit; The prefetch request is executed in the pipeline.

5. The method according to claim 4, characterized in that, Update the confidence based on the access vector, including: Count the number of bits that are 1 in the access vector; If the number is greater than the first threshold, increment the confidence level by 1; if the confidence level exceeds the maximum confidence level, set the confidence level to the maximum confidence level. If the quantity is less than the second threshold, the confidence level is reduced by 1; if the confidence level is less than or equal to 0, the confidence level is set to 0. Otherwise, keep the confidence level unchanged.

6. The method according to claim 4, characterized in that, Also includes: When the state of the hit storage entry is in the prefetch state, the number of bits with a confidence level of 1 and a value of 1 in the access vector is less than the second threshold, and the state of the storage entry is changed to the training state.

7. The method according to claim 4, characterized in that, Determine the address window width, including: Set the address window width to a fixed value, or determine the address window width based on the confidence level, or determine the address window width based on the step size.

8. The method according to claim 4, characterized in that, Update the base address and access vector based on the offset between the address and the base address in the current memory access request, including: If the offset is greater than or equal to a preset multiple of the step size, it is determined that the storage entry needs to be refreshed, the access vector is cleared to zero, and the base address is updated according to the following formula: BaseAddr + W × Stride, where BaseAddr is the base address, W is the address window width, and Stride is the step size; If the offset is less than a preset multiple of the step size, the base address and access vector remain unchanged.

9. The method according to claim 4, characterized in that, After filtering the prefetch addresses based on the access vector, a prefetch request is generated, including: If the bit value of the access vector corresponding to the prefetch address is 1, skip the prefetch address, obtain the address of the next step offset of the prefetch address, and generate a prefetch request; Alternatively, instead of filtering by access vector, a prefetch request can be generated directly using the prefetch address; Alternatively, a prefetch request can be generated after filtering the prefetch addresses using the access vector.

10. The method according to claim 4, characterized in that, The pipeline for loading the prefetch request onto the storage unit includes: If the pipeline of the load storage unit is idle, the prefetch request will be directly pipelined through arbitration; If the pipeline of the load storage unit is busy, the prefetch request is stored in the prefetch request queue, and the pipeline is selected from the prefetch request queue when the load storage unit is idle.

11. The method according to claim 3, characterized in that, When the state of the matched storage entry is in the training state, the state and payload information of the storage entry are updated, including: The payload information of the hit storage entry is decoded according to the training state to obtain the payload domain of the hit storage entry; Calculate the difference between the address in the current memory access request and the address in the previous request, and use it as the current address difference; If the address difference valid flag is 0, update the previous address to the address in the current memory access operation request, update the address difference to the current address difference, and set the address difference valid flag to 1; If the address difference is marked as valid (1), the status and load information of the storage entry are updated based on the current address difference and the load field of the hit storage entry.

12. The method according to claim 11, characterized in that, Based on the current address difference and the payload field of the hit storage entry, update the status and payload information of the storage entry, including: If the current address difference is equal to the address difference, increment the same difference counter by 1, update the different difference counter, and check if the same difference counter has reached the first counter threshold. If the first calculator threshold is reached, it is determined that a fixed step size has been identified, the state of the hit stored entry is updated from the training state to the prefetch state, and the payload domain of the prefetch state is initialized. If the first calculator threshold is not reached, update the load information of the hit storage entry.

13. The method according to claim 11, characterized in that, Based on the current address difference and the payload field of the hit storage entry, update the status and payload information of the storage entry, including: If the current address difference is not equal to the address difference, determine whether the current address difference meets the step size training requirements; If satisfied, update the address difference to the current address difference, update the previous address to the address in the current memory access operation request, increment the difference counter by 1, clear the difference counter to zero, and check if the difference counter has reached the second counter threshold. If the second calculator threshold is reached, it is determined that the address sequence corresponding to the RIP has no fixed step size, and the status of the hit storage entry is updated to the non-fixed step size state. If the second calculator threshold is not reached, update the load information of the hit storage entry; If the conditions are not met, the payload field of the matched storage entry will be updated to the initial value of the training state.

14. The method according to claim 1, characterized in that, Also includes: If the memory access request does not match a storage entry in the tag array, a new storage entry is allocated for the memory access request in the tag array; If the tag array is full, replace an existing tag array with a new tag array entry; If the label array is not full, initialize the state of the new storage entry to the training state, and initialize the payload information of the new storage entry in the training state.

15. The method according to claim 14, characterized in that, Also includes: If the memory access request triggers a request in the missing status handling register, a new storage entry is allocated for the memory access request in the tag array.

16. The method according to claim 14, characterized in that, Replace an existing storage entry in the tag array with the new storage entry, including: The storage entries to be replaced are selected based on a round-robin algorithm, a least recently used algorithm, or a pseudo least recently used algorithm. Alternatively, select the storage entry with low confidence as the storage entry to be replaced; Alternatively, select one of the stored entries that is in the training state or the non-fixed step state as the stored entry to be replaced.

17. The method according to claim 1, characterized in that, Also includes: When the state of the hit storage entry is a non-fixed step state, the number of times the storage entry in the tag array is hit is recorded by a global counter. Once the number of times a stored entry is hit reaches a threshold, the state of the stored entry is changed to training state.

18. A training apparatus for a fixed-step prefetcher based on instruction addresses, characterized in that, include: The hit determination module is used to determine, after receiving a memory access operation request, whether the memory access operation request hits a memory entry in the fixed step prefetcher based on the instruction address according to the tag array. The tag array stores the tag and status of the memory entry. The load reading module is used to read the load information of the hit storage entry in the state from the load array if the memory access operation request hits a storage entry, based on the state of the hit storage entry. The processing module is used to generate a prefetch request based on the payload information and execute it on the pipeline when the state of the hit storage entry is in the prefetch state; to update the state and payload information of the storage entry when the state of the hit storage entry is in the training state; and to skip directly when the state of the hit storage entry is in the non-fixed step size state.

19. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a computer program that, when executed by a processor, implements the method of any one of claims 1 to 17.

20. A computer program product, characterized in that, The computer program product includes a computer program that, when executed by a processor, implements the method of any one of claims 1 to 17.

21. A computer program product, characterized in that, The computer program product includes a computer program that, when executed by a processor, implements the method of any one of claims 1 to 17.

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