Time sequence optimization method and device, equipment and storage medium

Abstract

The invention provides a time sequence optimization method and device, equipment and a storage medium, and the method comprises the steps: firstly obtaining a logic path length, a capture clock length and a transmitting clock length of a register associated with an interface in a first module for solving an interface time sequence convergence problem of the first module and a second module in a chip; and in combination with the clock skew distance between the two modules, determining the clock length of an input / output interface and the skew clock length, and further calculating and optimizing the input time delay information and the output time delay information of the second module in stages. The time sequence optimization is carried out by combining the time sequence characteristics of the register and the clock skew between the modules, the limitation of traditional unified constraint is avoided, the problem of interface time sequence convergence can be efficiently solved, and the physical implementation period of a super-large-scale digital chip is shortened.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and more specifically, to a timing optimization method, apparatus, device, and storage medium. Background Technology

[0002] As chip performance continues to improve and chip size continues to increase, timing optimization can be achieved by using an early clock tree approach during the placement and routing phase to pre-position data paths and avoid subsequent timing issues. Alternatively, useful skew can be used during the place, clock tree synthesis, or postroute phases to converge timing. While these methods can achieve timing convergence within a module, for top-level modules, they may lead to length discrepancies in interface registers between modules, making it difficult to achieve timing convergence between modules.

[0003] Currently, to address the timing convergence issue between modules, the approach used is to apply timing constraints uniformly to all interfaces using timing constraint files. However, this method cannot adapt to the personalized timing requirements of different interfaces, thus making it difficult to achieve efficient timing convergence at the top-level clock. Summary of the Invention

[0004] The purpose of this application is to address the shortcomings of the prior art by providing a timing optimization method, apparatus, device, and storage medium to solve the problem that the existing technology's unified timing constraints on interfaces cannot adapt to the personalized timing requirements of different interfaces, thus making it difficult to achieve efficient timing convergence at the top-level clock.

[0005] To achieve the above objectives, the technical solution adopted in this application is as follows: Firstly, this application provides a timing optimization method, the method comprising: Obtain the register information corresponding to the second module in the first module. The register information includes: the logical path length of the register associated with the interface, the capture clock length, and the transmit clock length. The first module and the second module are functional units inside the chip that perform signal transmission and data interaction. Obtain the clock deviation distance between the first module and the second module, wherein the clock deviation distance is the deviation between the time when the clock signal arrives at the interface register of the first module and the time when the clock signal arrives at the interface register of the second module; The input interface clock length, output interface clock length, and deviation clock length of the first module are determined based on the register information and the clock deviation distance. The input delay information and output delay information of the second module are determined based on the logical path length, the capture clock length, the transmit clock length, the input interface clock length, the output interface clock length, and the offset clock length. The second module is optimized for latency based on the input latency information and the output latency information.

[0006] Secondly, this application provides a timing optimization apparatus, the apparatus comprising: The first acquisition module is used to acquire the register information corresponding to the second module in the first module. The register information includes: the logical path length, the capture clock length, and the transmit clock length of the register associated with the interface. The second acquisition module is used to acquire the clock deviation distance between the first module and the second module; The first determining module is used to determine the input interface clock length, output interface clock length, and deviation clock length of the first module based on the register information and the clock deviation distance. The second determining module is used to determine the input delay information and output delay information of the second module based on the logical path length, the capture clock length, the transmit clock length, the input interface clock length, the output interface clock length, and the deviation clock length. The latency optimization module is used to optimize the latency of the second module based on the input latency information and the output latency information.

[0007] Thirdly, this application provides an electronic device, including: a processor, a storage medium, and a bus, wherein the storage medium stores machine-readable instructions executable by the processor, and when the electronic device is running, the processor communicates with the storage medium via the bus, and the processor executes the machine-readable instructions to perform the steps of a timing optimization method as described in the first aspect.

[0008] Fourthly, this application provides a computer-readable storage medium storing a computer program that, when executed by a processor, performs the steps of the timing optimization method described in the first aspect.

[0009] The beneficial effects of this application are as follows: By obtaining the logical path length, capture clock length, and transmit clock length of the registers associated with the interface between the first module and the second module, and combining this with the clock deviation distance between the two modules, the clock length and deviation clock length of the input / output interface are determined, and then the input / output delay information of the second module is calculated and optimized. By combining the timing characteristics of the registers within the module with the clock deviation between modules to determine the timing constraints corresponding to the interfaces between modules, the limitations of traditional unified timing constraints are avoided. This effectively solves the timing convergence problem caused by inconsistent interface clock lengths in SOC design, ensuring that the timing path meets the setup and hold time requirements. Furthermore, the method of this application does not rely on large-scale top-level iterations and can be directly applied in the APR process. Each module can perform pre-checks and timing optimizations, improving the interface timing convergence efficiency. It is also adaptable to different clock domains and APR stages, exhibiting strong versatility and efficiently supporting the physical implementation of large-scale digital chips.

[0010] To make the above-mentioned objectives, features and advantages of this application more apparent and understandable, preferred embodiments are described below in detail with reference to the accompanying drawings. Attached Figure Description

[0011] To more clearly illustrate the technical solutions of the embodiments of this application, the accompanying drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of this application and should not be regarded as a limitation of the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0012] Figure 1 This illustration shows a schematic diagram of the design structure of a primary module according to an embodiment of this application; Figure 2 A flowchart of a timing optimization method provided in an embodiment of this application is shown; Figure 3 A schematic diagram of a module interface grouping provided in an embodiment of this application is shown; Figure 4 This illustration shows a schematic diagram of an internal connection structure of an interface provided in an embodiment of this application; Figure 5 This illustration shows a clock skew diagram provided in an embodiment of this application; Figure 6 This document illustrates a flowchart of a method for determining register information according to an embodiment of this application. Figure 7 This document illustrates a flowchart of determining an associated register according to an embodiment of this application. Figure 8 This document illustrates a flowchart of an embodiment of the present application for determining the input interface clock length and the output interface clock length. Figure 9 This illustration shows a flowchart of a method for determining input delay information and output delay information according to an embodiment of this application; Figure 10 This illustration shows a flowchart of another method for determining input delay information and output delay information provided in an embodiment of this application; Figure 11 This illustration shows a flowchart of another method for determining input delay information and output delay information provided in an embodiment of this application; Figure 12 This illustrates another flowchart of timing optimization provided by an embodiment of this application; Figure 13 This paper shows a schematic diagram of the structure of a timing optimization device provided in an embodiment of this application; Figure 14 A schematic diagram of the structure of an electronic device 140 provided in an embodiment of this application is shown. Detailed Implementation

[0013] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. The components of the embodiments of this application described and shown in the accompanying drawings can generally be arranged and designed in various different configurations. Therefore, the following detailed description of the embodiments of this application provided in the accompanying drawings is not intended to limit the scope of the claimed application, but merely represents selected embodiments of this application. All other embodiments obtained by those skilled in the art based on the embodiments of this application without inventive effort are within the scope of protection of this application.

[0014] It should be noted that the term "comprising" will be used in the embodiments of this application to indicate the presence of the features declared thereafter, but does not exclude the addition of other features.

[0015] The Automated Placement and Routing (APR) process in chip design backend consists of three main stages: placement, clock tree synthesis, and post-routing signal connection. During this process, due to the varying distances of different registers from the clock source, clock arrival times will differ, resulting in clock skew between different registers.

[0016] In existing technologies, two common approaches are used to achieve better timing closure within a module. The first is the early clock tree approach, which involves inserting a clock buffer in advance to stabilize the clock structure. The second is the useful skew approach, which introduces a controllable clock skew to alleviate the problem of excessively long data paths. For example, delaying the clock of a register allows more time for data transmission, thereby resolving setup time violations.

[0017] However, digital integrated circuits typically consist of multiple modules that interact with each other through numerous interfaces. Each module may have undergone internal optimization using the two methods mentioned above, but this can lead to inconsistent clock distributions among the modules. If these modules are integrated at the top level, the interface paths between them will face enormous timing pressure, making setup or hold time violations more likely.

[0018] Currently, the approach to addressing these technical issues is to set uniform input / output delay constraints for the entire chip or interface. However, this method ignores the actual clock skew and data path length differences between modules, resulting in imprecise constraints. These constraints can be either overly conservative and wasteful of resources, or overly aggressive and lead to violations. Furthermore, it is currently impossible to perform quantitative analysis and collaborative optimization of the interface's clock and data paths during the module design phase. Therefore, timing problems often only surface after top-level integration, requiring repeated modifications to lower-level modules and multiple APR (Advanced Process Reengineering) processes, thus extending the design cycle and reducing design efficiency.

[0019] In summary, as the scale of System on Chip (SoC) increases and the independent optimization of modules becomes more widespread, although timing convergence can be achieved within modules, timing issues caused by clock skew and path differences at the interface need to be addressed. Traditional unified constraint methods are no longer effective in dealing with these issues, so there is an urgent need for a refined, quantifiable, and proactive interface timing optimization scheme.

[0020] Based on this, this application proposes a timing optimization method. By obtaining the register information corresponding to the second module in the first module, including the logical path length, capture clock length, and transmit clock length of the interface-associated registers in the first module corresponding to the second module, and combining this with the register information of the first module and the clock offset distance between the first and second modules, the input interface clock length, output interface clock length, and offset clock length of the first module are determined. Based on these parameters, the required input delay information and output delay information of the second module are further calculated, and this delay information is used to set precise input and output delay constraints for the second module, achieving targeted delay optimization.

[0021] By incorporating the actual clock differences between modules caused by Early Clock Tree and Useful Skew, the path delay and deviation factors in the real physical implementation are included in the interface timing modeling. This makes the constraints closer to the actual circuit behavior, which can significantly improve the timing convergence capability of cross-module interfaces, reduce repeated iterations caused by violations after top-level integration, and support fine-grained constraint settings at different stages of the APR process to improve optimization efficiency. It also has good versatility and is applicable to various process nodes and complex SoC architectures. This can effectively shorten the design cycle of ultra-large-scale chips and enhance the robustness and predictability of physical implementation.

[0022] like Figure 1 The diagram shown is a schematic of a first-level module design, which includes five second-level modules. Assume... Figure 1 Of the five modules, Module 1 interacts with the other four modules. Therefore, Module 1 can be designated as the first module, and Modules 2, 3, 4, and 5 can be designated as second modules. Based on the method steps of this application, the input and output latency information of each second module is determined, and latency optimization is performed on each second module according to its input and output latency information. The following embodiments of this application use one of the second modules as an example for illustration. During the APR process, the timing optimization method of this application can be used to perform advance checks and timing optimization on each second module, thereby achieving timing convergence of the first module in all directions.

[0023] Next, combine Figure 2 The timing optimization method of this application is described, such as... Figure 2 As shown, the method includes: S201. Obtain the register information in the first module that corresponds to the second module.

[0024] The core of inter-module interface timing convergence lies in understanding the timing characteristics of the interface-associated registers. As the transmitter or receiver of signals, the register's logical path length determines the basic delay of signal transmission. The capture clock length and transmit clock length directly affect the synchronization relationship between the clock and data. Therefore, the delay constraints of the second module can be determined based on the register information corresponding to the second module in the first module, thereby achieving timing optimization for the second module.

[0025] The register information includes: the logical path length, capture clock length, and transmit clock length of the registers associated with the interface. Specifically, the registers associated with the interface refer to the registers associated with the interface in the first module that interacts with the second module.

[0026] The logical path length refers to the physical length or timing delay value of the signal logical transmission path where the interface associated register is located, which is used to reflect the time required for data signals to be transmitted between two modules.

[0027] The capture clock length refers to the path length of the capture clock to the clock terminal of the interface-associated register. The transmit clock length refers to the path length of the transmit clock to the clock terminal of the interface-associated register. The capture clock is the clock signal used to sample input interface data, and the transmit clock is the clock signal used to drive output interface data.

[0028] The first module and the second module refer to the functional units within the chip that perform signal transmission and data interaction. The first module and the second module interact with each other through an interface. (See reference...) Figure 1 The module structure diagram shown illustrates that if module one is considered the first module, then any one of the other four modules that have signal transmission or data interaction with module one can be considered the second module. Alternatively, if... Figure 1 If Module 2 is used as the first module, then Module 1, which has data interaction and signal transmission with Module 2, can be used as the second module.

[0029] The first module includes multiple interfaces, which are a set of boundary ports for signal transmission and data interaction between the first module and other modules, including input ports and output ports. In one possible implementation, the interfaces of the first module can be grouped based on their relative positions to other modules, with each interface group used to interact with a specific second module. (See reference...) Figure 3 The first module interface diagram shown can be interpreted according to the first module and... Figure 1 The positional relationship of the other four modules divides the interface of the first module into... Figure 3 The four interface groups shown are used to interact with a module, and each interface group has a corresponding register. For example, group 1 is used to interact with module 3, group 2 with module 2, group 3 with module 4, and group 4 with module 5. The register is located at the sending or receiving end of the interface and is used to synchronize the data transmission between the first module and other modules.

[0030] Reference Figure 4 The diagram shows an internal connection of an interface. The first module includes multiple interfaces for data interaction and signal transmission with the second module. Each interface is connected to at least one register. When the first module interacts with the second module or transmits signals, synchronization is achieved through the registers and interfaces shown in the diagram.

[0031] It should be noted that, Figure 3Grouping interfaces according to module location is one example provided in this application. Alternatively, interface registers can be pre-classified based on Integrated Clock Gating (ICG). Registers within the same ICG have similar clock path characteristics and can be grouped together for easier unified management. Furthermore, after grouping the interface registers, their placement can be predetermined based on the grouping to avoid unnecessary delays caused by excessive physical distance.

[0032] The register information corresponding to the second module can be the register information corresponding to the interface group that interacts with the second module. For example, the second module is... Figure 1 In module three, the register information corresponding to module two is: Figure 3 Register information corresponding to group 1 in the middle.

[0033] S202, Obtain the clock deviation distance between the first module and the second module.

[0034] In SOC design, due to buffer position and drive capability adjustments during clock tree synthesis, as well as routing resource limitations, the arrival times of the interface register clocks of different modules within the same clock domain differ. This deviation leads to clock and data asynchrony during data transmission. If this deviation is not quantified, subsequent delay constraints will be flawed, preventing timing convergence. Therefore, the clock deviation distance between the first and second modules can be obtained, allowing the establishment of timing constraints for the second module based on this distance, thus achieving timing optimization for the second module.

[0035] Clock skew distance is the difference in the arrival time of the clock signal in different registers caused by a combination of on-chip clock skew (OCV) and differences in clock tree structure. Specifically, the clock skew distance between the first module and the second module refers to the deviation between the time it takes for the clock signal to arrive at the interface register of the first module and the time it takes for the clock signal to arrive at the interface register of the second module.

[0036] In one possible implementation, during the clock tree synthesis stage, the complete paths of the clock signal to the interface registers of the first module and the second module can be traced based on the clock tree topology of the chip. The transmission delay of the clock signal on the two paths can be simulated by timing analysis tools to obtain the actual clock arrival time of the interface registers of the first module and the second module respectively. The difference between the arrival time of the first module and the arrival time of the second module can be calculated to obtain the clock deviation distance.

[0037] Reference Figure 5 This is a schematic diagram of the clock path deviation between the first module and the second module, referencing... Figure 5The clock path of the first module is shorter, while the clock path of the second module passes through more buffer units. Therefore, there is a time difference between when the registers of the two modules receive the clock signal. This time difference is called the clock deviation distance. For example, in the interface clock path between the first and second modules, if the clock arrives at the register of the first module at 1.2ns and at the register of the second module at 1.5ns, then the clock deviation distance is 0.3ns.

[0038] S203. Determine the input interface clock length, output interface clock length, and deviation clock length of the first module based on the register information and clock deviation distance.

[0039] The input interface clock length is a clock skew parameter corresponding to the input interface of the first module, reflecting the deviation of the input interface clock of the first module from the average clock length. It is used to optimize the clock path length of the output interface of the second module. The output interface clock length is a clock skew parameter corresponding to the output interface of the first module, reflecting the deviation of the output interface clock of the first module from the average clock length. It is used to optimize the clock path length of the input interface of the second module. The skew clock length refers to the additional timing variable caused by the clock skew distance, used to compensate for establishment and maintenance violations caused by the non-ideal distribution of the clock tree.

[0040] In one possible implementation, the clock lengths of all interface registers in the first module can be counted, and the average clock length can be calculated as a reference value. Then, the input interface clock length and output interface clock length can be determined based on the reference value, the capture clock length, and the transmit clock length.

[0041] Optionally, the clock skew distance can be converted into the skew clock length based on a preset strategy. For example, a mapping relationship between clock skew distance and skew clock length can be established in advance, and the skew clock length corresponding to the clock skew distance can be determined according to the established mapping relationship. Alternatively, the clock skew distance can be input as an input parameter into a pre-built function, and the skew clock length can be calculated and obtained through the function.

[0042] S204. Determine the input delay information and output delay information of the second module based on the logic path length, capture clock length, transmit clock length, input interface clock length, output interface clock length, and offset clock length.

[0043] The input delay information refers to the maximum allowable delay constraint value of the second module's input interface, used to ensure that the input interface data is stable and valid within the clock sampling window. The output delay information refers to the maximum allowable delay constraint value of the second module's output interface, used to ensure that the output interface data is transmitted to the interaction module on time.

[0044] The input delay information of the second module needs to match the transmission characteristics of the output data of the first module, while compensating for clock skew between modules; the output delay information needs to match the reception characteristics and clock skew of the input data of the first module. Since the clock states are different at different stages in the APR process, the delay information can be calculated in stages to ensure the effectiveness of the timing constraints at each stage.

[0045] Optionally, the input delay information includes the input delay information under the ideal clock in the Place stage and the input delay information under the real clock in the Clock Tree Synthesis (CTS) stage, and the output delay information includes the output delay information under the ideal clock in the Place stage and the output delay information under the real clock in the CTS stage.

[0046] S205. Optimize the latency of the second module based on the input latency information and the output latency information.

[0047] The input and output delay information provides clear constraints for the interface timing of the second module. By applying these constraints to the APR process of the second module, the placement and routing tools can be guided to adjust the cell position, routing path, clock tree structure, etc., to ensure that the interface timing of the second module matches that of the first module, eliminate setup time and hold time violations, and ultimately achieve timing convergence of the interface between the first and second modules.

[0048] Optionally, in the APR process of the second module, the input delay information can be used as the input delay constraint of the second module, and the output delay information can be used as the output delay constraint of the second module. During the Place phase, the cell placement is adjusted based on the delay constraints under an ideal clock to avoid excessive distance between interface registers causing logical path issues. During the CTS phase, the routing path is optimized based on the delay constraints to reduce signal transmission delay. After optimization, the timing margin of the second module interface is checked using timing analysis tools. If violations are found, the calculation parameters for adjusting the delay information are returned (such as re-selecting target registers and correcting clock offset distances), and the constraints and optimization are executed again until timing convergence.

[0049] In this embodiment, the logical path length, capture clock length, and transmit clock length of the registers associated with the interface between the first module and the second module are obtained. Combined with the clock deviation distance between the two modules, the input / output interface clock length and deviation clock length are determined. Then, the input / output delay information of the second module is calculated and optimized. By combining the timing characteristics of the registers within the module with the clock deviation between modules to determine the timing constraints corresponding to the interfaces between modules, the limitations of traditional unified timing constraints are avoided. This effectively solves the timing convergence problem caused by inconsistent interface clock lengths in SOC design, ensuring that the timing path meets the setup and hold time requirements. Furthermore, the method of this application does not rely on large-scale top-level iterations and can be directly applied in the APR process. Each module can perform pre-checks and timing optimizations, improving interface timing convergence efficiency. It is also adaptable to different clock domains and APR stages, exhibiting strong versatility and efficiently supporting the physical implementation of large-scale digital chips.

[0050] The following is a further explanation of how the register information corresponding to the second module in the first module is obtained, such as... Figure 6 As shown, the above step S201 includes: S601. Obtain all associated registers in the interface between the first module and the second module.

[0051] Data transmission between modules requires the use of registers for transmission or reception, and the timing characteristics of different registers directly affect the overall timing of the interface. Only by first locking down the registers associated with the interface interaction can timing parameters be accurately extracted, interference from irrelevant registers be avoided, and the subsequent timing analysis be made more targeted.

[0052] Among them, the associated register is the register in the first module that has a signal interaction relationship with the interface of the second module, and it is the transmitting end or receiving end of the interface data transmission in the first module. For example, all registers in the first module that have a signal interaction relationship with the interface of the second module can be obtained, and sorted according to the performance of the registers, and the register with the worst timing performance can be found as the target register.

[0053] Optionally, the interface signal type and transmission direction between the first module and the second module can be determined based on the chip system architecture, the transmission path of the signal within the first module can be traced, and all registers involved in the path can be located. In conjunction with the ICG association relationship, the registers of the ICG corresponding to the interface of the second module can be divided into a group, and all registers in the group are the associated registers that interact with the interface of the second module.

[0054] S602. Determine the target register based on the timing values ​​of each associated register.

[0055] Timing values ​​are parameters characterizing the timing performance of registers, including setup time margin, hold time margin, path delay, etc., used to judge the timing quality of registers and their impact on interface convergence. The target register can be the most timing-critical register selected from multiple associated registers based on the timing values ​​of each associated register. Its parameters can reflect the worst-case timing of the interface. For example, the target register can be the register with the worst timing.

[0056] It should be understood that the timing performance of multiple associated registers varies; some registers have ample timing margins, while others may have timing violations or very little margin. Using the timing parameters of ordinary registers as the basis for analysis would underestimate the interface's timing pressure, leading to insufficient subsequent latency constraints. Instead, the register with the worst timing performance is used as the target register. Therefore, the parameters of the target register reflect the most stringent timing scenarios of the interface, and constraints designed based on these parameters can ensure complete interface timing convergence.

[0057] In one possible implementation, timing values ​​of each associated register can be extracted using timing analysis tools in the APR process. By comparing the timing values ​​of all associated registers, the register with the smallest timing margin or the one with a timing violation can be selected as the target register.

[0058] S603. Based on the layout and routing results of the first module, obtain the logic path length, capture clock length, and transmit clock length of the target register.

[0059] The placement and routing results are the physical implementation data in the Postroute stage of the chip APR process, including data such as the physical location of registers, signal routing paths, and clock path lengths.

[0060] The placement and routing result is the actual data after the physical implementation of the registers, including the physical location of the registers and the details of the routing path. The timing parameters extracted based on this result best match the actual engineering situation. The logic path length directly determines the basic delay of signal transmission, while the capture clock length and transmit clock length can reflect the synchronization relationship between the clock and the data. These three are the core basic data for calculating subsequent delay information. If the data is extracted based on ideal design data, there will be deviations from the actual engineering scenario, leading to the failure of constraints.

[0061] In one possible implementation, physical design data from the Postroute phase of the first module, including routing files and clock tree topology files, can be read to determine the physical location of the target register, the routing paths of the signal input / output ports, and the path of the clock signal to the target register. The timing delay corresponding to the routing length from the input terminal to the interface port of the target register is calculated using tools as the logic path length. For the target register of the input interface, the delay corresponding to the path length of the capture clock from the clock source to the clock terminal of the target register is calculated. For the target register of the output interface, the delay corresponding to the path length of the transmit clock from the clock source to the clock terminal of the target register is calculated.

[0062] S604. Use the logical path length, capture clock length, and transmit clock length of the target register as register information.

[0063] The core function of register information is to provide the foundational data for subsequent latency calculations. The three parameters of the target register cover the key dimensions of interface timing: the logic path length reflects data transmission latency, and the capture clock length and transmit clock length reflect clock synchronization characteristics. Using these three parameters as register information ensures that subsequent calculations of input / output interface clock lengths and latency information focus on the most demanding timing scenarios of the interface, avoiding interference from redundant parameters, while ensuring the relevance and effectiveness of the data.

[0064] Optionally, the logic path length, capture clock length, and transmit clock length can be organized according to a preset format to form structured register information.

[0065] In this embodiment, by acquiring the associated registers that interact with the second module interface, the most timing-critical target registers are selected, and then their core timing parameters are extracted as register information based on the placement and routing results. This allows focusing on key timing nodes of the interface, eliminating irrelevant interference, and ensuring that the register information is consistent with engineering realities, accurate and reliable. This provides data support for subsequent delay calculations and optimizations, improves the targeting and effectiveness of timing optimization, solves the interface timing convergence problem, and shortens the physical implementation cycle of large-scale digital chips.

[0066] The following is a further explanation of the acquisition of at least one associated register in the interface interaction between the first module and the second module, as described above. Figure 7 As shown, the above step S601 includes: S701. Obtain the register group in the first module that corresponds to the second module.

[0067] Optionally, register grouping refers to a set of registers in the first module categorized according to inter-module interface interaction relationships, ICG association relationships, or front-end definitions. Registers within the same group all have signal interaction with the interface of a specific module, avoiding interference from unrelated registers. The register grouping corresponding to the second module can be a register grouping that has signal interaction with the interface of the second module.

[0068] It should be noted that in a SOC design, the first module may interface with multiple modules, resulting in a large number of registers. Directly filtering related registers can easily lead to the inclusion of registers unrelated to the second module, causing redundancy and decreased accuracy in timing parameter extraction. By pre-grouping registers corresponding to the second module, the target range can be narrowed down, ensuring the relevance of subsequent related register filtering, while reducing logic path redundancy and avoiding excessive clock skew during useful skew applications.

[0069] S702. Treat each register in the register group as an associated register.

[0070] The purpose of register grouping is to aggregate all critical registers that interact with the second module interface. Each register within a group directly participates in signal transmission between the two modules and is a key node affecting interface timing. Treating all registers within a group as associated registers comprehensively covers all transmission scenarios of the interface, avoiding incomplete parameter extraction caused by missing key timing nodes.

[0071] In one possible implementation, a complete list of register groups determined in step S701 above can be first determined, clarifying the identifier and physical location information of each register. Then, the registers in the list can be marked as associated registers that interact with the interface of the second module using a script or design tool.

[0072] In this embodiment, by first obtaining the register groups corresponding to the second module in the first module, and then using each register within the group as associated registers, the key timing nodes of the interface interaction can be accurately located, avoiding interference from irrelevant registers. The grouping method, combined with ICG association relationships, can reduce logic path redundancy and clock skew, making subsequent register information extraction more targeted, significantly improving the accuracy of interface timing parameters, effectively solving the problem of timing convergence difficulties under traditional constraint methods, and shortening the optimization cycle.

[0073] The following is a further explanation of the determination of the input interface clock length, output interface clock length, and offset clock length of the first module based on register information and clock offset distance. Step S203 above includes: The input interface clock length and output interface clock length are determined based on the capture clock length, the transmit clock length, and the pre-acquired average clock length.

[0074] The average clock length refers to the average clock length of multiple registers related to the interface in the first module.

[0075] The input and output interface clock lengths reflect the degree of clock deviation from the reference level, rather than the absolute length. The capture and transmit clock lengths are the actual clock parameters of the target register, while the average clock length is the reference level of the clock within the module. By calculating the correlation between these three, the impact of clock deviation on interface timing can be quantified, providing a precise basis for deviation compensation for subsequent delay information calculations in the second module, and avoiding constraint mismatches caused by directly using absolute clock lengths.

[0076] In one possible implementation, the clock lengths of all registers related to interface interaction in the first module can be counted, and the average clock length can be obtained by calculating the average value. Then, based on the difference between the capture clock length, the transmit clock length and the average clock length, the input interface clock length and the output interface clock length can be calculated respectively.

[0077] The process described above, which determines the input interface clock length and the output interface clock length based on the capture clock length, the transmit clock length, and the pre-acquired average clock length, is as follows: Figure 8 As shown, it includes: S801: The difference between the captured clock length and the average clock length is used as the input interface clock length.

[0078] The difference between the capture clock length and the average clock length reflects the direction and magnitude of the input interface clock's deviation from the module's overall clock reference. If the capture clock is longer than the average, the difference is positive, indicating a sampling clock delay in the first module, which needs to be compensated for in the output delay of the second module. If the capture clock is shorter than the average, the difference is negative, requiring corresponding adjustments to the constraints to ensure sampling synchronization.

[0079] The input interface clock length is calculated as: Input interface clock length = Capture clock length - Average clock length. For example, if the capture clock length is 1.5ns and the average clock length is 1.2ns, then the input interface clock length is 1.5 - 1.2 = 0.3ns; if the capture clock length is 1.0ns and the average clock length is 1.2ns, then the input interface clock length is -0.2ns.

[0080] S802, The difference between the transmit clock length and the average clock length is used as the output interface clock length.

[0081] The difference between the transmit clock length and the average clock length reflects the deviation of the output interface clock from the overall module clock reference. If the transmit clock is longer than the average, the difference is positive, meaning that the data transmission delay of the first module needs to be compensated for in the input delay of the second module; if the transmit clock is shorter than the average, the difference is negative, and the constraints are adjusted to ensure that the data transmission is synchronized with the receiving module clock.

[0082] The output interface clock length is calculated as follows: Output clock length = Transmit clock length - Average clock length. For example, if the transmit clock length is 1.4ns and the average clock length is 1.2ns, then the output interface clock length is 1.4 - 1.2 = 0.2ns; if the transmit clock length is 1.1ns and the average clock length is 1.2ns, then the output interface clock length is -0.1ns.

[0083] The following is a further explanation of how the input delay information and output delay information of the second module are determined based on the logic path length, input interface clock length, output interface clock length, and offset clock length. Figure 9 As shown, step S204 above includes: S901. During the unit layout stage, the input delay information and output delay information of the second module are determined based on the logic path length, input interface clock length, output interface clock length, and offset clock length.

[0084] During the cell layout phase, a real clock tree has not yet been built, and the clock is in an ideal state, but the delay caused by clock deviation already exists. The input interface clock length and output interface clock length can reflect the deviation relative to the average clock. By combining the logic path length and the deviation clock length, the delay constraint adapted for this phase can be calculated.

[0085] S902. During the clock tree synthesis stage, the input delay information and output delay information of the second module are determined based on the logic path length, the offset clock length, the capture clock length, and the transmit clock length.

[0086] In the clock tree synthesis phase, a real clock tree has been constructed. The capture clock length and transmit clock length are actual parameters of the real clock path, which are more consistent with the actual scenario than the input / output interface clock lengths. At this point, the real clock length can be used to replace the relative deviation parameter. By combining the logic path length and the deviation clock length, more accurate delay constraints can be calculated to ensure that the clock tree is synchronized with the data path and to avoid timing deviations caused by the real clock.

[0087] In this embodiment, the latency information of the second module is calculated using adapted parameters for the two key stages of cell layout and clock tree synthesis in the APR process, thereby adapting to the clock characteristics of different stages. This avoids the rigidity of traditional unified constraints, enabling latency constraints to accurately match the actual scenarios at each stage, effectively solving the timing deviation caused by the transition from ideal to reality, and improving the pertinence and effectiveness of timing optimization.

[0088] The following is a further explanation of how the input delay information and output delay information of the second module are determined based on the logic path length, input interface clock length, output interface clock length, and offset clock length. Figure 10 As shown, the above S901 step includes: S1001. The sum of the logic path length, the input interface clock length, and the offset clock length is used as the output delay information.

[0089] During the cell layout phase, the clock is set to an ideal clock. The input interface clock length and the offset clock length are the core sources of clock skew at this stage. They need to be added to the logic path length to fully cover the total data transmission delay. Considering only a single parameter can lead to insufficient or excessive delay constraints, failing to meet the timing requirements under the ideal clock and potentially affecting the timing convergence of subsequent processes.

[0090] Assuming the logic path length is denoted as A, the input interface clock length as C, and the offset clock length as F, the total delay information of the input data of the first module can be expressed as A + C + F. Based on the total delay information of the input data of the first module, the output interface of the second module is subject to delay constraints, i.e., the output delay information of the second module = logic path length + input interface clock length + offset clock length. For example, if A = 1.8ns, C = 0.4ns, and F = 0.6ns, then the input delay information = 1.8 + 0.4 + 0.6 = 2.8ns, which serves as the delay constraint for the output interface of the second module at this stage.

[0091] It should be noted that the sum of the logic path length, the input interface clock length, and the offset clock length constitutes the latency information of the input interface of the first module. Since the input interface of the first module interacts with the output interface of the second module, the latency information of the input interface of the first module can be used as the output latency information of the output interface of the second module. Similarly, the latency information of the output interface of the first module can be used as the input latency information of the input interface of the second module.

[0092] S1002. The sum of the logic path length, the output interface clock length, and the offset clock length is used as the input delay information.

[0093] The timing constraints of the input interface must match the ideal clock characteristics. The output interface clock length reflects the deviation of the first module's output clock from the reference. By superimposing the logic path length and the deviation clock length, the total delay requirement of the first module's output interface can be obtained. Since there is data interaction between the first and second modules, the input interface of the second module is then subject to delay constraints based on the total delay information of the first module's output interface. This ensures that the output data of the first module is synchronized with the clock of the second module, avoiding timing violations caused by constraint deviations.

[0094] Assuming the logical path length is denoted as A, the output interface clock length as E, and the offset clock length as F, the input delay information of the second module can be expressed as A + E + F, i.e., input delay information = logical path length + output interface clock length + offset clock length. For example, if A = 1.8ns, E = 0.3ns, and F = 0.6ns, then the output delay information = 1.8 + 0.3 + 0.6 = 2.7ns, which serves as the delay constraint for the input interface of the second module in this stage.

[0095] In this embodiment, the logic path length, interface clock length, and offset clock length in the cell layout stage are integrated into input / output delay information by summation calculation, which simplifies the calculation process and reduces the complexity of the calculation.

[0096] The following is a further explanation of how the input and output delay information of the second module is determined based on the logic path length, offset clock length, capture clock length, and transmit clock length. Figure 11 As shown, the above step S902 includes: S1101. The sum of the logic path length, the capture clock length, and the offset clock length is used as the output delay information.

[0097] During the clock tree synthesis phase, a real clock tree has been constructed. The captured clock length represents the actual clock path delay of the first module's input interface, not a relative deviation. The logic path length is the basic delay for data transmission, and the deviation clock length is the clock synchronization deviation between modules. The sum of these three factors can comprehensively cover the end-to-end delay of data transmission at the input interface, yielding the total delay of the first module's input interface. Ignoring the real clock parameters and using constraints under ideal clock conditions will lead to a disconnect between timing constraints and the actual scenario, resulting in timing violations.

[0098] Assuming the logic path length is denoted as A, the capture clock length as B, and the offset clock length as F, the total latency of the input interface of the first module can be expressed as A + B + F. Based on this total latency, the output interface of the second module is constrained, i.e., the output latency of the second module = logic path length + capture clock length + offset clock length. For example, if A = 2.2ns, B = 1.3ns, and F = 0.5ns, then the output latency = 2.2 + 1.3 + 0.5 = 4.0ns, serving as a precise constraint on the output interface of the second module at this stage.

[0099] S1102. The sum of the logic path length, transmit clock length, and offset clock length is used as the input delay information.

[0100] The actual timing constraints of the output interface of the first module need to be based on the actual transmit clock length, plus the logic path length and the offset clock length, to accurately reflect the total latency requirements of data transmission in the first module. This sum ensures that the output data transmission timing of the first module is synchronized with the actual clock of the second module, while compensating for clock skew between modules and avoiding timing convergence failures caused by mismatch between the actual clock and the constraints. Therefore, the total latency of the output interface of the first module can be used as the timing constraint of the input interface of the second module to compensate for the clock skew between the first and second modules.

[0101] Assuming the logical path length is denoted as A, the transmit clock length as D, and the offset clock length as F, the total delay information of the first module's output interface can be expressed as A + D + F. Based on this total delay information, the input interface of the second module is constrained, i.e., the input delay information of the second module = logical path length + transmit clock length + offset clock length. For example, if A = 2.2ns, D = 1.4ns, and F = 0.5ns, then the input delay information = 2.2 + 1.4 + 0.5 = 4.1ns, serving as a precise constraint on the second module's input interface at this stage.

[0102] In this embodiment, the logic path length, actual clock length, and offset clock length in the cell layout stage are integrated into input / output delay information by summation calculation, which simplifies the calculation process and reduces the complexity of the calculation.

[0103] The following is a further explanation of the latency optimization of the second module based on the input latency information and output latency information, such as... Figure 12 As shown, the above step S205 includes: S1201. Call the first timing constraint command to use the input delay information as the input delay of the input interface of the second module.

[0104] The first timing constraint command is used to configure the input delay of the module's input interface, which can solidify the input delay information into a design constraint. For example, the input delay of the second module can be set using the command "set_input_delay $value -clock vclk [get_ports *]".

[0105] S1202. Call the second timing constraint command to use the output delay information as the output delay of the second module's output interface.

[0106] The second timing constraint command is used to configure the output delay of the module's output interface, which can solidify the output delay information into design constraints. For example, the output delay of the second module can be set using the command "set_output_delay $value -clock vclk [get_ports *]".

[0107] This application embodiment solidifies the calculated input / output delay information into the interface constraints of the second module by invoking standardized timing constraint commands. This application achieves the engineering implementation of delay information, enabling APR tools to accurately perform timing optimization and avoiding the blindness of traditional unified constraints. Furthermore, it is simple to operate, highly adaptable, requires no large-scale top-level iterations, and can quickly transform theoretical calculations into actual timing convergence results, significantly improving the efficiency and reliability of timing optimization for ultra-large-scale chip interfaces.

[0108] Based on the same inventive concept, this application also provides a timing optimization device corresponding to the timing optimization method. Since the principle of the device in this application is similar to the timing optimization method described above in this application, the implementation of the device can refer to the implementation of the method, and the repeated parts will not be described again.

[0109] Figure 13 A module structure diagram of a timing optimization device provided in an embodiment of this application is shown below. Figure 13 As shown, the device includes: The first acquisition module 1301 is used to acquire the register information corresponding to the second module in the first module. The register information includes: the logical path length of the register associated with the interface, the capture clock length, and the transmit clock length. The second acquisition module 1302 is used to acquire the clock deviation distance between the first module and the second module; The first determining module 1303 is used to determine the input interface clock length, output interface clock length, and deviation clock length of the first module based on register information and clock deviation distance. The second determining module 1304 is used to determine the input delay information and output delay information of the second module based on the logic path length, the capture clock length, the transmit clock length, the input interface clock length, the output interface clock length, and the deviation clock length. The delay optimization module 1305 is used to optimize the delay of the second module based on the input delay information and the output delay information.

[0110] As one possible implementation, the first acquisition module 1301 is specifically used for: Retrieve all associated registers in the interface between the first module and the second module; The target register is determined based on the timing values ​​of each associated register; Based on the layout and routing results of the first module, obtain the logic path length, capture clock length, and transmit clock length of the target register; The logical path length, capture clock length, and transmit clock length of the target register are used as register information.

[0111] As one possible implementation, the first acquisition module 1301 is specifically used for: Obtain the register group corresponding to the second module in the first module; Each register in the register group is treated as an associated register.

[0112] As one possible implementation, the first acquisition module 1303 is specifically used for: The input interface clock length and output interface clock length are determined based on the capture clock length, the transmit clock length, and the pre-acquired average clock length.

[0113] As one possible implementation, the first determining module 1303 is specifically used for: The difference between the captured clock length and the average clock length is used as the input interface clock length; The difference between the transmit clock length and the average clock length is used as the output interface clock length.

[0114] As one possible implementation, the second determining module 1304 is specifically used for: During the unit layout stage, the input delay information and output delay information of the second module are determined based on the logic path length, input interface clock length, output interface clock length, and offset clock length. During the clock tree synthesis phase, the input delay information and output delay information of the second module are determined based on the logic path length, offset clock length, capture clock length, and transmit clock length.

[0115] As one possible implementation, the second determining module 1304 is specifically used for: The sum of the logic path length, the input interface clock length, and the offset clock length is used as the output delay information; The sum of the logic path length, the output interface clock length, and the offset clock length is used as the input delay information.

[0116] As one possible implementation, the second determining module 1304 is specifically used for: The sum of the logic path length, capture clock length, and offset clock length is used as the output delay information; The sum of the logical path length, transmit clock length, and offset clock length is used as the input delay information.

[0117] As one possible implementation, the latency optimization module 1305 is specifically used for: Invoke the first timing constraint command to use the input delay information as the input delay of the input interface of the second module; The second timing constraint command is invoked to use the output delay information as the output delay of the second module's output interface.

[0118] This application's embodiments obtain the logical path length, capture clock length, and transmit clock length of the registers associated with the interface between the first module and the second module. Combined with the clock deviation distance between the two modules, the input / output interface clock length and deviation clock length are determined, and then the input / output delay information of the second module is calculated and optimized. By combining the timing characteristics of registers within the module with the clock deviation between modules to determine the timing constraints corresponding to the interfaces between modules, the limitations of traditional unified timing constraints are avoided. This effectively solves the timing convergence problem caused by inconsistent interface clock lengths in SOC design, ensuring that the timing path meets setup and hold time requirements. Furthermore, the method of this application does not rely on large-scale top-level iterations and can be directly applied in the APR process. Each module can perform pre-checks and timing optimizations, improving interface timing convergence efficiency. It is also adaptable to different clock domains and APR stages, exhibiting strong versatility and efficiently supporting the physical implementation of large-scale digital chips.

[0119] This application also provides a computer device 140, such as... Figure 14 The diagram shown is a schematic representation of the structure of a computer device 140 provided in an embodiment of this application. It includes a processor 1401, a memory 1402, and optionally, a bus 1403. The memory 1402 stores machine-readable instructions executable by the processor 1401 (e.g., ...). Figure 13 (The execution instructions corresponding to each module in the device), when the computer device 140 is running, the processor 1401 and the memory 1402 communicate through the bus 1403. When the machine-readable instructions are executed by the processor 1401, the steps of the timing optimization method in the above method embodiment are executed.

[0120] This application also provides a computer-readable storage medium storing a computer program, which, when run by a processor, executes the steps of the timing optimization method described in the above method embodiments.

[0121] Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the specific working processes of the systems and devices described above can be referred to the corresponding processes in the method embodiments, and will not be repeated here. In the several embodiments provided in this application, it should be understood that the disclosed systems, devices, and methods can be implemented in other ways. The device embodiments described above are merely illustrative. For example, the division of modules is only a logical functional division, and in actual implementation, there may be other division methods. Furthermore, multiple modules or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the displayed or discussed mutual coupling or direct coupling or communication connection can be through some communication interfaces; the indirect coupling or communication connection of devices or modules can be electrical, mechanical, or other forms.

[0122] Furthermore, the functional units in the various embodiments of this application can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. If the functions are implemented as software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this invention, or the part that contributes to the prior art, or a part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of this invention. The aforementioned storage medium includes: USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, optical disks, and other media capable of storing program code.

[0123] The above are merely specific embodiments of this application, but the scope of protection of this application is not limited thereto. Any changes or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application.

Claims

1. A timing optimization method, characterized in that, include: Obtain the register information corresponding to the second module in the first module. The register information includes: the logical path length of the register associated with the interface, the capture clock length, and the transmit clock length. The first module and the second module are functional units inside the chip that perform signal transmission and data interaction. Obtain the clock deviation distance between the first module and the second module, wherein the clock deviation distance is the deviation between the time when the clock signal arrives at the interface register of the first module and the time when the clock signal arrives at the interface register of the second module; The input interface clock length, output interface clock length, and deviation clock length of the first module are determined based on the register information and the clock deviation distance. The input delay information and output delay information of the second module are determined based on the logical path length, the capture clock length, the transmit clock length, the input interface clock length, the output interface clock length, and the offset clock length. The second module is optimized for latency based on the input latency information and the output latency information.

2. The method according to claim 1, characterized in that, The step of obtaining the register information in the first module corresponding to the second module includes: Obtain all associated registers in the interface that interacts with the second module in the first module; The target register is determined based on the timing values ​​of each of the associated registers; Based on the layout and routing results of the first module, the logical path length, capture clock length, and transmit clock length of the target register are obtained; The logical path length, capture clock length, and transmit clock length of the target register are used as the register information.

3. The method according to claim 2, characterized in that, The step of obtaining at least one associated register in the first module that interacts with the interface of the second module includes: Obtain the register group in the first module that corresponds to the second module; Each register in the register group is treated as an associated register.

4. The method according to claim 1, characterized in that, The step of determining the input interface clock length, output interface clock length, and offset clock length of the first module based on the register information and the clock offset distance includes: The input interface clock length and the output interface clock length are determined based on the capture clock length, the transmit clock length, and the pre-acquired average clock length.

5. The method according to claim 4, characterized in that, The step of determining the input interface clock length and the output interface clock length based on the capture clock length, the transmit clock length, and the pre-acquired average clock length includes: The difference between the capture clock length and the average clock length is used as the input interface clock length; The difference between the transmit clock length and the average clock length is used as the output interface clock length.

6. The method according to claim 1, characterized in that, The step of determining the input delay information and output delay information of the second module based on the logical path length, input interface clock length, output interface clock length, and offset clock length includes: During the unit layout stage, the input delay information and output delay information of the second module are determined based on the logical path length, input interface clock length, output interface clock length, and offset clock length. During the clock tree synthesis stage, the input delay information and output delay information of the second module are determined based on the logic path length, the offset clock length, the capture clock length, and the transmit clock length.

7. The method according to claim 6, characterized in that, The step of determining the input delay information and output delay information of the second module based on the logical path length, input interface clock length, output interface clock length, and offset clock length includes: The sum of the logical path length, the input interface clock length, and the offset clock length is used as the output delay information of the second module; The sum of the logical path length, the output interface clock length, and the offset clock length is used as the input delay information of the second module.

8. The method according to claim 6, characterized in that, The step of determining the input delay information and output delay information of the second module based on the logical path length, the offset clock length, the acquisition clock length, and the transmission clock length includes: The sum of the logical path length, the capture clock length, and the offset clock length is used as the output delay information of the second module; The sum of the logical path length, the transmit clock length, and the offset clock length is used as the input delay information for the second module.

9. The method according to claim 1, characterized in that, The step of optimizing the latency of the second module based on the input latency information and the output latency information includes: Invoke the first timing constraint command to use the input delay information as the input delay of the input interface of the second module; The second timing constraint command is invoked to use the output delay information as the output delay of the output interface of the second module.

10. A timing optimization device, characterized in that, include: The first acquisition module is used to acquire the register information corresponding to the second module in the first module. The register information includes: the logical path length, the capture clock length, and the transmit clock length of the register associated with the interface. The second acquisition module is used to acquire the clock deviation distance between the first module and the second module; The first determining module is used to determine the input interface clock length, output interface clock length, and deviation clock length of the first module based on the register information and the clock deviation distance. The second determining module is used to determine the input delay information and output delay information of the second module based on the logical path length, the capture clock length, the transmit clock length, the input interface clock length, the output interface clock length, and the deviation clock length. The latency optimization module is used to optimize the latency of the second module based on the input latency information and the output latency information.

11. An electronic device, characterized in that, include: The device includes a processor, a storage medium, and a bus, wherein the storage medium stores machine-readable instructions executable by the processor, and when the electronic device is running, the processor communicates with the storage medium via the bus, and the processor executes the machine-readable instructions to perform the steps of a timing optimization method as described in any one of claims 1 to 9.

12. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a computer program that, when executed by a processor, performs the steps of a timing optimization method as described in any one of claims 1 to 9.

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