Output buffer circuit and memory

Abstract

The invention discloses an output buffer circuit and a memory, the output buffer circuit comprises a buffer and an output control circuit, an output signal is generated through the buffer according to a first control signal and a second control signal, and the output control circuit outputs a voltage to an output end according to at least one of the first control signal and the second control signal, the level switching time of the output signal can be reduced, and the system performance is further improved.

Description

Technical Field

[0001] This application relates to the field of storage technology, specifically to an output buffer circuit and a memory. Background Technology

[0002] The output time of an output buffer circuit refers to the time required from receiving a change in the input signal to generating a corresponding output change. This output time is a very important parameter for the system. When a fixed power supply voltage is used, the output time is relatively short.

[0003] However, when the power supply voltage varies over a wide range, the output time becomes longer, which degrades system performance. Summary of the Invention

[0004] This application provides an output buffer circuit and a memory to alleviate the technical problem of long output time caused by wide variations in power supply voltage.

[0005] In a first aspect, this application provides an output buffer circuit, which includes a buffer and an output control circuit. The buffer is connected to a power supply terminal, a ground terminal, and an output terminal, and is used to generate an output signal according to a first control signal and a second control signal. The output control circuit is connected to the power supply terminal, the ground terminal, and the output terminal, and is used to output a voltage to the output terminal according to at least one of the first control signal and the second control signal.

[0006] Secondly, this application also provides a memory that includes the output buffer circuit described above.

[0007] The output buffer circuit and memory provided in this application generate an output signal based on a first control signal and a second control signal through a buffer. The output control circuit outputs a voltage to the output terminal based on at least one of the first control signal and the second control signal, which can reduce the level switching time of the output signal and thus improve the system performance. Attached Figure Description

[0008] The technical solution and other beneficial effects of this application will become apparent from the following detailed description of specific embodiments in conjunction with the accompanying drawings.

[0009] Figure 1 This is a circuit diagram of a buffer in related technologies.

[0010] Figure 2 This is a schematic block diagram of the output buffer circuit provided in an embodiment of this application.

[0011] Figure 3 This is a block diagram illustrating the principle of accelerating a single path, as provided in an embodiment of this application.

[0012] Figure 4The circuit diagram of the output buffer circuit provided in the embodiment of this application.

[0013] Figure 5 This is a schematic diagram of the memory structure provided in an embodiment of this application. Detailed Implementation

[0014] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the scope of protection of this application.

[0015] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Features thus defined as "first" or "second" may explicitly or implicitly include one or more of the stated features. In the description of this invention, "a plurality of" means two or more unless otherwise explicitly specified.

[0016] In memory (such as Nor Flash), the output time, Tclqv, refers to the duration required from the falling edge of the system clock (active low) until the output data stabilizes at a recognizable logic level. This output time directly constrains the system's read timing; that is, the system must wait longer than Tclqv after the clock transitions low before it can sample the correct data.

[0017] Conventional memory operating voltages fall into two categories: a fixed 1.8V (1.65V ~ 2V) and a fixed 3.3V (2.7V ~ 3.6V). It's worth noting that there's another type of memory with a wider operating voltage range, typically 1.65V ~ 3.6V, while the load driven by the output pads is determined by the circuit board design and remains almost constant in practical applications. In this scenario, the memory's output time depends entirely on the output buffer circuit connected to the output pads.

[0018] Figure 1 This is a circuit schematic of a buffer in related technologies. The buffer includes a second transistor P0 and a fourth transistor N0. The first terminal of the second transistor P0 is connected to the power supply terminal, and the control terminal of the second transistor P0 is connected to the first control signal PUB. The second terminal of the second transistor P0 is connected to the first terminal of the fourth transistor N0 and the output pad DQ. The control terminal of the fourth transistor N0 is connected to the second control signal PD, and the second terminal of the fourth transistor N0 is connected to the ground terminal GND.

[0019] The second transistor P0 is a P-channel field-effect transistor (MOS), and the fourth transistor N0 is an N-channel field-effect transistor. When both the first control signal PUB and the second control signal PD are low, the output signal is high; when both the first control signal PUB and the second control signal PD are high, the output signal is low.

[0020] For a fixed power supply voltage, this type of buffer has a relatively simple circuit structure and fast speed. However, when the power supply voltage is over a wide range (VDDmin to VDDmax, e.g., VDDmin = 1.65V, VDDmax = 3.6V), both the second transistor P0 and the fourth transistor N0 need to be MOSFETs suitable for the highest power supply voltage (VDDmax, e.g., 3.6V) to improve system stability. The threshold voltage of a MOSFET suitable for 3.6V is higher than that of a MOSFET suitable for 1.8V. This results in slower transmission speeds for the second transistor P0 and the fourth transistor N0 at lower power supply voltages (e.g., VDDmin, e.g., 1.65V), significantly increasing output time and drastically reducing system performance.

[0021] In view of this, such as Figure 2 As shown, this embodiment provides an output buffer circuit 100, which includes a buffer 20 and an output control circuit 10. The buffer 20 is connected to a power supply terminal, a ground terminal GND, and an output terminal. The buffer 20 is used to generate an output signal OUT according to a first control signal PUB and a second control signal PD. The output control circuit 10 is connected to a power supply terminal, a ground terminal GND, and an output terminal. The output control circuit 10 is used to output a voltage to the output terminal according to at least one of the first control signal PUB and the second control signal PD.

[0022] It is understood that the output buffer circuit 100 provided in this embodiment generates an output signal OUT based on the first control signal PUB and the second control signal PD through the buffer 20. The output control circuit 10 outputs a voltage to the output terminal based on at least one of the first control signal PUB and the second control signal PD, in order to reduce the level switching time of the output signal OUT. When the level of at least one of the first control signal PUB and the second control signal PD changes, the level of the output signal OUT can switch to the target level more quickly. This reduces the output time of the output signal OUT when the power supply voltage (first voltage VDD) changes widely, thereby improving system performance.

[0023] It should be noted that the voltage at the power supply terminal is either the first voltage VDD or the power supply voltage. DQ is the output pad or output terminal for transmitting the output signal OUT. The output terminal connected to buffer 20 serves as the output terminal of the output buffer circuit 100 to transmit the output signal OUT.

[0024] In some embodiments, such as Figure 3 As shown, the output control circuit 10 includes a charge pump 11 and an output control module 12. The charge pump 11 is connected to the power supply terminal and is used to convert the first voltage VDD of the power supply terminal to a second voltage VPP according to the enable signal EN. The second voltage VPP is greater than or equal to the first voltage VDD. The output control module 12 is connected to the power supply terminal, the ground terminal GND, the charge pump 11, and the buffer 20. The output control module 12 is used to output a voltage to the output terminal according to at least one of the first control signal PUB and the second control signal PD and the second voltage VPP.

[0025] It should be noted that the output control module 12 can utilize the voltage difference between the first voltage VDD and the second voltage VPP to improve the pull-down or pull-up capability of the output signal OUT, thereby reducing the level switching time of the output signal OUT. The enable signal EN is used to control whether the charge pump 11 works. For example, when the enable signal EN is high, the charge pump 11 works, converting the first voltage VDD to the second voltage VPP; when the enable signal EN is low, the charge pump 11 stops working, and the second voltage VPP is equal to the first voltage VDD.

[0026] In some embodiments, such as Figure 4 As shown, the output control module 12 includes a first control submodule 121, which is connected to the charge pump 11, the power supply terminal, and the buffer 20. The first control submodule 121 is used to reduce the switching time of the output signal OUT from low level to high level according to the first control signal PUB and the second voltage VPP.

[0027] It should be noted that the first control submodule 121 can use the voltage difference change between the first voltage VDD and the second voltage VPP to improve the pull-up capability of the output signal OUT, thereby reducing the switching time of the output signal OUT from low level to high level, and thus reducing the level switching time of the output signal OUT.

[0028] In some embodiments, such as Figure 4As shown, the first control submodule 121 includes an inverter INV, a first level converter LS1, and a first transistor N1. The inverter INV is used to generate a first intermediate signal ZJ1 based on the input first control signal PUB. The first level converter LS1 is connected to the inverter INV and the charge pump 11. The first level converter LS1 is used to convert the first intermediate signal ZJ1 into a first drive signal PULS based on the second voltage VPP. The high level of the first drive signal PULS is the second voltage VPP. The first terminal of the first transistor N1 is connected to the power supply terminal, the control terminal of the first transistor N1 is connected to the first drive signal PULS, and the second terminal of the first transistor N1 is connected to the output terminal of the transmission output signal OUT.

[0029] It should be noted that the first transistor N1 is an N-channel transistor, and the second voltage VPP is greater than the sum of the first voltage VDD and the threshold voltage of the first transistor N1. Specifically, the second voltage VPP is greater than the sum of the maximum value of the first voltage VDD and the threshold voltage of the first transistor N1. The first terminal, the second terminal, and the control terminal of the first transistor N1 are the source, the drain, and the gate, respectively.

[0030] When the first control signal PUB is low, the first intermediate signal ZJ1 output by the inverter INV is high. After conversion by the first level converter LS1, the high level of the first intermediate signal ZJ1 is raised to the second voltage VPP. Therefore, the high level of the first drive signal PULS of the first level converter LS1 is the second voltage VPP. As the first voltage VDD decreases, the gate-source voltage difference Vgs of the first transistor N1 increases, and the current flowing through the first transistor N1 increases. This allows the output signal OUT to be pulled from low to high more quickly, thereby reducing the switching time of the output signal OUT from low to high.

[0031] In some embodiments, such as Figure 4 As shown, the buffer 20 includes a second transistor P0. The first terminal of the second transistor P0 is connected to the power supply terminal. The control terminal of the second transistor P0 is connected to the first control signal PUB. The second terminal of the second transistor P0 is connected to the output terminal of the transmission output signal OUT. The channel type of the second transistor P0 is different from the channel type of the first transistor N1.

[0032] It should be noted that the second transistor P0 is a P-channel transistor, with its first, second, and control terminals being the source, drain, and gate, respectively. When the first control signal PUB is low, as the first voltage VDD decreases, the absolute value of the gate-source voltage difference of the second transistor P0 decreases, and the current flowing through the second transistor P0 decreases. At the same time, the current flowing through the first transistor N1 increases. This results in the sum of the current flowing through the first transistor N1 and the current flowing through the second transistor P0 being higher than that of the second transistor P0. Therefore, the output signal OUT can be pulled high from low to the first voltage VDD more quickly, thereby reducing the switching time of the output signal OUT from low to high.

[0033] In some embodiments, the second transistor P0 is turned on or off synchronously with the first transistor N1.

[0034] It should be noted that the second transistor P0 and the first transistor N1 are turned on synchronously, which can pull the output signal OUT from low level to the first voltage VDD more quickly, thereby reducing the switching time of the output signal OUT from low level to high level. The second transistor P0 and the first transistor N1 are turned off synchronously, which can avoid affecting the smooth switching of the output signal OUT from high level to low level.

[0035] In some embodiments, such as Figure 4 As shown, the output control module 12 also includes a second control submodule 122. The second control submodule 122 is connected to the charge pump 11, the ground terminal GND and the buffer 20. The second control submodule 122 is used to reduce the switching time of the output signal OUT from high level to low level according to the second control signal PD and the second voltage VPP.

[0036] It should be noted that the second control submodule 122 can use the voltage difference change between the first voltage VDD and the second voltage VPP to improve the pull-down capability of the output signal OUT, thereby reducing the switching time of the output signal OUT from high level to low level, and thus reducing the level switching time of the output signal OUT.

[0037] In some embodiments, such as Figure 4As shown, the second control submodule 122 includes a second level converter LS2 and a third transistor N2. The second level converter LS2 is connected to the charge pump 11. The second level converter LS2 is used to convert the second control signal PD into a second drive signal PDLS based on the second voltage VPP. The high level of the second drive signal PDLS is the second voltage VPP. The first terminal of the third transistor N2 is connected to the output terminal of the transmission output signal OUT. The control terminal of the third transistor N2 is connected to the second drive signal PDLS. The second terminal of the third transistor N2 is connected to the ground terminal GND. The third transistor N2 is an N-channel transistor.

[0038] It should be noted that the first, second, and control terminals of the third transistor N2 are, respectively, the drain, source, and control terminal. When the second control signal PD is high, after conversion by the second level converter LS2, the high level of the second drive signal PDLS is equal to the second voltage VPP. The gate-source voltage difference of the third transistor N2, Vgs, is equal to the second voltage VPP, and the current flowing through the third transistor N2 remains at its maximum value. This allows the output signal OUT to be pulled down from high to ground more quickly, thereby reducing the switching time of the output signal OUT from high to low.

[0039] In some embodiments, such as Figure 4 As shown, the buffer 20 also includes a fourth transistor N0. The first terminal of the fourth transistor N0 is connected to the output terminal of the transmission output signal OUT. The control terminal of the fourth transistor N0 is connected to the second control signal PD. The second terminal of the fourth transistor N0 is connected to the ground terminal GND. The channel type of the fourth transistor N0 is the same as that of the third transistor N2.

[0040] It should be noted that the fourth transistor N0 is an N-channel transistor, with its first, second, and control terminals being the drain, source, and gate, respectively. When the second control signal PD is a high-level first voltage VDD, the fourth transistor N0 is turned on. The current flowing through the fourth transistor N0 increases with the increase of the first voltage VDD. At the same time, the current flowing through the third transistor N2 remains at its maximum value. This results in the sum of the currents flowing through the third transistor N2 and the fourth transistor N0 being greater than the sum of the currents flowing through the fourth transistor N0. Therefore, the output signal OUT can be pulled down from a high level to ground voltage more quickly, thereby reducing the switching time of the output signal OUT from high to low level.

[0041] In some embodiments, the fourth transistor N0 and the third transistor N2 are turned on or off synchronously. It should be noted that when the fourth transistor N0 and the third transistor N2 are turned on synchronously, the output signal OUT can be pulled down from a high level to ground voltage more quickly, thereby reducing the switching time of the output signal OUT from high to low level. When the fourth transistor N0 and the third transistor N2 are turned off synchronously, it avoids affecting the smooth switching of the output signal OUT from low to high level.

[0042] In some embodiments, the output control circuit 10 includes a first transistor N1 and a third transistor N2. The first terminal of the first transistor N1 is connected to a power supply terminal, the control terminal of the first transistor N1 is connected to a first drive signal PULS, and the second terminal of the first transistor N1 is connected to the output terminal of the transmission output signal OUT. The first transistor N1 is an N-channel transistor. The first terminal of the third transistor N2 is connected to the output terminal of the transmission output signal OUT, the control terminal of the third transistor N2 is connected to a second drive signal PDLS, and the second terminal of the third transistor N2 is connected to a ground terminal GND. The third transistor N2 is also an N-channel transistor.

[0043] Buffer 20 includes a second transistor P0 and a fourth transistor N0. The first terminal of the second transistor P0 is connected to the power supply terminal, the control terminal of the second transistor P0 is connected to the first control signal PUB, and the second terminal of the second transistor P0 is connected to the output terminal of the transmission output signal OUT. The second transistor P0 is a P-channel transistor. The first terminal of the fourth transistor N0 is connected to the output terminal of the transmission output signal OUT, the control terminal of the fourth transistor N0 is connected to the second control signal PD, and the second terminal of the fourth transistor N0 is connected to the ground terminal GND. The fourth transistor N0 is an N-channel transistor.

[0044] In some embodiments, buffer 20 is used to maintain the voltage of the output signal OUT.

[0045] In some embodiments, when the buffer 20 holds the voltage of the output signal OUT, the output control circuit 10 is turned off. This saves power consumption of the output control circuit 10, thereby reducing the total power consumption.

[0046] In summary, the second transistor P0 and the fourth transistor N0 are both low-voltage MOSFETs with a breakdown voltage of VDDmax; the first transistor N1 and the third transistor N2 are high-voltage MOSFETs of the same type with a higher breakdown voltage, exceeding VDDmax. The high potential of the first control signal PUB and the high potential of the second control signal PD are both the first voltage VDD, and the high potential of both control signals increases with the increase of the first voltage VDD.

[0047] When the memory 200 is in standby mode, the charge pump 11 is not working, and the second voltage VPP is equal to the first voltage VDD. The voltage of the first control signal PUB is the first voltage VDD, i.e., a high potential, and the voltage of the second control signal PD is a low potential, such as 0V. Therefore, the voltages of the first drive signal PULS and the second control signal PD are both low potentials, such as 0V. The first transistor N1, the third transistor N2, the second transistor P0, and the fourth transistor N0 are all in the off or cutoff state, and the output pad (DQ) is in an undriven state.

[0048] After the memory 200 enters the active mode, the output buffer circuit 100 does not output immediately. The enable signal EN becomes high, and the charge pump 11 starts working in advance, charging the second voltage VPP to the target potential (e.g., 5V). When there is no output, the first control signal PUB is high, the second control signal PD is low, the second transistor P0 is off, and the fourth transistor N0 is off; the first drive signal PULS is low, the second control signal PD is low, and both the first transistor N1 and the third transistor N2 are off, so the output pads are in an undriven state.

[0049] When the memory 200 enters the output mode, if both the first control signal PUB and the second control signal PD become low, the second transistor P0 turns on and the fourth transistor N0 turns off. After passing through the first level converter LS1, the voltage of the first drive signal PULS becomes a second voltage VPP that is greater than VDDmax + Vth (the threshold voltage of the first transistor N1). The first transistor N1 turns on and the third transistor N2 turns off. When the first voltage VDD approaches VDDmin, the second voltage VPP exceeds VDDmax + Vth, so the first transistor N1 can be fully turned on. The conduction current of the first transistor N1 is the largest. Although the second transistor P0 is also in the conducting state, the conduction current of the second transistor P0 is relatively small because the first voltage VDD is relatively small. At this time, the conduction current of the first transistor N1 is larger and dominates. In this way, the simultaneous conduction of the first transistor N1 and the second transistor P0 can achieve the purpose of shortening the output time. As the first voltage VDD increases, the on-current of the first transistor N1 decreases, while the on-current of the second transistor P0 increases. When the first voltage VDD approaches VDDmax, the on-current of the second transistor P0 continues to increase, while the on-current of the first transistor N1 continues to decrease. The current of the second transistor P0 becomes even larger and dominates. The output signal OUT then goes high.

[0050] When the memory 200 enters the output mode, if both the first control signal PUB and the second control signal PD become high, the second transistor P0 is turned off and the fourth transistor N0 is turned on. After passing through the first level converter LS1, the voltage of the first drive signal PULS becomes low, and the potential of the second drive signal PDLS becomes a second voltage VPP greater than VDDmax + Vth (the threshold voltage of the first transistor N1). The first transistor N1 is turned off, and the third transistor N2 is turned on. When the first voltage VDD is close to VDDmin, the gate voltage of the third transistor N2 is the second voltage VPP, and the conduction current is large. Although the fourth transistor N0 is also in the conducting state, the conduction current is small because the first voltage VDD is relatively small. At this time, the simultaneous conduction of the third transistor N2 and the fourth transistor N0 can shorten the output time. When the first voltage VDD increases, the conduction current of the third transistor N2 remains unchanged, while the conduction current of the fourth transistor N0 increases, and the output time will be shorter. When the first voltage VDD is close to VDDmax, the conduction current of the fourth transistor N0 continues to increase, while the conduction current of the third transistor N2 remains unchanged, and the output time continues to shorten. The output signal OUT goes low.

[0051] In some embodiments, such as Figure 5 As shown, this embodiment also provides a memory 200, which includes the output buffer circuit 100 described above.

[0052] It is understood that, since the memory 200 provided in this embodiment includes the aforementioned output buffer circuit 100, it can also generate an output signal OUT based on the first control signal PUB and the second control signal PD through the buffer 20. The output control circuit 10 outputs a voltage to the output terminal based on at least one of the first control signal PUB and the second control signal PD, in order to reduce the level switching time of the output signal OUT. When the level of at least one of the first control signal PUB and the second control signal PD changes, the level of the output signal OUT can switch to the target level more quickly, thereby reducing the output time of the output signal OUT when the power supply voltage changes widely, and thus improving the system performance.

[0053] It should be noted that the memory 200 can be, but is not limited to, Nor Flash, or other memory chips that are suitable for this solution.

[0054] In the above embodiments, the descriptions of each embodiment have different focuses. For parts not described in detail in a certain embodiment, please refer to the relevant descriptions in other embodiments.

[0055] The output buffer circuit 100 and memory 200 provided in the embodiments of this application have been described in detail above. Specific examples have been used to illustrate the principles and implementation methods of this application. The description of the above embodiments is only for the purpose of helping to understand the technical solutions and core ideas of this application. Those skilled in the art should understand that they can still modify the technical solutions described in the foregoing embodiments or make equivalent substitutions for some of the technical features. These modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this application.

Claims

1. An output buffer circuit, characterized in that, The output buffer circuit includes: The buffer is connected to the power supply terminal, the ground terminal, and the output terminal, and is used to generate an output signal based on the first control signal and the second control signal. An output control circuit, connected to the power supply terminal, the ground terminal, and the output terminal, is used to output a voltage to the output terminal according to at least one of the first control signal and the second control signal.

2. The output buffer circuit according to claim 1, characterized in that, The output control circuit includes: A charge pump, connected to the power supply terminal, is used to convert a first voltage of the power supply terminal into a second voltage according to an enable signal, wherein the second voltage is greater than or equal to the first voltage. An output control module, connected to the power supply terminal, the ground terminal, the charge pump, and the buffer, is used to output a voltage to the output terminal according to at least one of the first control signal and the second control signal and the second voltage.

3. The output buffer circuit according to claim 2, characterized in that, The output control module includes a first control submodule connected to the charge pump, the power supply terminal, and the buffer, for reducing the switching time of the output signal from low level to high level according to the first control signal and the second voltage.

4. The output buffer circuit according to claim 3, characterized in that, The first control submodule includes: An inverter is used to generate a first intermediate signal based on the first control signal received. A first level converter, connected to the inverter and the charge pump, is used to convert the first intermediate signal into a first drive signal based on the second voltage, wherein the high level of the first drive signal is the second voltage; The first transistor has its first terminal connected to the power supply terminal, its control terminal connected to the first drive signal, and its second terminal connected to the output terminal that transmits the output signal.

5. The output buffer circuit according to claim 4, characterized in that, The first transistor is an N-channel transistor, and the second voltage is greater than the sum of the first voltage and the threshold voltage of the first transistor.

6. The output buffer circuit according to claim 5, characterized in that, The buffer includes a second transistor, the first terminal of which is connected to the power supply terminal, the control terminal of which is connected to the first control signal, and the second terminal of which is connected to the output terminal that transmits the output signal. The channel type of the second transistor is different from that of the first transistor.

7. The output buffer circuit according to claim 6, characterized in that, The second transistor is turned on or off synchronously with the first transistor.

8. The output buffer circuit according to any one of claims 2-7, characterized in that, The output control module further includes a second control submodule connected to the charge pump, the ground terminal, and the buffer, for reducing the switching time of the output signal from high level to low level according to the second control signal and the second voltage.

9. The output buffer circuit according to claim 8, characterized in that, The second control submodule includes: A second level converter, connected to the charge pump, is used to convert the second control signal into a second drive signal based on the second voltage, wherein the high level of the second drive signal is the second voltage; The third transistor has its first terminal connected to the output terminal that transmits the output signal, its control terminal connected to the second drive signal, and its second terminal connected to the ground terminal. The third transistor is an N-channel transistor.

10. The output buffer circuit according to claim 9, characterized in that, The buffer further includes a fourth transistor, the first terminal of which is connected to the output terminal that transmits the output signal, the control terminal of which is connected to the second control signal, the second terminal of which is connected to the ground terminal, and the channel type of the fourth transistor is the same as that of the third transistor.

11. The output buffer circuit according to claim 10, characterized in that, The fourth transistor is turned on or off synchronously with the third transistor.

12. The output buffer circuit according to claim 10, characterized in that, The first transistor and the third transistor both have a first breakdown voltage, and the second transistor and the fourth transistor both have a second breakdown voltage. The first breakdown voltage is higher than the second breakdown voltage.

13. The output buffer circuit according to any one of claims 1-7, characterized in that, The output control circuit includes: The first transistor has its first terminal connected to the power supply terminal, its control terminal connected to the first drive signal, and its second terminal connected to the output terminal that transmits the output signal. The first transistor is a P-channel transistor. The third transistor has its first terminal connected to the output terminal that transmits the output signal, its control terminal connected to the second drive signal, and its second terminal connected to the ground terminal. The third transistor is an N-channel transistor. The buffer includes: The second transistor has its first terminal connected to the power supply terminal, its control terminal connected to the first control signal, and its second terminal connected to the output terminal that transmits the output signal. The second transistor is an N-channel transistor. The fourth transistor has its first terminal connected to the output terminal that transmits the output signal, its control terminal connected to the second control signal, and its second terminal connected to the ground terminal. The fourth transistor is an N-channel transistor.

14. The output buffer circuit according to any one of claims 1-7, characterized in that, The buffer is used to maintain the voltage of the output signal.

15. The output buffer circuit according to claim 14, characterized in that, The output control circuit is turned off while the buffer maintains the voltage of the output signal.

16. A memory, characterized in that, The memory includes the output buffer circuit as described in any one of claims 1-15.

Images