Memory system, memory device and operating method thereof

Abstract

Memory systems, devices, and methods of operating the same are disclosed. In one aspect, a system includes a first memory device. The first memory device comprises a first memory element, a first input port and a first internal scan chain coupled between the first memory element and the first input port. The system comprises a second memory device. The second memory device includes a second memory element, a second input port, and a second internal scan chain coupled between the second memory element and the second input port. The system includes a control circuit configured to propagate a first test vector via the first internal scan chain and a second test vector via the second internal scan chain. The individual device-specific scan chain of the memory system enables more accurate and finer-grained evaluation of functionality and performance of each memory device within the memory system.

Description

Technical Field

[0001] This disclosure relates to a memory system, a memory device, and a method of operating the memory device. Background Technology

[0002] The semiconductor industry has experienced rapid development due to the continuous increase in the integration density of various electronic components, such as transistors, diodes, resistors, capacitors, etc. In most cases, this increase in integration density is due to the iterative reduction in the minimum feature size, which allows more components to be integrated into a given area. Summary of the Invention

[0003] This disclosure includes a memory system comprising: a first memory device including: a first memory element, a first input port, and a first internal scan chain coupled between the first memory element and the first input port; a second memory device including: a second memory element, a second input port, and a second internal scan chain coupled between the second memory element and the second input port; and control circuitry for propagating a first test vector via the first internal scan chain and a second test vector via the second internal scan chain.

[0004] This disclosure includes a memory device comprising: a memory element, an input port and an output port; an internal scan chain coupled between the input port and the memory element; and an interface scan chain coupled to the input port and the output port.

[0005] This disclosure includes a method for operating a memory device, comprising the following steps: a control circuit configuring a first memory device and a second memory device of a memory system for testing operations; the control circuit propagating a first vector of the test operation via a first scan chain coupled to the first memory device; the control circuit propagating a second vector of the test operation via a second scan chain coupled to the second memory device; and the control circuit generating a first characteristic of the first memory device and a second characteristic of the second memory device based on multiple outputs from the first scan chain and the second scan chain. Attached Figure Description

[0006] The various features disclosed herein can be best understood by reading the following detailed description in conjunction with the accompanying drawings. It should be noted that, in accordance with industry standard practice, the features are not drawn to scale. In fact, the dimensions of the features may be arbitrarily increased or decreased for clarity of explanation.

[0007] Figure 1 A diagram illustrating an example memory testing system for implementing memory device-specific tests according to some embodiments;

[0008] Figure 2A diagram illustrating an instance memory device implementing an internal scan chain according to some embodiments;

[0009] Figure 3 A diagram of an example memory device illustrates an implementation of an interface scan chain that is separate from the internal scan chain of the memory device, according to some embodiments;

[0010] Figure 4 A diagram of an example memory device illustrating an interface scan chain that is coupled to an internal scan chain of a memory device according to some embodiments;

[0011] Figure 5 A flowchart illustrates an example method for implementing an example memory test circuit of a specific scan chain of a memory device according to some embodiments.

[0012] [Symbol Explanation]

[0013] 100: Memory Testing System

[0014] 102: Control Circuit

[0015] 104, 104A~104N: Test vectors

[0016] 106, 106A~106N, 201, 300, 400: Memory devices

[0017] 108, 108A~108N: Test Output

[0018] 200: Figure

[0019] 202, 303, D, DM[0]~DM[n-1], SI, SE: Input ports

[0020] 204: Memory Core

[0021] 206: Clock control circuit

[0022] 207, 207A, 207B, 405: Internal scan chain

[0023] 208: Output Switching Circuit

[0024] 209A, 209B: Data Path

[0025] 210: Output Multiplexer

[0026] 212, 305, Q, Q[0]~Q[n-1]: Output ports

[0027] 302, 302A~302N, 402, 402A~402N: Input interface logic

[0028] 304, 404: Memory circuit

[0029] 306, 306A~306N, 406, 406A~406N: Output Interface Logic

[0030] 312, 412: Input vectors

[0031] 314, 414: Output data

[0032] 316, 416: Input temporary registers

[0033] 318, 418: Output registers

[0034] 402: Input Interface Logic

[0035] 406: Output Interface Logic

[0036] 500: Methods

[0037] 502, 504, 506, 508: Operation

[0038] BIST: Test Enable Signal

[0039] BWEB[0]~BWEB[n-1], BWEBM[0]~BWEBM[n-1], D[0]~D[n-1]: Ports

[0040] CLK: Clock signal

[0041] DFTBYP: Test bypass signal

[0042] SE: Scanning enable signal

[0043] SIC: Scan Input Control

[0044] SID[0], SID[1]: SID signal

[0045] SOC: Output signal

[0046] SOD[0], SOD[1]: Scan output port Detailed Implementation

[0047] The following disclosure provides numerous different embodiments or instances for implementing various features of the provided subject matter. Specific examples of components and configurations described below are for the purpose of simplifying this disclosure. Of course, these are merely examples and are not intended to be limiting. For instance, in the following description, forming a first feature above or on a second feature may include embodiments where the first and second features are formed in direct contact, and may also include embodiments where an additional feature is formed between the first and second features so that the first and second features are not in direct contact. Furthermore, reference numerals and / or letters may be repeated in various instances in this disclosure. This repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0048] Additionally, for ease of description, spatial relative terms such as “below,” “under,” “lower,” “above,” “upper,” “top,” “bottom,” and similar terms are used herein to describe the relationship between one element or feature and another illustrated in the figures. Besides the orientations depicted in the figures, spatial relative terms are also intended to cover different orientations of the device in use or operation. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptors used herein shall be interpreted accordingly.

[0049] Memory circuitry includes static random-access memory (SRAM) circuitry, typically comprising an array of memory cells selectively controlled for read and write operations. Scan chains can be used to verify memory circuitry. Scan chains are implemented in the Design for Testability (DFT) methodology for testing integrated circuits. Scan chain circuitry may include interconnected flip-flops that allow sequential testing of logic circuitry (such as memory circuitry) within a semiconductor device. Conventionally, scan chains have been used to test memory devices by configuring them into groups. Each group of memory devices is then configured into a single scan chain, and a single test pattern is applied via a shared scan chain to test all memory devices in that group.

[0050] Such methods for testing memory devices can be used to test various characteristics of the group, including the minimum voltage (Vmin) of the memory devices. However, this grouping strategy has several limitations. For example, when using a single test vector to test all memory devices in a group, only the Vmin of the lowest-performing memory device will be identified, not the specific memory device with the lowest-performing Vmin characteristic. Therefore, this method often fails to accurately reflect the performance of all SRAMs in a design. Furthermore, conventional DFT tests implemented using Direct Memory Access (DMA) controllers typically only evaluate a subset of the overall functionality of the associated hardware components. Limited testing of logic components implemented by simultaneously testing arrays of memory devices fails to individually verify the full functionality and timing of each memory device.

[0051] To overcome these drawbacks, the techniques described herein provide a dedicated scan chain for each individual memory device in a semiconductor design. Each memory device can be equipped with both an internal scan chain and an interface scan chain, enabling targeted and precise characterization of its Vmin requirements, as well as its overall accuracy and timing. This personalized testing eliminates reliance on group-based evaluation and provides a more accurate representation of the performance characteristics of each memory device.

[0052] Internal scan chains provide test coverage of the inherent characteristics of memory devices and can be used to evaluate the performance of triggers coupled to the memory device. Internal scan chains can also be used to evaluate whether the memory device responds to input test vectors and produces the expected output signal. Interface scan chains can be used to evaluate the characteristics associated with the input / output interfaces coupled to the memory device under test. These characteristics include, but are not limited to, the setup and hold time parameters of the memory device's interface logic.

[0053] Implementing device-specific scan chains enables targeted test operations focused on evaluating the specific characteristics of each individual memory device. In contrast to conventional methods that evaluate characteristics common to a group of memory devices, the targeted test circuitry described herein implements device-specific scan chains, enabling a more precise and granular evaluation of the functionality and performance of each memory device within the memory system. Because the scan chain is implemented for each memory device, in some embodiments, the test control circuitry can perform test operations on multiple memory devices in parallel using device-specific test vectors.

[0054] Figure 1A diagram illustrates an example memory test system 100 for implementing specific tests of memory devices according to some embodiments. The memory test system 100 can be included in any type of integrated circuit (IC), semiconductor device, or memory system. In at least one embodiment, memory devices 106A to 106N can be included in an IC. In another embodiment, one or more of memory devices 106A to 106N can be included in a separate IC or memory system.

[0055] Each of the components shown in the memory test system 100 may receive power from one or more voltage sources. The memory test system 100 may include one or more logic gates and sub-circuits, each of which may be composed of one or more logic gates. A logic gate is an electronic device that performs logical operations on one or more input signals to produce a single output signal. Various embodiments of the circuitry and logic gates implementing the memory test system 100 may include various transistors. The transistors described herein may have a specific type (n-type or p-type), but the embodiments are not limited thereto. The transistor can be any suitable type of transistor, including but not limited to metal oxide semiconductor field effect transistors (MOSFETs), complementary metal oxide semiconductor (CMOS) transistors, P-channel metal-oxide semiconductor (PMOS), N-channel metal-oxide semiconductor (NMOS), bipolar junction transistors (BJTs), high-voltage transistors, high-frequency transistors, P-channel and / or N-channel field effect transistors (PFETs / N-channel field effect transistors, NFETs), FinFETs, planar MOS transistors with raised source / drain electrodes, nanosheet FETs, nanowire FETs, or the like.

[0056] It should be understood that, although Figure 1The memory testing system 100 shown may be part of a larger memory circuit, comprising any number or configuration of memory devices 106A to 106N, which can be accessed using corresponding internal scan chains and / or interface scan chains, as further described herein. Similarly, although not shown here for visual clarity, various additional circuitry may be included to address (e.g., select one or more of the memory devices 106A to 106N) for various memory operations, such as write operations, read operations, or test operations.

[0057] The memory testing system 100 is shown as including one or more control circuits 102, which provide a set of test vectors 104A to 104N (sometimes collectively referred to as "test vectors 104") for performing various test operations. The memory testing system 100 is also shown as including a set of memory devices 106A to 106N (sometimes collectively referred to as "memory devices 106"), which may include various logic circuit systems that receive corresponding test vectors 104 and perform test operations to measure the characteristics of the memory devices 106. Figure 2 , Figure 3 and Figure 4 Further details of the scan variations that can be achieved by the collection of memory devices 106 are described.

[0058] Each memory device 106 may be any type of memory device capable of storing at least one bit of memory data, including but not limited to SRAM cells, sets of SRAM cells (e.g., rows, columns, or libraries of SRAM cells), dynamic random access memory (DRAM) cells, or sets of DRAM cells (e.g., rows, columns, or libraries of DRAM cells). In contrast to the conventional approach where multiple memory devices share a single scan chain for DFT and / or built-in self-test (BIST) operations, the memory devices 106 of the memory test system 100 are each shown receiving a separate test vector 104. Each memory device 106 may include logic gates, transistors, or other circuit elements that control the operation of the memory device to perform read, write, or test operations. In some embodiments, each memory device 106 may include one or more input flip-flops and / or output flip-flops storing signals to be propagated through one or more memory cells of the memory device 106.

[0059] In this example, each memory device 106 is shown receiving a respective test vector 104. Each test vector 104 may contain a set of signal sequences that will be used to control various circuit systems of the corresponding memory device 106 for test operations. In some embodiments, the test vector 104 may be or include a BIST vector. The test vector 104 may be provided as an input stimulus to the memory device 106 under test to elicit specific output responses, which are then compared with expected values. The test vector 104 may be a predetermined vector tailored to various states of the memory device 106 to test its functionality and timing, and may be generated based on memory architecture, operating conditions, and desired test objectives.

[0060] In one example, test vector 104 can be used to evaluate the Vmin requirement of a memory device. In this example, test vector 104 may include progressively decreasing the supply voltage while applying a signal of a predefined data pattern to the memory device under test 106. The output data extracted from the memory device 106 is then analyzed to identify any errors or inconsistencies that indicate performance degradation below the Vmin threshold. To evaluate timing characteristics such as set-and-hold times, test vector 104 may include or provide rapid transitions in the input signals, where precise timing control is applied to measure the memory device 106's ability to reliably capture and hold data during such transients. In some implementations, test vector 104 may be generated to simulate potential faults or anomalies within the memory device 106, such that the response of the memory device 106 determines the fault tolerance or robustness of the memory device under test 106.

[0061] Memory testing system 100 is shown as a set including test outputs 108A to 108N (sometimes collectively referred to as "test outputs 108"). Test outputs 108 may contain any data generated or otherwise produced by the memory device in response to an application corresponding to test vector 104. In some embodiments, test vector 104 may contain data to be written to memory device 106, and test outputs 108 may contain that data read from memory device 106. In some embodiments, the respective sets of test outputs 108 may themselves correspond to a vector corresponding to each entry in the corresponding test vector 104. For example, if test vector 104 contains a sequence of data to be written to memory device 106, then test outputs 108 may contain a corresponding sequence of data read from memory device 106.

[0062] The format of test output 108 may depend on the type of memory device 106 and the test process performed that results in the generation of test output 108 (e.g., the provided test vector 104). In some embodiments, test output 108 may include one or more of the following: a representation containing data stored in the corresponding memory device 106, one or more error flags indicating any detected fault in memory device 106, or status bits reflecting the operating state of memory device 106, and other data that may be generated by memory device 106 (or its logic circuitry).

[0063] A memory testing system 100 is shown comprising one or more control circuits 102. The control circuits 102 may comprise circuitry, software, hardware, or a combination thereof, which may provide one or more test vectors 104 to test one or more memory devices 106. In some embodiments, the control circuits 102 may be built-in self-test (BIST) control circuitry 102 located on the same integrated circuit as each of the one or more memory devices 106. In some embodiments, the control circuits 102 reside on a separate integrated circuit coupled to / communicating with an integrated circuit containing one or more of the memory devices 106. In some embodiments, the control circuits may communicate with multiple integrated circuits, each of which contains one or more memory devices 106.

[0064] Control circuitry 102 acquires and / or generates test vectors 104. In some embodiments, control circuitry 102 may access Waveform Generation Language (WGL) data to generate one or more test vectors 104 for one or more memory devices 106. Control circuitry 102 may access and / or generate one or more test vectors 104 in response to one or more signals / requests for initiating a test process for one or more of the memory devices 106A to 106N. Signals / requests may indicate which memory devices 106 to be tested, the test vectors 104 to be accessed / generated / provided to the specified memory device 106, and the characteristics of the specified memory device 106 to be measured / monitored in the resulting test output 108.

[0065] The control circuit 102 can provide the test vector 104 to the memory device 106 by shifting the signal of the test vector via each of the registers in one or more scan chains of the memory device 106. (As in conjunction with...) Figure 2 , Figure 3 and Figure 4In further detail, each memory device 106 may include an internal scan chain and an interface scan chain. Depending on the type of test operation being performed, the control circuitry 102 may provide test vectors 104 to the internal scan chain, the interface scan chain, or both. Providing test vectors 104 to the scan chains of memory device 106 may involve shifting the test vectors via each of the registers in the scan chains. The control circuitry 102 may provide additional signals to control the clock, supply voltage, and / or other states of the memory device under test 106.

[0066] In some embodiments, before providing the test vector 104 via the scan chain of memory device 106, control circuitry 102 may provide various configuration signals to enable a test mode for the memory device. In one example, this may include providing a scan enable signal to configure one or more triggers of memory device 106 into one or more scan chains. In some embodiments, control circuitry 102 may provide a scan clock signal that synchronizes the input of test vector 104 to the scan chain of memory device 106.

[0067] The control circuit 102 can perform test operations on the memory device 106 individually or in parallel (e.g., by setting corresponding control signals, providing test vectors 104, etc.). In some embodiments, the control circuit 102 can provide different test vectors 104 to each of the memory devices 106 under test. In some embodiments, the control circuit 102 can provide the same test vector 104 to each of the memory devices 106 under test. The control circuit 102 can coordinate the setting and holding time, Vmin, or other characteristics of the memory device 106 during testing.

[0068] Control circuitry 102 can receive / access test outputs 108 generated by the memory device under test 106 to evaluate different characteristics of the device under test. In some embodiments, control circuitry 102 can provide one or more test vectors 104 to test the functionality and timing of various components of the memory device 106. For example, characteristics such as the functionality of the input triggers of the memory device 106 (e.g., whether the components are operating under normal conditions), Vmin, set-up and / or hold-up times can be tested by comparing the test output 108 with an expected output associated with the test vector 104. If the expected output does not match the test output 108 under certain operating conditions, control circuitry 102 can determine under those conditions that the memory device 106 is not operating correctly. For example, the supply voltage at which the memory device 106 no longer operates correctly can be identified as the Vmin threshold of the memory device 106. A similar method can be used to determine the set-up / hold-up time at which the memory device 106 can operate.

[0069] By implementing a device-specific scan chain for each memory device 106, the control circuitry 102 can individually monitor and determine the characteristics of each of the memory devices 106. This provides improved test coverage compared to conventional group-based methods. These methods can be used to efficiently and accurately determine Vmin for each of the memory devices 106 in a memory system, and to determine specific set / hold violations for certain memory devices, triggers / scan chains, or other components of memory device 106. The memory test system 100 also enables logic to isolate and test individual memory devices 106 while deactivating test logic for other memory devices 106 in the system. Figure 2 , Figure 3 and Figure 4 Examples of scan chains that can be implemented according to the techniques described in this paper are described.

[0070] refer to Figure 2 FIG200 illustrates an example memory device 201 implementing internal scan chains 207A and 207B according to some embodiments. The memory device 201 may be similar to... Figure 1 The memory device 106 and includes Figure 1 The memory device 106 may have any structure and functionality. The memory device 201 may include a set of input ports, one of which corresponds to a BIST mode (e.g., preceded by "BIST" or followed by the character "M"). For example, for n memory cells of memory core 204, ports D[0] to D[n-1] correspond to data inputs, while input ports DM[0] to DM[n-1] correspond to data inputs for normal operation and BIST mode (e.g., test mode), respectively.

[0071] Ports BWEB[0] to BWEB[n-1] correspond to the byte writeable bar (BWEB) used for normal operation (e.g., write enable signal), while ports BWEBM[0] to BWEBM[n-1] correspond to the test write enable signal, respectively. The PIN_A and PIN_B group signals of memory device 201 may correspond to the control signals of memory device 201, while the BIST PIN_A and BIST PIN_B groups may correspond to the test control signals of memory device 201. When a test operation is performed, in addition to providing one or more test vectors via scan chains 207A and 207B, the control circuit (e.g., control circuit 102) may also generate input signals for each of the test input ports (e.g., DM, BWEBM, BIST PIN_A group, BIST PIN_B group, etc.), as described in further detail herein.

[0072] Memory device 201 includes clock control circuitry 206, which receives a clock signal CLK for normal operation and a scan-in control (SIC) signal, which may be a set of control signals provided by control circuitry during test mode. Memory device 102 includes a scan input data port, which receives data from one or more test vectors (e.g., test vector 104) and propagates the data via scan chains 207A and 207B of memory device 201. In this example, there are two SID signals, SID[0] and SID[1], which correspond to scan chains 207A and 207B (sometimes collectively referred to as "scan chain 207"), respectively. However, it should be understood that in some embodiments, memory device 201 may include a single scan chain or more than two scan chains 207.

[0073] Memory device 201 is shown to include memory core 204. Memory core 204 may include a set of memory cells, which may include SRAM memory cells, DRAM memory cells, or any other type of memory cells. Each memory cell in memory core 204 may store one bit of metadata, which may be provided during normal device operation via one of output ports Q[0] to Q[n-1]. The memory cells of memory core may receive input data for write operations via signals D[0] to D[n-1]. Write operations may be performed in response to a corresponding write enable signal (e.g., for each of the n memory cells of memory core 204, one of BWEB[0] to BWEB[n-1]). During the test operation, the multiplexer circuit coupled to the input port can provide test signals DM[0] to DM[n-1] and BWEBM[0] to BWEBM[n-1] as inputs to the memory cells of memory core 204 (e.g., based on the test enable signal BIST, as shown in the figure).

[0074] Memory device 201 is shown as including internal scan chains 207A and 207B. Although two internal scan chains 207A and 207B are shown in this example, it should be understood that any number of internal scan chains can be implemented in memory device 201. Scan chain 207B may each contain a sequence of interconnected flip-flops, wherein the output of each flip-flop is provided as an input to the next flip-flop in the sequence. As shown, each of scan chains 207A and 207B receives an input signal from scan input data ports SID[0] and SID[1]. As shown, in this example, each of the flip-flops in scan chain 207 includes input ports D, SI, and SE. In normal operating mode, input port D can be the standard data input of the flip-flop. The scan input (Scan-In, SI) port can be used to input test data into the flip-flop during scan chain testing. The scan enable (Scan Enable, SE) port can be used to control whether the flip-flop operates in normal mode or scan mode. In scan mode, the flip-flop is used to shift a data string via the chain. The SI port receives data that will be shifted from the previous flip-flop in the scan chain into the flip-flop. The flip-flop includes an output port Q, which provides data as output.

[0075] As shown in the figure, when the scan enable signal is valid, scan input data (e.g., test vectors) on the SID[0] and SID[1] ports are propagated via scan chains 207A and 207B, and scan output ports SOD[0] and SOD[1] of output port 212 are propagated along data paths 209A and 209B, respectively. In some embodiments, a lookup latch (as shown here) can be used to verify that the data passed through scan chains 207A and 207B matches the expected output. In such embodiments, the lookup latch can store the expected output, which can be addressed by providing the lookup latch with a corresponding sequence of test vectors (e.g., by shifting via scan chain registers). As shown in the figure, if the input matches the expected value, the lookup latch can provide an output indication via the SOD[0] or SOD[1] port. In some embodiments, a lookup latch may not be used, and the comparison functionality may be implemented by control circuitry (e.g., control circuitry 102).

[0076] In some implementations, clock control circuitry 206 may switch the clock signal provided to the triggers in scan chain 207 based on whether memory device 201 is in scan mode (e.g., test mode) or in normal operating mode. For example, the control circuitry may change the clock signal CLK according to different test operations. Memory device 201 is shown to include output multiplexer 210, which switches between providing the output data of each trigger in scan chain 207 as outputs at output ports Q[0] to Q[n-1] and providing the output of memory core 204 as outputs at output ports Q[0] to Q[n-1]. Output multiplexer 210 may be switched by output switching circuitry 208, which may use logic to switch the multiplexer signal based on scan enable signal SE and / or test bypass signal (DFTBYP). For example, if the scan enable signal SE or DFTBYP is valid, the multiplexer 210 can provide the outputs of the flip-flops of scan chains 207A and 207B to the output ports Q[0] to Q[n-1].

[0077] Memory device 201 is shown as a collection of output ports 212. The output ports may include output data ports Q[0] through Q[n-1]. Output ports 212 may include shift output control (SOC) signal ports. Signals at the SOC ports may be provided via clock control circuitry 206, which is shown as a sequence of two flip-flops that receive and propagate the SIC signal (e.g., corresponding to two sets of memory cells A (e.g., cells 0 through n / 2-1) and B (e.g., cells n / 2 through n-1)). In some embodiments, the output of the flip-flop chain of clock control circuitry 206 may be provided to a corresponding lookup latch that performs a similar pattern matching as described herein and generates an indication of whether the SIC control input has been correctly propagated via the flip-flops of clock control circuitry 206.

[0078] As described herein, control circuitry (e.g., control circuitry 102) can provide a combination of Figure 2 Any input signal described herein may be used to perform various test operations. This may include shifting data via the SID input port; modifying the clock and / or supplying voltage signals to measure timing and / or Vmin respectively; and providing test-specific control signals to configure scan chain 207 to perform the various operations described herein. As the test vector is propagated via memory device 201, the control circuitry may measure / access these output signals when they appear on output port 212 and compare them with expected values.

[0079] If the output signal matches the expected value, the memory device 201 can be considered to have passed the given test. If the output signal does not match the expected value, the memory device 201 can be considered to be faulty and / or has failed the given test. The supply voltage provided when the memory device 201 begins to fail can indicate the Vmin of the memory device. In some embodiments, data provided on output ports Q[0] to Q[n-1] can be propagated to input data ports D[0] to D[n-1], so that data propagated via scan chains 207A and 207B can be written to the memory cells of the memory core 204. In such embodiments, data written to the scan chain can be propagated via the memory core 204 to evaluate the performance (e.g., Vmin, timing, etc.) of the memory cells of the memory core 204.

[0080] refer to Figure 3 This illustrates an example memory device 300 that implements an interface scan chain separate from the internal scan chain of the memory device according to some embodiments. The memory device 300 may be or include... Figure 1 The memory device 106 may be any structural or functional. The memory device 300 is shown as including memory circuitry 304, which includes an internal scan chain. Memory circuitry 304 may be similar to... Figure 2 The memory device 201 and includes such Figure 2 The memory device 201 may have any structure and functionality. For example, the memory circuit 304 may include a memory core (e.g., memory core 204), an internal scan chain (e.g., one or more internal scan chains 207), and a corresponding multiplexer (e.g., output multiplexer 210) or other logic for initializing the internal scan chains.

[0081] Similar to Figure 2 The memory device 201, memory circuitry 304 may contain data or otherwise receive data via one or more input ports 303 and provide data via one or more output ports 305. In this example, the input ports 303 and output ports may be similar to... Figure 2 The input port 202 and output port 212 and include, for example Figure 2 Any structure or functionality of the input port 202 and output port 212. In some embodiments, the input port 303 may include a clock input port (e.g., Figure 2 CLK port), scan input data port (e.g.) Figure 2 The SID[0] and SID[1] ports), and the scan input control port (e.g. Figure 2 (SIC port) or test specific ports, such as scanning enabled ports and / or testing bypass ports (e.g., SE ports, Figure 2 (e.g., DFBTYP port).

[0082] In this example, each of the input ports is shown as coupled to a corresponding input interface logic 302A–302N (sometimes collectively referred to as “input interface logic 302”). Input interface logic 302 may include registers / flip-flops, logic gates, transistors, or other components that propagate signals from the flip-flops of the input register 316 constituting the interface scan chain into appropriate control and data signals compatible with the architecture of memory circuitry 304. Input interface logic 302 may include input buffers, address decoders, or data multiplexers, as well as other components. In some embodiments, input interface logic 302 may include timing-dependent components that facilitate the setting and holding time parameters of the input ports 303 of memory circuitry 304. Such timing components may include delay circuitry, synchronization circuitry, or additional flip-flops or latches that facilitate data input from the input registers 316 of the interface scan chain and the corresponding input ports 303 of memory circuitry 304.

[0083] Memory circuitry 304 may include output data or otherwise provide output data via one or more input ports 303, which may be similar to Figure 2 The memory device 201 has an output port 212. In this example, each of the output ports 305 is shown as coupled to a corresponding output interface logic 306A-306N (sometimes collectively referred to as "output interface logic 306"). The output interface logic 306 may include registers / flip-flops, logic gates, transistors, or other components that propagate signals from the output port 305 to the output register 318 of the interface scan chain into appropriate output signals that are coupled to compatible external components of the memory circuit 304, such as control circuitry (e.g., control circuitry 102) for evaluating test outputs of the memory circuit 304 and / or the interface scan chain (e.g., input registers 316 and / or output registers 318 of the interface scan chain). The output interface logic 306 may include input buffers, address decoders, or data multiplexers, and other components. In some embodiments, the output interface logic 306 may include timing-dependent components that facilitate the implementation of set-up and hold-up time parameters for the output ports 305 of the memory circuit 304.

[0084] The interface scan chain of memory device 300 is shown as including an input register chain 316 connected to an output register chain 318. Wiring through each of the input registers 316 and the output registers 318 indicates the data flow through the interface scan chain. Data shifted via the scan chain may include one or more input vectors 312, which may contain... Figure 1 Any structure and / or functionality of test vector 104. Similar to... Figure 2The operation of the internal scan chain 207 is shown in the figure. The interface scan chain can sequentially receive the input vector 312 and propagate the input vector 312 through each of the input register 316 and the output register 318 of the scan chain.

[0085] In some implementations, data in each input register 316 can be propagated via each corresponding input interface logic 302 to test various operational characteristics of the input interface logic 302, memory circuit 304, input port 303, output port 305, and / or output interface logic 306. Propagating input vectors via input registers 316 and output registers 318 verifies that the input registers 316 and 318 operate under normal operating conditions. Additional tests (e.g., coordinated / configured by control circuitry such as control circuitry 102) can be performed to evaluate the timing characteristics of the input registers 316, output registers 318, input interface logic 302, and / or output interface logic 306.

[0086] Any suitable test / verification process can be used to test the functionality (e.g., whether the device operates correctly under normal conditions, Vmin data, etc.) and / or timing characteristics (e.g., setup and hold times under various timing conditions, etc.) of the memory device 300. The output data 314 produced by the output register 318 of the interface scan chain can be compared with the expected data of the corresponding test vector 312 to verify whether any state of the memory device 300 is operating correctly or incorrectly. Although shown herein as being provided by only a single output register 318, it should be understood that in some embodiments, the output data 314 may be provided by more than one output register 318, for example, after one or more memory operations performed via test vector 312 (e.g., provided in parallel, etc.). In some embodiments, data in the output register 318 may be shifted out of the output register 318 for subsequent comparison with expected data (e.g., via a lookup latch, via control circuitry, etc.).

[0087] In this example, the internal scan chain and interface scan chain of memory circuit 304 are separate. Therefore, in some implementations, the interface scan chain may receive the first test vector 312, and the internal scan chain (e.g., internal scan chain 207) may receive one or more additional test vectors, either alone or in parallel with the testing of the interface scan chain. The separate scan chains provide additional test coverage compared to group-based testing methods. (Similar to combined...) Figure 2 The described method controls / configures the interface scan chain via corresponding configuration signals provided by the control circuitry. The internal scan chain can be controlled / configured on a per-memory device basis, allowing each memory device in the memory system to be evaluated individually, rather than in groups, as in combination. Figure 1 As described.

[0088] Figure 4 A diagram illustrates an example memory device 400 that implements an interface scan chain (e.g., including input register 416 and output register 418) of an internal scan chain 405 coupled to memory circuitry 404 according to some embodiments. The memory device 400 may be or include... Figure 1 The memory device 106 may contain any structure or functionality. The memory device 400 is shown as including memory circuitry 404, which includes at least one internal scan chain 405. The internal scan chain 405 may be similar to scan chain 207 and may contain any structure and / or functionality of scan chain 207. The memory circuitry 404 may be similar to... Figure 2 Memory device 201 or Figure 3 The memory circuit 304 and includes, for example Figure 2 Memory device 201 or Figure 3 The memory circuit 304 may have any structure and functionality. For example, the memory circuit 404 may include a memory core (e.g., memory core 204) and a corresponding multiplexer (e.g., output multiplexer 210) or other logic for initializing the internal scan chain 405.

[0089] Similar to Figure 2 The memory device 201, memory circuitry 404 may include or otherwise access via one or more input ports (e.g., similar to...). Figure 3 The input port 303 (not shown here for visual clarity) receives data and outputs data via one or more output ports (e.g., similar to...). Figure 3 The output port 305 (not shown here for visual clarity) provides data. Similar to... Figure 3 With this configuration, the input ports of memory circuit 404 can be coupled to corresponding input interface logic 402A~402N (sometimes collectively referred to as "input interface logic 402"). Input interface logic 402 may include... Figure 3 The input interface logic 302 can have any structure and functionality. The output port of the memory circuit 404 can be coupled to the corresponding output interface logic 406A~406N (sometimes collectively referred to as "output interface logic 406"). Output interface logic 406 may contain... Figure 3 The output interface logic 306 can be any structure and functionality.

[0090] The interface scan chain of memory device 400 is shown as including an input register chain 416 connected to the output register chain 418. Similar to... Figure 3The configuration, with wiring instructions passing through each of the input registers 416 and output registers 418, indicates the data flow through the interface scan chain. In this configuration, the internal scan chain 405 is shown as receiving the input vector 412 (e.g., test vector 104) and providing outputs to the input registers 416 of the interface scan chain, rather than being separate from the interface scan chain. Depending on the configuration of the input vector 412 and control signals provided by the control circuitry (e.g., control circuitry 102), data shifted via the internal scan chain 405 can also be propagated through each register in the interface scan chain.

[0091] In some implementations, data in each input register 416 can be propagated via each corresponding input interface logic 402 to test various operational characteristics of the input interface logic 402, memory circuitry 404, and / or output interface logic 406. Propagating input vectors via input registers 416 and output registers 418 verifies that the input registers 416 and 418 operate under normal operating conditions. Additional tests (e.g., coordinated / configured by control circuitry such as control circuitry 102) can be performed to evaluate the timing characteristics of the input registers 416, output registers 418, input interface logic 402, and / or output interface logic 406.

[0092] Any suitable test / verification process can be used to test the functionality (e.g., whether the device operates correctly under normal conditions, Vmin data, etc.) and / or timing characteristics (e.g., setup and hold times under various timing conditions, etc.) of the memory device 400. The output data produced by the output register 418 of the interface scan chain can be compared with the expected data of the corresponding test vector 412 to verify whether any state of the memory device 400 is operating correctly or incorrectly. Although shown herein as being provided by only a single output register 418, it should be understood that in some embodiments, the output data may be provided by more than one output register, for example, after one or more memory operations performed via test vector 412 (e.g., provided in parallel, etc.). In some embodiments, data in the output register 418 may be shifted out of the output register 418 for subsequent comparison with expected data (e.g., via a lookup latch, via control circuitry, etc.).

[0093] In this configuration, test vector 412 can be used to include data that evaluates the performance of both the internal scan chain 405 and the interface scan chain together in a single test operation. In doing so, control circuitry (e.g., control circuitry 102) can propagate corresponding control signals to ensure that scan input data (e.g., input vector 412) and output data 414 are correctly provided and captured for verification. This may include sending scan enable signals, bypass signals, and / or other control signals to perform the requested test operation. In some embodiments, testing the operating characteristics of memory device 400 may include modifying the supply voltage, clock frequency, or timing between signals to ensure that the threshold value Vmin and set / hold time constraints are met for the memory device. (As in...) Figure 1 In the configuration shown, the techniques described herein can be used to evaluate each memory device 400 individually rather than in groups, thereby enabling precise verification of the characteristics of individual memory devices.

[0094] Figure 5 A flowchart illustrating an example method 500 for implementing an example memory test circuit of a specific scan chain of a memory device according to some embodiments is provided. Method 500 can be used to operate memory circuits (e.g., memory test system 100, memory devices 201, 300, 400, etc.). It should be noted that method 500 is merely an example and is not intended to limit this disclosure. Therefore, it should be understood that... Figure 5 Additional operations are provided before, during, and after Method 500, and some of these additional operations may be described only briefly in this document.

[0095] In short, method 500 begins with operation 502, which configures the memory system for testing operations, for the first and second memory devices. Method 500 continues with operation 504, which propagates a first vector of the test operation via a first scan chain coupled to the first memory device. Method 500 continues with operation 506, which propagates a second vector of the test operation via a second scan chain coupled to the second memory device. Method 500 continues with operation 508, which generates a first characteristic of the first memory device and a second characteristic of the second memory device based on the outputs from the first and second scan chains.

[0096] Referring to operation 502, a first memory device (e.g., memory device 106A) and a second memory device (e.g., memory device 106B) can be configured for test operations. The first and second memory devices may comprise any suitable type of memory device, which includes a device-specific scan chain comprising an internal scan chain (e.g., internal scan chain 207, internal scan chain 405) and / or an interface scan chain (e.g., ...). Figure 3 and Figure 4(As shown in the diagram). This configuration can be performed via a control circuit (e.g., control circuit 102). Configuring the first and second memory devices may include components (e.g., triggers, multiplexers, etc.) that provide corresponding configuration signals (e.g., scan enable signals) to initialize the memory devices for corresponding test operations. In some embodiments, configuring the first and second memory devices may include accessing / loading corresponding test vectors (e.g., test vectors 104A, 104B) to perform test operations on the memory devices.

[0097] Referring to operation 504, via a first scan chain coupled to a first memory device (e.g., scan chain 207), Figure 3 or Figure 4 The second vector (e.g., test vector 104A) of the test operation is propagated via the first scan chain. Propagating the first test vector via the first scan chain may involve sequentially providing each bit / data signal to a first register of the first scan chain. For each clock cycle, the next bit / data signal in the first register may be propagated to the next register in the first scan chain, while the next bit / data signal is provided to the first register of the first scan chain. This process is repeated until all data in the first test vector has been propagated via each register in the scan chain.

[0098] In some implementations, signals propagated via a register in the scan chain can be provided to one or more components of the first memory device (e.g., the memory core). For example, in step 508, the signals propagated via the memory device can be verified by control circuitry to verify various characteristics of the memory device. In some implementations, in addition to providing test vectors via the scan chain, the control circuitry can also modify one or more control or power signals of the first memory device. For example, the control circuitry can progressively reduce the voltage supplied to the memory device while monitoring its operation (e.g., each shift of the test vector). When the voltage drops below a certain threshold, the output signal from the memory device may become unreliable or significantly deviate from the expected value, which can be detected during step 508 to determine the characteristics of the memory device.

[0099] Referring to operation 506, a second scan chain (e.g., scan chain 207) coupled to a second memory device (e.g., memory device 106B) may be used. Figure 3 or Figure 4The second test vector (e.g., test vector 104B) is propagated via the interface scan chain. Propagating the second test vector via the second scan chain may include performing operations similar to those described in step 504 regarding the sequential provision of each bit / data signal to a second register of the second scan chain. The signals propagated via the registers of the second scan chain may be provided to one or more components of the second memory device (e.g., memory cores). For example, in step 508, the signals propagated via the second memory device may be verified by control circuitry to verify various characteristics of the second memory device.

[0100] As described herein, the first and second scan chains can be device-specific scan chains and are not interconnected. Therefore, the first and second test vectors can be propagated individually or in parallel via the first and second memory devices by one or more control circuits to independently verify the operational characteristics of the first and second memory devices. This achieves improved accuracy and test coverage compared to group-based methods, where a single scan chain / test vector is used to verify the characteristics of a group of memory devices. In some embodiments, the control circuitry can provide a signal to deactivate the scan chain of the first memory device while propagating the second vector via the second scan chain of the second memory device. For example, the control circuitry can deactivate a scan enable signal for the first memory device while propagating the second vector via the second scan chain, such that the first and second memory devices are tested sequentially.

[0101] Referring to operation 508, a first characteristic (e.g., Vmin, set / hold characteristic, device functionality) of the first memory device and a second characteristic (e.g., Vmin, set / hold characteristic, device functionality) of the second memory device are generated based on outputs from the first and second scan chains (e.g., output signals SOC, SOD, output data 314, output data 414, etc.). To determine the minimum voltage requirement (referred to herein as Vmin), the control circuit may progressively decrease the supply voltage to the two memory devices while simultaneously propagating test vectors via their respective scan chains. As the voltage decreases, the output signal from each memory device is monitored for any deviation from the expected value. Vmin is identified as the lowest voltage at which all outputs remain stable and consistent with the expected responses to the first and second test vectors.

[0102] To evaluate set-up / hold-up time characteristics, specific timing patterns are incorporated into the first test vector. These patterns involve altering the arrival time of the data signal relative to the clock edge of the memory device. This may also include modifying the input clock frequency and / or duty cycle while propagating the test vector via the scan chain. In some implementations, control circuitry may adjust the timing of the first and second test vectors while monitoring the output signal from each memory device. By analyzing output errors or inconsistencies under different input signal delays, the set-up and hold-up time parameters can be accurately determined. The set-up time represents the shortest duration for which a valid data signal must exist before the rising edge of the clock, while the hold-up time specifies the shortest duration for which a valid data signal must remain stable after the falling edge of the clock. The first and second test vectors can also be used to verify, using similar techniques, that the memory device components and / or triggers of the scan chain are operating under normal operating conditions.

[0103] As described herein, the first and second scan chains can be device-specific scan chains and are not interconnected. Therefore, one or more control circuits can independently, rather than as a group, verify the operational characteristics of the first and second memory devices. This achieves improved accuracy and test coverage compared to group-based methods, which use a single scan chain / test vector to verify the characteristics of a group of memory devices.

[0104] In one embodiment of this disclosure, a system is disclosed. The system includes a first memory device comprising a first memory element, a first input port, and a first internal scan chain coupled between the first memory element and the first input port. The system also includes a second memory device comprising a second memory element, a second input port, and a second internal scan chain coupled between the second memory element and the second input port. The system includes control circuitry for propagating a first test vector via the first internal scan chain and a second test vector via the second internal scan chain.

[0105] In some embodiments, the control circuitry is further configured to propagate a first test vector and a second test vector in parallel via a first internal scan chain and a second internal scan chain. In some embodiments, the control circuitry is further configured to verify a first characteristic of a first memory device and a second characteristic of a second memory device in response to propagating the first test vector and the second test vector via the first internal scan chain and the second internal scan chain. In some embodiments, the first characteristic and the second characteristic include one or more of a minimum voltage (Vmin), a set time, or a hold time. In some embodiments, the first memory device further includes: a first interface scan chain; and a first interface logic set coupled between a first input port and the first interface scan chain. In some embodiments, the output of the first internal scan chain is coupled to the input of the first interface scan chain. In some embodiments, the control circuitry is further configured to propagate a third test vector via the first interface scan chain. In some embodiments, the control circuitry is further configured to verify a third characteristic of the first memory device. In some embodiments, the third characteristic includes one of the set time or hold time of a first input port or a first output port of the first memory device. In some embodiments, the control circuitry is configured to deactivate the first internal scan chain of the first memory device while propagating the second test vector via the second internal scan chain of the second memory device. In some embodiments, the first memory device further includes an output port, and wherein control circuitry is further configured to propagate a first test vector via a first internal scan chain and receive an output via the output port.

[0106] In another embodiment of this disclosure, a memory device is disclosed. The memory device includes a memory element, an input port, and an output port. The memory device includes an internal scan chain coupled between the input port and the memory element. The memory device includes an interface scan chain coupled to the input port and the output port.

[0107] In some embodiments, the memory device further includes input logic coupled between the interface scan chain and the input port. In some embodiments, the memory device further includes output logic coupled between the interface scan chain and the output port. In some embodiments, the output register of the internal scan chain is coupled to the input register of the interface scan chain. In some embodiments, the internal scan chain receives a first test vector via a configuration self-control circuit, and the interface scan chain is configured to receive a second test vector via the self-control circuit. In some embodiments, the input port of the memory device is configured to select between a first set of multiple input signals and a second set of multiple test signals based on a test enable signal.

[0108] In another embodiment of this disclosure, a method is disclosed. The method includes configuring a first memory device and a second memory device of a memory system for test operations by control circuitry. The method includes propagating a first vector of test operations by the control circuitry via a first scan chain coupled to the first memory device. The method includes propagating a second vector of test operations by the control circuitry via a second scan chain coupled to the second memory device. The method includes generating a first characteristic of the first memory device and a second characteristic of the second memory device by the control circuitry based on outputs from the first and second scan chains.

[0109] In some embodiments, the first scan chain includes a first internal scan chain of a first memory device, and the second scan chain includes a second internal scan chain of a second memory device. In some embodiments, the first and second characteristics include one or more of a minimum voltage (Vmin), a set time, or a hold time.

[0110] As used herein, the terms “about” and “approximately” generally mean plus or minus 10% of a specified value. For example, about 0.5 would include 0.45 and 0.55, about 10 would include 9 to 11, and about 1000 would include 900 to 1100.

[0111] The foregoing summary outlines features of several embodiments, enabling those skilled in the art to better understand the various aspects of this disclosure. Those skilled in the art will understand that they can readily use this disclosure as a basis for designing or improving other processes and structures to achieve the same purposes and / or advantages of the embodiments introduced herein. Those skilled in the art will also recognize that such equivalent constructions do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and modifications can be made herein without departing from the spirit and scope of this disclosure.

Claims

1. A memory system, characterized in that, include: A first memory device, comprising: A first memory element, A first input port, and A first internal scan chain, coupled between the first memory element and the first input port; a second memory device, comprising: A second memory element, A second input port, and A second internal scan chain, coupled between the second memory element and the second input port; and A control circuit for propagating a first test vector via the first internal scan chain and a second test vector via the second internal scan chain.

2. The memory system as described in claim 1, characterized in that, The control circuit is further configured to respond to the propagation of the first test vector and the second test vector via the first internal scan chain and the second internal scan chain to verify a first characteristic of the first memory device and a second characteristic of the second memory device.

3. The memory system as described in claim 2, characterized in that, The first characteristic and the second characteristic include one or more of a minimum voltage, a set time, or a hold time.

4. The memory system as described in claim 1, characterized in that, The first memory device further includes: A first interface scan chain; and A first interface logic set is coupled between the first input port and the first interface scan chain.

5. The memory system as described in claim 4, characterized in that, The control circuit is further used to propagate the third test vector via the first interface scan chain.

6. The memory system as claimed in claim 1, characterized in that, The control circuit is used to activate the first internal scan chain of the first memory device, and at the same time propagate the second test vector through the second internal scan chain of the second memory device.

7. The memory system as claimed in claim 1, characterized in that, The first memory device further includes an output port, and the control circuitry is further configured to propagate the first test vector via the first internal scan chain and receive an output via the output port.

8. A memory device, characterized in that, include: A memory element, an input port, and an output port; An internal scan chain is coupled between the input port and the memory element; and An interface scan chain is coupled to the input port and the output port.

9. The memory device as claimed in claim 8, characterized in that, The input port of the memory device is used to select between a first set of multiple input signals and a second set of multiple test signals based on a test enable signal.

10. A method for operating a memory device, characterized in that, Includes the following steps: A control circuit configures a first memory device and a second memory device of a memory system for a test operation; A first vector of the test operation is propagated by the control circuit via a first scan chain coupled to the first memory device; A second vector of the test operation is propagated by the control circuit via a second scan chain coupled to the second memory device; and The control circuit generates a first characteristic of the first memory device and a second characteristic of the second memory device based on multiple outputs from the first scan chain and the second scan chain.

Images