A charging power supply chip circuit

Abstract

This invention proposes a charging power supply chip circuit, including a power input port, a reference source circuit, a control unit, a digital-to-analog converter circuit, and a charging drive circuit. An external power source is input to the input terminal of the reference source circuit through the power input port. The input terminal of the charging drive circuit is connected to the output terminal of the reference source circuit. The controlled terminal is connected to the output terminal of the control unit through the digital-to-analog converter circuit. The output terminal is used to charge an externally connected battery. The reference source circuit includes a bias circuit and a reference core circuit. The bias circuit is connected to the reference core circuit and provides a bias voltage to some MOSFETs in the reference core circuit, enabling them to operate in the weak inversion region. The reference core circuit generates a reference voltage that is unaffected by changes in ambient temperature and outputs it to the corresponding load module through the output port. This invention reduces overall power consumption and provides temperature compensation and stable power output through the bias circuit and reference core circuit.

Description

Technical Field

[0001] This invention relates to the field of electronic circuit technology, and more specifically, to a charging power supply chip circuit. Background Technology

[0002] With the development of technology, battery charging chips have been widely used. A battery charging chip typically includes a power input circuit, a reference source circuit, a control unit, and a charging drive circuit. External power enters the reference source circuit through the power input circuit, and the reference source circuit provides a stable reference power to the input terminal of the charging drive circuit. The charging drive circuit is regulated under the control of the control unit to supply the battery with the required charging power. To maintain stable charging, a stable reference power is first required for the charging drive circuit. The reference source circuit needs to ensure a stable output of the reference source while also having sufficiently low power consumption.

[0003] Traditional battery charging chips typically use transistors and resistors in their reference source circuitry, making it difficult to reduce power consumption. Furthermore, traditional reference source circuits have a large voltage margin between their output voltage and the supply voltage, requiring a relatively high supply voltage to maintain normal operation. When these traditional reference source circuits are used in charging chips, they result in poor charging stability and hinder power consumption reduction. Summary of the Invention

[0004] The problem solved by this invention is how to provide a charging power chip with stable output and low power consumption.

[0005] To address the aforementioned issues, this invention proposes a charging power chip circuit, comprising a power input port, a reference source circuit, a control unit, a digital-to-analog converter circuit, and a charging drive circuit. An external power source is input to the input terminal of the reference source circuit through the power input port. The input terminal of the charging drive circuit is connected to the output terminal of the reference source circuit. The controlled terminal is connected to the output terminal of the control unit through the digital-to-analog converter circuit, and the output terminal is used to charge an externally connected battery.

[0006] The reference source circuit includes a bias circuit and a reference core circuit.

[0007] The bias circuit is connected to the reference core circuit, providing bias voltage to some of the MOSFETs in the reference core circuit, enabling them to operate in the weak inversion region. The reference core circuit generates a reference voltage that is unaffected by changes in ambient temperature and outputs it to the corresponding load module through the output port.

[0008] The bias circuit includes port VZDA, and the reference core circuit includes ports VZIS and VRE. Port VZDA is connected to port VZIS and is used to transmit the bias voltage Vcxp. Port VRE is the output port and is used to output the reference voltage Vrf.

[0009] The bias circuit includes a startup circuit and a bias voltage generation circuit.

[0010] The startup circuit is connected to the bias voltage generation circuit. Upon system power-up, the startup circuit applies a startup bias voltage to the MOSFET in the bias voltage generation circuit, enabling the circuit to escape its initial zero-current state and enter normal operation. Based on its circuit structure, the bias voltage generation circuit generates and outputs a bias voltage Vcxp to the reference core circuit with low power consumption.

[0011] The core circuit of the reference circuit includes a temperature coefficient compensation circuit and a reference voltage generation circuit.

[0012] The temperature coefficient compensation circuit is connected to the reference voltage generation circuit, providing a compensation voltage with a positive temperature coefficient. Based on this compensation voltage, the reference voltage generation circuit generates a reference voltage Vrf that is unaffected by changes in ambient temperature, and outputs it through port VRE.

[0013] The charging power chip circuit also includes a signal input circuit. The input terminal of the signal input circuit receives external configuration signals through a configuration signal port, and the output terminal is connected to the function setting signal receiving terminal of the control unit.

[0014] The charging power chip circuit also includes an LED driver circuit. The input of the LED driver circuit is connected to the control unit, and the output is used to connect to an external LED indicator. According to the signal from the control unit, the LED indicator is driven to indicate the battery charging status.

[0015] Compared with the prior art, the beneficial effects of the present invention are:

[0016] The charging power supply chip circuit employs a stable, low-power reference source circuit. The main MOSFETs in the reference source circuit operate in the weak inversion region, requiring extremely low power consumption. The bias circuit includes a startup circuit and a bias voltage generation circuit. The bias voltage generation circuit, based on its circuit structure, can eliminate losses caused by rising ambient temperature, significantly reducing system power consumption. The core reference circuit includes a temperature coefficient compensation circuit and a reference voltage generation circuit. The temperature coefficient compensation circuit has a simple structure and exhibits low power consumption while meeting temperature compensation requirements. The reference voltage generated by the reference voltage generation circuit has a small voltage margin between it and the supply voltage, reducing voltage requirements. This results in better stability and lower power consumption when the charging power supply chip using the above-mentioned reference source circuit charges the battery. Attached Figure Description

[0017] Figure 1 This is a schematic diagram illustrating the overall principle of the present invention;

[0018] Figure 2This is a schematic diagram of the reference source circuit of the present invention;

[0019] Figure 3 This is a schematic diagram of the bias circuit of the present invention.

[0020] Figure 4 This is a schematic diagram of the principle structure of the reference core circuit of the present invention;

[0021] Figure 5 This is a schematic diagram of the charging power chip package of the present invention;

[0022] Figure 6 This is a schematic diagram illustrating a typical application of the charging power supply chip of the present invention.

[0023] Explanation of reference numerals in the attached figures:

[0024] 1-Bias circuit; 2-Reference core circuit; 3-Power input port; 4-Control unit; 5-Charging drive circuit; 6-Digital-to-analog conversion circuit; 7-Signal input circuit; 8-LED drive circuit; 11-Start-up circuit; 12-Bias voltage generation circuit; 21-Temperature coefficient compensation circuit; 22-Reference voltage generation circuit. Detailed Implementation

[0025] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0026] like Figure 1 As shown, this invention proposes a charging power chip circuit, including a power input port 3, a reference source circuit, a control unit 4, a digital-to-analog converter circuit 6, a charging drive circuit 5, an LED drive circuit 8, and a signal input circuit 7. An external power supply is input to the input terminal of the reference source circuit through the power input port 3. The input terminal of the charging drive circuit 5 is connected to the output terminal of the reference source circuit. The controlled terminal is connected to the output terminal of the control unit 4 through the digital-to-analog converter circuit 6, and the output terminal is used to charge an external battery. The input terminal of the signal input circuit 7 receives an external configuration signal through a configuration signal port, and the output terminal is connected to the function setting signal receiving terminal of the control unit 4. The input terminal of the LED drive circuit 8 is connected to the control unit 4, and the output terminal is used to connect an external LED indicator. According to the signal from the control unit 4, the LED indicator is driven to indicate the battery charging status.

[0027] During operation, external power enters the reference source circuit through power input port 3, and the reference source circuit provides a stable reference power to the input terminal of the charging drive circuit 5. The external function setting digital signal enters the control unit 4 through the signal input circuit 7, which can set the charging working mode. The control unit 4 sends a drive signal according to the internal mode parameter settings, and after digital-to-analog conversion, it reaches the charging drive circuit 5. The charging drive circuit 5 is adjusted under the control of the control unit 4 to supply the required charging power to the battery. The charging power chip circuit adopts a stable and low-power reference source circuit, which makes the charging power chip of this embodiment more tolerant of input voltage requirements, and provides a more stable power supply to the charging drive circuit 5, resulting in better stability and lower power consumption during battery charging.

[0028] like Figure 2 As shown, the reference source circuit includes a bias circuit 1 and a reference core circuit 2.

[0029] Bias circuit 1 is connected to reference core circuit 2. Bias circuit 1 provides bias voltage to some of the MOSFETs in reference core circuit 2, enabling them to operate in the weak inversion region. The reference core circuit generates a reference voltage that is unaffected by changes in ambient temperature and outputs it to the corresponding load module through the output port.

[0030] The bias circuit 1 includes port VZDA, and the reference core circuit 2 includes ports VZIS and VRE. Port VZDA is connected to port VZIS and is used to transmit the bias voltage Vcxp. Port VRE is an output port used to output the reference voltage Vrf.

[0031] The bias circuit 1 includes a startup circuit 11 and a bias voltage generation circuit 12.

[0032] The startup circuit 11 is connected to the bias voltage generation circuit 12. When the system is powered on, the startup circuit 11 applies a startup bias voltage to the MOSFET in the bias voltage generation circuit 12, causing the bias voltage generation circuit 12 to escape its initial zero-current state and enter normal operation. Based on its circuit structure, the bias voltage generation circuit 12 generates and outputs a bias voltage Vcxp to the reference core circuit 2 with low power consumption.

[0033] The reference core circuit 2 includes a temperature coefficient compensation circuit 21 and a reference voltage generation circuit 22.

[0034] Temperature coefficient compensation circuit 21 is connected to reference voltage generation circuit 22, and provides a compensation voltage with a positive temperature coefficient to reference voltage generation circuit 22. Reference voltage generation circuit 22 generates a reference voltage Vrf that is unaffected by changes in ambient temperature based on the compensation voltage with a positive temperature coefficient, and outputs it through port VRE.

[0035] like Figure 3 As shown, the startup circuit 11 includes a self-shutdown circuit and a startup circuit.

[0036] The self-shutdown circuit is connected to the turn-on circuit. When the system is powered on, the self-shutdown circuit turns on the turn-on circuit. After the system is running stably, the self-shutdown circuit turns off the turn-on circuit to reduce power consumption. After the turn-on circuit is turned on, it provides the starting conditions for the bias voltage generation circuit 12, enabling the bias voltage generation circuit 12 to get out of the zero-current state and gradually enter the stable operating state.

[0037] The self-shutdown circuit includes MOSFETs M1, M2, and M3, and capacitor C1.

[0038] The source of MOSFET M1 is connected to the power supply VDD, and the gate of MOSFET M1 is connected to the drain of MOSFET M1. The drain of MOSFET M1 is connected to the source of MOSFET M2. The source of MOSFET M2 is connected to the gate of MOSFET M1, and the gate of MOSFET M2 is grounded. The drain of MOSFET M2 is connected to the upper end of capacitor C1, and the lower end of capacitor C1 is grounded. The source of MOSFET M3 is connected to the source of MOSFET M1, the gate of MOSFET M3 is connected to the drain of MOSFET M2, and the drain of MOSFET M3 is connected to the drain of MOSFET M4.

[0039] MOSFETs M1, M2, and M3 are P-channel MOSFETs. When the system powers on, the gate voltage of MOSFET M3 is zero, and MOSFET M3 is turned on. The conduction of MOSFET M3 makes the gate voltage of MOSFET M5 equal to the power supply voltage VDD, thus turning on MOSFET M5. MOSFETs M1 and M2 are also turned on when the system powers on, forming a charging path for capacitor C1, causing the voltage across capacitor C1 to increase from zero. When the voltage across capacitor C1 rises to a certain value, MOSFET M3 turns off, MOSFET M4 turns on, and subsequently, MOSFET M5 turns off.

[0040] The power-on circuit includes MOSFETs M4, M5, and M6.

[0041] The drain of MOSFET M4 is connected to the drain of MOSFET M3, the gate of MOSFET M4 is connected to the gate of MOSFET M3, and the source of MOSFET M4 is grounded. The drain of MOSFET M5 is connected to the gate of MOSFET M7, the gate of MOSFET M5 is connected to the drain of MOSFET M3, and the source of MOSFET M5 is connected to the drain of MOSFET M6. The drain of MOSFET M6 is connected to the source of MOSFET M5, the gate of MOSFET M6 is connected to the drain of MOSFET M6, and the source of MOSFET M6 is grounded.

[0042] MOSFETs M4, M5, and M6 are all N-channel MOSFETs. When the system powers on, MOSFET M3 turns on, providing the gate of MOSFET M5 with the power supply voltage VDD, which in turn turns on MOSFETs M5 and M6. Since the gates of MOSFETs M7 and M13 are connected to the drain of MOSFET M5, after MOSFETs M5 and M6 turn on, MOSFETs M7 and M13 receive the gate-source voltages required for conduction. The conduction of MOSFETs M7 and M13 provides operating voltage to the other MOSFETs in the bias voltage generation circuit 12, enabling the bias voltage generation circuit 12 to escape the zero-current state and begin stable operation.

[0043] After the bias voltage generation circuit 12 escapes the zero-current state, capacitor C1 is continuously charging. When the voltage across capacitor C1 rises to a certain value, MOSFET M3 turns off and MOSFET M4 turns on. This causes the gate voltage of MOSFET M5 to drop to zero, and MOSFETs M5 and M6 enter the off state. The startup circuit 11 stops working to reduce system power consumption.

[0044] like Figure 3 As shown, the bias voltage generating circuit 12 includes an output circuit and a negative feedback circuit.

[0045] The output circuit is connected to the negative feedback circuit. All MOSFETs in the output circuit are biased and operate in the weak inversion region, generating a bias voltage Vcxp. This bias voltage Vcxp is output to the reference core circuit 2 through port VZDA. The output circuit also provides a bias voltage to the negative feedback circuit, ensuring its normal operation. The negative feedback circuit maintains a stable bias voltage Vcxp when the ambient temperature changes, thus providing negative feedback.

[0046] The output circuit includes MOSFETs M7, M8, M9, M13, M14, and M15, and port VZDA.

[0047] The source of MOSFET M7 is connected to the power supply VDD, the gate of MOSFET M7 is connected to the gate of MOSFET M13, and the drain of MOSFET M7 is connected to the drain of MOSFET M8. The drain of MOSFET M8 is connected to the drain of MOSFET M7, the gate of MOSFET M8 is connected to the gate of MOSFET M14, and the source of MOSFET M8 is connected to the drain of MOSFET M9. The drain of MOSFET M9 is connected to the source of MOSFET M8, the gate of MOSFET M9 is connected to the gate of MOSFET M15, and the source of MOSFET M9 is grounded.

[0048] The source of MOSFET M13 is connected to the source of MOSFET M7, the gate of MOSFET M13 is connected to the drain of MOSFET M13, and the drain of MOSFET M13 is connected to the drain of MOSFET M14. The drain of MOSFET M14 is connected to port VZDA, the gate of MOSFET M14 is connected to the drain of MOSFET M8, and the source of MOSFET M14 is connected to the drain of MOSFET M15. The drain of MOSFET M15 is connected to the source of MOSFET M14, the gate of MOSFET M15 is connected to the drain of MOSFET M9, and the source of MOSFET M15 is connected to the drain of MOSFET M16.

[0049] All six MOSFETs in the output circuit are biased to operate in the weak inversion region. Based on the circuit structure of the output circuit, the expression for the drain-source current Ids13 flowing through MOSFET M13 is as follows:

[0050] ;

[0051] In the formula, u13 is the carrier mobility of MOSFET M13, Cox is the gate oxide capacitance, Ut is the thermal voltage, W13 is the conductive channel width of MOSFET M13, L13 is the conductive channel length of MOSFET M13, K13 is the capacitor voltage division ratio, VG13 is the gate voltage of MOSFET M13, VS13 is the source voltage of MOSFET M13, and Vth13 is the threshold voltage of MOSFET M13.

[0052] As can be seen from the expression for current Ids13, current Ids13 will increase exponentially with increasing ambient temperature. Current Ids13 is the branch current of the branch containing MOSFET M13, flowing through MOSFETs M14 and M15 respectively. The output circuit uses the voltage at the connection node between the drains of MOSFET M13 and M14 as the bias voltage Vcxp, and outputs it through port VZDA.

[0053] The gate of MOSFET M9 is connected to the drain of MOSFET M9, and is also connected to the gate and drain of MOSFET M10, thereby providing bias voltage for MOSFETs M10, M11 and M12, so that they operate in the saturation region.

[0054] The negative feedback circuit includes MOSFETs M10, M11, M12, M16, M17, and M18.

[0055] The drain of MOSFET M10 is connected to the gate of MOSFET M9, the gate of MOSFET M10 is connected to the drain of MOSFET M10, and the source of MOSFET M10 is connected to the drain of MOSFET M11. The drain of MOSFET M11 is connected to the source of MOSFET M10, the gate of MOSFET M11 is connected to the drain of MOSFET M11, and the source of MOSFET M11 is connected to the drain of MOSFET M12. The drain of MOSFET M12 is connected to the source of MOSFET M11, the gate of MOSFET M12 is connected to the drain of MOSFET M12, and the source of MOSFET M12 is grounded.

[0056] The drain of MOSFET M16 is connected to the source of MOSFET M15, the gate of MOSFET M16 is connected to the source of MOSFET M10, and the source of MOSFET M16 is connected to the drain of MOSFET M17. The drain of MOSFET M17 is connected to the source of MOSFET M16, the gate of MOSFET M17 is connected to the gate of MOSFET M16, and the source of MOSFET M17 is connected to the drain of MOSFET M18. The drain of MOSFET M18 is connected to the source of MOSFET M17, the gate of MOSFET M18 is connected to the gate of MOSFET M17, and the source of MOSFET M18 is grounded.

[0057] MOSFETs M10, M11, and M12 are connected in series as diodes. The voltage Vbz at the junction of the drain of MOSFET M11 and the source of MOSFET M10 is used as the bias voltage for MOSFETs M16, M17, and M18, causing them to operate in the deep weak inversion region. MOSFETs M16, M17, and M18 are interconnected and used as variable resistors in the circuit.

[0058] As the temperature rises, the current Ids13 flowing through the branch containing MOSFET M13 increases, thereby increasing the current loss of the bias voltage generation circuit 12. Since the voltage Vbz decreases with increasing temperature, the resistance of the variable resistor (composed of MOSFETs M16, M17, and M18) biased to operate in the deep weak inversion region increases. Because MOSFET M13 and the variable resistor are in the same branch, the increase in the variable resistor's resistance reduces the current in that branch, thus decreasing the current Ids13. This negative feedback reduces the current loss of the bias voltage generation circuit 12 and maintains the stability of the output bias voltage Vcxp.

[0059] like Figure 4 As shown, the temperature coefficient compensation circuit 21 includes a primary compensation circuit and an enhanced output circuit.

[0060] The primary compensation circuit is connected to the enhancement output circuit. The primary compensation circuit generates a compensation voltage Vfbc with a positive temperature coefficient and outputs it to the enhancement output circuit. The enhancement output circuit enhances the compensation voltage Vfbc in a superimposed manner to meet the temperature compensation voltage requirements. The enhancement output circuit outputs the enhanced compensation voltage Vwz to the reference voltage generation circuit 22.

[0061] The primary compensation circuit includes MOSFET M19 and MOSFET M20.

[0062] The drain of MOSFET M19 is connected to the power supply VDD, the gate of MOSFET M19 is connected to the gate of MOSFET M20, and the source of MOSFET M19 is connected to the drain of MOSFET M20. The drain of MOSFET M20 is connected to the source of MOSFET M19, the gate of MOSFET M20 is connected to the source of MOSFET M20, and the source of MOSFET M20 is grounded.

[0063] Both MOSFETs M19 and M20 are biased and operate in the weak inversion region. The expressions for the drain-source current Ids19 of MOSFET M19 and the drain-source current Ids20 of MOSFET M20 are shown below.

[0064] ;

[0065] ;

[0066] In the above formulas, u19 is the carrier mobility of MOSFET M19, Cox is the gate oxide capacitance, Ut is the thermal voltage, W19 is the conductive channel width of MOSFET M19, L19 is the conductive channel length of MOSFET M19, K19 is the capacitor voltage division ratio, and Vth19 is the threshold voltage of MOSFET M19. u20 is the carrier mobility of MOSFET M20, W20 is the conductive channel width of MOSFET M20, L20 is the conductive channel length of MOSFET M20, K20 is the capacitor voltage division ratio, and Vth20 is the threshold voltage of MOSFET M20. Vfbc is the voltage at the junction of the source and drain of MOSFET M19 and MOSFET M20, i.e., the compensation voltage output by the primary compensation circuit.

[0067] Since MOSFETs M19 and M20 are in the same branch, the drain-source current Ids19 of MOSFET M19 is equal to the drain-source current Ids20 of MOSFET M20, i.e., Ids19 = Ids20. Let K19 = K20 = Ka, then the expression for the compensation voltage Vfbc can be obtained.

[0068] ;

[0069] In the above formula, Ut is the thermal voltage, Ka is the voltage division ratio of the MOSFET capacitor, N19 is the width-to-length ratio of MOSFET M19, u19 is the carrier mobility of MOSFET M19, N20 is the width-to-length ratio of MOSFET M20, u20 is the carrier mobility of MOSFET M20, Vth19 is the threshold voltage of MOSFET M19, and Vth20 is the threshold voltage of MOSFET M20.

[0070] As can be seen from the expression for the compensation voltage Vfbc, the compensation voltage Vfbc is unaffected by fluctuations in the power supply voltage VDD. When the width-to-length ratio N19 of MOSFET M19 is set to be greater than the width-to-length ratio N20 of MOSFET M20, the compensation voltage Vfbc has a positive temperature coefficient.

[0071] The enhanced output circuit includes MOSFETs M21, M22, M23, M24, M25, and M26.

[0072] The drain of MOSFET M21 is connected to the drain of MOSFET M19, and the gate of MOSFET M21 is connected to the source of MOSFET M19. The source of MOSFET M21 is connected to the drain of MOSFET M22. The drain of MOSFET M22 is connected to the source of MOSFET M21, and the gate of MOSFET M22 is connected to the source of MOSFET M22. The source of MOSFET M22 is grounded. The drain of MOSFET M23 is connected to the drain of MOSFET M21, and the gate of MOSFET M23 is connected to the source of MOSFET M21. The source of MOSFET M23 is connected to the drain of MOSFET M24.

[0073] The drain of MOSFET M24 is connected to the source of MOSFET M23, and the gate of MOSFET M24 is connected to the source of MOSFET M24. The source of MOSFET M24 is grounded. The drain of MOSFET M25 is connected to the drain of MOSFET M23, and the gate of MOSFET M25 is connected to the source of MOSFET M23. The source of MOSFET M25 is connected to the drain of MOSFET M26. The drain of MOSFET M26 is connected to the source of MOSFET M25, and the gate of MOSFET M26 is connected to the source of MOSFET M26. The source of MOSFET M26 is grounded.

[0074] MOSFETs M21, M22, M23, M24, M25, and M26 are all biased and operate in the weak inversion region. The gate of MOSFET M21 is connected to the source of MOSFET M19, receiving the compensation voltage Vfbc. MOSFETs M21 and M22 are connected in series, operating in the same manner as the connection structure of MOSFETs M19 and M20, to enhance the compensation voltage Vfbc, which is then passed to the next stage (composed of MOSFETs M23 and M24). MOSFETs M25 and M26 are connected to form the final stage, and the voltage at the connection node between the source of MOSFET M25 and the drain of MOSFET M26 is output as the enhanced compensation voltage Vwz to the reference voltage generation circuit 22. The expression for the enhanced compensation voltage Vwz is shown below.

[0075] ;

[0076] In the formula, Vfbc is the compensation voltage, Ut is the thermal voltage, Ka is the voltage division ratio of the MOSFET capacitor, the width-to-length ratio of MOSFETs M21, M23, and M25 is Ns, and the width-to-length ratio of MOSFETs M22, M24, and M26 is Nr. The carrier mobility of MOSFETs M21, M23, and M25 is us, and the carrier mobility of MOSFETs M22, M24, and M26 is ur. The threshold voltage of MOSFETs M21, M23, and M25 is Vths, and the threshold voltage of MOSFETs M22, M24, and M26 is Vthr.

[0077] As can be seen from the expression for the enhanced compensation voltage Vwz, when Ns is greater than Nr, the enhanced compensation voltage Vwz has a positive temperature coefficient. Furthermore, by adjusting the series in the formula for the enhanced compensation voltage Vwz, its value and the slope of the positive temperature coefficient can be changed.

[0078] like Figure 4 As shown, the reference voltage generation circuit 22 includes MOSFETs M27, M28, M29, and M30, port VZIS, and port VRE.

[0079] The source of MOSFET M27 is connected to power supply VDD, the gate of MOSFET M27 is connected to port VZIS, and the drain of MOSFET M27 is connected to the source of MOSFET M28. The gate of MOSFET M28 is connected to the source of MOSFET M25, and the drain of MOSFET M28 is grounded. The source of MOSFET M29 is connected to the source of MOSFET M27, the gate of MOSFET M29 is connected to the gate of MOSFET M27, and the drain of MOSFET M29 is connected to the source of MOSFET M30. The source of MOSFET M30 is connected to port VRE, the gate of MOSFET M30 is connected to the source of MOSFET M28, and the drain of MOSFET M30 is grounded.

[0080] MOSFETs M27, M28, M29, and M30 are all biased and operate in the weak inversion region. The gate of MOSFET M27 is connected to port VZIS and receives the bias voltage Vcxp through this port. The gate of MOSFET M28 is connected to the source of MOSFET M25, and this connection provides the enhancement compensation voltage Vwz. The gate of MOSFET M29 is connected to the gate of MOSFET M27 to obtain the same bias voltage Vcxp. The voltage Vecb at the junction of the drain of MOSFET M27 and the source of MOSFET M28 serves as the bias voltage for MOSFET M30 and is input to the gate of MOSFET M30.

[0081] Since MOSFET M27 operates in the weak inversion region, the expression for the current Ids27 flowing through the drain and source of MOSFET M27 is as follows.

[0082] ;

[0083] In the formula, Cox is the gate oxide capacitance, u27 is the carrier mobility of MOSFET M27, Ut is the thermal voltage, W27 is the conductive channel width of MOSFET M27, L27 is the conductive channel length of MOSFET M27, K27 is the capacitor voltage division ratio, Vcxp is the bias voltage output by bias circuit 1, VDD is the power supply voltage, and Vth27 is the threshold voltage of MOSFET M27.

[0084] Similarly, since MOSFET M28 also operates in the weak inversion region, the expression for the current Ids28 flowing through the drain and source of MOSFET M28 is as follows.

[0085] ;

[0086] In the formula, Cox is the gate oxide capacitance, u28 is the carrier mobility of MOSFET M28, Ut is the thermal voltage, W28 is the conductive channel width of MOSFET M28, L28 is the conductive channel length of MOSFET M28, K28 is the capacitor voltage division ratio, Vwz is the enhanced compensation voltage output by temperature coefficient compensation circuit 21, Vs28 is the source voltage of MOSFET M28, and Vth28 is the threshold voltage of MOSFET M28.

[0087] Let the threshold voltages of MOSFETs M27, M28, M29, and M30 all be Vthm, i.e., Vth27 = Vth28 = Vth29 = Vth30 = Vthm. Also, K27 = K28 = K29 = K30 = Kb. Since MOSFETs M27 and M28 are in the same branch, Ids27 = Ids28. Since MOSFETs M29 and M30 are in the same branch, Ids29 = Ids30. Ids29 is the current flowing through the drain and source of MOSFET M29, and Ids30 is the current flowing through the drain and source of MOSFET M30. The reference voltage generation circuit 22 outputs the voltage at the connection node between the drain of MOSFET M29 and the source of MOSFET M30 as the reference voltage Vrf through port VRE. Based on the above conditions, the expression for the reference voltage Vrf can be derived as follows.

[0088] ;

[0089] In the above formula, Ut is the thermal voltage, Kb is the voltage division ratio of the MOSFET capacitor, N27 is the width-to-length ratio of MOSFET M27, N28 is the width-to-length ratio of MOSFET M28, N29 is the width-to-length ratio of MOSFET M29, N30 is the width-to-length ratio of MOSFET M30, u27 is the carrier mobility of MOSFET M27, u28 is the carrier mobility of MOSFET M28, u29 is the carrier mobility of MOSFET M29, u30 is the carrier mobility of MOSFET M30, VDD is the power supply voltage, Vcxp is the bias voltage output by bias circuit 1, and Vwz is the enhanced compensation voltage output by temperature coefficient compensation circuit 21.

[0090] As shown in the formula, the enhanced compensation voltage Vwz has a positive temperature coefficient, while when N27×N29 is less than N28×N30, the first term in the formula for the reference voltage Vrf has a negative temperature coefficient. Therefore, by adjusting the width-to-length ratio of MOSFETs M27, M28, M29, and M30, the temperature coefficients in the formula for the reference voltage Vrf can be complementary, meaning that the reference voltage Vrf is unaffected by changes in ambient temperature.

[0091] Furthermore, the formula for the reference voltage Vrf shows that there is a small voltage margin between the reference voltage Vrf and the power supply voltage VDD, which significantly reduces the system's requirement for a high power supply voltage.

[0092] In application, the above circuit system is packaged inside the chip. The charging power supply chip adopts an ESOP8 package, and the pins of the charging power supply chip are as follows: Figure 5 As shown, VDD is the interface pin of power input port 3, through which external DC power is input to the input terminal of the reference source circuit. BAT is the battery connection port, through which the output terminal of the charging drive circuit 5 is connected to the battery to control the charging of the battery. LED and VOUT pins are used to connect the positive and negative terminals of the LED indicator, and are internally connected to the output terminal of the LED drive circuit 8. SEL1, SEL2, and K1 pins are internally connected to the input terminals of the signal input circuit 7. SEL1 and SEL2 are function setting pins, through which the control unit 4 can confirm the working mode by its high and low level signals. Its level has four states: 00, 01, 10, and 11, corresponding to four working modes of the control unit 4. K1 pin is the button pin, used to input button signals to the control unit 4.

[0093] One typical application of charging power supply chips is as follows: Figure 6 As shown, in this embodiment, the 5V of USB is used to power the VDD pin, SEL1 and SEL2 are grounded and are both at low level, the K1 pin is connected to the button SW1, the LED and VOUT pins are connected to the indicator light to indicate the charging status, and the BAT port charges the battery.

Claims

1. A charging power supply chip circuit, comprising a power input port (3), a reference source circuit, a control unit (4), a digital-to-analog converter circuit (6), and a charging drive circuit (5), wherein an external power supply is input to the input terminal of the reference source circuit through the power input port (3), the input terminal of the charging drive circuit (5) is connected to the output terminal of the reference source circuit, the controlled terminal of the charging drive circuit (5) is connected to the output terminal of the control unit (4) through the digital-to-analog converter circuit (6), and the output terminal of the charging drive circuit (5) is used to charge an externally connected battery, characterized in that, The reference source circuit includes a bias circuit (1) and a reference core circuit (2); The bias circuit (1) is connected to the reference core circuit (2). The bias circuit (1) provides a bias voltage to the MOS transistor in the reference core circuit (2) so that it operates in the weak inversion region. The reference core circuit generates a reference voltage that is unaffected by changes in ambient temperature and outputs it to the corresponding load module through the output port; The bias circuit (1) includes a startup circuit (11) and a bias voltage generation circuit (12); The startup circuit (11) includes a self-shutdown circuit and a startup circuit; The self-shutdown circuit is connected to the turn-on circuit; when the system is powered on, the self-shutdown circuit enables the turn-on circuit to conduct. After the system is running stably, the self-shutdown circuit stops the start-up circuit from working, thereby reducing circuit power consumption. After the turn-on circuit is turned on, it provides the start-up conditions for the bias voltage generating circuit (12), so that the bias voltage generating circuit (12) gets rid of the zero current state and gradually enters the stable working state. The bias voltage generation circuit (12) includes an output circuit and a negative feedback circuit; The output circuit is connected to the negative feedback circuit. The MOS transistors in the output circuit are all biased to work in the weak inversion region and generate a bias voltage Vcxp. The bias voltage Vcxp generated by the output circuit is output to the reference core circuit (2) through the port VZDA. The output circuit also provides a bias voltage to the negative feedback circuit, enabling the negative feedback circuit to operate normally; the negative feedback circuit maintains a stable bias voltage Vcxp when the ambient temperature changes. The reference core circuit (2) includes a temperature coefficient compensation circuit (21) and a reference voltage generation circuit (22). The temperature coefficient compensation circuit (21) is connected to the reference voltage generation circuit (22), and the temperature coefficient compensation circuit (21) provides the reference voltage generation circuit (22) with a positive temperature coefficient. The reference voltage generation circuit (22) generates a reference voltage Vrf that is not affected by changes in ambient temperature based on the compensation voltage with a positive temperature coefficient, and outputs it through the port VRE.

2. The charging power supply chip circuit according to claim 1, characterized in that, The temperature coefficient compensation circuit (21) includes a primary compensation circuit and an enhanced output circuit; The primary compensation circuit is connected to the enhanced output circuit; the primary compensation circuit generates a compensation voltage Vfbc with a positive temperature coefficient and outputs it to the enhanced output circuit. The enhanced output circuit enhances the compensation voltage Vfbc in a superimposed manner to meet the requirements of the temperature compensation voltage; the enhanced output circuit outputs the enhanced compensation voltage Vwz to the reference voltage generation circuit (22).

3. The charging power supply chip circuit according to claim 2, characterized in that, The reference voltage generation circuit (22) includes MOSFETs M27, M28, M29, and M30, port VZIS, and port VRE; The source of MOSFET M27 is connected to power supply VDD, the gate of MOSFET M27 is connected to port VZIS, and the drain of MOSFET M27 is connected to the source of MOSFET M28. The gate of MOSFET M28 is connected to the source of MOSFET M25, and the drain of MOSFET M28 is grounded. The source of MOSFET M29 is connected to the source of MOSFET M27, the gate of MOSFET M29 is connected to the gate of MOSFET M27, and the drain of MOSFET M29 is connected to the source of MOSFET M30. The source of MOSFET M30 is connected to port VRE, the gate of MOSFET M30 is connected to the source of MOSFET M28, and the drain of MOSFET M30 is grounded.

4. The charging power supply chip circuit according to claim 1, characterized in that, It also includes a signal input circuit (7), whose input terminal receives external configuration signals through a configuration signal port, and whose output terminal is connected to the function setting signal receiving terminal of the control unit (4).

5. A charging power supply chip circuit according to claim 1, characterized in that, It also includes an LED driver circuit (8), the input of which is connected to the control unit (4), and the output is used to connect to an external LED indicator. According to the signal from the control unit (4), the LED indicator is driven to indicate the battery charging status.

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