Multi-phase BUCK converter and high-dynamic adaptive phase cutting method

Abstract

The invention discloses a multiphase BUCK converter and a high-dynamic self-adaptive phase cutting method. The multiphase BUCK converter comprises a 16-phase power level, a current sampling module, an MOS driving module, a digital control module, a CMCOT simulation main control loop and a dynamic detection circuit. The MOS driving module controls a switching tube in the 16-phase power level, the current sampling module collects an inductive current signal, the input end of the CMCOT simulation main control loop is connected with the output end of the current sampling module, and a PWM control signal is output to the digital control module; the input end of the dynamic detection circuit is connected with an output signal of a voltage loop gain in the CMCOT analog main control loop, and a mark signal is generated and output to the digital control module; the digital control module generates a phase cutting signal. A phase cutting strategy is correspondingly provided, the number of PWM started by a phase cutting signal is adaptively changed, the transient voltage undershoot is reduced, meanwhile, voltage overregulation is avoided, and the transient performance is remarkably improved.

Description

Technical Field

[0001] This invention relates to switching power supplies, specifically to a multiphase BUCK converter, and also to a high-dynamic adaptive phase-cutting method. Background Technology

[0002] With the rapid development of science and technology, various electronic products are increasingly used in work and daily life. Microprocessors are the foundation of computing systems. To achieve more powerful and efficient computing and data processing, microprocessors integrate more and more transistors and faster clocks, leading to increasingly higher current demands. The power density of processors is gradually reaching tens of thousands of watts per square centimeter. One solution is to reduce the supply voltage. Furthermore, as processor computing speeds increase, their load change rate also increases, requiring VRMs (Voltage Regulators) to have stronger transient performance. With the increasing supply current, multiphase BUCK power supplies are now increasingly diverse, with some reaching 16 phases or even exceeding 20 phases. Multiphase power supplies also offer advantages such as lower ripple and more even heat dissipation.

[0003] When the load decreases stepwise, overshoot voltage may occur, causing the processor's operating temperature to rise. This could shorten the processor's lifespan or even damage it. Increased temperature may also cause the processor to operate at low power, directly reducing its performance. When the load increases stepwise, undershoot voltage may occur, leading to system lock-up, a blue screen, or data corruption. Due to increasingly stringent transient requirements, VRMs require more and more output capacitors, resulting in larger VRMs and increased costs. To reduce size and cost, it's necessary to reduce output capacitors by improving VRM control. Transient recovery time is a determining factor in the maximum rate of load change; overshoot also affects voltage recovery speed. Furthermore, as the output voltage decreases, the tolerable voltage deviation window shrinks, so it's also necessary to reduce the amount of voltage change during transients.

[0004] Compared to constant-frequency control, constant-on-time (COT) control offers superior load transient performance and higher load-carrying capacity for high-current loads. For light-load applications, COT control can automatically reduce the frequency, thus typically exhibiting higher efficiency under light loads. COT control modes are divided into RBCOT and V... 2 COT, CMCOT, etc. RBCOT has a simple structure and does not require a compensation loop. However, it operates based on output voltage ripple; the ESR ripple must dominate the output voltage ripple, otherwise subharmonic oscillations will occur. Therefore, an output capacitor with a large ESR is needed to ensure that the ESR ripple is dominant, resulting in a relatively large output ripple. For V, which is also based on ripple control... 2 COT control also requires a large ESR output capacitor, and the delay caused by capacitor ripple may lead to V2 COT control generates subharmonic oscillations. Compared with other control modes, CMCOT control adds a feedback loop that samples the inductor current, which can respond to both voltage and current changes, improving the loop's response speed and eliminating the subharmonic oscillation problem. Summary of the Invention

[0005] The purpose of this invention is to provide a multiphase BUCK converter and a high-dynamic adaptive phase-cutting method. Based on the comparison of the dynamic detection signal with different thresholds, different dynamic control modes are adopted to adaptively change the number of PWM signals activated in a single phase-cutting signal. This reduces transient voltage undershoot while avoiding voltage overshoot, thus significantly improving transient performance.

[0006] To achieve the above functions, this invention designs a multiphase BUCK converter, including a 16-phase power stage, a current sampling module, a MOS drive module, an analog control module, and a digital control module, wherein the analog control module includes a CMCOT analog main control loop and a dynamic detection circuit.

[0007] Among them, the MOS drive module synchronously controls the switching transistors of each phase in the 16-phase power stage, the current sampling module collects the inductor current signal of each phase in the 16-phase power stage, the input terminal of the CMCOT analog main control loop is connected to the output terminal of the current sampling module, and the output terminal is connected to the digital control module. The CMCOT analog main control loop is based on voltage loop gain and current loop dual-loop control, outputs PWM control signal VTR, and outputs to the digital control module.

[0008] The input of the dynamic detection circuit is connected to the output signal of the voltage loop gain in the CMCOT analog main control loop. After high-pass filtering, it is compared with a preset threshold to generate a flag signal flag_r, which is then output to the digital control module.

[0009] The digital control module monitors the current of each phase in real time through ADC sampling. Combined with the PWM control signal VTR of the CMCOT analog main control loop and the flag signal flag_r of the dynamic detection circuit, it generates a phase-cutting signal and outputs it to the MOS drive module to dynamically adjust the phase allocation strategy of the MOS drive module.

[0010] As a preferred embodiment of the present invention: the CMCOT analog main control loop includes an error amplifier, a ramp generator, a voltage summing module, a current summing module, a high-pass filter, and a comparator;

[0011] The current sampling module collects the inductor current signals of each phase in the 16-phase power stage and inputs them into the current summing module. The output of the current summing module is connected to the input of the high-pass filter. The output signal Isum of the high-pass filter is output to the negative input of the comparator. The negative input of the error amplifier receives the voltage feedback signal Vout of each phase in the 16-phase power stage, and the positive input receives the reference voltage Vref. The error signal Vc output by the error amplifier and the ramp signal Vramp output by the ramp generator are input into the voltage summing module. The output signal of the voltage summing module is output to the positive input of the comparator, and the comparator outputs the PWM control signal VTR.

[0012] As a preferred embodiment of the present invention, the dynamic detection circuit includes a high-pass filter and a threshold comparator;

[0013] The high-pass filter is input to the error signal Vc output by the error amplifier in the CMCOT analog main control loop. The output of the high-pass filter is connected to the input of the threshold comparator. The threshold comparator presets thresholds Vth1, Vth2, and Vth3 and outputs a flag signal flag_r.

[0014] As a preferred technical solution of the present invention: the digital control module includes an ADC sampling module, a phase allocation and constant conduction time generation module, and a current sharing loop;

[0015] The ADC sampling module inputs the output signal Isum of the high-pass filter in the CMCOT analog main control loop, and the sampling signal output by the ADC sampling module is output to the current sharing loop. The output of the current sharing loop is connected to the phase distribution and constant conduction time generation module.

[0016] The phase allocation and constant on-time generation module takes into account the PWM control signal VTR output by the comparator in the CMCOT analog main control loop, the flag signal flag_r output by the threshold comparator, and the output signal of the current sharing loop. The phase allocation and constant on-time generation module integrates a blank_time timer and generates a constant on-time Ton_time. The output terminal generates a phase-cutting signal and outputs it to the MOS drive module.

[0017] The present invention also designs a highly dynamic adaptive phase-cutting method, which, based on the aforementioned multiphase BUCK converter, executes steps S1-S3 to complete the dynamic adjustment of the phase allocation strategy of the MOS drive module;

[0018] Step S1: Set up a nonlinear control mode consisting of multiple transient enhancement stages. The timing is started when the PWM control signal VTR output by the comparator in the CMCOT analog main control loop is high. When the time when the PWM control signal VTR is high exceeds the threshold blank_time set by the phase allocation and constant conduction time generation module, the nonlinear control mode is entered.

[0019] Step S2: When a rising pulse of the inductor current signal of each phase in the 16-phase power stage is detected, the dynamic detection signal output by the high-pass filter in the CMCOT analog main control loop is compared with the preset threshold. Based on the comparison result, the transient enhancement stage is selected accordingly, and the MOS drive module adjusts the number of PWM phases in the 16-phase power stage that are turned on each time the phase is switched.

[0020] Step S3: When the output voltage in the 16-phase power stage starts to recover towards VID, the transient enhancement stage is automatically downgraded according to the change of the dynamic detection signal output by the high-pass filter, thus completing the dynamic adjustment of the phase allocation strategy of the MOS drive module.

[0021] As a preferred technical solution of the present invention, the nonlinear control mode described in step S1 is as follows:

[0022] A phase-cutting signal is generated every blank_time interval. The high-pass filter in the dynamic detection circuit outputs a dynamic detection signal Vdif to the threshold comparator. The threshold comparator compares the dynamic detection signal Vdif with the preset first threshold Vth1, second threshold Vth2, and third threshold Vth3, respectively, and sets transient enhancement stages 1, 2, 3, and 4. Specifically, transient enhancement stage 1 is selected when the PWM control signal VTR is high for a period of time exceeding the threshold blank_time set by the phase allocation and constant conduction time generation module; transient enhancement stage 2 is selected when the dynamic detection signal Vdif is greater than the first threshold Vth1; transient enhancement stage 3 is selected when the dynamic detection signal Vdif is greater than the second threshold Vth2; and transient enhancement stage 4 is selected when the dynamic detection signal Vdif is greater than the third threshold Vth3.

[0023] As a preferred technical solution of the present invention, the specific method of step S2 is as follows:

[0024] When a current rise pulse is detected, the dynamic detection signal Vdif begins to rise. At this time, the dynamic detection signal Vdif is lower than the first threshold Vth1, and the system enters transient enhancement stage 1, where N1 PWM phases are activated every blank_time_1 time interval. If the load current jump is large enough to cause the dynamic detection signal Vdif to exceed the first threshold Vth1, the system upgrades to transient enhancement stage 2, where N2 PWM phases are activated simultaneously every blank_time_2 time interval, where N2 > N1. When the dynamic detection signal Vdif further increases and exceeds the second threshold Vth2, the system enters transient enhancement stage 3, where N3 PWM phases are activated simultaneously every blank_time_3 time interval, where N3 > N2. When the dynamic detection signal Vdif exceeds the third threshold Vth3, the system enters transient enhancement stage 4, where N4 PWM phases are activated simultaneously every blank_time_4 time interval, where N4 > N3.

[0025] As a preferred technical solution of the present invention, the specific method of step S3 is as follows:

[0026] When the output voltage begins to recover towards VID, if the dynamic detection signal Vdif output by the high-pass filter decreases to the third threshold Vth3, the system reverts from transient enhancement stage 4 to transient enhancement stage 3; if the dynamic detection signal Vdif decreases to the second threshold Vth2, the system reverts from transient enhancement stage 3 to transient enhancement stage 2; if the dynamic detection signal Vdif decreases to the first threshold Vth1, the system reverts from transient enhancement stage 2 to transient enhancement stage 1; when the dynamic detection signal Vdif is less than the first threshold Vth1 or when the falling edge of the PWM control signal VTR is detected, the set threshold blank_time is adjusted to be equal to the PWM interleaving time of adjacent phases in steady state, denoted as blank_time_recovery.

[0027] Beneficial effects: Compared with the prior art, the advantages of the present invention include:

[0028] 1. The adaptive high-dynamic phase-switching control algorithm proposed in this invention achieves multi-mode transient enhancement control by comparing the dynamically detected signal with multi-level thresholds. The system can automatically switch between transient enhancement modes of different intensities according to changes in load current, significantly improving PWM overlap capability during high current steps, effectively reducing output voltage undershoot and avoiding overshoot. This nonlinear control algorithm ensures fast response while maintaining steady-state stability through the blank_time parameter and phase number adjustment mechanism, providing a reliable solution for high-frequency load-switching scenarios.

[0029] 2. This invention employs a hybrid analog-digital control architecture, introducing a digital control module while retaining the fast response characteristics of the CMCOT analog main loop. The digital section, through the collaborative operation of a high-performance PWM control module and a fully digital steady-state current-sharing loop, significantly reduces the system's dependence on hardware such as high-speed ADCs. This architecture not only reduces circuit size and cost but also provides high flexibility through configurable digital controller parameters.

[0030] 3. This invention optimizes the transient performance of multiphase architectures. By controlling phase overlap, the response speed of the BUCK converter can be improved as the number of phases increases. This feature solves the problem of transient performance degradation in traditional multiphase BUCK converters with increasing phase number, providing a more scalable solution for powering high-performance processors. While maintaining the advantages of interleaved buck converters, the system achieves an optimized balance between ripple cancellation and current sharing for heat dissipation.

[0031] 4. The control method proposed in this invention exhibits excellent adaptability across all operating conditions, capable of handling large current jumps of up to 600A while also optimizing response characteristics under medium and small current loads. Through a dynamic downsizing mechanism, the system automatically matches the optimal control mode under different load conditions, ensuring both rapid response under high current and smooth transition under low current, thus achieving a balance between transient performance and stability. Attached Figure Description

[0032] Figure 1 This is a system architecture diagram of a multiphase BUCK converter according to an embodiment of the present invention;

[0033] Figure 2 This is a CMCOT analog main control loop architecture diagram provided according to an embodiment of the present invention;

[0034] Figure 3 This is a flowchart of a highly dynamic adaptive phase-cutting method provided by an embodiment of the present invention;

[0035] Figure 4 This is a waveform diagram provided by an embodiment of the present invention, taking N1=1, N2=2, N3=3, N4=4 as an example;

[0036] Figure 5 This is a performance comparison chart of the present invention embodiment and the conventional COT controller under a 600A current load step;

[0037] Figure 6 This is a performance comparison chart of the present invention embodiment and the conventional COT controller under a 200A small current transient. Detailed Implementation

[0038] The present invention will be further described below with reference to the accompanying drawings. The following embodiments are only used to more clearly illustrate the technical solution of the present invention, and should not be used to limit the scope of protection of the present invention.

[0039] An embodiment of the present invention provides a multiphase BUCK converter, referring to... Figure 1 It includes a 16-phase power stage, a current sampling module, a MOS drive module, an analog control module, and a digital control module. The analog control module includes a CMCOT analog main control loop and a dynamic detection circuit.

[0040] Among them, the MOS drive module synchronously controls the switching transistors of each phase in the 16-phase power stage, the current sampling module collects the inductor current signal of each phase in the 16-phase power stage, the input terminal of the CMCOT analog main control loop is connected to the output terminal of the current sampling module, and the output terminal is connected to the digital control module. The CMCOT analog main control loop adopts a three-branch parallel processing structure, based on voltage loop gain and current loop dual-loop control, and outputs the PWM control signal VTR, which is output to the digital control module.

[0041] The input of the dynamic detection circuit is connected to the output signal of the voltage loop gain in the CMCOT analog main control loop. After high-pass filtering, it is compared with a preset threshold to generate a flag signal flag_r, which is then output to the digital control module.

[0042] The digital control module monitors the current of each phase in real time through ADC sampling. Combined with the PWM control signal VTR of the CMCOT analog main control loop and the flag signal flag_r of the dynamic detection circuit, it generates a phase-cutting signal and outputs it to the MOS drive module to dynamically adjust the phase allocation strategy of the MOS drive module.

[0043] The multiphase BUCK converter system architecture proposed in this invention refers to... Figure 1 The system employs a mixed-signal design to achieve high-precision closed-loop regulation. Centered on a 16-phase power stage, the system synchronously controls the switches of each phase via a MOS drive module. Inductor current signals iL1-iL16 are processed by the voltage summing module output after current loop gain adjustment. The analog main loop includes dual-loop control of voltage loop gain and current loop. The comparator module receives outputs from the ramp generator and voltage loop to generate the PWM control signal VTR. The digital control section includes an adaptive phase distributor and a current sharing loop. It monitors the current of each phase in real time via ADC sampling and dynamically adjusts the phase distribution strategy based on the Ton_time parameter output by the constant on-time generation module, ensuring system stability over a wide load range. This architecture combines the fast response of the analog loop with the precise adjustment of the digital control, achieving excellent performance of the multiphase Buck converter under both steady-state and transient conditions.

[0044] Figure 2The CMCOT analog main control loop architecture diagram provided by the present invention includes an error amplifier, a ramp generator, a voltage summing module, a current summing module, a high-pass filter, and a comparator.

[0045] The error amplifier forms the voltage loop gain, the current summing module and the high-pass filter form the current loop gain, the voltage loop is responsible for the precise adjustment of the output voltage, the current loop realizes the rapid tracking of the inductor current, and the ramp generates branches to improve the overall stability of the system.

[0046] The inductor current signals of each phase in the 16-phase power stage collected by the current sampling module are input to the current summing module. The output of the current summing module is connected to the input of the high-pass filter. The output signal Isum of the high-pass filter is output to the negative input of the comparator. The negative input of the error amplifier is input to the voltage feedback signal Vout of each phase in the 16-phase power stage, and the positive input of the error amplifier is input to the reference voltage Vref. The error signal Vc output by the error amplifier and the ramp signal Vramp output by the ramp generator are input to the voltage summing module. The output signal of the voltage summing module is output to the positive input of the comparator, and the comparator outputs the PWM control signal VTR. The ramp signal Vramp, the error signal Vc, and the output signal Isum of the high-pass filter work together to generate the PWM control signal VTR. This design ensures both voltage regulation accuracy and fast current response.

[0047] The dynamic detection circuit includes a high-pass filter and a threshold comparator;

[0048] The high-pass filter inputs the error signal Vc output by the error amplifier in the CMCOT analog main control loop. The high-pass filter extracts the transient component and connects the output to the input of the threshold comparator. The threshold comparator presets thresholds Vth1, Vth2, and Vth3, determines its dynamic control mode, and outputs a flag signal flag_r to the dynamic phase-cutting strategy engine of the digital control module.

[0049] The input of the dynamic detection circuit performs high-pass filtering on the amplified error voltage signal and directly compares it with a preset threshold to determine the dynamic control mode. Compared with the traditional low-pass filtering + differentiation scheme, this design does not require buffer isolation, resulting in a simpler circuit structure, reduced dynamic detection delay, improved system response speed to load changes, reduced impedance matching issues, and faster response speed. The real-time comparison results of the dynamic detection signal Vdif with multi-level thresholds (Vth1, Vth2, Vth3, etc.) provide a basis for state judgment in subsequent high-dynamic control algorithms.

[0050] The digital control module includes an ADC sampling module, a phase allocation and constant on-time generation module, and a current sharing loop;

[0051] The ADC sampling module inputs the output signal Isum of the high-pass filter in the CMCOT analog main control loop, and the sampling signal output by the ADC sampling module is output to the current sharing loop. The output of the current sharing loop is connected to the phase distribution and constant conduction time generation module.

[0052] The phase allocation and constant on-time generation module takes into account the PWM control signal VTR output by the comparator in the CMCOT analog main control loop, the flag signal flag_r output by the threshold comparator, and the output signal of the current sharing loop. The phase allocation and constant on-time generation module integrates a blank_time timer and generates a constant on-time Ton_time. The output terminal generates a phase-cutting signal and outputs it to the MOS drive module.

[0053] During steady-state operation, the phase distributor maintains a fixed phase shift in the PWM output. When a transient event is detected, the corresponding phase-switching strategy is activated based on the flag_r signal, dynamically adjusting the number of PWM trigger phases. The module integrates a blank_time timer, which automatically triggers a nonlinear control mode when the VTR high-level duration exceeds a set threshold, ensuring effective PWM triggering even under severe transient conditions.

[0054] The Ton_time output by the constant on-time generation module is the system's COT control parameter, used to control the on-time of the upper switch and the off-time of the lower switch in the 16-phase power stage. It, along with the duty cycle, controls the system's switching frequency and has an effect in both dynamic and static states. The preset blank_time only applies when the system enters a transient nonlinear control mode, controlling the number of phases activated in each phase switch of the 16-phase power stage. Its value needs to be set according to the value of Ton_time.

[0055] The ramp generator module receives the flag_r signal from the digital control module and the VTR signal from the main loop comparator at its input terminal, and outputs a ramp signal that is fed back to the main loop comparator. In state 1 (discharge mode), the internal timer of the module starts counting reset_time cycles; after entering state 2 (charging mode), it continuously builds the ramp voltage for counter_max-reset_time clock cycles; when state 3 (hold mode) is reached, the maximum output value is maintained until a rising edge of VTR is detected or the flag_r signal triggers state 4 (transient mode). This operating mode enables the ramp generator to meet both steady-state accuracy requirements and rapid response to transient events.

[0056] The phase allocation and constant on-time generation module is written in Veriliog. The digital control module intelligently generates phase-cutting signals based on the control signal VTR and dynamic detection results. It maintains normal phase interleaving control in steady state and adaptively adjusts the phase-cutting strategy according to the degree of load change during transients. This module can simultaneously activate different numbers of PWM phases based on the degree of output voltage overshoot or undershoot, significantly improving transient response speed.

[0057] This invention also provides a high-dynamic adaptive phase-cutting method, based on the aforementioned multiphase BUCK converter, with reference to... Figure 3 Execute steps S1-S3 to complete the dynamic adjustment of the phase allocation strategy of the MOS drive module;

[0058] Step S1: Set up a nonlinear control mode consisting of multiple transient enhancement stages. The timing is started when the PWM control signal VTR output by the comparator in the CMCOT analog main control loop is high. When the time when the PWM control signal VTR is high exceeds the threshold blank_time set by the phase allocation and constant conduction time generation module, the nonlinear control mode is entered.

[0059] The nonlinear control mode described in step S1 is as follows:

[0060] A phase-cutting signal is generated every blank_time interval to accelerate the recovery of the undershoot voltage. The high-pass filter in the dynamic detection circuit outputs a dynamic detection signal Vdif to the threshold comparator. The threshold comparator compares the dynamic detection signal Vdif with the preset first threshold Vth1, second threshold Vth2, and third threshold Vth3, respectively, and sets transient enhancement stages 1, 2, 3, and 4. Specifically, transient enhancement stage 1 is selected when the PWM control signal VTR is high for a period of time exceeding the threshold blank_time set by the phase allocation and constant conduction time generation module; transient enhancement stage 2 is selected when the dynamic detection signal Vdif is greater than the first threshold Vth1; transient enhancement stage 3 is selected when the dynamic detection signal Vdif is greater than the second threshold Vth2; and transient enhancement stage 4 is selected when the dynamic detection signal Vdif is greater than the third threshold Vth3.

[0061] Step S2: When a rising pulse of the inductor current signal of each phase in the 16-phase power stage is detected, the dynamic detection signal output by the high-pass filter in the CMCOT analog main control loop is compared with the preset threshold. Based on the comparison result, the transient enhancement stage is selected accordingly, and the MOS drive module adjusts the number of PWM phases in the 16-phase power stage that are turned on each time the phase is switched.

[0062] The specific method for step S2 is as follows:

[0063] When a current rise pulse is detected, the dynamic detection signal Vdif begins to rise. At this time, the dynamic detection signal Vdif is lower than the first threshold Vth1, and the system enters transient enhancement stage 1, where N1 PWM phases are activated every blank_time_1 time interval. If the load current jump is large enough to cause the dynamic detection signal Vdif to exceed the first threshold Vth1, the system upgrades to transient enhancement stage 2, where N2 PWM phases are activated simultaneously every blank_time_2 time interval, where N2 > N1. When the dynamic detection signal Vdif further increases and exceeds the second threshold Vth2, the system enters transient enhancement stage 3, where N3 PWM phases are activated simultaneously every blank_time_3 time interval, where N3 > N2. When the dynamic detection signal Vdif exceeds the third threshold Vth3, the system enters transient enhancement stage 4, where N4 PWM phases are activated simultaneously every blank_time_4 time interval, where N4 > N3. This algorithm significantly improves the current rise rate when the system experiences transients, ensuring that the system can achieve the optimal dynamic response and stability balance when dealing with load steps of varying intensities.

[0064] Step S3: When the output voltage in the 16-phase power stage starts to recover towards VID, the transient enhancement stage is automatically downgraded according to the change of the dynamic detection signal output by the high-pass filter, thus completing the dynamic adjustment of the phase allocation strategy of the MOS drive module.

[0065] The specific method for step S3 is as follows:

[0066] When the output voltage begins to recover towards VID, if the dynamic detection signal Vdif output by the high-pass filter decreases to the third threshold Vth3, the system retreats from transient enhancement stage 4 back to transient enhancement stage 3; if the dynamic detection signal Vdif decreases to the second threshold Vth2, the system retreats from transient enhancement stage 3 back to transient enhancement stage 2; if the dynamic detection signal Vdif decreases to the first threshold Vth1, the system retreats from transient enhancement stage 2 back to transient enhancement stage 1. When the dynamic detection signal Vdif is less than the first threshold Vth1 or a falling edge of the PWM control signal VTR is detected, the set threshold blank_time is adjusted to be equal to the PWM interleaving time between adjacent phases in steady state, recorded as blank_time_recovery, to counteract the decreasing trend of Vdif. This gradual exit mechanism ensures smooth recovery of the output voltage and effectively avoids overshoot. Throughout the process, the matching of the set threshold blank_time and the number of active phases achieves a balance between response speed and stability.

[0067] Figure 4The waveform diagram is shown using N1=1, N2=2, N3=3, and N4=4 as an example. This algorithm achieves intelligent phase allocation through multi-level threshold detection and is verified using a 16-phase 12-1V Buck converter. The steady-state operating mode (S0) serves as the initial state, employing a basic phase allocation strategy to maintain the staggered distribution of PWM phases. When the high-level duration of VTR exceeds the blank_time threshold, the system enters transient enhancement stage 1 (S1). In this state, the controller triggers a phase increment operation every blank_time_1 cycles, activating N1 phase PWM each time. If the dynamic detection signal Vdif exceeds the first threshold Vth1, it upgrades to transient enhancement stage 2 (S2), activating N2 phase PWM every blank_time_2 cycles. When Vdif further exceeds the second threshold Vth2, the system enters transient enhancement stage 3 (S3), activating N3 phase PWM every blank_time_3 cycles. When Vdif exceeds the third threshold Vth3, the system enters transient enhancement stage 4 (S4), activating N4 phase PWM every blank_time_4 cycles. This algorithm maximizes transient response capability while ensuring system stability, significantly improving the system's instantaneous load-carrying capacity.

[0068] Figure 5 The graph shows a performance comparison between the present invention and a traditional COT controller under a 600A current load step, where (a) represents the performance of the present invention and (b) represents the performance of the traditional COT controller. Under a 600A current load step, the present invention implements an adaptive phase allocation strategy through dynamic detection, reducing the output voltage undershoot from 151mV in the traditional scheme to 60mV, and shortening the recovery time from 17μs to 4μs. This closed-loop adaptive mechanism effectively resolves the contradiction between voltage drop and recovery stability under high current transients.

[0069] Figure 6 The graph shows a performance comparison between the present invention and a traditional COT controller under a 200A low-current transient, where (a) is the performance graph of the present invention and (b) is the performance graph of the traditional COT controller. Although the absolute undershoot difference is small, the present invention still achieves a 40% improvement in recovery time through a control strategy that precisely matches the transient intensity. This demonstrates that the present invention can achieve optimal dynamic response to load steps of different amplitudes while maintaining overshoot-free characteristics.

[0070] The embodiments of the present invention have been described in detail above with reference to the accompanying drawings. However, the present invention is not limited to the above embodiments. Within the scope of knowledge possessed by those skilled in the art, various changes can be made without departing from the spirit of the present invention.

Claims

1. A multiphase BUCK converter, characterized in that, It includes a 16-phase power stage, a current sampling module, a MOS drive module, an analog control module, and a digital control module. The analog control module includes a CMCOT analog main control loop and a dynamic detection circuit. Among them, the MOS drive module synchronously controls the switching transistors of each phase in the 16-phase power stage, the current sampling module collects the inductor current signal of each phase in the 16-phase power stage, the input terminal of the CMCOT analog main control loop is connected to the output terminal of the current sampling module, and the output terminal is connected to the digital control module. The CMCOT analog main control loop is based on voltage loop gain and current loop dual-loop control, outputs PWM control signal VTR, and outputs to the digital control module. The input of the dynamic detection circuit is connected to the output signal of the voltage loop gain in the CMCOT analog main control loop. After high-pass filtering, it is compared with a preset threshold to generate a flag signal flag_r, which is then output to the digital control module. The digital control module monitors the current of each phase in real time through ADC sampling. Combined with the PWM control signal VTR of the CMCOT analog main control loop and the flag signal flag_r of the dynamic detection circuit, it generates a phase-cutting signal and outputs it to the MOS drive module to dynamically adjust the phase allocation strategy of the MOS drive module.

2. A multiphase BUCK converter according to claim 1, characterized in that, The CMCOT analog main control loop includes an error amplifier, a ramp generator, a voltage summator, a current summator, a high-pass filter, and a comparator. The current sampling module collects the inductor current signals of each phase in the 16-phase power stage and inputs them into the current summing module. The output of the current summing module is connected to the input of the high-pass filter. The output signal Isum of the high-pass filter is output to the negative input of the comparator. The negative input of the error amplifier receives the voltage feedback signal Vout of each phase in the 16-phase power stage, and the positive input receives the reference voltage Vref. The error signal Vc output by the error amplifier and the ramp signal Vramp output by the ramp generator are input into the voltage summing module. The output signal of the voltage summing module is output to the positive input of the comparator, and the comparator outputs the PWM control signal VTR.

3. A multiphase BUCK converter according to claim 2, characterized in that, The dynamic detection circuit includes a high-pass filter and a threshold comparator; The high-pass filter is input to the error signal Vc output by the error amplifier in the CMCOT analog main control loop. The output of the high-pass filter is connected to the input of the threshold comparator. The threshold comparator presets thresholds Vth1, Vth2, and Vth3 and outputs a flag signal flag_r.

4. A multiphase BUCK converter according to claim 3, characterized in that, The digital control module includes an ADC sampling module, a phase allocation and constant on-time generation module, and a current sharing loop; The ADC sampling module inputs the output signal Isum of the high-pass filter in the CMCOT analog main control loop, and the sampling signal output by the ADC sampling module is output to the current sharing loop. The output of the current sharing loop is connected to the phase distribution and constant conduction time generation module. The phase allocation and constant on-time generation module takes into account the PWM control signal VTR output by the comparator in the CMCOT analog main control loop, the flag signal flag_r output by the threshold comparator, and the output signal of the current sharing loop. The phase allocation and constant on-time generation module integrates a blank_time timer and generates a constant on-time Ton_time. The output terminal generates a phase-cutting signal and outputs it to the MOS drive module.

5. A high-dynamic adaptive phase-cutting method, characterized in that, Based on the multiphase BUCK converter according to claim 4, steps S1-S3 are executed to complete the dynamic adjustment of the phase allocation strategy of the MOS drive module; Step S1: Set up a nonlinear control mode consisting of multiple transient enhancement stages. The timing is started when the PWM control signal VTR output by the comparator in the CMCOT analog main control loop is high. When the time when the PWM control signal VTR is high exceeds the threshold blank_time set by the phase allocation and constant conduction time generation module, the nonlinear control mode is entered. Step S2: When a rising pulse of the inductor current signal of each phase in the 16-phase power stage is detected, the dynamic detection signal output by the high-pass filter in the CMCOT analog main control loop is compared with the preset threshold. Based on the comparison result, the transient enhancement stage is selected accordingly, and the MOS drive module adjusts the number of PWM phases in the 16-phase power stage that are turned on each time the phase is switched. Step S3: When the output voltage in the 16-phase power stage starts to recover towards VID, the transient enhancement stage is automatically downgraded according to the change of the dynamic detection signal output by the high-pass filter, thus completing the dynamic adjustment of the phase allocation strategy of the MOS drive module.

6. The high dynamic adaptive phase cutting method according to claim 5, characterized in that, The nonlinear control mode described in step S1 is as follows: A phase-cutting signal is generated every blank_time interval. The high-pass filter in the dynamic detection circuit outputs a dynamic detection signal Vdif to the threshold comparator. The threshold comparator compares the dynamic detection signal Vdif with the preset first threshold Vth1, second threshold Vth2, and third threshold Vth3, respectively, and sets transient enhancement stages 1, 2, 3, and 4. Specifically, transient enhancement stage 1 is selected when the PWM control signal VTR is high for a period of time exceeding the threshold blank_time set by the phase allocation and constant conduction time generation module; transient enhancement stage 2 is selected when the dynamic detection signal Vdif is greater than the first threshold Vth1; transient enhancement stage 3 is selected when the dynamic detection signal Vdif is greater than the second threshold Vth2; and transient enhancement stage 4 is selected when the dynamic detection signal Vdif is greater than the third threshold Vth3.

7. The high dynamic adaptive phase cutting method according to claim 5, characterized in that, The specific method for step S2 is as follows: When a current rise pulse is detected, the dynamic detection signal Vdif begins to rise. At this time, the dynamic detection signal Vdif is lower than the first threshold Vth1, and the system enters transient enhancement stage 1, where N1 PWM phases are activated every blank_time_1 time interval. If the load current jump is large enough to cause the dynamic detection signal Vdif to exceed the first threshold Vth1, the system upgrades to transient enhancement stage 2, where N2 PWM phases are activated simultaneously every blank_time_2 time interval, where N2 > N1. When the dynamic detection signal Vdif further increases and exceeds the second threshold Vth2, the system enters transient enhancement stage 3, where N3 PWM phases are activated simultaneously every blank_time_3 time interval, where N3 > N2. When the dynamic detection signal Vdif exceeds the third threshold Vth3, the system enters transient enhancement stage 4, where N4 PWM phases are activated simultaneously every blank_time_4 time interval, where N4 > N3.

8. The high dynamic adaptive phase cutting method according to claim 5, characterized in that, The specific method for step S3 is as follows: When the output voltage begins to recover towards VID, if the dynamic detection signal Vdif output by the high-pass filter decreases to the third threshold Vth3, the system reverts from transient enhancement stage 4 to transient enhancement stage 3; if the dynamic detection signal Vdif decreases to the second threshold Vth2, the system reverts from transient enhancement stage 3 to transient enhancement stage 2; if the dynamic detection signal Vdif decreases to the first threshold Vth1, the system reverts from transient enhancement stage 2 to transient enhancement stage 1; when the dynamic detection signal Vdif is less than the first threshold Vth1 or when the falling edge of the PWM control signal VTR is detected, the set threshold blank_time is adjusted to be equal to the PWM interleaving time of adjacent phases in steady state, denoted as blank_time_recovery.

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