Compact-size low-power-consumption CMOS (Complementary Metal Oxide Semiconductor) broadband low-noise amplifier

Abstract

The invention discloses a CMOS (Complementary Metal Oxide Semiconductor) broadband low-noise amplifier with compact size and low power consumption. The CMOS broadband low-noise amplifier comprises a first matching transformer, a first-stage differential amplifier, an intermediate matching transformer, an intermediate resonant network, a second-stage differential amplifier and a second matching transformer, the first matching transformer is used for receiving a radio frequency input signal and realizing impedance matching; the first-stage differential amplifier is used for performing first-stage amplification on the radio frequency input signal; the intermediate matching transformer is used for transmitting the radio frequency signal after the first-stage amplification; the intermediate resonance network is used for carrying out resonance processing on the amplified radio frequency signal; the second-stage differential amplifier is used for performing second-stage amplification on the radio frequency signal after resonance processing; and the second matching transformer is used for realizing output impedance matching and outputting the radio frequency signal after second-stage amplification. According to the differential low-noise amplifier, high-gain broadband can be realized, and meanwhile, the area is compact and the power consumption is low.

Description

Technical Field

[0001] This invention belongs to the field of radio frequency integrated circuit design technology, and particularly relates to a compact, low-power CMOS broadband low-noise amplifier. Background Technology

[0002] The rapid development of millimeter-wave communication systems such as 5G millimeter-wave, satellite internet, and high-speed wireless data links has greatly stimulated the demand for highly integrated and energy-efficient transceivers. As the first active stage in the receiver front-end, the low-noise amplifier plays a crucial role in the overall sensitivity and noise performance of the system. Specifically, for applications operating in the Ka-band, the low-noise amplifier must simultaneously provide wideband gain, low noise figure, and compact integration to support the large-scale array-based architecture of next-generation communication systems.

[0003] CMOS technology, due to its low cost and ease of integration, has become the mainstream manufacturing process for modern chip and SoC design. It is also one of the leading technologies in the development of radio frequency integrated circuits. In recent years, various techniques have been proposed to improve the performance of CMOS low-noise amplifiers at millimeter-wave frequencies. Transformer-based matching networks, noise cancellation topologies, GM enhancement, and coupled-line feedback have all shown significant improvements in NF, gain, and bandwidth (BW) extension.

[0004] However, existing amplifiers suffer from complex designs, large areas, and high noise levels. Therefore, there is an urgent need for a compact, low-power CMOS broadband low-noise amplifier. Summary of the Invention

[0005] To address the aforementioned technical problems, this invention proposes a compact, low-power CMOS broadband low-noise amplifier. The differential low-noise amplifier of this invention can achieve high gain and wide bandwidth while maintaining a compact size and low power consumption.

[0006] To achieve the above objectives, the present invention provides a compact, low-power CMOS broadband low-noise amplifier, comprising: a first matching transformer, a first-stage differential amplifier, an intermediate matching transformer, an intermediate resonant network, a second-stage differential amplifier, and a second matching transformer;

[0007] The first matching transformer is used to receive radio frequency input signals and achieve impedance matching;

[0008] The first-stage differential amplifier is used to amplify the radio frequency input signal in the first stage.

[0009] The intermediate matching transformer is used to transmit the first-stage amplified radio frequency signal;

[0010] The intermediate resonant network is used to perform resonant processing on the amplified radio frequency signal.

[0011] The second-stage differential amplifier is used to amplify the resonant radio frequency signal in the second stage.

[0012] The second matching transformer is used to achieve output impedance matching and output the second-stage amplified radio frequency signal.

[0013] Optionally, the first-stage differential amplifier includes: a first transistor M1, a second transistor M2, a first cross-neutralizing capacitor Cn1, and a second cross-neutralizing capacitor Cn2, wherein the first transistor M1 and the second transistor M2 are a differential pair, and the sources of the first transistor M1 and the second transistor M2 are connected to ground; the gate of the first transistor M1 is connected to the differential positive output of the first matching transformer TF1, which is the positive signal input of the first-stage differential amplifier; the gate of the second transistor M2 is connected to the differential negative output of the first matching transformer TF1, which is the negative signal input of the first-stage differential amplifier; the drain of the first transistor M1 is connected to the differential positive input of the intermediate matching transformer TF2, which is the positive signal output of the first-stage differential amplifier; the drain of the second transistor M2 is connected to the differential negative input of the intermediate matching transformer TF2, which is the negative signal output of the first-stage differential amplifier; the first cross-neutralizing capacitor Cn1 is connected to the gate of the first transistor M1 and the drain of the second transistor M2, and the second cross-neutralizing capacitor Cn2 is connected to the gate of the second transistor M2 and the drain of the first transistor M1.

[0014] Optionally, the intermediate resonant network includes: a first inductor L1, a second inductor L2, and a capacitor C2;

[0015] The first inductor L1 and the second inductor L2 are connected between the intermediate matching transformer and the second-stage differential amplifier. The input of the first inductor L1 is connected to the differential positive output of the intermediate matching transformer TF2, and the output of the first inductor L1 is connected to the positive terminal of the capacitor C2 and the positive signal input terminal of the second-stage differential amplifier. The input of the second inductor L2 is connected to the differential negative output of the intermediate matching transformer TF2, and the output of the second inductor L2 is connected to the negative terminal of the capacitor C2 and the negative signal input terminal of the second-stage differential amplifier.

[0016] The capacitor C2 is connected between two series inductors to form a resonance with the parasitic capacitance of the second-stage differential amplifier. The positive terminal of the capacitor C2 is connected to the output of the first inductor L1 and the positive signal input terminal of the second-stage differential amplifier; the negative terminal of the capacitor C2 is connected to the output of the second inductor L2 and the negative signal input terminal of the second-stage differential amplifier.

[0017] Optionally, the second-stage differential amplifier includes: a third transistor M3, a fourth transistor M4, a third cross-neutralizing capacitor Cn3, and a fourth cross-neutralizing capacitor Cn4, wherein the third transistor M3 and the fourth transistor M4 are a differential pair, and the sources of the third transistor M3 and M4 are connected to ground; the gate of the third transistor M3 is connected to the output of the first inductor L1, which is the positive signal input of the second-stage differential amplifier; the gate of the fourth transistor M4 is connected to the output of the second inductor L2, which is the negative signal input of the second-stage differential amplifier; the drain of the third transistor M3 is connected to the differential positive input of the second matching transformer TF3, which is the positive signal output of the second-stage differential amplifier; the drain of the fourth transistor M4 is connected to the differential negative input of the second matching transformer TF3, which is the negative signal output of the second-stage differential amplifier; the third cross-neutralizing capacitor Cn3 is connected to the gate of the third transistor M3 and the drain of the fourth transistor M4, and the fourth cross-neutralizing capacitor Cn4 is connected to the gate of the fourth transistor M4 and the drain of the third transistor M3.

[0018] Optionally, the gate width of the transistor is 16μm, the total gate width is 32μm, the gate interdigit length is 1μm, and the number of interdigits is 16.

[0019] Optionally, the first matching transformer, the intermediate matching transformer, and the second matching transformer are all on-chip integrated transformers, and the inductance values ​​of the primary and secondary coils of the on-chip integrated transformers are in the range of 160pH to 310pH.

[0020] Optionally, the CMOS broadband low-noise amplifier also includes: a first parallel resonant capacitor C1, a second parallel resonant capacitor C2, and a third parallel resonant capacitor C3;

[0021] The first parallel resonant capacitor C1 is connected between the differential positive and negative output poles of the secondary coil of the first matching transformer;

[0022] The second parallel resonant capacitor C2 is connected between the output terminals of the first inductor L1 and the second inductor L2 of the intermediate resonant network.

[0023] The third parallel resonant capacitor C3 is connected between the differential positive and negative output poles of the primary coil of the second matching transformer.

[0024] Optionally, the operating voltage of the first-stage differential amplifier and the second-stage differential amplifier is 1V, and the power consumption of a single stage is 8mW.

[0025] Compared with the prior art, the present invention has the following advantages and technical effects:

[0026] This invention uses a transformer as an impedance matching network in the circuit, which can effectively reduce the circuit area. The addition of a parallel resonant capacitor effectively reduces the transformer coil area. The two inductors L1 and L2 connected in series after the interstage transformer TF2 are used to enhance the bandwidth of the low-noise amplifier. Attached Figure Description

[0027] The accompanying drawings, which form part of this application, are used to provide a further understanding of this application. The illustrative embodiments and descriptions of this application are used to explain this application and do not constitute an undue limitation of this application. In the drawings:

[0028] Figure 1 This is a structural diagram of a compact, low-power CMOS broadband low-noise amplifier according to an embodiment of the present invention;

[0029] Figure 2 This is an optimized design diagram of the circuit and layout of the two-stage amplifier in this embodiment of the invention;

[0030] Figure 3 The following are simulation comparison diagrams of the overall low-noise amplifier circuits with and without L1 and L2 in this embodiment of the invention.

[0031] Figure 4 This is a simulation diagram of a low-noise amplifier in an embodiment of the present invention;

[0032] Figure 5 This is a core layout and dimension diagram of the low-noise amplifier according to an embodiment of the present invention. Detailed Implementation

[0033] It should be noted that, unless otherwise specified, the embodiments and features described in this application can be combined with each other. This application will now be described in detail with reference to the accompanying drawings and embodiments.

[0034] It should be noted that the steps shown in the flowchart in the accompanying drawings can be executed in a computer system such as a set of computer-executable instructions, and although a logical order is shown in the flowchart, in some cases the steps shown or described may be executed in a different order than that shown here.

[0035] This embodiment proposes a compact, low-power CMOS broadband low-noise amplifier, such as... Figure 1 As shown, it specifically includes: a first matching transformer, a first-stage differential amplifier, an intermediate matching transformer, an intermediate resonant network, a second-stage differential amplifier, and a second matching transformer;

[0036] The first matching transformer is used to receive radio frequency input signals and achieve impedance matching.

[0037] The first-stage differential amplifier is used to amplify the radio frequency input signal in the first stage.

[0038] An intermediate matching transformer is used to transmit the radio frequency signal after the first stage of amplification.

[0039] An intermediate resonant network is used to resonate the amplified radio frequency signal.

[0040] The second-stage differential amplifier is used to amplify the resonant radio frequency signal in the second stage.

[0041] The second matching transformer is used to achieve output impedance matching and output the second-stage amplified RF signal.

[0042] Specifically, the purpose of this embodiment is to propose a Ka-band differential broadband low-noise amplifier based on 65-nm CMOS technology, while also considering a compact area and low power consumption design, for use in millimeter-wave wireless communication receiver front-ends. Currently, low-power designs focus on single-ended circuits. Differential circuits have significant advantages in anti-interference and signal transmission performance, but their power consumption is relatively high. Broadband, high-gain low-noise amplifiers often employ multi-stage amplification or complex circuit structures, occupying a large circuit area. This invention aims to realize a high-gain, broadband differential low-noise amplifier that simultaneously achieves a compact area and low power consumption design, suitable for millimeter-wave wireless communication front-end applications.

[0043] More specifically, the input matching transformer TF1 (first matching transformer) consists of two coils, a primary coil and a secondary coil, used to match the input RF signal and provide a suitable input signal for the subsequent first-stage differential amplifier.

[0044] Output matching transformer TF3 (second matching transformer): It consists of two coils and is used to match the output signal of the second-stage differential amplifier with the external load, so that the amplified RF signal is output from the RFout terminal.

[0045] Further, the first-stage differential amplifier includes: a first transistor M1, a second transistor M2, a first cross-neutralizing capacitor Cn1, and a second cross-neutralizing capacitor Cn2, wherein the first transistor M1 and the second transistor M2 are a differential pair, and the sources of the first transistor M1 and the second transistor M2 are connected to ground; the gate of the first transistor M1 is connected to the differential positive output of the first matching transformer TF1, which is the positive signal input of the first-stage differential amplifier; the gate of the second transistor M2 is connected to the differential negative output of the first matching transformer TF1, which is the negative signal input of the first-stage differential amplifier; the drain of the first transistor M1 is connected to the differential positive input of the intermediate matching transformer TF2, which is the positive signal output of the first-stage differential amplifier; the drain of the second transistor M2 is connected to the differential negative input of the intermediate matching transformer TF2, which is the negative signal output of the first-stage differential amplifier; the first cross-neutralizing capacitor Cn1 is connected to the gate of the first transistor M1 and the drain of the second transistor M2, and the second cross-neutralizing capacitor Cn2 is connected to the gate of the second transistor M2 and the drain of the first transistor M1.

[0046] Specifically, the first-stage differential amplifier Amp-1 includes transistors M1 and M2, capacitors Cn1 and Cn2, and related connecting lines. Among them, M1 and M2 are common-source differential pairs that amplify the signal, while Cn1 and Cn2 are cross-neutralizing capacitors that improve the stability and gain of the amplifier.

[0047] More specifically, the intermediate matching transformer TF2, also composed of two coils, serves to match and transmit signals between the first-stage differential amplifier and the intermediate resonant network (composed of L1, L2, and C2).

[0048] Furthermore, the intermediate resonant network includes: a first inductor L1, a second inductor L2, and a capacitor C2;

[0049] The first inductor L1 and the second inductor L2 are connected between the intermediate matching transformer and the second-stage differential amplifier. The input of the first inductor L1 is connected to the differential positive output of the intermediate matching transformer TF2, and the output of the first inductor L1 is connected to the positive terminal of the capacitor C2 and the positive signal input terminal of the second-stage differential amplifier. The input of the second inductor L2 is connected to the differential negative output of the intermediate matching transformer TF2, and the output of the second inductor L2 is connected to the negative terminal of the capacitor C2 and the negative signal input terminal of the second-stage differential amplifier.

[0050] Capacitor C2 is connected between two series inductors to form resonance with the parasitic capacitance of the second-stage differential amplifier. The positive terminal of capacitor C2 is connected to the output of the first inductor L1 and the positive signal input terminal of the second-stage differential amplifier; the negative terminal of capacitor C2 is connected to the output of the second inductor L2 and the negative signal input terminal of the second-stage differential amplifier.

[0051] Specifically, the intermediate resonant network consists of inductors L1 and L2 and capacitor C2, and is used to resonate the signal, improve the high-frequency response of the signal, and extend the operating bandwidth of the circuit.

[0052] Furthermore, the second-stage differential amplifier includes: a third transistor M3, a fourth transistor M4, a third cross-neutralizing capacitor Cn3, and a fourth cross-neutralizing capacitor Cn4. The third transistor M3 and the fourth transistor M4 are a differential pair, with their sources connected to ground. The gate of the third transistor M3 is connected to the output of the first inductor L1, serving as the positive signal input of the second-stage differential amplifier. The gate of the fourth transistor M4 is connected to the output of the second inductor L2, serving as the negative signal input of the second-stage differential amplifier. The drain of the third transistor M3 is connected to the differential positive input of the second matching transformer TF3, serving as the positive signal output of the second-stage differential amplifier. The drain of the fourth transistor M4 is connected to the differential negative input of the second matching transformer TF3, serving as the negative signal output of the second-stage differential amplifier. The third cross-neutralizing capacitor Cn3 connects the gate of the third transistor M3 and the drain of the fourth transistor M4, and the fourth cross-neutralizing capacitor Cn4 connects the gate of the fourth transistor M4 and the drain of the third transistor M3.

[0053] Specifically, the second-stage differential amplifier Amp-2 consists of transistors M3 and M4, capacitors Cn3 and Cn4, etc. Similar to Amp-1, M3 and M4 are the core amplification components, and Cn3 and Cn4 are cross-neutralizing capacitors.

[0054] Furthermore, the transistor has a gate width of 16 μm, a total gate width of 32 μm, a gate interdigitation length of 1 μm, and 16 interdigitations.

[0055] Furthermore, the first matching transformer, the intermediate matching transformer, and the second matching transformer are all on-chip integrated transformers, and the inductance values ​​of the primary and secondary coils of the on-chip integrated transformers are in the range of 160pH to 310pH.

[0056] Furthermore, the CMOS broadband low-noise amplifier also includes: a first parallel resonant capacitor C1, a second parallel resonant capacitor C2, and a third parallel resonant capacitor C3;

[0057] The first parallel resonant capacitor C1 is connected between the differential positive and negative output poles of the secondary coil of the first matching transformer;

[0058] The second parallel resonant capacitor C2 is connected between the output terminals of the first inductor L1 and the second inductor L2 of the intermediate resonant network.

[0059] The third parallel resonant capacitor C3 is connected between the differential positive and negative output poles of the primary coil of the second matching transformer.

[0060] Furthermore, the first-stage differential amplifier and the second-stage differential amplifier operate at a voltage of 1V, with a single-stage power consumption of 8mW, which is very low for a differential amplifier. Generally, low-power designs focus on single-ended amplifier circuits because a differential amplifier contains a pair of MOSFETs, and its power consumption is naturally twice that of a similar single-ended amplifier. However, differential amplifiers have significant advantages in terms of anti-interference and signal transmission performance.

[0061] The connection relationships between the structures in this embodiment are described in detail below with reference to the accompanying drawings:

[0062] The radio frequency input signal is input from the RFin terminal and first enters the input matching transformer TF1. The output terminal of TF1 is connected to the input terminal of the first-stage differential amplifier Amp-1.

[0063] The output of Amp-1 is connected to the input of the intermediate matching transformer TF2, and the output of TF2 is connected to the intermediate resonant network (L1, L2, C2).

[0064] The output of the intermediate resonant network is connected to the input of the second-stage differential amplifier Amp-2. The output of Amp-2 is connected to the input of the output matching transformer TF3. Finally, the amplified signal is output from the output terminal RFout of TF3.

[0065] The circuit structure and working process include:

[0066] Input matching stage: After the RF signal RFin is input, it passes through the input matching transformer TF1. TF1 performs impedance matching on the input signal, so that the signal can be input to the first-stage differential amplifier Amp-1 with low loss. At the same time, Vb1 provides bias voltage to Amp-1 through the coil tap of TF1, and C1 plays a certain matching resonance role.

[0067] First-stage amplification: The matched signal enters the first-stage differential amplifier Amp-1, where transistors M1 and M2 amplify the signal initially. Cn1 and Cn2, in conjunction with M1 and M2, suppress noise and improve stability while achieving amplification. VDD provides the operating power to Amp-1.

[0068] Intermediate Matching and Resonance Stage: After being amplified by the first stage, the signal is matched by the intermediate matching transformer TF2 and then enters the intermediate resonant network composed of L1, L2, and C2. This network performs resonant frequency selection on the signal, improving the high-frequency response and enhancing the bandwidth. The signal then passes through and is transmitted to the second-stage differential amplifier Amp-2, filtering out interference signals of other frequencies. Vb2 provides a bias voltage to Amp-2 through the coil tap of TF2.

[0069] Second-stage amplification: The signal, after resonant frequency selection, enters the second-stage differential amplifier Amp-2. Under the action of transistors M3 and M4, the signal is further amplified. Cn3 and Cn4 assist M3 and M4 to continue suppressing noise, ensuring signal amplification quality, and improving stability. VDD provides the operating power for Amp-2.

[0070] Output matching and output stage: The signal after the second stage of amplification enters the output matching transformer TF3. TF3 performs output impedance matching on the signal, so that the amplified RF signal can be output from the RFout terminal with high efficiency. C3 plays an auxiliary role in signal resonance matching.

[0071] To reduce the power consumption of the amplifier in this invention, the circuit and layout of the two-stage amplifier were optimized, such as... Figure 2 As shown, the main reason for choosing smaller MOS transistors (total gate width of a single MOS transistor is 32um) is that MOS transistors with smaller total gate widths also generate less power consumption.

[0072] Meanwhile, each amplifying MOS transistor (M1~M4) employs a structure of two MOS transistors with a gate width of 16um connected in parallel, resulting in a total gate width of 32um. The gate fork length of each individual MOS transistor is set to 1um, with 16 fork fingers. This layout allows for more even connection of signal lines to each gate fork finger, reducing signal loss due to parasitic resistance of the signal lines and lowering the power consumption of the MOS transistors.

[0073] The neutralizing capacitors Cn1~Cn4 of the differential amplifier are used to offset the parasitic capacitance Cgd between the gate and drain of the MOS transistor, reduce the negative feedback caused by the parasitic capacitance, and improve the gain of the differential amplifier.

[0074] Through simulation results comparison, the single-stage differential amplifier designed using this invention consumes 8mW when the operating voltage VDD=1V; while the traditional differential amplifier using larger MOSFETs (such as a total gate width of 64um) consumes 16.7mW under the same conditions; and the differential amplifier using a single MOSFET layout with a gate width of 32um consumes 11mW. This verifies the effectiveness of this design in reducing power consumption.

[0075] Because the MOSFETs in a differential amplifier have parasitic capacitance, resulting in a large imaginary part of impedance, a large transformer coil is needed to provide a large inductance to offset the imaginary capacitance and achieve impedance matching. To reduce the transformer coil inductance (inductance occupies a significant area, and reducing the inductance value can effectively reduce the circuit area), this invention incorporates parallel resonant capacitors C1 to C3. By connecting these capacitors in parallel with the MOSFET's parasitic capacitance, capacitive reactance is reduced. According to the formula, the larger the capacitance value, the smaller the corresponding capacitive reactance. parC represents the parasitic capacitance of a MOSFET. x This represents the parallel resonant capacitors C1 to C3. This reduces the inductor area.

[0076] The two inductors L1 and L2 connected in series after the interstage transformer TF2 are used to enhance the bandwidth of the low-noise amplifier. The series inductors can divide the parasitic capacitance between the preceding and following stages of the circuit, so that the capacitance that needs to be charged when the signal current is input is reduced, thereby reducing the rise time and expanding the bandwidth.

[0077] We conducted simulation comparisons of the overall low-noise amplifier circuits with and without L1 and L2, as follows: Figure 3 As shown,

[0078] The low-noise amplifier designed in this embodiment underwent simulations of its S-parameters and noise figure, and the results are as follows: Figure 4 As shown, the maximum gain reaches 16.5dB, the 3-dB bandwidth reaches 12 GHz (covering 22-34 GHz), and the minimum noise figure is 3dB. The power consumption is 16mW (operating voltage VDD=1V, the overall circuit includes two stages of differential amplifiers, each stage 8mW).

[0079] The completed CMOS low-noise amplifier has a core area of ​​only 0.45 × 0.17 mm. 2 (0.076mm) 2 ),like Figure 5 As shown, it has a very compact size, while maintaining excellent performance across the board.

[0080] The specific implementation parameters of the low-noise amplifier designed in this embodiment are as follows:

[0081] The two-stage differential amplifier has the MOSFET parameters as described above; the neutralizing capacitors Cn1-Cn4 are 18fF.

[0082] The coil inductance values ​​of the matching transformers are as follows: TF1: main coil 260pH, secondary coil 310pH; TF2: main coil 260pH, secondary coil 240pH; TF3: main coil 310pH, secondary coil 160pH.

[0083] The values ​​of the parallel resonant capacitors are C1=80fF, C2=90fF, and C3=40fF;

[0084] The series inductors L1 and L2, which enhance bandwidth, are set to 100 pH.

[0085] The above are merely preferred embodiments of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A compact, low-power CMOS broadband low-noise amplifier, characterized in that, include: First matching transformer, first stage differential amplifier, intermediate matching transformer, intermediate resonant network, second stage differential amplifier and second matching transformer; The first matching transformer is used to receive radio frequency input signals and achieve impedance matching; The first-stage differential amplifier is used to amplify the radio frequency input signal in the first stage. The intermediate matching transformer is used to transmit the first-stage amplified radio frequency signal; The intermediate resonant network is used to perform resonant processing on the amplified radio frequency signal. The second-stage differential amplifier is used to amplify the resonant radio frequency signal in the second stage. The second matching transformer is used to achieve output impedance matching and output the second-stage amplified radio frequency signal.

2. The compact, low-power CMOS broadband low-noise amplifier according to claim 1, characterized in that, The first-stage differential amplifier includes: a first transistor M1, a second transistor M2, a first cross-neutralizing capacitor Cn1, and a second cross-neutralizing capacitor Cn2. The first transistor M1 and the second transistor M2 are a differential pair, with their sources connected to ground. The gate of the first transistor M1 is connected to the differential positive output of the first matching transformer TF1, serving as the positive signal input of the first-stage differential amplifier. The gate of the second transistor M2 is connected to the differential negative output of the first matching transformer TF1, serving as the negative signal input of the first-stage differential amplifier. The drain of the first transistor M1 is connected to the differential positive input of the intermediate matching transformer TF2, serving as the positive signal output of the first-stage differential amplifier. The drain of the second transistor M2 is connected to the differential negative input of the intermediate matching transformer TF2, serving as the negative signal output of the first-stage differential amplifier. The first cross-neutralizing capacitor Cn1 is connected to the gate of the first transistor M1 and the drain of the second transistor M2, and the second cross-neutralizing capacitor Cn2 is connected to the gate of the second transistor M2 and the drain of the first transistor M1.

3. The compact, low-power CMOS broadband low-noise amplifier according to claim 1, characterized in that, The intermediate resonant network includes: a first inductor L1, a second inductor L2, and a capacitor C2; The first inductor L1 and the second inductor L2 are connected between the intermediate matching transformer and the second-stage differential amplifier. The input of the first inductor L1 is connected to the differential positive output of the intermediate matching transformer TF2, and the output of the first inductor L1 is connected to the positive terminal of the capacitor C2 and the positive signal input terminal of the second-stage differential amplifier. The input of the second inductor L2 is connected to the differential negative output of the intermediate matching transformer TF2, and the output of the second inductor L2 is connected to the negative terminal of the capacitor C2 and the negative signal input terminal of the second-stage differential amplifier. The capacitor C2 is connected between two series inductors to form a resonance with the parasitic capacitance of the second-stage differential amplifier. The positive terminal of the capacitor C2 is connected to the output of the first inductor L1 and the positive signal input terminal of the second-stage differential amplifier; the negative terminal of the capacitor C2 is connected to the output of the second inductor L2 and the negative signal input terminal of the second-stage differential amplifier.

4. The compact, low-power CMOS broadband low-noise amplifier according to claim 1, characterized in that, The second-stage differential amplifier includes: a third transistor M3, a fourth transistor M4, a third cross-neutralizing capacitor Cn3, and a fourth cross-neutralizing capacitor Cn4. The third transistor M3 and the fourth transistor M4 are a differential pair, with their sources connected to ground. The gate of the third transistor M3 is connected to the output of the first inductor L1, serving as the positive signal input of the second-stage differential amplifier. The gate of the fourth transistor M4 is connected to the output of the second inductor L2, serving as the negative signal input of the second-stage differential amplifier. The drain of the third transistor M3 is connected to the differential positive input of the second matching transformer TF3, serving as the positive signal output of the second-stage differential amplifier. The drain of the fourth transistor M4 is connected to the differential negative input of the second matching transformer TF3, serving as the negative signal output of the second-stage differential amplifier. The third cross-neutralizing capacitor Cn3 connects the gate of the third transistor M3 and the drain of the fourth transistor M4, and the fourth cross-neutralizing capacitor Cn4 connects the gate of the fourth transistor M4 and the drain of the third transistor M3.

5. A compact, low-power CMOS broadband low-noise amplifier according to claim 2 or 4, characterized in that, The transistor has a gate width of 16μm, a total gate width of 32μm, a gate interdigitation length of 1μm, and 16 interdigitations.

6. A compact, low-power CMOS broadband low-noise amplifier according to claim 1, characterized in that, The first matching transformer, the intermediate matching transformer, and the second matching transformer are all on-chip integrated transformers, and the inductance values ​​of the primary and secondary coils of the on-chip integrated transformers are in the range of 160pH to 310pH.

7. A compact, low-power CMOS broadband low-noise amplifier according to claim 1, characterized in that, The CMOS broadband low-noise amplifier also includes: a first parallel resonant capacitor C1, a second parallel resonant capacitor C2, and a third parallel resonant capacitor C3; The first parallel resonant capacitor C1 is connected between the differential positive and negative output poles of the secondary coil of the first matching transformer; The second parallel resonant capacitor C2 is connected between the output terminals of the first inductor L1 and the second inductor L2 of the intermediate resonant network. The third parallel resonant capacitor C3 is connected between the differential positive and negative output poles of the primary coil of the second matching transformer.

8. A compact, low-power CMOS broadband low-noise amplifier according to claim 1, characterized in that, The first-stage differential amplifier and the second-stage differential amplifier operate at 1V, and the power consumption of a single stage is 8mW.

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