High-frequency broadband low-noise amplifier of low-voltage CMOS (complementary metal oxide semiconductor) process

Abstract

The invention discloses a high-frequency broadband low-noise amplifier of a low-voltage CMOS (complementary metal oxide semiconductor) process, and belongs to the field of radio frequency integrated circuits. The amplifier adopts a four-stage cascade structure and comprises two stages of single-ended common-source amplifiers and two stages of differential common-source amplifiers. An adjustable matching network is arranged between the single-end amplification stage and the differential amplification stage, and broadband impedance matching is achieved through a multi-tap inductor and a switched capacitor array. The single-ended amplifier adopts a transistor structure with an MOM capacitor array and an isolating ring to reduce noise. And the differential amplifier adopts an active MOS (Metal Oxide Semiconductor) tube neutralizing capacitor and a source electrode adjustable inductor, so that the bandwidth is effectively expanded and the common-mode interference is inhibited. According to the invention, high gain, low noise and broadband characteristics are realized under low power supply voltage, and the antenna is suitable for millimeter wave communication and a radar receiving front end.

Description

Technical Field

[0001] This invention belongs to the field of radio frequency integrated circuits, and particularly relates to a high-frequency broadband low-noise amplifier using low-voltage CMOS technology. Background Technology

[0002] The rapid development of E-band communication (60-64 GHz) and W-band autonomous driving radar (76-81 GHz) technologies has placed higher performance demands on low-noise amplifiers (LNAs), a key component of millimeter-wave transceiver front-ends. LNAs need to achieve high gain, low noise, and wide bandwidth simultaneously at high-frequency millimeter waves, while also being compatible with low-voltage digital processes.

[0003] Currently, CMOS technology has become the mainstream choice for realizing millimeter-wave LNAs due to its high integration and low cost. With advancements in process technology, the standard power supply voltage for 22nm / 28nm CMOS processes has dropped to 0.8-0.9V, significantly lower than the 1.2-3.3V of traditional processes. This reduction in power supply voltage leads to a significant decrease in the output swing of MOSFETs, resulting in a gain of single-stage common-source amplifiers generally below 6dB in the 60GHz band, a decrease of more than 30% compared to the 28GHz band. This presents a significant challenge to designing high-gain, low-noise amplifiers under low-voltage, high-frequency millimeter-wave conditions.

[0004] Existing technologies, such as patent CN111371412A, disclose a millimeter-wave broadband low-noise amplifier based on a 55nm CMOS process, with an operating voltage of 1V. If its circuit structure is directly transplanted to a 22 / 28nm low-voltage process, its performance will significantly deteriorate due to the further reduction in operating and bias voltages, failing to meet system requirements. Therefore, there is an urgent need for a low-noise amplifier solution specifically optimized for low-voltage, high-frequency millimeter-wave applications. Summary of the Invention

[0005] This invention proposes a high-frequency broadband low-noise amplifier using low-voltage CMOS technology to solve the problems existing in the prior art.

[0006] To achieve the above objectives, the present invention provides a high-frequency broadband low-noise amplifier using a low-voltage CMOS process, comprising: The input matching inductor has one end connected to the RF input port and the other end connected to the input DC blocking capacitor. The other end of the input DC blocking capacitor is connected to the input terminal of the first-stage single-ended amplifier; The first drain inductor has one end connected to the output of the first stage single-ended amplifier and the other end connected to the interstage matching inductor. The other end of the interstage matching inductor is connected to the input terminal of the second-stage single-ended amplifier; The second drain inductor has one end connected to the output of the second stage single-ended amplifier and the other end connected to the primary coil of the transformer balun. The transformer balun has a first adjustable resonant capacitor and a second adjustable resonant capacitor connected in parallel across its secondary coil. The two ends of the secondary coil are also connected to the differential input terminal of the first-stage differential amplifier. An interstage matching transformer, the primary coil of which is connected to the differential output terminal of the first stage differential amplifier, and the secondary coil of which is connected to the differential input terminal of the second stage differential amplifier; The output matching transformer has its primary coil connected to the differential output terminal of the second-stage differential amplifier, and its secondary coil connected to the differential RF output port.

[0007] Optionally, the first-stage single-ended amplifier may further include a gate input inductor and a source feedback inductor.

[0008] Optionally, the second drain inductor is a multi-tap inductor, including a first sub-inductor, a second sub-inductor, and a third sub-inductor connected in series.

[0009] Optionally, the multi-tap inductor is provided with taps selectable by a first switch and a second switch.

[0010] Optionally, the first adjustable resonant capacitor and the second adjustable resonant capacitor are switched capacitors.

[0011] Optionally, both the first-stage differential amplifier and the second-stage differential amplifier include differential pair transistors.

[0012] Optionally, the first-stage differential amplifier and the second-stage differential amplifier further include a neutralizing capacitor transistor, the gate and drain of which are respectively connected to the gate and drain of the differential pair transistor.

[0013] Optionally, the first-stage differential amplifier and the second-stage differential amplifier further include an adjustable source inductor network connected in series with the source of the differential pair transistors.

[0014] Optionally, the adjustable source inductor network includes a first inductor and a second inductor, wherein the first inductor and the second inductor are adjustable inductors selected by a third switch and a fourth switch.

[0015] Optionally, an MOM capacitor array and an isolation ring are disposed around the first transistor in the first-stage single-ended amplifier and the second transistor in the second-stage single-ended amplifier.

[0016] Compared with the prior art, the present invention has the following advantages and technical effects: This invention's low-noise amplifier achieves synergistic optimization of high gain, low noise, and wide bandwidth under low supply voltage conditions through a hybrid architecture employing two cascaded single-ended and two differential amplifier stages. The single-ended input stage effectively reduces overall circuit noise and facilitates direct antenna connection, while the subsequent differential stage significantly enhances gain and suppresses common-mode interference. An innovative adjustable matching network effectively extends the amplifier's operating bandwidth by dynamically adjusting impedance. For the transistors themselves, the introduction of substrate noise absorption and isolation structures improves the high-frequency performance of individual transistors; active neutralization and source-adjustable inductor technology in the differential stage effectively overcome the limitations of parasitic capacitance and common-mode interference on bandwidth and stability. The overall circuit structure is compact and fully compatible with advanced low-voltage CMOS processes, making it ideal for integrated receiver front-ends in high-performance millimeter-wave wireless communication and radar systems. Attached Figure Description

[0017] The accompanying drawings, which form part of this application, are used to provide a further understanding of this application. The illustrative embodiments and descriptions of this application are used to explain this application and do not constitute an undue limitation of this application. In the drawings: Figure 1 This is a schematic diagram of the overall circuit of the low-noise amplifier according to an embodiment of the present invention.

[0018] Figure 2 This is a schematic diagram of the layout of a single-ended MOS common-source amplifier transistor with an MOM capacitor array and an isolation ring in an embodiment of the present invention.

[0019] Figure 3 This is a simulation comparison of the gain and noise of the MOS single-ended common-source amplifier before and after the improvement in this embodiment of the invention.

[0020] Figure 4 This is a schematic diagram of the adjustable matching network between the single-ended amplification stage and the differential amplification stage in an embodiment of the present invention.

[0021] Figure 5 This is a schematic diagram of the circuit design of the differential amplifier stage in an embodiment of the present invention.

[0022] Figure 6 The simulation results of the gain S21 and noise figure NF of the low-noise amplifier designed for an embodiment of the present invention are shown in the figure. Detailed Implementation

[0023] It should be noted that, unless otherwise specified, the embodiments and features described in this application can be combined with each other. This application will now be described in detail with reference to the accompanying drawings and embodiments.

[0024] It should be noted that the steps shown in the flowchart in the accompanying drawings can be executed in a computer system such as a set of computer-executable instructions, and although a logical order is shown in the flowchart, in some cases the steps shown or described may be executed in a different order than that shown here.

[0025] Example 1 like Figure 1 As shown, this embodiment provides a high-frequency broadband low-noise amplifier using a low-voltage CMOS process, comprising: Input matching inductor L1, one end of which is connected to the RF input port RF in The other end is connected to the input DC blocking capacitor C1; The other end of the input DC blocking capacitor C1 is connected to the input terminal of the first-stage single-ended amplifier Amp-1; The first drain inductor L3 has one end connected to the output of the first stage single-ended amplifier Amp-1, and the other end connected to the interstage matching inductor L5. The other end of the interstage matching inductor L5 is connected to the input terminal of the second-stage single-ended amplifier Amp-2; The second drain inductor L6 has one end connected to the output of the second stage single-ended amplifier Amp-2, and the other end connected to the primary coil of the transformer balun. The transformer balun has a first adjustable resonant capacitor C2 and a second adjustable resonant capacitor C3 connected in parallel across the two ends of its secondary coil L7. The two ends of the secondary coil L7 are also connected to the differential input terminal of the first-stage differential amplifier DA-1. Interstage matching transformer TF inter Its primary coil is connected to the differential output terminal of the first-stage differential amplifier DA-1, and its secondary coil is connected to the differential input terminal of the second-stage differential amplifier DA-2. Output matching transformer TF out Its primary coil is connected to the differential output terminal of the second-stage differential amplifier DA-2, and its secondary coil is connected to the differential RF output port.

[0026] Figure 1In this amplifier, the first-stage single-ended amplifier Amp-1 and the second-stage single-ended amplifier Amp-2 are first-stage and second-stage single-ended common-source amplifiers, respectively. The first amplifying transistor M1 and the second amplifying transistor M2 are MOS transistors used in the single-ended common-source amplifiers. The first-stage differential amplifier DA-1 and the second-stage differential amplifier DA-2 are third-stage and fourth-stage differential common-source amplifiers. The input matching inductor L1 and the gate input inductor L2 are the input matching inductors of the amplifiers, and the input DC blocking capacitor C1 is the input DC blocking capacitor. The first drain inductor L3 and the inter-stage matching inductor L5 form the matching inductor coil from the output of the first-stage single-ended amplifier Amp-1 to the input of the second-stage single-ended amplifier Amp-2. The source feedback inductor L4 is the source feedback inductor of the first-stage single-ended amplifier Amp-1. The second drain inductor L6 includes the first sub-inductor L... 6_1 Second sub-inductor L 6_2 Third sub-inductor L 6_3 The secondary inductor L7 of the three-segment coil and interstage matching transformer balun is a single-ended to differential matching transformer balun connecting the output of the second-stage single-ended amplifier Amp-2 to the input of the first-stage differential amplifier DA-1; the first adjustable resonant capacitor C2 and the second adjustable resonant capacitor C3 are matching resonant switching capacitors connecting the output of the second-stage single-ended amplifier Amp-2 to the input of the first-stage differential amplifier DA-1; the interstage matching transformer TF inter It is the interstage matching transformer for the first-stage differential amplifier DA-1 and the second-stage differential amplifier DA-2, and the output matching transformer TF. out It is the output matching transformer of the second-stage differential amplifier DA-2, which outputs the differential signal to the subsequent circuitry of the receiving front end; RF input port RF in and the non-inverting output terminal RF + out Inverting output terminal RF - out These are the input and output signal interfaces of the amplifier, respectively; power supply terminal V. DD The operating voltage and bias voltage V of each amplifier stage. b The bias voltage for each stage of the amplifier; the first switch V P0 Second switch V P1 The switching control voltage for segmenting the second drain inductor L6 coil is selected; the third switch V P2 Fourth switch V P3 It is a switching control voltage that selects whether the first adjustable resonant capacitor C2 and the second adjustable resonant capacitor C3 are turned on.

[0027] The amplifier adopts a four-stage cascaded architecture. The first two stages are single-ended common-source amplifiers, which are used to achieve low noise input and easy connection with single-ended antennas. The last two stages are differential common-source amplifiers, which are used to provide high gain and effectively suppress common-mode interference and spurious emissions.

[0028] Using a single-transistor common-source amplifier structure as the input stage of the first two stages can reduce input noise, because a large part of the noise comes from the carrier movement of the MOSFET itself. The number of MOSFETs in a single-transistor amplifier is half that of a differential pair amplifier. Reducing the number of MOSFETs can significantly reduce circuit noise. Using a single-transistor amplifier as the input stage facilitates connection to a receiving antenna, as the antenna is a single-ended component that can be directly connected to the single-transistor amplifier, reducing losses. Connecting to a differential pair amplifier, however, requires a single-ended to differential matching circuit, increasing losses, leading to decreased gain and increased noise. Amplifier design always requires impedance matching to achieve optimal gain or noise performance within the target frequency range. The optimal noise matching impedance and the optimal gain matching impedance of an amplifier often differ significantly, requiring a trade-off in the design. In this invention, the first-stage single-transistor amplifier primarily considers noise matching to achieve low input noise, while the second-stage single-transistor amplifier balances gain and noise, ensuring low noise while providing a certain level of gain. Cascading the two single-transistor amplifiers simplifies the matching circuit design and achieves lower losses. According to the noise formula for cascaded circuits: ; In the formula, F represents the total noise, F1~F n These represent the individual noise levels of each amplifier stage, g1~g n These represent the gain of each amplifier stage; It can be concluded that the first-stage noise F1 has the greatest impact on the system noise F, while the noise F of subsequent stages of the circuit decreases. x The impact on system F gradually decreases, and the larger the gains g1 and g2 of the first and second stages, the smaller the impact of noise from subsequent stages on the overall circuit. Therefore, the noise and gain design of the first two amplifier stages is crucial to the overall circuit performance.

[0029] Differential amplifiers, as a 3-4 stage amplification structure, can effectively improve circuit gain and suppress common-mode spurious emissions. The design of the 3rd and 4th stage amplifiers mainly considers gain improvement to ensure that the overall circuit has sufficient gain. Differential amplifiers have advantages in terms of gain, and the differential circuit structure can suppress common-mode spurious emissions and improve circuit stability.

[0030] This low-noise amplifier consists of an input matching inductor L1, an input DC blocking capacitor C1, a first-stage single-ended amplifier Amp-1, a single-ended matching inductor L5, a second-stage single-ended amplifier Amp-2, an interstage matching transformer balun consisting of a second drain inductor L6 and a secondary coil L7, a first adjustable resonant capacitor C2 and a second adjustable resonant capacitor C3, a first-stage differential amplifier DA-1, and a differential amplifier matching transformer TF. interSecond-stage differential amplifier DA-2, output matching transformer TF out It consists of several parts. Radio frequency signals originate from RF... in Terminal input, after amplification, from RF + out and RF － out Output.

[0031] The structural composition of each component is as follows: Input matching and DC blocking unit: Composed of input matching inductor L1 and input DC blocking capacitor C1, it realizes input signal impedance matching and DC isolation; The first-stage single-ended amplifier Amp-1 includes a first amplifying transistor M1, a gate input inductor L2, a first drain inductor L3, and a source feedback inductor L4, which completes the pre-amplification of the signal into a single-ended low-noise amplifier. Matching inductors between single-ended amplifier stages: the first drain inductor L3 and the interstage matching inductor L5 complete the transmission of the Amp-1 to Amp-2 signal; The second-stage single-ended amplifier Amp-2 includes the second amplifying transistor M2 and the second drain inductor L6, completing the second-stage single-ended low-noise amplification of the signal. Single-ended to differential conversion and resonant unit: It consists of an interstage matching transformer balun composed of a second drain inductor L6 and the secondary inductor L7 of the interstage matching transformer balun, as well as a first adjustable resonant capacitor C2 and a second adjustable resonant capacitor C3, to realize the conversion of single-ended signal to differential signal and adjust the matching according to the frequency. Differential amplifier and interstage matching transformer: including the first-stage differential amplifier DA-1 and the interstage matching transformer TF inter The second-stage differential amplifier DA-2 achieves efficient amplification of differential signals and inter-stage impedance matching; Output matching unit: Output matching transformer TF out It consists of two coils, a primary coil and a secondary coil, which are matched to the differential amplified signal and the output load, and finally output from the non-inverting RF terminal. + out Inverting output terminal RF - out Output differential signal.

[0032] The connections between the various structures are as follows: RF input signal from RF in The input first enters the input matching inductor L1 and the input DC blocking capacitor C1. The output of the input DC blocking capacitor C1 is connected to the input terminal of the first-stage single-ended amplifier Amp-1.

[0033] The output signal of the first-stage single-ended amplifier Amp-1 is coupled to the input of the second-stage single-ended amplifier Amp-2 through the first drain inductor L3 and the interstage matching inductor L5. The output of the second-stage single-ended amplifier Amp-2 is connected to the differential input of the first-stage differential amplifier DA-1 through a single-ended to differential conversion and resonant unit consisting of the second drain inductor L6, the secondary inductor L7 of the interstage matching transformer balun, the first adjustable resonant capacitor C2, and the second adjustable resonant capacitor C3.

[0034] The output of the first-stage differential amplifier DA-1 is connected to the interstage matching transformer TF. inter Connect to the input of the second-stage differential amplifier DA-2. Finally, the output signal of the second-stage differential amplifier DA-2 passes through the output matching transformer TF. out Connect to the non-inverting output terminal RF + out and inverting output terminal RF - out Port output.

[0035] The circuit operation process includes: Input matching and isolation stage; Radio frequency signals from the radio frequency input port RF in The input first enters the input matching inductor L1. Based on the inductor impedance characteristics, the input matching inductor L1 matches the impedance of the external signal source with the input impedance of the subsequent first-stage single-ended amplifier Amp-1, reducing signal reflection loss and ensuring efficient signal input.

[0036] The signal matched by the input matching inductor L1 enters the input DC blocking capacitor C1. The input DC blocking capacitor C1 uses the characteristic of "passing AC and blocking DC" to block the DC signal in the subsequent circuit from flowing back into the signal source, while transmitting the radio frequency AC signal without loss, and finally transmitting the pure AC signal to the input terminal of the first stage single-ended amplifier Amp-1.

[0037] Single-ended amplification stage; First-stage single-ended amplifier: The first-stage single-ended amplifier Amp-1 is biased at voltage V. b With power supply V DD When operating under power supply, the weak signal transmitted by the input DC blocking capacitor C1 is amplified in the first stage; the gate input inductor L2 is connected in parallel to the power supply terminal of the first-stage single-ended amplifier Amp-1 to filter out high-frequency noise at the power supply terminal, stabilize the amplifier operating point, and ensure the signal-to-noise ratio of the amplified signal.

[0038] Interstage matching and second-stage single-ended amplification: The signal output from the first-stage single-ended amplifier Amp-1 enters the first drain inductor L3. The first drain inductor L3 and the interstage matching inductor L5 are used to match the output impedance of the first-stage single-ended amplifier Amp-1 with the input impedance of the second-stage single-ended amplifier Amp-2, reducing signal attenuation during interstage transmission. The matched signal then enters the second-stage single-ended amplifier Amp-2. The second-stage single-ended amplifier Amp-2 is biased by voltage V... b With power supply V DD When powered, it performs a second-stage amplification of the signal to further increase the signal amplitude.

[0039] Single-ended to differential conversion and resonant matching; The signal input after the second-stage single-ended amplification is supplied by an inter-stage matching transformer balun, which consists of the second drain inductor L6 and the secondary inductor L7 of the inter-stage matching transformer balun. The inter-stage matching transformer balun utilizes the principle of mutual inductance coupling to convert the single-ended signal into two differential signals with a 180° phase difference, while simultaneously matching the single-ended output impedance and the differential input impedance. The second drain inductor L6 consists of three segments of the first sub-inductor L... 6_1 Second sub-inductor L 6_2 and the third sub-inductor L 6_3 It is connected in series, and is connected through the first switch V P0 Second switch V P1 Segmented selection is performed. The differential signal enters the first adjustable resonant capacitor C2 and the second adjustable resonant capacitor C3 respectively. The first adjustable resonant capacitor C2 and the second adjustable resonant capacitor C3 form an LC resonant circuit with the balun coil inductor. By selecting the switching on and off of the first adjustable resonant capacitor C2 and the second adjustable resonant capacitor C3, different parallel capacitance values ​​can be obtained. Together with the segmented selection of the second drain inductor L6, inter-stage impedance matching can be performed according to different operating frequency bands, thereby improving the operating bandwidth of the circuit.

[0040] Differential amplification stage; First-stage differential amplifier: The first-stage differential amplifier DA-1 is biased at voltage V. b With power supply V DD Under power supply, the differential signal after resonance is amplified by the first stage to improve the signal gain; the differential architecture itself has the advantage of suppressing common-mode noise.

[0041] Interstage matching and second-stage differential amplification: The differential signal output from the first-stage differential amplifier DA-1 enters the interstage matching transformer TF. inter ; through interstage matching transformer TF interThe winding turns ratio is designed to match the output impedance of the first-stage differential amplifier DA-1 with the input impedance of the second-stage differential amplifier DA-2, thus solving the signal loss problem caused by impedance mismatch between differential signal stages. The matched differential signal enters the second-stage differential amplifier DA-2, which performs second-stage differential amplification under stable power supply, so that the signal reaches the gain requirement.

[0042] Signal output stage; The signal after the second-stage differential amplification enters the output matching transformer TF. out Output matching transformer TF out Based on the output impedance of the second-stage differential amplifier DA-2 and the external load impedance, the output matching transformer TF... out The winding impedance matching design eliminates signal reflection at the output end, ensuring that the amplified differential signal is efficiently transmitted to the load.

[0043] Finally, after passing through the output matching transformer TF out The matched differential RF signals are respectively output from the non-inverting RF terminal. + out Inverting output terminal RF - out Output, completing the entire low-noise amplification process.

[0044] This embodiment of the single-transistor common-source amplifier differs from traditional single-transistor designs that only optimize size. Through substrate isolation and synergistic device structure, it improves the noise and gain of the MOSFET at low voltages. (See attached diagram) Figure 2 As shown, a MOM (Metal-on-Metal) oxide-metal-on-metal structure capacitor array is added around the first amplifying transistor M1 and the second amplifying transistor M2 to absorb substrate high-frequency noise greater than 60GHz, and an isolation ring is added to block the lateral propagation of noise. Simultaneously, the MOS transistor size is optimized, reducing the gate width and increasing the gate fork index. Through these improvements, the simulation results of the common-source single transistor's amplification performance are as follows: Figure 3 As shown, in the 60-80GHz range, the maximum gain Gmax and minimum noise Fmin are improved by an average of approximately 0.2dB and 0.3dB, respectively, before and after the improvement.

[0045] Between the second-stage single-tube amplifier Amp-2 and the first-stage differential amplifier DA-1, an adjustable interstage matching network is designed using a "multi-tap transformer and switched capacitor array" structure, as shown in the attached diagram. Figure 4 As shown. The primary coil and second drain inductance L6 at the output of the single transistor are connected to a switch V with three taps. P0 and V P1 Switching corresponds to the first sub-inductance L of the 3-segment coil. 6_1 Second sub-inductor L 6_2 and the third sub-inductor L 6_3It adapts to impedances across different frequency bands. Two switchable resonant capacitors, the first adjustable resonant capacitor C2 and the second adjustable resonant capacitor C3, are connected in parallel after the secondary inductor L7 of the interstage matching transformer balun in the secondary coil. This allows for adjustment and compensation based on the high-frequency parasitic capacitance of the amplifier at different frequencies, improving the signal transmission efficiency and operating bandwidth of the interstage matching network.

[0046] The differential amplifier stages of this invention, specifically the first stage differential amplifier DA-1 and the second stage differential amplifier DA-2, use active MOS transistors and neutralizing capacitors instead of traditional fixed metal plate capacitors, and incorporate adjustable inductors connected in series with the source to suppress current coupling of common-mode signals, as shown in the attached diagram. Figure 5 As shown. The differential pair transistor Mx is an amplified common-source differential pair MOS transistor, and the neutralizing capacitor transistor Mn is an active MOS transistor used as a neutralizing capacitor; the adjustable source inductor network is a source-series adjustable inductor, including the first series inductor L. s1 Second inductor L s2 and switch V P3 and V P4 The differential signal is input from the Vin+ and Vin- ports, amplified, and output from the Vout+ and Vout- ports. In a common-source differential amplifier circuit, the gate-drain and gate-source parasitic capacitances of CMOS devices become significant in the EW band, worsening the Miller effect and reducing the bandwidth and gain of the common-source differential amplifier circuit. Conventional fixed metal neutralizing capacitors can only cancel parasitic capacitance at a single frequency point, and their effect is poor over a wide frequency range. However, using active MOSFETs instead of fixed metal capacitors allows their gate-drain capacitance to cancel out the parasitic capacitance of the differential amplifier transistor, making it effective over a wide frequency range.

[0047] The parameters of the low-voltage, high-frequency, low-noise amplifier designed in this embodiment are as follows: the MOS transistors M1, M2, and Mx of the two-stage single-ended and two-stage differential amplifiers use a gate width of 32µm; the active neutralizing capacitor MOS transistor Mn of the two-stage differential amplifier uses a PMOS with a gate width of 16µm; the values ​​of the inductors in the circuit are: L1=120pH, L2=60pH, L3=150pH, L4=80pH, L5=240pH, L6=180pH (L 6_1 =40pH, L 6_2 =60 pH, L 6_3 =80pH), L7=300pH; The values ​​of the capacitors in the circuit are: C1=500fF, C2=50fF, C3=100fF; The values ​​of the transformer coil in the circuit are: TF inter The primary coil is at 260 pH, and the secondary coil is at 220 pH; TF out The main coil is at 240 pH, and the secondary coil is at 140 pH. This embodiment also includes simulations of S-parameters and noise figure, the results of which are attached. Figure 6 As shown, the maximum gain reaches 19.2dB, the 3-dB bandwidth reaches 21GHz (covering 62-83GHz), and the noise figure is 4.6-5.8dB in the 62-83GHz range. Operating voltage V DD =0.8V, bias voltage V b =0.4V. Under low-voltage process conditions, performance essentially the same as low-noise amplifiers designed with high-voltage processes is achieved.

[0048] The above are merely preferred embodiments of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A high-frequency broadband low-noise amplifier using low-voltage CMOS technology, characterized in that, include: The input matching inductor (L1) has one end connected to the RF input port (RF). in The other end is connected to the input DC blocking capacitor (C1); The other end of the input DC blocking capacitor (C1) is connected to the input terminal of the first-stage single-ended amplifier (Amp-1); The first drain inductor (L3) has one end connected to the output of the first stage single-ended amplifier (Amp-1) and the other end connected to the interstage matching inductor (L5). The other end of the interstage matching inductor (L5) is connected to the input of the second-stage single-ended amplifier (Amp-2); The second drain inductor (L6) has one end connected to the output of the second stage single-ended amplifier (Amp-2) and the other end connected to the primary coil of the transformer balun. The transformer balun has a first adjustable resonant capacitor (C2) and a second adjustable resonant capacitor (C3) connected in parallel across its secondary coil (L7). The two ends of its secondary coil (L7) are also connected to the differential input terminal of the first-stage differential amplifier (DA-1). Interstage matching transformer (TF) inter Its primary coil is connected to the differential output terminal of the first stage differential amplifier (DA-1), and its secondary coil is connected to the differential input terminal of the second stage differential amplifier (DA-2). Output matching transformer (TF) out Its primary coil is connected to the differential output of the second-stage differential amplifier (DA-2), and its secondary coil is connected to the differential RF output port.

2. The low-noise amplifier according to claim 1, characterized in that, The first-stage single-ended amplifier (Amp-1) also includes a gate input inductor (L2) and a source feedback inductor (L4).

3. The low-noise amplifier according to claim 1, characterized in that, The second drain inductor (L6) is a multi-tap inductor, including a first sub-inductor (L) connected in series. 6_1 ), second sub-inductor (L 6_2 ) and the third sub-inductor (L 6_3 ).

4. The low-noise amplifier according to claim 3, characterized in that, The multi-tap inductor is provided with a first switch (V) P0 ) and the second switch (V P1 Selected tap.

5. The low-noise amplifier according to claim 1, characterized in that, The first adjustable resonant capacitor (C2) and the second adjustable resonant capacitor (C3) are switched capacitors.

6. The low-noise amplifier according to claim 1, characterized in that, Both the first-stage differential amplifier (DA-1) and the second-stage differential amplifier (DA-2) include differential pair transistors (Mx).

7. The low-noise amplifier according to claim 6, characterized in that, The first-stage differential amplifier (DA-1) and the second-stage differential amplifier (DA-2) further include a neutralizing capacitor transistor (Mn), the gate and drain of which are respectively connected to the gate and drain of the differential pair transistor (Mx).

8. The low-noise amplifier according to claim 6, characterized in that, The first-stage differential amplifier (DA-1) and the second-stage differential amplifier (DA-2) also include an adjustable source inductor network connected in series with the source of the differential pair transistor (Mx).

9. The low-noise amplifier according to claim 8, characterized in that, The adjustable source inductor network includes a first inductor (L s1 ) and second inductor (L s2 ), the first inductor (L s1 ) and the second inductor (L s2 ) for through the third switch (V P3 ) and the fourth switch (V P4 The selected adjustable inductor.

10. The low-noise amplifier according to claim 1, characterized in that, A MOM capacitor array and an isolation ring are arranged around the first transistor (M1) in the first stage single-ended amplifier (Amp-1) and the second transistor (M2) in the second stage single-ended amplifier (Amp-2).

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