SAR ADC-based sampling and conversion methods, chips, and devices

By monitoring the operation of the internal power circuit of the chip and delaying the sampling and conversion time, the accuracy and reliability problems of SAR ADC under noise interference are solved, achieving higher conversion accuracy and system stability, which is suitable for mobile terminals, automotive electronics and communication equipment.

CN121567126BActive Publication Date: 2026-06-02SHANGHAI CHIPANALOG MICROELECTRONICS LTD
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Patent Information

Application Number
CN202511716387.5
Authority / Receiving Office
CN · China
Patent Type
Patents(China)
Current Assignee / Owner
Filing Date
2025-11-21
Publication Date
2026-06-02
Estimated Expiration
2045-11-21

AI Technical Summary

Technical Problem

Noise and current transient interference generated by high-power drive and power supply chips during operation can be coupled to the chip pins through board-level parasitic parameters or spatial electromagnetic fields, resulting in a decrease in the conversion accuracy and reliability of SAR ADCs, especially when the analog-to-digital converter is integrated inside the chip.

Method used

By monitoring the operation of the internal power circuit of the chip, delaying the sampling and conversion stages to avoid system interference and ensure voltage stability, a digital logic control strategy is adopted to dynamically adjust the delay time to adapt to different interference conditions.

Benefits of technology

It significantly improves the conversion accuracy and reliability of SAR ADCs in harsh power environments, avoids the impact of interference on conversion results, and is low in cost and requires no changes to the hardware circuit.

✦ Generated by Eureka AI based on patent content.

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Abstract

The application provides a sampling and conversion method, a chip and a device based on a SAR ADC. The method comprises: in a sampling stage of the SAR ADC, monitoring whether a preset power action occurs in a power circuit inside the chip; if it is monitored that the power action occurs, delaying for a first preset time, and then ending the sampling and entering a conversion stage; the length of the first preset time is configured to make a sampling input voltage of the SAR ADC stable before the sampling ends; in the conversion stage of the SAR ADC, monitoring whether a preset power action occurs in the power circuit inside the chip; if it is monitored that the power action occurs, delaying for a second preset time, and then performing a comparator latching operation of a current bit; the length of the second preset time is configured to make a reference voltage and / or a power supply voltage of the SAR ADC stable before the comparator latches. The embodiments of the application can actively avoid a moment when system interference is large, and ensure that the voltage of a key operation node is stable.
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Citation Information

Patent Citations

  • Method and apparatus for subclocking a sar analog-to-digital converter

    CN1981442A