A semiconductor device and a method of fabricating the same

Abstract

The application provides a semiconductor device and a preparation method thereof, including: providing a semiconductor structure including a substrate, a bit line layer, a first interlayer dielectric layer, a word line layer and a second interlayer dielectric layer; the bit line layer includes a plurality of bit lines; the word line layer includes a plurality of word lines; forming a channel hole penetrating through the second interlayer dielectric layer, the word line and the second interlayer dielectric layer and exposing the bit line in the semiconductor structure, the aspect ratio of the channel hole is greater than or equal to 2; forming a gate dielectric layer covering the side wall of the channel hole; forming a channel layer covering the gate dielectric layer and the bottom wall of the channel hole; forming a first isolation layer covering the channel layer; forming a second isolation layer with a gap formed therein; removing part of the second isolation layer and the first isolation layer, forming an inner recess on the remaining first isolation layer and the remaining second isolation layer, the top surface of the remaining first isolation layer is lower than the highest point of the top surface of the remaining second isolation layer and does not expose the gap, and the inner recess exposes the upper part of the channel layer; filling the inner recess to form a drain layer.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and more specifically to a semiconductor device and a method for fabricating the same. Background Technology

[0002] In the memory cells of Dynamic Random Access Memory (DRAM), access transistors are responsible for controlling the charging and discharging of the storage capacitors. With the continuous improvement in functional integration and large-capacity storage requirements of mobile consumer electronics, the design and manufacturing of transistor components have gradually transitioned from planar to vertical, and their channels have also evolved from planar to annular. For vertical channel transistors, the depth of the etch-back of the isolation layer in the channel via determines the contact area between the channel and the drain. The larger the contact area, the larger the turn-on current of the device, and the magnitude of the turn-on current directly affects the final yield of the device.

[0003] However, as device feature sizes continue to shrink, the aspect ratio of vias increases. During the deposition of the isolation layer in the vias, the filling capacity of the high aspect ratio structure is limited, easily leading to voids within the isolation layer. These voids directly restrict the depth of the isolation layer etch-back. To increase the contact area between the channel and the drain, the etch-back depth of the isolation layer needs to be increased. During this etch-back process, the voids within the isolation layer will be encountered. Subsequently, during drain layer deposition, these voids will be filled by the drain material, resulting in poorer gate control capability, slower speed, and increased leakage current. To avoid encountering voids during subsequent etch-back, the etch-back depth of the isolation layer needs to be reduced, leading to a smaller contact area between the channel and the drain, which in turn reduces the device's turn-on current and affects device yield.

[0004] Therefore, improvements are needed to at least partially address the aforementioned problems. Summary of the Invention

[0005] The summary section introduces a series of simplified concepts, which will be further explained in detail in the detailed description section. This summary section is not intended to limit the key and essential technical features of the claimed technical solution, nor is it intended to determine the scope of protection of the claimed technical solution.

[0006] To address the existing problems, this application provides a method for fabricating a semiconductor device, comprising: providing a semiconductor structure, the semiconductor structure including a substrate and a bit line layer, a first interlayer dielectric layer, a word line layer, and a second interlayer dielectric layer sequentially formed on the substrate; wherein: the bit line layer includes a plurality of bit lines spaced apart along a first direction and extending along a second direction, adjacent bit lines being isolated by an insulating material, the first direction and the second direction intersecting and both parallel to the substrate; the word line layer includes a plurality of word lines spaced apart along the second direction and extending along the first direction, adjacent word lines being isolated by an insulating material; and forming a channel hole in the semiconductor structure penetrating the second interlayer dielectric layer, the word lines, and the first interlayer dielectric layer, exposing a portion of the bit lines, the depth of the channel hole being... Aspect ratio greater than or equal to 2 is used; a gate dielectric layer is formed that conformally covers the sidewalls of the channel hole; a channel layer is formed that conformally covers the gate dielectric layer and the bottom wall of the channel hole; a first isolation layer is formed that conformally covers at least the channel layer; the remaining space of the channel hole is filled to form a second isolation layer, the second isolation layer having voids; and a portion of the second isolation layer and a portion of the first isolation layer are etched back to remove them, such that a recess is formed on the remaining first isolation layer and the remaining second isolation layer, the top surface of the remaining first isolation layer is lower than the highest point of the top surface of the remaining second isolation layer and the voids are not exposed, the recess exposes the upper part of the channel layer, and the height of the lowest point of the bottom surface of the recess is flush with or higher than the upper surface of the word line layer; the recess is filled to form a drain layer.

[0007] Exemplarily, the gate dielectric layer further covers the surface of the second interlayer dielectric layer, and the second isolation layer includes, in addition to the portion located within the channel via, a portion located above the second interlayer dielectric layer; the step of etching back to remove a portion of the second isolation layer and a portion of the first isolation layer includes a first etch-back process and a second etch-back process executed sequentially; the first etch-back process removes at least the portion of the second isolation layer located above the second interlayer dielectric layer, wherein the etching rate of the first etch-back process for the second isolation layer is higher than the etching rate for the first isolation layer; the second etch-back process removes a portion of the first isolation layer and a portion of the second isolation layer, wherein the etching rate of the second etch-back process for the first isolation layer is higher than the etching rate for the second isolation layer.

[0008] For example, the first etching process and the second etching process are dry etching processes. The first etching process removes a portion of the second isolation layer located at the top of the channel hole. The first etching process uses a first etching gas, and the second etching process uses a second etching gas.

[0009] For example, the first etching process is a dry etching process using a first etching gas; the second etching process is a wet etching process using a first etching solution.

[0010] For example, the first etching gas includes fluoromethane, and the second etching gas includes carbon tetrafluoride.

[0011] For example, the first etching solution includes dilute hydrofluoric acid or a buffer mixture of hydrofluoric acid and ammonium fluoride.

[0012] For example, the top surface of the remaining second isolation layer is an arcuate top surface that bulges toward the side away from the substrate.

[0013] For example, the inner groove is Ω-shaped.

[0014] This application, in another aspect, provides a semiconductor device, comprising: a semiconductor structure, the semiconductor structure including a substrate and a bit line layer, a first interlayer dielectric layer, a word line layer, and a second interlayer dielectric layer sequentially formed on the substrate; wherein: the bit line layer includes a plurality of bit lines spaced apart along a first direction and extending along a second direction, adjacent bit lines being isolated by an insulating material, the first direction and the second direction intersecting and both parallel to the substrate; the word line layer includes a plurality of word lines spaced apart along the second direction and extending along the first direction, adjacent word lines being isolated by an insulating material; and a channel via disposed in the semiconductor structure and penetrating the second interlayer dielectric layer, the word lines, and the second interlayer dielectric layer. A dielectric layer is formed by exposing a portion of the bit line, and the aspect ratio of the channel hole is greater than or equal to 2; a gate dielectric layer is formed by covering the sidewall of the channel hole; a channel layer is formed by conformally covering the gate dielectric layer and the bottom wall of the channel hole; a first isolation layer is formed by conformally covering a portion of the channel layer; a second isolation layer with internal gaps is formed by filling and protruding from the groove formed by the first isolation layer, forming an inner groove surrounded by the channel layer, the first isolation layer and the second isolation layer, the inner groove being located inside the channel hole, wherein the top surface of the first isolation layer is lower than the highest point of the top surface of the second isolation layer, and the top surface of the second isolation layer does not expose the gaps; a drain layer is formed by filling the internal space of the inner groove.

[0015] For example, the top surface of the second isolation layer is an arc-shaped top surface that bulges toward the side away from the substrate.

[0016] For example, the inner groove is Ω-shaped.

[0017] The semiconductor device and its fabrication method provided in this application sequentially form a gate dielectric layer, a channel layer, a first isolation layer, and a second isolation layer containing voids in a channel hole with an aspect ratio greater than or equal to 2. The first and second isolation layers are then etched back, so that the top surface of the remaining first isolation layer is lower than the highest point of the top surface of the second isolation layer. At the same time, the etch-back process ensures that the voids inside the second isolation layer are not exposed, effectively avoiding the problem of device gate control capability degradation caused by the subsequent drain layer filling the voids. The formed groove exposes the upper part of the channel layer, ensuring the contact area between the channel and the drain, increasing the device's turn-on current, and improving the device's electrical performance and yield. Attached Figure Description

[0018] The following drawings, which are incorporated herein by reference as part of this invention, are provided for understanding the invention. The drawings illustrate embodiments of the invention and their descriptions, serving to explain the principles of the invention.

[0019] In the attached image:

[0020] Figures 1A to 1H A schematic diagram of the semiconductor device obtained by sequentially implementing the semiconductor device fabrication method of the related technology of this application is shown;

[0021] Figure 2 A flowchart illustrating a method for fabricating a semiconductor device according to a specific embodiment of this application is shown;

[0022] Figures 3A to 3F The figure shows a schematic diagram of a semiconductor device obtained by sequentially carrying out a method for fabricating a semiconductor device according to a specific embodiment of this application. Detailed Implementation

[0023] The invention will now be described more fully with reference to the accompanying drawings, which illustrate embodiments of the invention. However, the invention can be embodied in various forms and should not be construed as limited to the embodiments set forth herein. Rather, providing these embodiments will make the disclosure thorough and complete, and will fully convey the scope of the invention to those skilled in the art. In the drawings, for clarity, the dimensions and relative dimensions of layers and regions may be exaggerated. The same reference numerals denote the same elements throughout.

[0024] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, components, areas, layers, and / or portions, these elements, components, areas, layers, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, area, layer, or portion from another element, component, area, layer, or portion. Therefore, without departing from the teachings of this invention, the first element, component, area, layer, or portion discussed below may be referred to as the second element, component, area, layer, or portion.

[0025] Spatial relation terms such as “below,” “under,” “below,” “below,” “above,” “above,” etc., are used herein for convenience of description to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms are intended to also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, then the element or feature described as “below” or “below” other elements or features will be oriented “above” other elements or features. Therefore, the exemplary terms “below” and “under” can include both above and below orientations. The device may be otherwise oriented (rotated 90 degrees or otherwise) and the spatial descriptive terms used herein will be interpreted accordingly.

[0026] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the invention. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprise” and / or “comprising,” when used in this specification, identify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0027] To fully understand this application, detailed steps and structures will be presented in the following description to illustrate the technical solutions proposed in this application. Preferred embodiments of this application are described in detail below; however, in addition to these detailed descriptions, this application may have other implementation methods.

[0028] In related technologies, firstly, such as Figure 1A As shown, a bit line layer 11, a first interlayer dielectric layer 12, a word line layer 13, and a second interlayer dielectric layer 14 are sequentially formed above the substrate 10. Then, a channel via 15 is formed penetrating the second interlayer dielectric layer 14, the word line layer 13, and the first interlayer dielectric layer 12. A gate dielectric layer 16 is formed on the sidewall of the channel via 15, and a channel layer 17 is formed on the gate dielectric layer 16. Next, as... Figure 1B As shown, an isolation layer 18 is formed to fill the channel hole 15. A void 19 is formed in the isolation layer 18. The presence of the void directly limits the depth of the back etching of the isolation layer 18.

[0029] To address this problem, relevant technologies mainly adopt two strategies: such as Figures 1C to 1E As shown, the first strategy is to etch back the isolation layer 18 in the channel via 15 to a conventional depth to maximize the contact area between the channel and the drain. However, when the etch back depth is large, it exposes the voids 19 in the isolation layer 18, causing the voids 19 to be filled with drain material during the subsequent deposition of the drain layer 101. This conductive path will disrupt the local dielectric integrity, weaken the device's gate control over the channel, and cause problems such as increased leakage current and decreased device speed. Figures 1F to 1H As shown, the second strategy is to reduce the depth of the back etch of the isolation layer 18 to avoid exposing the gap 19 in the subsequent back etch, and to ensure that the etch endpoint is located above the gap 19. Although this method can avoid exposing the gap 19 and the subsequent drain layer 101 will not fill the gap 19, it also significantly reduces the effective contact area between the channel and the drain, thereby reducing the turn-on current of the device and affecting the yield of the device.

[0030] Therefore, in view of the aforementioned technical problems, this application proposes a method for fabricating a semiconductor device, such as... Figure 2 As shown, it mainly includes the following steps:

[0031] Step S1: Provide a semiconductor structure, the semiconductor structure including a substrate and a bit line layer, a first interlayer dielectric layer, a word line layer and a second interlayer dielectric layer sequentially formed on the substrate; wherein: the bit line layer includes a plurality of bit lines spaced apart along a first direction and extending along a second direction, adjacent bit lines are isolated by an insulating material, the first direction and the second direction intersect and are both parallel to the substrate; the word line layer includes a plurality of word lines spaced apart along the second direction and extending along the first direction, adjacent word lines are isolated by an insulating material;

[0032] Step S2: Form a channel hole in the semiconductor structure that penetrates the second interlayer dielectric layer, the word line and the first interlayer dielectric layer and exposes part of the bit line. The aspect ratio of the channel hole is greater than or equal to 2.

[0033] Step S3: Form a conformal gate dielectric layer covering the sidewall of the channel hole;

[0034] Step S4: Form a conformal covering of the gate dielectric layer and the channel layer at the bottom of the channel hole;

[0035] Step S5: Form a first isolation layer that conforms to the shape of the trench layer;

[0036] Step S6, filling the remaining space of the channel hole to form a second isolation layer, the second isolation layer having voids; and

[0037] Step S7: Etch back to remove part of the second isolation layer and the first isolation layer, so that an inner groove is formed on the remaining first isolation layer and the remaining second isolation layer. The top surface of the remaining first isolation layer is lower than the highest point of the top surface of the remaining second isolation layer and no gap is exposed. The inner groove exposes the upper part of the channel layer, and the height of the lowest point of the bottom surface of the inner groove is flush with or higher than the upper surface of the word line layer.

[0038] Step S8: Fill the inner groove to form a drain layer.

[0039] The semiconductor device and its fabrication method according to the embodiments of this application are formed sequentially in a channel hole with an aspect ratio greater than or equal to 2, including a gate dielectric layer, a channel layer, a first isolation layer, and a second isolation layer with voids. The first isolation layer and the second isolation layer are etched back, so that the top surface of the remaining first isolation layer is lower than the highest point of the top surface of the second isolation layer. At the same time, it is ensured that the voids inside the second isolation layer are not exposed during the etch-back process. This effectively avoids the problem of device gate control capability degradation caused by the subsequent drain layer filling the voids. The formed groove exposes the upper part of the channel layer, ensuring the contact area between the channel and the drain, increasing the device's turn-on current, and improving the device's electrical performance and yield.

[0040] Example 1

[0041] Below, for reference Figure 2 as well as Figures 3A to 3F The method for fabricating the semiconductor device of this application is described in detail, wherein, Figure 2 A flowchart illustrating a method for fabricating a semiconductor device according to a specific embodiment of this application is shown. Figures 3A to 3F The diagram shows a semiconductor device obtained by sequentially implementing a method for fabricating a semiconductor device according to a specific embodiment of this application.

[0042] For example, the method for fabricating the semiconductor device of this application includes the following steps:

[0043] First, step S1 is performed to provide a semiconductor structure, which includes a substrate and a bit line layer, a first interlayer dielectric layer, a word line layer, and a second interlayer dielectric layer sequentially formed on the substrate; wherein: the bit line layer includes a plurality of bit lines spaced apart along a first direction and extending along a second direction, adjacent bit lines are isolated by an insulating material, the first direction and the second direction intersect and are both parallel to the substrate; the word line layer includes a plurality of word lines spaced apart along the second direction and extending along the first direction, adjacent word lines are isolated by an insulating material.

[0044] In one example, such as Figure 3A As shown, a substrate 20 is provided, and the material of the substrate 20 includes, but is not limited to, at least one of the following materials: silicon (Si), germanium (Ge), silicon germanium (SiGe), silicon carbide (SiC), silicon germanium carbon (SiGeC), indium arsenide (InAs), gallium arsenide (GaAs), indium phosphide (InP), sapphire, or other III / V compound semiconductors; or silicon-on-insulator (SOI), silicon-on-insulator (SSOI), silicon-on-insulator (S-SiGeOI), silicon-on-insulator (SiGeOI), and germanium-on-insulator (GeOI); or it may be a double-sided polished wafer (DSP), a ceramic substrate such as alumina, a quartz, or a glass substrate, etc. Although several examples of materials that can form the substrate have been described herein, any material that can serve as a substrate falls within the spirit and scope of the invention.

[0045] In one example, such as Figure 3A As shown, a bit line layer 21 is formed on the substrate 20. The bit line layer 21 can be made of a low-resistance, high-conductivity material, including but not limited to polysilicon, metals, and metal silicides. The metal material can include tungsten (W), which has a high melting point and good electromigration resistance; or copper (Cu), which has low resistance. Specifically, firstly, a bit line material layer can be formed on the substrate 20 using methods including but not limited to atomic layer deposition (ALD) or physical vapor deposition (PVD). Next, a patterned mask layer is formed on the bit line material layer. For example, a photoresist layer can be spin-coated onto the bit line material layer. The photoresist layer is then exposed and developed to form a pattern defining multiple bit lines. Finally, the patterned photoresist layer is used as a mask to perform dry or wet etching on the bit line material layer to form multiple bit lines.

[0046] For example, the bit line layer 21 includes multiple bit lines, which are spaced apart along a first direction and extend along a second direction. Adjacent bit lines are isolated by an insulating material. The first and second directions intersect and are both parallel to the substrate 20. The bit lines can be a composite film structure made of multiple materials or a single film structure; there is no specific limitation. The insulating material includes, but is not limited to, silicon oxide, silicon nitride, or low-k dielectric materials.

[0047] In one example, such as Figure 3A As shown, a first interlayer dielectric layer 22 is formed on the bit line layer 21. The first interlayer dielectric layer 22 is formed on the bit line layer 21, and its main function is to provide electrical isolation between the bit line layer and the word line layer above it, and to suppress interlayer parasitic capacitance. Exemplarily, the methods for forming the first interlayer dielectric layer 22 include, but are not limited to, high-density plasma chemical vapor deposition (HDP-CVD), plasma-enhanced chemical vapor deposition (PECVD), or atomic layer deposition (ALD). The materials of the first interlayer dielectric layer 22 include, but are not limited to, phosphosilicate glass (PSG), borosilicate glass (BPSG), silicon dioxide (SiO2), silicon nitride (Si3N4), carbon-doped oxides, or low-k dielectric materials, etc., and are not specifically limited thereto. The first interlayer dielectric layer 22 may include a combination of one or more dielectric materials.

[0048] In one example, such as Figure 3A As shown, a word line layer 23 is formed on the first interlayer dielectric layer 22. The word line layer 23 includes multiple word lines spaced apart along a second direction and extending along a first direction, with adjacent word lines isolated by an insulating material. Specifically, the formation steps of the word line layer 23 include: firstly, depositing a word line material layer and a photoresist layer sequentially on the first interlayer dielectric layer, wherein the word line material layer can be formed by physical vapor deposition (PVD), chemical vapor deposition (CVD), or atomic layer deposition (ALD); exposing and developing the photoresist layer to form a pattern defining the multiple word lines; and then using the patterned photoresist layer as a mask to perform dry or wet etching on the word line material layer to form multiple word lines. The gaps after etching are then filled by a filling process, such as atomic layer deposition (ALD) to deposit an insulating material to isolate adjacent word lines. Exemplarily, the material of the word line layer can include metallic materials, such as tungsten or copper, or polysilicon or other conductive materials. The insulating material includes, but is not limited to, silicon oxide, silicon nitride, or low-k dielectric materials.

[0049] For example, a barrier layer may be formed on the first interlayer dielectric layer 22 before forming the word line layer 23. The barrier layer is used to prevent the word line layer from diffusing into the first interlayer dielectric layer, thereby improving the stability and reliability of the semiconductor structure. The material of the barrier layer includes, but is not limited to, titanium nitride.

[0050] In one example, such as Figure 3A As shown, a second interlayer dielectric layer 24 is formed on the word line layer 23. Its main function is to provide sufficient dielectric thickness support for subsequent etching of vias, achieve electrical isolation between the word line layer and the upper structure (e.g., drain), and suppress crosstalk and parasitic capacitance between adjacent vias. Exemplarily, the methods for forming the second interlayer dielectric layer 24 include, but are not limited to, high-density plasma chemical vapor deposition (HDP-CVD), plasma-enhanced chemical vapor deposition (PECVD), or atomic layer deposition (ALD). The materials of the second interlayer dielectric layer 24 include, but are not limited to, silicon phosphosilicate glass (PSG), borosilicate glass (BPSG), silicon dioxide (SiO2), silicon nitride (Si3N4), carbon-doped oxides, or low-k dielectric materials, etc., without specific limitation. The second interlayer dielectric layer 24 may include a combination of one or more dielectric materials.

[0051] Next, step S2 is performed to form a channel hole in the semiconductor structure that penetrates the second interlayer dielectric layer, the word line and the first interlayer dielectric layer and exposes part of the bit line. The aspect ratio of the channel hole is greater than or equal to 2.

[0052] In one example, such as Figure 3A As shown, a channel hole 25 is formed in the semiconductor structure, penetrating the second interlayer dielectric layer 24, the word line, and the first interlayer dielectric layer 22, and exposing a portion of the bit line. Specifically, firstly, a patterned mask layer is formed on the second interlayer dielectric layer 24. The mask layer may include an amorphous carbon layer, an anti-reflection coating, and a photoresist layer formed sequentially. Then, the photoresist layer is patterned through photolithography processes such as pre-baking, exposure, development, and hardening. The patterned photoresist layer defines the shape and position of the channel hole. Then, using the patterned photoresist layer as a mask, a channel hole 25 perpendicularly penetrating the second interlayer dielectric layer 24, the word line, and the first interlayer dielectric layer 22 is formed through a dry etching process. The dry etching can be a conventional etching process such as reactive ion etching (RIE), ion beam etching, or plasma etching. After etching, the mask layer can be removed by at least one of the following processes: ashing, wet etching, and chemical mechanical polishing. For example, the aspect ratio of the channel hole 25 is greater than or equal to 2.

[0053] Next, step S3 is performed to form a conformal gate dielectric layer covering the sidewalls of the channel aperture.

[0054] In one example, such as Figure 3AAs shown, a conformal gate dielectric layer 26 is formed covering the sidewalls of the channel via 25, and also covers the surface of the second interlayer dielectric layer 24. Exemplarily, the gate dielectric layer 26 can be formed using methods including, but not limited to, chemical vapor deposition (CVD), physical vapor deposition (PVD), or atomic layer deposition (ALD). The material of the gate dielectric layer 26 includes, but is not limited to, silicon oxide, silicon oxynitride, or high-k materials, such as hafnium oxide or zirconium oxide. The main function of the gate dielectric layer is to provide reliable electrical insulation between the subsequently formed channel layer and word line layer, and to serve as a dielectric interface between the gate and the channel to regulate carrier transport and suppress leakage current. It should be noted that during the formation of the gate dielectric layer 26, the gate dielectric layer material covers not only the sidewalls of the channel via 25, but also the bottom wall of the channel via 25, i.e., the exposed bit line surface. The gate dielectric layer material located on the bottom wall of the channel via 25 needs to be removed using a dry etching process.

[0055] Continue, execute step S4 to form a conformal covering of the gate dielectric layer and the channel layer on the bottom wall of the channel hole.

[0056] In one example, such as Figure 3A As shown, a conformal channel layer 27 is formed covering the gate dielectric layer 26 and the bottom wall of the channel via 25. Exemplarily, the channel layer 27 can be formed using methods including, but not limited to, chemical vapor deposition (CVD) or atomic layer deposition (ALD), and the material of the channel layer 27 includes, but is not limited to, polycrystalline silicon or amorphous silicon. As the active region of the device, the channel layer 27 forms a vertical conductive path in the three-dimensional structure. It is coupled to the surrounding word line layer through the gate dielectric layer to achieve the gate-controlled current switching function. Simultaneously, its bottom forms an ohmic contact with the bit line, ensuring effective transmission of the drain signal and determining the device's turn-on current and overall electrical reliability.

[0057] Then, step S5 is performed to form a first isolation layer that at least conforms to the trench layer.

[0058] In one example, such as Figure 3BAs shown, a first isolation layer 28 is formed to conformally cover at least the surface of the channel layer 27, including its sidewalls and bottom. Exemplarily, the first isolation layer 28 can be formed using methods including, but not limited to, atomic layer deposition (ALD), low-pressure chemical vapor deposition (LPCVD), or plasma-enhanced chemical vapor deposition (PECVD). The material of the first isolation layer 28 includes, but is not limited to, silicon dioxide, silicon nitride, or silicon oxynitride. In this embodiment, the material of the first isolation layer 28 can be silicon dioxide. The first isolation layer serves to cooperate with the second isolation layer in constructing the recessed morphology during subsequent etch-back processes, protecting the sidewalls of the channel layer from damage. Simultaneously, it acts as a local dielectric barrier between the drain layer and the channel layer, preventing electrical contact between the drain polysilicon and non-target areas of the channel layer, thereby ensuring precise contact positioning, increasing device turn-on current, and maintaining gate control capability.

[0059] Continue, proceed to step S6, fill the remaining space of the channel hole to form a second isolation layer, and form voids within the second isolation layer.

[0060] In one example, such as Figure 3C As shown, a second isolation layer 29 is formed, which covers the first isolation layer 28 and fills the remaining space of the channel via 25. The second isolation layer 29 includes not only the portion located within the channel via 25 but also the portion located above the second interlayer dielectric layer 24. Exemplarily, the second isolation layer 29 can be formed using methods including, but not limited to, atomic layer deposition (ALD), low-pressure chemical vapor deposition (LPCVD), or plasma-enhanced chemical vapor deposition (PECVD). The material of the second isolation layer 29 includes, but is not limited to, silicon dioxide, silicon nitride, or silicon oxynitride. In this embodiment, the material of the second isolation layer 29 can be silicon nitride. The second isolation layer, in conjunction with the first isolation layer, is etched back to form an inner groove to expose the upper part of the channel layer 27. Its top provides deposition support, and the internal voids are not exposed, preventing drain material from seeping in, thus balancing contact performance and reliability.

[0061] In the case of the channel hole 25, the aspect ratio is greater than or equal to 2. During the process of filling the channel hole 25 with a high aspect ratio, the second isolation layer 29 will form a closed void 250 inside the channel hole 25 due to the narrow opening at the top of the channel hole 25 and its deep depth, as well as the limitations of the fluidity of the deposited material and the step coverage ability.

[0062] Continue, execute step S7, etch back to remove part of the second isolation layer and part of the first isolation layer, so that an inner groove is formed on the remaining first isolation layer and the remaining second isolation layer. The top surface of the remaining first isolation layer is lower than the highest point of the top surface of the remaining second isolation layer and no gap is exposed. The inner groove exposes the upper part of the channel layer, and the height of the lowest point of the bottom surface of the inner groove is flush with or higher than the upper surface of the word line layer.

[0063] In one example, such as Figure 3D As shown, the etch-back process removes a portion of the second isolation layer 29 and a portion of the first isolation layer 28. This etch-back process includes a first etch-back process and a second etch-back process executed sequentially. The specific steps are as follows:

[0064] First, a first etch process is performed to remove at least the second isolation layer 29 located above the second interlayer dielectric layer 24. The first etch process has a higher etching rate for the second isolation layer 29 than for the first isolation layer 28. For example, this first etch process uses a gas system with a high etching rate for the second isolation layer 29 (e.g., silicon nitride) and a lower etching rate for the first isolation layer 28 (e.g., silicon oxide). A fluoromethane (CH3F) gas system can be used to selectively etch the second isolation layer 29 under appropriate bias power and chamber pressure. This first etch process initially removes the second isolation layer 29 covering the top of the second interlayer dielectric layer, initially exposing the via region and laying the foundation for the subsequent second etch process to form an Ω-shaped indentation.

[0065] Subsequently, a second etching process is performed to further etch and remove a portion of the first isolation layer 28 and a portion of the second isolation layer 29, that is, to remove a portion of the first isolation layer 28 and a portion of the second isolation layer 29 within the channel hole 25 to form an inner groove 290. In this second etching process, the etching rate for the first isolation layer 28 is higher than the etching rate for the second isolation layer 29. Etching conditions with a higher etching rate for the first isolation layer 28 and a slower etching rate for the second isolation layer 29 are employed. For example, when the first isolation layer 28 is an oxide and the second isolation layer 29 is silicon nitride, wet etching with dilute hydrofluoric acid (DHF) or high-selectivity dry etching with carbon tetrafluoride (CF4) gas can be used, or an atomic layer etching process can be employed to preferentially remove the oxide, while the remaining silicon nitride portion forms a relatively raised top structure.

[0066] Through the above two-step etching back, the structure formed in the final channel hole 25 satisfies the following: the top surface of the remaining first isolation layer 28 is lower than the highest point of the top surface of the remaining second isolation layer 29, and the two together form an inner groove 290. The inner groove 290 exposes the upper region of the channel layer 27, and the height of the lowest point of its bottom surface is not lower than the upper surface of the word line layer 23. That is, the height of the lowest point of the bottom surface of the inner groove 290 is flush with or higher than the upper surface of the word line layer 23. This ensures sufficient contact area between the channel and the drain, and avoids exposing the voids inside the second isolation layer due to excessive etching, effectively maintaining the gate's control capability over the channel and the device reliability.

[0067] In the first and second etching processes, while removing part of the second isolation layer 29 and the first isolation layer 28, the channel layer 27 and the gate dielectric layer 26 on the second interlayer dielectric layer 24 are also etched away.

[0068] In one example, the first and second etching processes are dry etching processes. The first etching process removes a portion of the second isolation layer 29 located at the top of the channel hole 25. The first etching process uses a first etching gas, and the second etching process uses a second etching gas. Specifically, both the first and second etching processes are dry etching processes. The first etching gas includes, but is not limited to, one or more of fluoromethane (CH3F), trifluoromethane (CHF3), or octafluorocyclobutane (C4F8), and the second etching gas includes, but is not limited to, carbon tetrafluoride (CF4).

[0069] In another example, the first etching process is a dry etching process using a first etching gas; the second etching process is a wet etching process using a first etching solution. Specifically, the first etching process is a dry etching process using a first etching gas to selectively remove a portion of the second isolation layer 29 located at the top of the via 25 and above the second interlayer dielectric layer 24. The first etching gas includes, but is not limited to, one or more of fluoromethane (CH3F), trifluoromethane (CHF3), or octafluorocyclobutane (C4F8). The second etching process is a wet etching process using a first etching solution that is highly selective for the first isolation layer 28. The first etching solution includes, but is not limited to, dilute hydrofluoric acid (DHF) or fluorinated... The ammonium buffer mixture preferentially dissolves the exposed first isolation layer 28, while having a low etching rate on the second isolation layer 29. This allows for further excavation of the inner groove 290, making the top surface of the remaining first isolation layer 28 lower than the highest top surface of the remaining second isolation layer 29, exposing the upper part of the channel layer 27. The lowest point of the bottom surface of the inner groove 290 is not lower than the upper surface of the word line layer 23. At the same time, it ensures that the voids 250 inside the second isolation layer 29 are not exposed during the entire etch-back process. This achieves a synergistic optimization of sufficient contact area and good gate control capability while avoiding drain layer penetration.

[0070] In one example, the top surface of the remaining second isolation layer 29 is an arc-shaped top surface that bulges toward the side away from the substrate 20. This morphology depends on the partial etching of the second isolation layer 29 by the first etching process and the selective removal of the first isolation layer 28 and the second isolation layer 29 by the second etching process. This causes the top of the second isolation layer 29 to naturally form an upward arched profile due to the difference in etching rate. This arc-shaped top surface helps guide the subsequent drain layer to fill from both sides, raising the joint position to avoid the channel region, thereby improving device reliability.

[0071] In one example, the groove 290 is Ω-shaped. The Ω-shaped structure not only increases the contact area between the channel and the drain layer and improves the turn-on current of the device, but also effectively ensures the gate control capability and reliability of the device.

[0072] Finally, step S8 is performed to fill the groove to form the drain layer.

[0073] In one example, such as Figure 3E and Figure 3F As shown, the drain layer 291 is formed by filling the recess 290. The specific steps for forming the drain layer 291 include: First, a drain material is deposited in the recess 290 using processes including but not limited to chemical vapor deposition (CVD) or low-pressure chemical vapor deposition (LPCVD). The drain material includes, but is not limited to, polysilicon. Next, a planarization process, such as chemical mechanical polishing (CMP) or etching, is performed to remove excess drain material on the second interlayer dielectric layer 24, making the drain layer 291 flush with the surface of the second interlayer dielectric layer 24. This forms a vertical drain contact between the upper part of the electrical connection channel layer and the external interconnect structure. The drain layer 291 not only achieves a low-resistance ohmic contact, but its filling process also lifts any seams that may be formed to the upper region away from the channel due to the guiding effect of the Ω-shaped recess, effectively avoiding conductive defects from affecting the gate control performance.

[0074] It is worth mentioning that the above steps are only examples, and the order of the steps can be adjusted without conflict.

[0075] Thus, the process steps of the semiconductor device fabrication method according to the embodiments of this application are completed. It is understood that the semiconductor device fabrication method of this embodiment includes not only the above steps, but may also include other necessary steps before, during or after the above steps, all of which are included within the scope of the fabrication method of this embodiment.

[0076] In summary, the semiconductor device fabrication method of this application involves sequentially forming a gate dielectric layer, a channel layer, a first isolation layer, and a second isolation layer containing voids in a channel hole with an aspect ratio greater than or equal to 2, and then performing back etching on the first and second isolation layers so that the top surface of the remaining first isolation layer is lower than the highest point of the top surface of the second isolation layer. At the same time, it ensures that the voids inside the second isolation layer are not exposed during the back etching process, effectively avoiding the problem of device gate control capability degradation caused by the subsequent drain layer filling the voids. The formed groove exposes the upper part of the channel layer, ensuring the contact area between the channel and the drain, increasing the device's turn-on current, and improving the device's electrical performance and yield.

[0077] Example 2

[0078] This application also provides a semiconductor device, which can be prepared by the method of the aforementioned embodiment one, or can be prepared by other suitable preparation methods.

[0079] Below, refer to Figures 3A to 3F The semiconductor device of the present invention will be described in detail. It is worth mentioning that, in order to avoid repetition, only a brief description will be given for the same components and structures as in the foregoing embodiments. For a detailed explanation and description, please refer to the description in Embodiment 1.

[0080] Specifically, such as Figures 3A to 3F As shown, the semiconductor device of this application includes: a semiconductor structure, the semiconductor structure including a substrate 20 and a bit line layer 21, a first interlayer dielectric layer 22, a word line layer 23, and a second interlayer dielectric layer 24 sequentially formed on the substrate 20; wherein: the bit line layer 21 includes a plurality of bit lines spaced apart along a first direction and extending along a second direction, adjacent bit lines are isolated by an insulating material, the first direction and the second direction intersect and are both parallel to the substrate; the word line layer 23 includes a plurality of word lines spaced apart along the second direction and extending along the first direction, adjacent word lines are isolated by an insulating material; a channel via 25 is disposed in the semiconductor structure, and penetrates the second interlayer dielectric layer 24, the word lines and the first interlayer dielectric layer 22 and exposes part of the bit lines, the channel... The aspect ratio of the aperture 25 is greater than or equal to 2; the gate dielectric layer 26 covers the sidewall of the channel aperture 25; the channel layer 27 conformally covers the bottom wall of the gate dielectric layer 26 and the channel aperture 25; the first isolation layer 28 conformally covers part of the channel layer 27; the second isolation layer 29, which has an internal gap 250, fills and protrudes from the groove formed by the first isolation layer 28, forming an inner groove 290 surrounded by the channel layer 27, the first isolation layer 28 and the second isolation layer 29, the inner groove 290 is located inside the channel aperture 25, wherein the top surface of the first isolation layer 28 is lower than the highest point of the top surface of the second isolation layer 29, and the top surface of the second isolation layer 29 does not expose the gap 250; the drain layer 291 fills the internal space of the inner groove 290.

[0081] For example, the top surface of the second isolation layer 29 is an arc-shaped top surface that bulges toward the side away from the substrate 20. This arc-shaped top surface helps guide the subsequent drain layer 291 to fill from both sides, raising the seam position to avoid the channel region, thereby improving device reliability.

[0082] For example, the inner groove 290 is Ω-shaped. The Ω-shaped structure not only increases the contact area between the channel and the drain layer and improves the turn-on current of the device, but also effectively ensures the gate control capability and reliability of the device.

[0083] The semiconductor device of this application sequentially forms a gate dielectric layer, a channel layer, a first isolation layer, and a second isolation layer containing voids in a channel hole with an aspect ratio greater than or equal to 2. The first and second isolation layers are then etched back, so that the top surface of the remaining first isolation layer is lower than the highest point of the top surface of the second isolation layer. At the same time, the etch-back process ensures that the voids inside the second isolation layer are not exposed, effectively avoiding the problem of device gate control capability degradation caused by the subsequent drain layer filling the voids. The formed groove exposes the upper part of the channel layer, ensuring the contact area between the channel and the drain, increasing the device's turn-on current, and improving the device's electrical performance and yield.

[0084] Although several embodiments have been described herein, it should be understood that many other modifications and embodiments will be conceived by those skilled in the art, all of which will fall within the spirit and scope of the disclosed concept. More particularly, various modifications and changes can be made in terms of the arrangement and / or components of the subject matter within the scope of the disclosure, drawings, and appended claims. In addition to modifications and changes in components and / or arrangement, the use of alternative methods will also be obvious to those skilled in the art.

Claims

1. A method of manufacturing a semiconductor device, characterized by, The preparation method comprises: providing a semiconductor structure comprising a substrate and a bit line layer, a first interlayer dielectric layer, a word line layer and a second interlayer dielectric layer formed in sequence on the substrate; wherein: the bit line layer comprises a plurality of bit lines arranged at intervals along a first direction and extending along a second direction, adjacent two of the bit lines are separated by insulating material, the first direction and the second direction intersect and are both parallel to the substrate; the word line layer comprises a plurality of word lines arranged at intervals along the second direction and extending along the first direction, adjacent two of the word lines are separated by insulating material; forming a channel hole in the semiconductor structure, the channel hole penetrating through the second interlayer dielectric layer, the word line and the first interlayer dielectric layer and exposing part of the bit line, the aspect ratio of the channel hole being greater than or equal to 2; forming a gate dielectric layer conformally covering the sidewall of the channel hole; forming a channel layer conformally covering the gate dielectric layer and the bottom wall of the channel hole; forming a first isolation layer conformally covering at least the channel layer; filling the remaining space of the channel hole to form a second isolation layer, the second isolation layer having a void formed therein; and etching back to remove part of the second isolation layer and part of the first isolation layer, so that an inner groove is formed on the remaining first isolation layer and the remaining second isolation layer, the top surface of the remaining first isolation layer being lower than the highest point of the top surface of the remaining second isolation layer and not exposing the void, the inner groove exposing the upper part of the channel layer, and the bottom surface of the inner groove being flush with or higher than the upper surface of the word line layer at the lowest point; filling the inner groove to form a drain layer.

2. The production method according to claim 1, wherein The gate dielectric layer also covers the surface of the second interlayer dielectric layer, and the second isolation layer comprises a part located above the second interlayer dielectric layer in addition to a part located in the channel hole; The step of etching back to remove part of the second isolation layer and part of the first isolation layer comprises a first etching back process and a second etching back process performed in sequence; The first etching back process removes at least the part of the second isolation layer located above the second interlayer dielectric layer, wherein the etching rate of the first etching back process on the second isolation layer is higher than the etching rate on the first isolation layer; The second etching back process removes part of the first isolation layer and part of the second isolation layer, wherein the etching rate of the second etching back process on the first isolation layer is higher than the etching rate on the second isolation layer.

3. The production method according to claim 2, wherein The first etching back process and the second etching back process are dry etching processes, the first etching back process removes the part of the second isolation layer located at the top of the channel hole, the first etching back process uses a first etching gas, and the second etching back process uses a second etching gas.

4. The production method according to claim 2, wherein The first etching back process is a dry etching process and uses a first etching gas; The second etching back process is a wet etching process and uses a first etching liquid.

5. The production method according to claim 3, wherein The first etching gas comprises fluoromethane, and the second etching gas comprises carbon tetrafluoride.

6. The production method according to claim 4, wherein The first etching liquid comprises dilute hydrofluoric acid or a buffered mixture of hydrofluoric acid and ammonium fluoride.

7. The production method according to claim 1, wherein The top surface of the remaining second isolation layer is an arc-shaped top surface protruding towards a side away from the substrate.

8. The production method according to claim 1, wherein The shape of the inner groove is an Ω shape.

9. A semiconductor device, characterized by Comprise: A semiconductor structure, comprising a substrate and a bit line layer, a first interlayer dielectric layer, a word line layer and a second interlayer dielectric layer formed in sequence on the substrate; wherein: the bit line layer comprises a plurality of bit lines arranged at intervals along a first direction and extending along a second direction, the adjacent two bit lines are isolated by insulating material, and the first direction and the second direction intersect and are both parallel to the substrate; the word line layer comprises a plurality of word lines arranged at intervals along the second direction and extending along the first direction, the adjacent two word lines are isolated by insulating material; A channel hole is arranged in the semiconductor structure and penetrates the second interlayer dielectric layer, the word line and the first interlayer dielectric layer and exposes part of the bit line, and the aspect ratio of the channel hole is greater than or equal to 2; A gate dielectric layer covers the side wall of the channel hole; A channel layer conformally covers the gate dielectric layer and the bottom wall of the channel hole; A first isolation layer conformally covers part of the channel layer; A second isolation layer with internal voids fills and protrudes in the groove formed by the first isolation layer, forming an inner groove enclosed by the channel layer, the first isolation layer and the second isolation layer, and the inner groove is located in the channel hole, wherein the top surface of the first isolation layer is lower than the highest point of the top surface of the second isolation layer, and the top surface of the second isolation layer does not expose the void; A drain layer fills the internal space of the inner groove.

10. The semiconductor device of claim 9, wherein, The top surface of the second isolation layer is an arc-shaped top surface protruding towards a side away from the substrate.

11. The semiconductor device of claim 9, wherein the first and second semiconductor layers are formed of a same material. The shape of the inner groove is an Ω shape.

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