Power MOS tube with grid anti-surge function

Abstract

The invention discloses a power MOS tube with a grid anti-surge function. The power MOS tube comprises a substrate layer; the epitaxial layer is positioned on the front surface of the substrate layer; the MOS tube main body is formed on the epitaxial layer and is provided with a channel structure, a source electrode structure and a grid electrode structure; the grid protection structure is composed of an in-grid resistor, an out-grid resistor and a grid protection zener transistor pair; the in-gate resistor is formed at the tail end of a gate bus of the MOS tube main body; the gate external resistor and the gate protection zener transistor pair are formed below the gate bonding pad metal layer; wherein a first end of the in-gate resistor is in short circuit with a gate bus of the MOS tube main body, a first end of the out-gate resistor and a first end of the gate protection zener pair are in short circuit with a second end of the in-gate resistor, and a second end of the gate protection zener pair is in short circuit with a source electrode of the MOS tube main body. The second end of the external gate resistor is in short circuit with the gate pad metal layer. The gate structure of the MOS tube can be effectively protected from surge voltage impacts of various frequencies, the application range of the power MOS tube is expanded, and the continuously-increasing miniaturization requirement of an existing electronic product is met.

Description

Technical Field

[0001] This invention relates to semiconductor products, and more particularly to MOSFETs. Background Technology

[0002] The existing manufacturing process for power MOSFETs typically includes: First, fabricating several transistor units on the same wafer. Each transistor unit further includes a source, drain, and gate formed on the same substrate and epitaxial layer. The source, drain, and gate are respectively connected to metal to form source contacts, drain contacts, and gate contacts that can be used for external connection. Then, the separate individual transistor units are packaged, that is, a package housing such as plastic is formed to cover the individual transistor units, and source pins, drain pins, and gate pins are provided exposed outside the package housing. The source pins, drain pins, and gate pins are shorted to the source contacts, drain contacts, and gate contacts of the transistor unit, respectively.

[0003] In electronic product application circuit boards, such power MOSFETs are usually paired with external devices such as resistors and diodes, depending on the application environment. For example, in order to ensure that the MOSFET can withstand surge impact, external devices are connected around the MOSFET to form an input protection circuit, which makes the size of the entire application circuit board larger and cannot well meet the ever-increasing miniaturization requirements of current electronic products. Summary of the Invention

[0004] The technical problem to be solved by the present invention is that, in view of the above-mentioned defects of the prior art, the present invention proposes a power MOSFET with gate surge protection function, which can effectively protect the gate structure of the MOSFET from surge voltage impacts of various frequencies, which is conducive to expanding the application range of power MOSFETs and meeting the ever-increasing miniaturization requirements of existing electronic products.

[0005] The technical solution adopted by the present invention to solve its technical problem includes: providing a power MOSFET with gate surge protection function, comprising: a substrate layer; an epitaxial layer located on the front side of the substrate layer; a MOSFET body formed on the epitaxial layer, having a channel structure, a source structure, and a gate structure; a gate protection structure composed of an internal gate resistor, an external gate resistor, and a gate protection Zener diode pair; the internal gate resistor is formed at the end of the gate bus of the MOSFET body; the external gate resistor and the gate protection Zener diode pair are formed below the gate pad metal layer; wherein, the first end of the internal gate resistor is shorted to the gate bus of the MOSFET body, the first end of the external gate resistor and the first end of the gate protection Zener diode pair are both shorted to the second end of the internal gate resistor, the second end of the gate protection Zener diode pair is shorted to the source of the MOSFET body, and the second end of the external gate resistor is shorted to the gate pad metal layer.

[0006] In some embodiments, the gate-protected Zener diode pair consists of one or more pairs of back-to-back Zener diodes.

[0007] In some embodiments, the gate internal resistance, the gate external resistance, and the gate protection Zener diode pair are formed on the same polysilicon layer.

[0008] In some embodiments, the internal gate resistance is positioned closer to the gate of the MOS transistor body than the external gate resistance; the gate protection Zener diode is positioned around the external gate resistance.

[0009] In some embodiments, the wafer area occupied by the gate protection structure is less than 5% larger than that occupied by a conventional power MOSFET without a gate protection structure.

[0010] In some embodiments, the MOSFET body is a trench MOSFET, IGBT, superjunction MOSFET, isolation gate MOSFET, silicon carbide MOSFET, or gallium nitride HMET.

[0011] In some embodiments, the MOS transistor body is a trench MOS, and the wafer fabrication of the power MOS transistor uses five photomasks, which are used to form a trench layer, a gate protection zone etching layer, a source injection layer, a metal etching layer, and a metal wiring layer, respectively.

[0012] In some embodiments, the MOS transistor body is an N-type MOS.

[0013] In some embodiments, the MOS transistor body is a P-type MOS.

[0014] In some embodiments, the source of the MOS transistor body is formed on the epitaxial layer, and the drain of the MOS transistor body is formed on the back side of the substrate layer.

[0015] Compared with the prior art, the power MOSFET with gate surge protection function of the present invention forms a gate protection structure composed of an internal gate resistor, an external gate resistor, and a gate protection Zener diode pair. The gate protection structure is connected in series between the gate contact and the gate structure of the MOSFET body, thus organically combining the gate protection structure and the MOSFET body. This effectively protects the gate structure of the MOSFET from surge voltage impacts of various frequencies, which is conducive to expanding the application range of power MOSFETs and meeting the ever-increasing miniaturization requirements of existing electronic products. Attached Figure Description

[0016] Figure 1 An example of the power MOSFET of the present invention is illustrated.

[0017] Figure 2 The diagram illustrates the horizontal arrangement of the gate protection structure of the present invention.

[0018] Figure 3The diagram illustrates the horizontal arrangement of the gate protection structure and a portion of the MOS body of the present invention.

[0019] Figures 4-12 The wafer fabrication process of the power MOSFET of the present invention is illustrated.

[0020] The reference numerals in the attached figures are explained as follows: 10 Power MOSFET; 1 MOS body; 11 Gate; 2 Gate protection structure; 21 In-gate resistance; 22 Out-of-gate resistance; 23 Gate protection Zener diode pair; 5 Gate contact; 6 Source contact; 7 Drain contact; 101 Substrate layer; 102 Epitaxial layer; 103 MOS body; 104 Trench doping; 105 Isolation oxide layer; 106 Polysilicon layer; 107 In-gate resistance; 108 Out-of-gate resistance; 109 Gate protection Zener diode pair; 110 Interlayer dielectric; 111 Source metal; 112 Gate bus; 113, 113a Gate protection Zener diode pair connection metal; 114 Out-of-gate resistance connection metal. Implementation

[0021] The preferred embodiments of the present invention will now be described in detail with reference to the accompanying drawings.

[0022] See Figure 1 This invention proposes a power MOSFET 10, comprising: a MOSFET body 1, a gate protection structure 2, a gate contact 5, a source contact 6, and a drain contact 7. The MOSFET body 1 has a gate 11. The gate protection structure 2 is composed of an internal gate resistor 21, an external gate resistor 22, and a gate protection Zener diode pair 23, and is connected to the gate 11, enabling the power MOSFET 10 to have gate surge voltage protection functionality.

[0023] The first terminal of the gate resistor 21 is shorted to the gate 11 of the MOSFET body 1. The first terminal of the gate resistor 22 and the first terminal of the gate protection Zener diode pair 23 are both shorted to the second terminal of the gate resistor 21. The second terminal of the gate protection Zener diode pair 23 is shorted to the source of the MOSFET body 1. The second terminal of the gate resistor 22 is shorted to the gate contact 5. The source contact 6 and the drain contact 7 are shorted to the source and drain of the MOSFET body 1, respectively.

[0024] See Figure 2 and Figure 3 The gate resistor 21 is positioned closer to the gate of the MOS transistor body 1 than the gate resistor 22; the gate protection Zener diode pair 23 is arranged around the gate resistor 22.

[0025] It is worth mentioning that the wafer area occupied by the gate protection structure 2 is much smaller than that occupied by the MOSFET body 1. For example, the wafer area occupied by the gate protection structure 2 is less than 5% larger than that occupied by a traditional power MOSFET without a gate protection structure. That is, only less than 5% of the wafer area overhead (i.e., a very small cost overhead) is needed to add a gate protection structure, enabling the power MOSFET 10 to have the function of protecting the gate from surge voltage impact.

[0026] For example, the MOSFET body 1 is a trench MOSFET, an N-type MOSFET, with the following characteristics: a withstand voltage of 16 volts and a current capability of 60 amperes; the external gate resistor 22 has a resistance of 100 kilohms; the internal gate resistor 21 has a resistance of 100 kilohms; the gate protection Zener diode pair 23 consists of a pair of back-to-back Zener diodes, with a set voltage regulation value of 15 volts.

[0027] It is understood that the characteristic parameters of the MOSFET body 1 are not limited to the values ​​mentioned above, and can be quite broad, for example: a withstand voltage of -200 volts to 250 volts and a current capability of 10 mA to 200 amperes. The MOSFET body 1 is not limited to an N-type MOSFET, and can be a P-type MOSFET.

[0028] It is worth mentioning that the MOSFET body 1 is not limited to the aforementioned silicon-based trench MOSFET, but can also be IGBT (Insulated Gate Bipolar Transistor), SJ (Super Junction) MOSFET, SGT (Shielded Gate Transistor) MOSFET, SiC (Silicon Carbide) MOSFET or GAN (Gallium Nitride) HMET (High Electron Mobility Transistors).

[0029] The following describes in detail the wafer manufacturing process of the power MOSFET 10 of the present invention, taking the MOSFET body 1 as an example of a trench MOSFET.

[0030] See Figure 4 The diagram illustrates the basic material structure of a trench MOS, which consists of a substrate layer 101 and an epitaxial layer 102, which can be either N-type or P-type, and is defined as type I doping.

[0031] See Figure 5 The diagram illustrates the key manufacturing steps of a trench MOS, with the MOS body 103 formed on the epitaxial layer 102. Specifically, these steps include photolithography, trench etching, gate oxide growth, polysilicon filling of the gate trench, and surface planarization.

[0032] See Figure 6 This illustrates the MOS channel doping 104, where the doping type is opposite to the substrate type and is defined as type II doping. The channel doping simultaneously provides doping protection for the gate protection region and the area beneath the gate resistor region to be fabricated.

[0033] See Figure 7 The diagram illustrates the deposition of an isolation oxide layer 105, a polysilicon layer 106, and the second type of doping of the polysilicon layer 106.

[0034] See Figure 8 The diagram illustrates the photolithography and etching of the aforementioned polysilicon layer 106 and isolation oxide layer 105, resulting in the formation of an active region (including the gate and source of the MOS body 103; the drain of the MOS body 1 is formed on the back side of the substrate layer 101), an internal gate resistor 107, an external gate resistor 108, and a gate protection Zener diode pair 109. The internal gate resistor 107, the external gate resistor 108, and the gate protection Zener diode pair 109 are formed on the same polysilicon layer 106. See also... Figure 11 The diagram shows the top view of the external gate resistor 108 and the gate protection Zener diode pair 109.

[0035] See Figure 9 The diagram illustrates photolithography and the implantation and propagation of first-type doping ions into the MOS host 103, the external gate resistor 108, and the gate protection Zener diode pair 109, resulting in an alternating N / P ring-shaped doping distribution in the gate protection Zener diode pair 109. Specifically, the internal gate resistor 107 is either undoped or entirely doped with first-type doping; the external gate resistor 108 is doped with first-type doping. See also... Figure 12 The diagram shows the top view of the external gate resistor 108 and the gate protection Zener diode pair 109.

[0036] See Figure 10 The diagram illustrates the deposition and etching of the isolation layer, the deposition and etching of the metal interconnects, the external gate resistor 108, and the gate protection Zener diode pair 109, all formed below the gate pad metal layer. The source metal 111, located above the interlayer dielectric 110, ensures source region connectivity. The internal gate resistor 107 is formed at the end of the gate bus (also known as the gate runner, gate channel, or gate finger) 112 of the MOSFET body 103, with the gate bus 112 connected to the gate trench and the internal gate resistor 107. The gate protection Zener diode pair connecting metals 113 and 113a are connected to the outside of the internal gate resistor 108 and the gate protection Zener diode 109. The external gate resistor 107 is connected to the gate pad metal layer, and the external gate resistor connecting metal 114 forms the gate contact point (also known as the gate pad).

[0037] It is understandable that the wafer fabrication of the aforementioned power MOSFET uses five photomasks, which are used to form the trench layer, the gate protection zone etching layer, the source injection layer, the metal etching layer, and the metal wiring layer, respectively.

[0038] Compared with the prior art, the power MOSFET 10 of the present invention forms a gate protection structure 2 consisting of an internal gate resistor 21 (or 107), an external gate resistor 22 (or 108), and a gate protection Zener diode pair 23 (or 109). The gate protection structure 2 is connected in series between the gate contact point 5 and the gate structure of the MOSFET body 1 (or 103). The gate protection structure 2 and the MOSFET body 1 (or 103) are organically combined, which can effectively protect the gate structure of the MOSFET from surge voltage impacts of various frequencies. This is beneficial to expanding the application range of power MOSFETs and meeting the ever-increasing miniaturization requirements of existing electronic products.

[0039] It should be understood that the above embodiments are only used to illustrate the technical solutions of the present invention, and are not intended to limit them. Those skilled in the art can modify the technical solutions described in the above embodiments, or make equivalent substitutions for some of the technical features; and these modifications and substitutions should all fall within the protection scope of the appended claims of the present invention.

Claims

1. A power MOSFET with gate surge protection function, characterized in that, include: Substrate layer; Epitaxial layer, located on the front side of the substrate layer; The MOS transistor body is formed on the epitaxial layer and has a channel structure, a source structure and a gate structure. The gate protection structure consists of an internal gate resistor, an external gate resistor, and a gate protection Zener diode pair; the internal gate resistor is formed at the end of the gate bus of the MOS transistor body; the external gate resistor and the gate protection Zener diode pair are formed below the gate pad metal layer. Specifically, the first end of the gate resistor is shorted to the gate bus of the MOS transistor body, the first end of the gate resistor and the first end of the gate protection Zener diode pair are both shorted to the second end of the gate resistor, the second end of the gate protection Zener diode pair is shorted to the source of the MOS transistor body, and the second end of the gate resistor is shorted to the gate pad metal layer.

2. The power MOSFET with gate surge protection function according to claim 1, characterized in that, The gate protection Zener diode pair consists of one or more pairs of back-to-back Zener diodes.

3. The power MOSFET with gate surge protection function according to claim 1, characterized in that, The gate internal resistor, the gate external resistor, and the gate protection Zener diode are formed on the same polysilicon layer.

4. The power MOSFET with gate surge protection function according to claim 3, characterized in that, The internal gate resistance is positioned closer to the gate of the MOS transistor body than the external gate resistance; the gate protection Zener diode is positioned around the external gate resistance.

5. The power MOSFET with gate surge protection function according to claim 1, characterized in that, The wafer area occupied by this gate protection structure is less than 5% larger than that occupied by a traditional power MOSFET without a gate protection structure.

6. The power MOSFET with gate surge protection function according to claim 1, characterized in that, The main body of the MOSFET is a trench MOSFET, IGBT, superjunction MOSFET, shielded gate trench MOSFET, silicon carbide MOSFET, or gallium nitride HMET.

7. The power MOSFET with gate surge protection function according to claim 1, characterized in that, The main body of this MOSFET is a trench MOSFET. The wafer fabrication of this power MOSFET uses five photomasks, which are used to form the trench layer, the gate protection zone etching layer, the source injection layer, the metal etching layer, and the metal wiring layer, respectively.

8. The power MOSFET with gate surge protection function according to claim 1, characterized in that, The main body of this MOSFET is an N-type MOSFET.

9. The power MOSFET with gate surge protection function according to claim 1, characterized in that, The main body of this MOSFET is a P-type MOSFET.

10. The power MOSFET with gate surge protection function according to claim 1, characterized in that, The source of the MOS transistor is formed on the epitaxial layer, and the drain of the MOS transistor is formed on the back side of the substrate.

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