Layout structure of double-groove SiC power cascade device
By optimizing the layout structure of SiC heterogeneous integrated power Cascode devices, adopting a dual-trench design and integrated gate wiring, the problem of electrode interruption by connection wiring is solved, realizing high current density and low cost SiC power Cascode devices.
Patent Information
- Application Number
- CN202511722037.X
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-11-21
- Publication Date
- 2026-02-24
AI Technical Summary
The layout of existing SiC heterogeneous integrated power Cascode devices has the problem of cutting off electrodes when integrating SiC JFETs and Si MOSFETs, resulting in low chip area utilization, reduced current density, and increased cost.
By adopting a dual-trench SiC power Cascode device layout structure, and by rationally designing the position and size relationship between the first cell structure and the second cell structure, and using a square wave form for the gate traces and a tree-branch structure for the deep trenches, the isolation and connection of the first cell structure and the second cell structure are achieved, forming an integrated structure.
It increases current density, reduces chip area, lowers production costs, and reduces parasitic effects.
Smart Images
Figure CN121568434A_ABST
Abstract
Description
Technical Field
[0001] This invention belongs to the field of semiconductor technology, specifically relating to a layout structure of a dual-trench SiC power cascode device. Background Technology
[0002] Heterogeneous integrated power cascode devices, formed by connecting Si MOSFETs and SiC JFETs in series, use Si MOSFETs to control the signal, while the series-connected SiC JFETs withstand reverse voltage. The low-voltage devices have lower parasitic capacitance and on-resistance, resulting in faster switching speeds. Combined with the voltage withstand advantage of high-voltage devices, the circuit maintains low losses even in high-frequency, high-voltage scenarios. Simultaneously, the cascode structure naturally suppresses the Miller effect, reducing voltage oscillations during switching and minimizing thermal stress concentration, thus improving long-term operational stability. Compared to all-high-voltage device solutions, low-voltage devices are less expensive and have lower switching losses. Furthermore, compared to all-low-voltage device solutions, no additional voltage protection circuitry is required, simplifying the design and reducing power consumption. Therefore, they are attracting increasing attention.
[0003] In existing layout structures, monolithic vertical SiC heterogeneous integrated power Cascode integrates SiC JFETs and Si MOSFETs on the same substrate. Due to the heterogeneity of Si and SiC materials, additional implantation and etching processes are required during device fabrication to achieve device interconnection. If square cells are used, the interconnect wiring will cut off the electrodes, requiring additional isolation layers and metal wiring processes to resolve this. If elongated cells are used, the MOSFET device channel width will be shortened, significantly reducing current density and sacrificing chip area utilization, which contradicts the high integration requirements of power devices and increases chip cost. Summary of the Invention
[0004] To address the aforementioned problems in the prior art, this invention provides a dual-trench SiC power cascode device layout structure. The technical problem to be solved by this invention is achieved through the following technical solution: This invention provides a dual-trench SiC power cascode device layout structure. The dual-trench SiC power cascode device layout structure is composed of several vertical distribution units, with deep trenches formed between adjacent vertical distribution units. Each vertical distribution unit is composed of several horizontal distribution units, each horizontal distribution unit including two first cell structures and two second cell structures, which are diagonally distributed. A pair of first cell structures and second cell structures are separated by deep trenches. The area of the first cell structure in each horizontal distribution unit is larger than the area of the second cell structure. All first cell structures and second cell structures in each vertical distribution unit are integrated through gate traces, with the first cell structures and second cell structures alternating in the gate trace connections. Both the first cell structure and the second cell structure are dual-groove SiC power cascode devices.
[0005] In one embodiment of the present invention, viewed from the top, in each horizontal distribution unit, the first cell structure is a long strip cell and the second cell structure is a square cell; in each horizontal distribution unit, the long side of the first cell structure is longer than the side length of the second cell structure, and the short side of the first cell structure is equal to the side length of the second cell structure.
[0006] In one embodiment of the present invention, the long side of the first cell structure in each lateral distribution unit is 1.0 μm to 2.0 μm longer than the side length of the second cell structure.
[0007] In one embodiment of the present invention, the length of the long side of the first cell structure in each lateral distribution unit is 6.4 μm to 8.4 μm.
[0008] In one embodiment of the present invention, from a top view, the gate traces of all first and second cell structures in each longitudinally distributed unit are in the form of square waves.
[0009] In one embodiment of the present invention, from a top view, the deep trenches formed between adjacent longitudinal distribution units have a tree branch structure; in any longitudinal distribution unit, for any transverse distribution unit: the tree branch structure on one side separates a pair of first cell structures and second cells in the transverse distribution unit, and the tree branch structure on the other side surrounds another pair of first cell structures and second cells.
[0010] In one embodiment of the present invention, the integrated structure of the first cell structure and the second cell structure in the gate wiring connection includes: Drain contact metal; SiC N+ substrate, located on drain contact metal; SiC N- epitaxial layer, located on SiC N+ substrate; The P-well is located within the SiC N-epitaxial layer in the intermediate region between the first and second cell structures. Si N-epitaxial layer, located on SiC N-epitaxial layer; The P-implantation region is located within the Si N-epitaxial layer in the region between the first and second cell structures, and is in contact with the corresponding P-well. The P+ injection region is located within the P- injection region in the middle region between the first and second cell structures, and is in contact with the corresponding P-well. The shallow N+ injection region is located in the P- injection region on both sides of the corresponding P+ injection region and does not contact the corresponding P-well. The deep N+ implantation region penetrates the Si N- epitaxial layers at both ends of the device and extends into the SiC N- epitaxial layer; Deep trenches are located in the deep N+ injection regions at both ends of the device; The shallow trench is in the step-shaped region between the first and second cell structures. The lowest region of the shallow trench extends through the P+ injection region to the upper surface of the P-well. The step region of the shallow trench extends through part of the P+ injection region and is flush with the lower surface of the shallow N+ injection region. The source contact metal is located on part of the P-well and P+ injection region within the shallow trench, and on the sidewalls of the P+ injection region and shallow N+ injection region within the shallow trench. The gate oxide layer is located on the Si N-epitaxial layer, P-implantation region, and shallow N+ implantation region between the deep trenches and shallow trenches at both ends of the device, and on the Si N-epitaxial layer, P-implantation region, and shallow N+ implantation region between the two shallow trenches in the middle of the device. The gate is located on the gate oxide layer, and its outer contour is smaller than that of the gate oxide layer.
[0011] In one embodiment of the present invention, the distance between the shallow N+ injection region and the deep trench is 1.5 μm to 2.0 μm.
[0012] In one embodiment of the present invention, the gate width between the two shallow trenches located in the middle of the device is 2.4 μm to 3.4 μm.
[0013] The beneficial effects of this invention are: The dual-trench SiC power cascode device layout structure proposed in this invention consists of several vertically distributed units, with deep trenches forming between adjacent vertically distributed units. Each vertically distributed unit consists of several horizontally distributed units, each horizontally distributed unit including two first cell structures and two second cell structures, which are diagonally distributed, with a pair of first and second cell structures separated by deep trenches. The area of the first cell structure in each horizontally distributed unit is larger than the area of the second cell structure. All first and second cell structures in each vertically distributed unit are connected by gate traces, with the first and second cell structures alternating in the gate trace connections. Both the first and second cell structures are dual-trench SiC power cascode devices. It can be seen that this invention, by rationally designing the position and size relationship of the first and second cell structures and changing the layout of the gate traces and deep trenches (e.g., the gate traces are in a square wave form, and the deep trenches are in a tree-branch structure), can increase current density and reduce the area of the final chip. Furthermore, compared to existing layout structures, the layout structure designed in this invention allows for a smaller chip area to achieve the same function, reducing parasitic effects and production costs.
[0014] The present invention will be further described in detail below with reference to the accompanying drawings and embodiments. Attached Figure Description
[0015] Figure 1 This is a schematic diagram of a dual-trench SiC power cascode device layout structure provided in an embodiment of the present invention; Figure 2 This is a schematic diagram of the lateral distribution unit in the layout structure of the dual-trench SiC power cascode device provided in this embodiment of the invention; Figure 3 This is provided by the embodiments of the present invention. Figure 2 A cross-sectional view of the central region along the AB tangent line; Figure 4 This is provided by the embodiments of the present invention. Figure 2 A cross-sectional view of the central region along the BA tangent line; Figure 5 This is provided by the embodiments of the present invention. Figure 2 A cross-sectional view of the central region along the CD line; Figure 6 This is provided by the embodiments of the present invention. Figure 2 A cross-sectional view of the central region along the EF tangent. Detailed Implementation
[0016] The present invention will be further described in detail below with reference to specific embodiments, but the implementation of the present invention is not limited thereto.
[0017] To improve current density, reduce chip area, and lower cost, please refer to [link / reference needed]. Figure 1 This invention provides a layout structure for a dual-trench SiC power cascode device. The layout structure comprises several vertically distributed units, with deep trenches forming between adjacent vertically distributed units. Each vertically distributed unit comprises several horizontally distributed units, each including two first cell structures and two second cell structures, arranged diagonally. A pair of first and second cell structures are separated by deep trenches. The area of the first cell structure in each horizontally distributed unit is larger than the area of the second cell structure. All first and second cell structures in each vertically distributed unit are integrated through gate traces, with the first and second cell structures alternating in the gate trace connections. Both the first and second cell structures are dual-trench SiC power cascode devices.
[0018] like Figure 2 As shown, from a top-down view, in each horizontally distributed unit, the first cell structure is a long strip cell and the second cell structure is a square cell; in each horizontally distributed unit, the long side of the first cell structure is longer than the side length of the second cell structure, and the short side of the first cell structure is equal to the side length of the second cell structure.
[0019] In this embodiment of the invention, the longer side of the first cell structure in each lateral distribution unit is 1.0 μm to 2.0 μm longer than the side length of the second cell structure; the length of the longer side of the first cell structure in each lateral distribution unit is 6.4 μm to 8.4 μm. For example, the side length of the second cell structure is 5.4 μm to 6.4 μm.
[0020] In this embodiment of the invention, viewed from a top-down perspective, the gate traces of all first and second cell structures in each vertically distributed unit are in the form of square waves. It should be noted that the gate traces are not limited to a square wave form; the illustration here focuses more on the gate trace configuration.
[0021] From a top view, the deep trenches formed between adjacent longitudinal distribution units in this embodiment of the invention have a tree-branch structure. Within any longitudinal distribution unit, for any transverse distribution unit: the tree-branch structure on one side separates a pair of first and second cells within that transverse distribution unit, while the tree-branch structure on the other side surrounds another pair of first and second cells. It should be noted that the deep trenches are not limited to a tree-branch structure; the more important illustration here is the isolation of the first and second cells within the transverse distribution unit by the deep trenches.
[0022] For ease of understanding, the embodiments of the present invention will... Figure 2 In the horizontally distributed unit shown, the cell structures are numbered 1, 2, 3, and 4 from left to right and top to bottom. Cells 1 and 4 are the first cell structures, and cells 2 and 3 are the second cell structures. Cross-sections are shown along AB, BA, CD, and EF lines from the central region, and the corresponding structural diagrams are as follows. Figure 3 , Figure 4 , Figure 5 , Figure 6 As can be seen, the first cell structure and the second cell structure in the gate wiring connection are both integrated structures.
[0023] Taking the integrated structure of the first cell structure and the second cell structure in the gate wiring connection under the AB tangent line in the central region as an example, the integrated structure of the first cell structure and the second cell structure in this gate wiring connection is as follows: Figure 3 As shown, the device includes: a drain contact metal 1; a SiC N+ substrate 2 located on the drain contact metal 1; a SiC N- epitaxial layer 3 located on the SiC N+ substrate 1; a P-well located within the SiC N- epitaxial layer 3 in the region between the first and second cell structures; a SiN- epitaxial layer 4 located on the SiC N- epitaxial layer 3; a P-implantation region located within the SiN- epitaxial layer 4 in the region between the first and second cell structures, and in contact with the corresponding P-well; a P+ implantation region located within the P-implantation region in the region between the first and second cell structures, and in contact with the corresponding P-well; a shallow N+ implantation region located within the P-implantation regions on both sides of the corresponding P+ implantation region, and not in contact with the corresponding P-well; and a deep N+ implantation region 6 penetrating the SiN- epitaxial layers 4 at both ends of the device, extending to the SiC N+ substrate 1. The device is located within the N-epitaxial layer 3; deep trenches 5, located within the deep N+ implantation regions 6 at both ends of the device; stepped shallow trenches, located in the middle region between the first and second cell structures, with the lowest region of the shallow trench extending through the P+ implantation region to the upper surface of the P-well, and the stepped region extending through a portion of the P+ implantation region and flush with the lower surface of the shallow N+ implantation region; source contact metal, located partly on the P-well and P+ implantation region within the shallow trench, and partly on the sidewalls of the P+ and shallow N+ implantation regions within the shallow trench, forming an ohmic contact; gate oxide layer 8, located on the Si N-epitaxial layer 4, P-implantation region, and shallow N+ implantation region between the deep and shallow trenches at both ends of the device, and on the Si N-epitaxial layer 4, P-implantation region, and shallow N+ implantation region between the two shallow trenches in the middle of the device; and gate 7, located on the gate oxide layer 8, with its outer contour smaller than that of the gate oxide layer 8.
[0024] To better understand the integrated structure of the first and second cell structures, the first cell structure numbered 1 includes a P-well 101, a P+ injection region 102, a shallow N+ injection region 103, a P- injection region 104, and a stepped shallow trench 105; the second cell structure numbered 2 includes a P-well 201, a P+ injection region 202, a shallow N+ injection region 203, a P- injection region 204, and a stepped shallow trench 205; the second cell structure numbered 3 includes a P-well 301, a P+ injection region 302, a shallow N+ injection region 303, a P- injection region 304, and a stepped shallow trench 305; and the first cell structure numbered 4 includes a P-well 401, a P+ injection region 402, a shallow N+ injection region 403, a P- injection region 404, and a stepped shallow trench 405. Figure 3 This illustrates the integrated structure of the first and second cell structures, corresponding to numbers 1 and 2. Figure 4 This illustrates the integrated structure of the first and second cell structures, corresponding to numbers 3 and 4. Figure 5 This illustrates the integrated structure of the first and second cell structures, corresponding to numbers 1 and 3. Figure 6 The diagram illustrates the integrated structure of the first and second cell structures, corresponding to numbers 2 and 4. Both the first and second cell structures have P-wells (101, 201, 301, 401) at their largest central regions. The overlapping region of the P-injection region (104, 204, 304, 404), the shallow N+ injection region (103, 203, 303, 403), and the Si N-epitaxial layer 4 below the gate 7 forms the MOSFET channel region.
[0025] In all the first and second cell structures of this invention: the P-wells (101, 201, 301, 401) have a depth of 1μm~1.5μm and a width of 1.9μm~2.4μm. The specifications of the P-wells (101, 201, 301, 401) depend on the specifications of the gate 7 and the widths of the shallow N+ implantation regions (103, 203, 303, 403) and deep N+ implantation regions; the P+ implantation regions (102, 202, 302, 402) have a depth of 0.5μm~0.8μm and a width of 0.3μm~1.0μm; the shallow N+ implantation regions (103, 203, 303, 403) have a depth of 0.2μm~0.7μm and a width of 0.5μm~1.0μm. The depth of the P-implanted regions (104, 204, 304, 404) is 0.7μm~1.5μm, and the width is 0.8μm~2.0μm; the depth of the deep N+ implanted regions 6 is 0.6μm~1.1μm, and the width is 1.0μm~2.0μm; the distance between the shallow N+ implanted regions (103, 203, 303, 403) and the deep trench 5 is 1.5μm~2.5μm; in order to minimize the cell area, the gate width between the two shallow trenches in the middle of the device in the integrated structure of the first cell structure and the second cell structure is 2.4μm~3.4μm. For example, the width of the shallow N+ implanted regions at both ends of the device is 0.2μm, the width of the P-implanted regions is 0.5μm, and the width of the Si N-epitaxial layer is 1.0μm~2.0μm.
[0026] It should be noted that, in Figure 2 The source contact metal width of the first and second cell structures in the lateral distribution unit shown is 2.0 μm, which is the smallest process size that can be achieved at present, ensuring that the cell area is as small as possible.
[0027] Based on the overall structure of the above-mentioned lateral distribution units, this embodiment of the invention also provides a method for fabricating a dual-groove SiC power cascode cell structure, specifically including the following steps: Step 1: Provide a SiC N+ substrate 2, and form a SiC N- epitaxial layer 3 on the SiC N+ substrate.
[0028] Step 2: P-wells (101, 201, 301, 401) are formed in the P-well region on the SiC N-epitaxial layer 3 by ion implantation of low-concentration Al elements.
[0029] Step 3: Grow SiN-epitaxial layer 4 on SiC N-epitaxial layer 3 by chemical vapor deposition (CVD).
[0030] Step 4: Low-concentration Al elements are implanted into the P-implantation region on the Si N-epitaxial layer 4 to form P-implantation regions (104, 204, 304, 404).
[0031] Step 5: In the P-implantation region (104, 204, 304, 404), high concentration of Al elements are implanted by ion implantation to form P+ implantation region (102, 202, 302, 402).
[0032] Step 6: In the N+ implantation region of the P-implantation region (104, 204, 304, 404), a higher concentration of P element is implanted by ion implantation to form a shallow N+ implantation region (103, 203, 303, 403).
[0033] Step 7: High-concentration P elements are implanted into the SiC N-epitaxial layer 3 and Si N-epitaxial layer 4 at both ends of the device to form a deep N+ implantation region 6.
[0034] Step 8: Create the active region graphic.
[0035] Step 9: Grow the gate oxide layer 8.
[0036] Step 10: Deposit a polysilicon gate to fabricate gate 7.
[0037] Step 11: Etch deep trench 5, etch gate 7 at deep N+ implantation region 6 up to Si N- epitaxial layer 4, clean back and front sides of material, deposit pure Ni with a thickness of 200nm, rapidly anneal at 1000℃ for 3min, and then wash away metal.
[0038] Step 12: Etch a stepped shallow trench (105, 205, 305, 405), and etch the gate 7 at the P+ implantation region (102, 202, 302, 402). The lowest region of the shallow trench extends through the P+ implantation region (102, 202, 302, 402) to the upper surface of the P-well (101, 201, 301, 401). The step region of the shallow trench extends through part of the P+ implantation region (102, 202, 302, 402) and is flush with the lower surface of the shallow N+ implantation region (103, 203, 303, 403). Deposit pure Ni and Cr with a thickness of 200 nm in the shallow trench (105, 205, 305, 405), perform rapid thermal annealing at 450°C for 5 min, and then wash away the metal.
[0039] Step 13: Fabricate source contact metal within stepped shallow trenches (105, 205, 305, 405) to form the source electrode.
[0040] Step Fourteen: Fabricate drain contact metal 1 on the lower surface of SiC N+ substrate 2 to form a drain and perform rapid thermal annealing.
[0041] Step 15: Fabricate the source and drain connection metal. Thus, the fabrication of the dual-groove SiC power cascode cell structure was completed. It should be noted that the specific implementation steps of the above preparation method can be implemented with reference to existing related technologies, and the embodiments of the present invention will not be described in detail here. In summary, the dual-trench SiC power cascode device layout structure proposed in this embodiment of the invention consists of several vertical distribution units, with deep trenches forming between adjacent vertical distribution units. Each vertical distribution unit consists of several horizontal distribution units, each horizontal distribution unit including two first cell structures and two second cell structures, which are diagonally distributed, with a pair of first and second cell structures separated by deep trenches. The area of the first cell structure in each horizontal distribution unit is larger than the area of the second cell structure. All first and second cell structures in each vertical distribution unit are connected by gate traces, with the first and second cell structures alternating in the gate trace connections. Both the first and second cell structures are dual-trench SiC power cascode devices. It is evident that by rationally designing the position and size relationship of the first and second cell structures, and altering the layout of the gate traces and deep trenches (e.g., the gate traces are in a square wave form, and the deep trenches are in a tree-branch structure), this invention can increase current density and reduce the area of the final chip. Furthermore, compared to existing layout structures, the layout structure designed in this invention allows for a smaller chip area to achieve the same function, reducing parasitic effects and production costs.
[0042] In the description of this invention, it should be understood that the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this invention, "a plurality of" means two or more, unless otherwise explicitly specified.
[0043] Although the invention has been described herein in conjunction with various embodiments, those skilled in the art, by reviewing the specification and accompanying drawings, will understand and implement other variations of the disclosed embodiments in carrying out the claimed invention. In the specification, the word "comprising" does not exclude other components or steps, and "a" or "an" does not exclude a plurality. While certain measures are described in different embodiments, this does not mean that these measures cannot be combined to produce good results.
[0044] The above description, in conjunction with specific preferred embodiments, provides a further detailed explanation of the present invention. It should not be construed that the specific implementation of the present invention is limited to these descriptions. For those skilled in the art, various simple deductions or substitutions can be made without departing from the concept of the present invention, and all such modifications and substitutions should be considered within the scope of protection of the present invention.
Claims
1. A layout structure for a dual-trench SiC power cascode device, characterized in that, The layout structure of the dual-trench SiC power cascode device consists of several vertical distribution units, with deep trenches formed between adjacent vertical distribution units. Each vertical distribution unit consists of several horizontal distribution units, each horizontal distribution unit including two first cell structures and two second cell structures. The first cell structures and second cell structures are diagonally distributed, and a pair of first cell structures and second cell structures are separated by deep trenches. The area of the first cell structure in each horizontal distribution unit is larger than the area of the second cell structure. All first cell structures and second cell structures in each vertical distribution unit are integrated into a single structure through gate traces, and the first cell structures and second cell structures alternate in the gate trace connections. Both the first cell structure and the second cell structure are dual-groove SiC power cascode devices.
2. The layout structure of the dual-trench SiC power cascode device according to claim 1, characterized in that, From a top-down view, in each horizontally distributed unit, the first cell structure is a long strip cell and the second cell structure is a square cell; in each horizontally distributed unit, the long side of the first cell structure is longer than the side of the second cell structure, and the short side of the first cell structure is equal to the side of the second cell structure.
3. The layout structure of the dual-trench SiC power cascode device according to claim 2, characterized in that, In each lateral distribution unit, the longer side of the first cell structure is 1.0 μm to 2.0 μm longer than the side of the second cell structure.
4. The layout structure of the dual-trench SiC power cascode device according to claim 3, characterized in that, The length of the long side of the first cell structure in each lateral distribution unit is 6.4 μm to 8.4 μm.
5. The layout structure of the dual-trench SiC power cascode device according to claim 1, characterized in that, Viewed from above, the gate traces of all first and second cell structures in each vertically distributed unit are in the form of square waves.
6. The layout structure of the dual-trench SiC power cascode device according to claim 1, characterized in that, From a top-down view, the deep trenches formed between adjacent longitudinal distribution units have a tree-branch structure; in any longitudinal distribution unit, for any transverse distribution unit: the tree-branch structure on one side separates a pair of first cell structures and second cells in the transverse distribution unit, while the tree-branch structure on the other side surrounds another pair of first cell structures and second cells.
7. The layout structure of the dual-trench SiC power cascode device according to claim 1, characterized in that, The integrated structure of the first cell structure and the second cell structure in the gate wiring connection includes: Drain contact metal; SiC N+ substrate, located on drain contact metal; SiC N- epitaxial layer, located on SiC N+ substrate; The P-well is located within the SiC N-epitaxial layer in the intermediate region between the first and second cell structures. Si N-epitaxial layer, located on SiC N-epitaxial layer; The P-implantation region is located within the Si N-epitaxial layer in the region between the first and second cell structures, and is in contact with the corresponding P-well. The P+ injection region is located within the P- injection region in the middle region between the first and second cell structures, and is in contact with the corresponding P-well. The shallow N+ injection region is located in the P- injection region on both sides of the corresponding P+ injection region and does not contact the corresponding P-well. The deep N+ implantation region penetrates the Si N- epitaxial layers at both ends of the device and extends into the SiC N- epitaxial layer; Deep trenches are located in the deep N+ injection regions at both ends of the device; The shallow trench is in the step-shaped region between the first and second cell structures. The lowest region of the shallow trench extends through the P+ injection region to the upper surface of the P-well. The step region of the shallow trench extends through part of the P+ injection region and is flush with the lower surface of the shallow N+ injection region. The source contact metal is located on part of the P-well and P+ injection region within the shallow trench, and on the sidewalls of the P+ injection region and shallow N+ injection region within the shallow trench. The gate oxide layer is located on the Si N-epitaxial layer, P-implantation region, and shallow N+ implantation region between the deep trenches and shallow trenches at both ends of the device, and on the Si N-epitaxial layer, P-implantation region, and shallow N+ implantation region between the two shallow trenches in the middle of the device. The gate is located on the gate oxide layer, and its outer contour is smaller than that of the gate oxide layer.
8. The layout structure of the dual-trench SiC power cascode device according to claim 7, characterized in that, The distance between the shallow N+ injection region and the deep trench is 1.5 μm to 2.5 μm.
9. The layout structure of the dual-trench SiC power cascode device according to claim 7, characterized in that, The gate width between the two shallow trenches in the middle of the device is 2.4μm~3.4μm.