Solar cell and preparation method thereof

Abstract

The invention relates to the field of photovoltaic technology, and discloses a solar cell and a preparation method thereof. The solar cell comprises a silicon substrate, wherein the back surface of the silicon substrate comprises first regions and second regions which are alternately arranged; the first dielectric layer is located in the first region; the first doping layer is positioned on one side, deviating from the silicon substrate, of the first dielectric layer; the second doping layer is located on the side, away from the first dielectric layer, of the first doping layer; wherein the crystallization rate of the first doping layer is greater than that of the second doping layer, and the thickness of the second doping layer is greater than that of the first doping layer. The passivation contact performance of the battery can be improved, and the conversion efficiency of the battery is improved.

Description

Technical Field

[0001] This application relates to the field of photovoltaic technology, specifically to solar cells and methods for their fabrication. Background Technology

[0002] Tunneling passivated back contact (TBC) solar cell technology is a novel solar cell structure that combines the passivation contact technology of TOPCon (Tunnel Oxide Passivated Contact) cells with the back contact structure of IBC (Interdigitated back contact) cells. TBC cells offer the advantages of high conversion efficiency and low degradation performance inherent in TOPCon cells with their tunneling passivated contact, while retaining the full back contact structure of IBC cells to effectively reduce photocurrent loss, thus achieving even higher conversion efficiency.

[0003] In TBC (Thin-Cell Batteries) cell structures, the high passivation quality and good contact of the doped polycrystalline silicon layer play a crucial role in improving cell efficiency. However, the passivation contact performance of the doped polycrystalline silicon layer in related technologies is still not ideal, and the efficiency of solar cells needs further improvement. Summary of the Invention

[0004] This application aims to address at least one of the technical problems existing in related technologies. To this end, this application proposes a solar cell and a method for its fabrication, which can improve the passivation contact performance of the cell and increase its conversion efficiency.

[0005] In a first aspect, this application provides a method for preparing a solar cell, comprising: A silicon substrate is provided, the back side of which includes alternating first and second regions; A first dielectric layer is formed in the first region of the silicon substrate; A first doped layer and a second doped layer are sequentially formed on the side of the first dielectric layer away from the silicon substrate; wherein the crystallinity of the first doped layer is greater than that of the second doped layer, and the thickness of the second doped layer is greater than that of the first doped layer.

[0006] According to the solar cell provided in this application, a first doped layer and a second doped layer are formed on the side of the first dielectric layer away from the silicon substrate, and the crystallinity of the first doped layer is greater than that of the second doped layer. This allows the first doped layer with a higher crystallinity to be composite passivated with the first dielectric layer, improving passivation contact performance, reducing the depth of doped atoms (such as phosphorus atoms) expanding into the silicon substrate, increasing minority carrier lifetime, and improving open-circuit voltage and short-circuit current, thereby improving cell conversion efficiency. Furthermore, the thickness of the second doped layer with a lower crystallinity is greater than that of the first doped layer with a higher crystallinity, avoiding risks such as film warping and ensuring process feasibility.

[0007] According to one embodiment of this application, the step of "sequentially forming a first doped layer and a second doped layer on the side of the first dielectric layer opposite to the silicon substrate" includes: A first silicon substrate, a second silicon substrate, and a third silicon substrate are sequentially formed on the side of the first dielectric layer away from the silicon substrate; wherein the first silicon substrate is formed under a first temperature and a first time, the second silicon substrate is formed under a second temperature and a second time, and the third silicon substrate is formed under a third temperature and a third time, wherein the first temperature and the third temperature are respectively greater than the second temperature, and the second time is respectively greater than the first time and the third time. The first silicon substrate, the second silicon substrate, and the third silicon substrate are subjected to diffusion treatment to form a first doped layer, a second doped layer, and a third doped layer, respectively. Remove the third doped layer.

[0008] According to one embodiment of this application, in the direction from the second doped layer to the first doped layer, the doping concentration of the second doped layer gradually decreases; and / or, the doping concentrations of the third doped layer, the second doped layer, and the first doped layer decrease sequentially.

[0009] According to one embodiment of this application, the first temperature is 600°C to 630°C; and / or, The second temperature is 550℃~590℃; and / or, The third temperature is 600℃~630℃.

[0010] According to one embodiment of this application, the first time is 150s~210s; and / or, The second time is 2900s~4100s; and / or, The third time is 160s~300s.

[0011] Secondly, this application provides a solar cell, comprising: A silicon substrate, the back side of which includes alternating first and second regions; A first dielectric layer is located in the first region; A first doped layer is located on the side of the first dielectric layer opposite to the silicon substrate; A second doped layer is located on the side of the first doped layer that is away from the first dielectric layer; Wherein, the crystallinity of the first doped layer is greater than that of the second doped layer, and the thickness of the second doped layer is greater than that of the first doped layer.

[0012] According to one embodiment of this application, the doping concentration of the second doped layer is greater than the doping concentration of the first doped layer.

[0013] According to one embodiment of this application, the doping concentration of the second doped layer gradually decreases in the direction from the second doped layer toward the first doped layer.

[0014] According to one embodiment of this application, the doping concentration of the first doped layer is less than 6 × 10⁻⁶. 20 cm -3 ; and / or, The doping concentration of the second doped layer is 6 × 10⁻⁶. 20 cm -3 ~7×10 20 cm -3 .

[0015] According to one embodiment of this application, the crystallinity of the first doped layer is 70%~85%; and / or, The crystallinity of the second doped layer is less than 50%.

[0016] According to one embodiment of this application, the thickness of the first doped layer is 4 nm to 25 nm; and / or, The thickness of the second doped layer is 100 nm to 220 nm; and / or, The total thickness of the first doped layer and the second doped layer is 120nm~240nm.

[0017] According to one embodiment of this application, the solar cell further includes: A second dielectric layer is located between the first doped layer and the second doped layer.

[0018] According to one embodiment of this application, the thickness of the second dielectric layer is less than the thickness of the first dielectric layer.

[0019] According to one embodiment of this application, the thickness of the first dielectric layer is 1.3 nm to 1.6 nm; and / or, The thickness of the second dielectric layer is 1 nm to 1.3 nm.

[0020] According to one embodiment of this application, the solar cell further includes: A third dielectric layer, wherein the third dielectric layer is located in the second region; A fourth doped layer is located on the side of the third dielectric layer away from the silicon substrate, and the doping type of the fourth doped layer is opposite to that of the first doped layer. A passivation layer covering the second doped layer and the fourth doped layer; A first metal electrode, which penetrates the passivation layer and is in contact with the second doped layer; The second metal electrode penetrates the passivation layer and is in contact with the fourth doped layer.

[0021] According to one embodiment of this application, the first dielectric layer and the third dielectric layer are tunneling layers, the first doped layer and the fourth doped layer are doped polycrystalline silicon layers, and the second doped layer is a doped microcrystalline silicon layer.

[0022] According to one embodiment of this application, the first dielectric layer is a tunneling layer, the first doped layer is a doped polycrystalline silicon layer, the second doped layer is a doped microcrystalline silicon layer, the third dielectric layer is an intrinsic amorphous silicon layer or a microcrystalline silicon layer, and the fourth doped layer is an amorphous doped layer or a microcrystalline doped layer.

[0023] According to one embodiment of this application, the back side of the silicon substrate further includes an isolation region located between the first region and the second region.

[0024] According to one embodiment of this application, the first region is an N-type doped region, the second region is a P-type doped region, and the width of the first region is smaller than the width of the second region.

[0025] The above-described one or more technical solutions in the embodiments of this application have at least one of the following technical effects: By forming a first doped layer and a second doped layer on the side of the first dielectric layer away from the silicon substrate, and the crystallinity of the first doped layer being greater than that of the second doped layer, the first doped layer with higher crystallinity is combined with the first dielectric layer for passivation, which improves the passivation contact performance, reduces the depth of doped atoms (such as phosphorus atoms) expanding into the silicon substrate, improves minority carrier lifetime, and increases open-circuit voltage and short-circuit current, thereby improving the cell conversion efficiency. Furthermore, the thickness of the second doped layer with lower crystallinity is greater than that of the first doped layer with higher crystallinity, avoiding risks such as film warping and ensuring process feasibility.

[0026] Additional aspects and advantages of this application will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of this application. Attached Figure Description

[0027] The above and / or additional aspects and advantages of this application will become apparent and readily understood from the description of the embodiments taken in conjunction with the following drawings, in which: Figure 1 A schematic flowchart illustrating the method for fabricating a solar cell according to an embodiment of this application; Figure 2 This is one of the structural schematic diagrams of a solar cell provided in the embodiments of this application; Figure 3 This is a second schematic diagram of the structure of a solar cell provided in an embodiment of this application. Detailed Implementation

[0028] The embodiments of this application are described in detail below, with examples of these embodiments shown in the accompanying drawings. However, unnecessary detailed descriptions may be omitted. For example, detailed descriptions of well-known matters and repetitive descriptions of practically identical structures may be omitted. This is to avoid unnecessarily lengthy descriptions and to facilitate understanding by those skilled in the art. Furthermore, the accompanying drawings and the following description are provided to enable those skilled in the art to fully understand this application and are not intended to limit the subject matter of the claims.

[0029] Unless otherwise defined, all technical and scientific terms used in this application have the same meaning as commonly understood by one of ordinary skill in the art to which this application pertains; the terminology used in this application is for the purpose of describing particular embodiments only and is not intended to limit this application; unless otherwise stated, the values ​​of the parameters mentioned in this application can be measured using various measurement methods commonly used in the art (e.g., they can be tested according to the methods given in the embodiments of this application).

[0030] The terms “comprising” and “having”, and any variations thereof, in the specification and claims of this application are open-ended expressions, meaning they include what is specified in this application but do not exclude other aspects.

[0031] In the description of this application, all figures disclosed herein, whether or not the words "approximately" or "about" are used, are approximate values. Each figure may vary by less than 10% or by a difference that is considered reasonable by one of the art, such as 1%, 2%, 3%, 4%, or 5%.

[0032] The "range" disclosed in this application is defined by a lower limit and an upper limit. A given range is defined by selecting a lower limit and an upper limit, which define the boundaries of a particular range. Ranges defined in this way can include or exclude endpoints and can be arbitrarily combined; that is, any lower limit can be combined with any upper limit to form a range. For example, if ranges of 60-120 and 80-110 are listed for a specific parameter, it is expected that ranges of 60-110 and 80-120 are also included. Furthermore, if minimum range values ​​of 1 and 2 are listed, and if maximum range values ​​of 3, 4, and 5 are listed, then the following ranges are all expected: 1-3, 1-4, 1-5, 2-3, 2-4, and 2-5. In this application, unless otherwise stated, the numerical range "ab" represents a shortened representation of any combination of real numbers between a and b, where a and b are real numbers. For example, the numerical range "0-5" indicates that all real numbers between "0-5" have been listed in this article; "0-5" is simply a shortened representation of these numerical combinations. Furthermore, when a parameter is stated as an integer ≥2, it is equivalent to disclosing that the parameter is, for example, an integer such as 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, etc.

[0033] Unless otherwise specified, all embodiments and optional embodiments of this application can be combined to form new technical solutions.

[0034] Unless otherwise specified, all technical features and optional technical features of this application may be combined to form new technical solutions.

[0035] The solar cells and their preparation methods provided in this application will be described in detail below with reference to the accompanying drawings, through specific embodiments and application scenarios.

[0036] Figure 1 This is a schematic flowchart illustrating the fabrication method of the solar cell provided in the embodiments of this application. The solar cell may include a TBC (TOPCon Back Contact) cell or an HTBC (heterojunction tunnel oxide passivated contact hybrid passivated back contact photovoltaic cells) cell. The solar cell may also include other types of cells, which are not specifically limited here.

[0037] like Figure 1 As shown, the method for preparing a solar cell provided in this application includes steps 110 to 150.

[0038] Step 110: Provide a silicon substrate, the back side of which includes alternating first and second regions.

[0039] Combination Figure 2 As shown, the doping type of silicon substrate 1 can be N-type or P-type. As an example, silicon substrate 1 can be an N-type silicon substrate.

[0040] The back side of the silicon substrate 1 may include a first region 11 and a second region 12, which are arranged alternately along a first direction. One of the first region 11 and the second region 12 is an N-type doped region, and the other is a P-type doped region. As an example, the first region 11 is an N-type doped region, and the second region 12 is a P-type doped region. The first region 11 and the second region 12 may form a height difference, such that the first region 11 and the second region 12 are spaced apart.

[0041] In some embodiments, the first region 11 is an N-type doped region, and the second region 12 is a P-type doped region. The width A1 of the first region 11 (i.e., the dimension of the first region 11 along the first direction) is smaller than the width A2 of the second region 12 (i.e., the dimension of the second region 12 along the first direction). The lengths of the first region 11 and the second region (i.e., the dimensions along the second direction, which is perpendicular to the first direction) can be the same, such that the area of ​​the first region 11 is smaller than the area of ​​the second region 12. By increasing the area ratio of the second region 12, the carrier collection capability is improved, further enhancing the battery conversion efficiency.

[0042] In some embodiments, the back side of the silicon substrate 1 may further include an isolation region 13, which is located between the first region 11 and the second region 12. The isolation region 13 separates the first region 11 and the second region 12 to prevent leakage current caused by short circuits.

[0043] Step 120: Form a first dielectric layer in a first region of the silicon substrate.

[0044] Combination Figure 2 As shown, a first dielectric layer 2 is formed in a first region 11 of a silicon substrate 1 using a thin film deposition process. The first dielectric layer 2 can be located in the entire first region 11 of the silicon substrate 1.

[0045] In some embodiments, the material of the first dielectric layer 2 may include one or more of silicon oxide, silicon carbide, silicon nitride, and silicon oxynitride.

[0046] In some embodiments, the thickness of the first dielectric layer 2 is 1.3 nm to 1.6 nm.

[0047] As an example, during the formation of the first dielectric layer 2, the pressure is 760 Torr, the temperature is 590 ℃~605 ℃ (e.g., 600 ℃), the oxygen flow rate is 20000 sccm~40000 sccm (e.g., 30000 sccm), and the time is 600 s~800 s (e.g., 600 s), resulting in a first dielectric layer 2 with a thickness of 1.5 nm. This ensures that the first dielectric layer 2 possesses good carrier transport and passivation properties.

[0048] Step 130: A first doped layer and a second doped layer are sequentially formed on the side of the first dielectric layer away from the silicon substrate; wherein the crystallinity of the first doped layer is greater than that of the second doped layer, and the thickness of the second doped layer is greater than that of the first doped layer.

[0049] Combination Figure 2 As shown, the crystallinity of the first doped layer 3 is greater than that of the second doped layer 4, that is, the crystallinity of the first doped layer 3 is set to be larger to ensure the passivation effect of the first doped layer 3, so that the first doped layer 3 and the first dielectric layer 2 are composite passivated, improving the passivation contact performance, and reducing the depth of doped atoms (such as phosphorus atoms) expanding into the silicon substrate 1, thereby improving minority carrier lifetime, increasing open circuit voltage and short circuit current, and thus improving battery conversion efficiency.

[0050] Furthermore, a high crystallinity of the doped layer can easily lead to risks such as film warping, resulting in low process feasibility. In this embodiment, the thickness of the second doped layer 4, which has a lower crystallinity, is greater than the thickness of the first doped layer 3, which has a higher crystallinity, to avoid risks such as film warping and ensure process feasibility.

[0051] In some embodiments, the step of "sequentially forming a first doped layer and a second doped layer on the side of the first dielectric layer away from the silicon substrate" includes: A first silicon substrate, a second silicon substrate, and a third silicon substrate are sequentially formed on the side of the first dielectric layer away from the silicon substrate; wherein the first silicon substrate is formed under a first temperature and a first time, the second silicon substrate is formed under a second temperature and a second time, and the third silicon substrate is formed under a third temperature and a third time, wherein the first temperature and the third temperature are respectively greater than the second temperature, and the second time is respectively greater than the first time and the third time. Diffusion treatment is performed on the first silicon substrate, the second silicon substrate, and the third silicon substrate to form the first doped layer, the second doped layer, and the third doped layer, respectively. Remove the third doped layer.

[0052] Combination Figure 2As shown, a first silicon substrate is formed on the side of the first dielectric layer 2 away from the silicon substrate 1 under a first temperature and a first time condition using a thin film deposition process, such as LPCVD (Low Pressure Chemical Vapor Deposition). A second silicon substrate is formed on the side of the first silicon substrate away from the first dielectric layer 2 under a second temperature and a second time condition using a thin film deposition process, such as LPCVD. A third silicon substrate is formed on the side of the second silicon substrate away from the first silicon substrate under a third temperature and a third time condition using a thin film deposition process, such as LPCVD.

[0053] The crystallinity of the first silicon substrate is greater than that of the second silicon substrate. That is, the crystallinity of the first silicon substrate is set to be larger so that the crystallinity of the first doped layer 3 formed subsequently is larger, so that the first doped layer 3 and the first dielectric layer 2 can be composite passivated, improving the passivation contact performance and reducing the depth of doped atoms expanding into the silicon substrate 1, thereby improving the minority carrier lifetime.

[0054] The crystallinity of the third silicon substrate is greater than that of the second silicon substrate, meaning that the crystallinity of the third silicon substrate is set to be relatively large, in order to ensure that the subsequent diffusion of doped atoms achieves a high surface concentration of the third doped layer.

[0055] In some embodiments, the first silicon substrate and the third silicon substrate may be polycrystalline silicon layers, and the second silicon substrate may be a microcrystalline silicon layer.

[0056] In some embodiments, the crystallinity of the first silicon substrate is 70% to 85%. This ensures the passivation effect of the first silicon substrate, facilitating the subsequent composite passivation of the first doped layer 3 and the first dielectric layer 2, improving passivation contact performance, reducing the depth of doped atoms expanding into the silicon substrate 1, and increasing minority carrier lifetime. Furthermore, the crystallinity of the first silicon substrate should not be too high to avoid increasing defect density.

[0057] In some embodiments, the crystallinity of the second silicon substrate is less than 50%. This ensures process feasibility.

[0058] In some embodiments, the crystallinity of the third silicon substrate is greater than 70%. This ensures that subsequent diffusion of dopant atoms achieves a high surface concentration.

[0059] Polycrystalline silicon layers prepared at high temperatures have high crystallinity, while those prepared at low temperatures have low crystallinity. The crystallinity of the first, second, and third silicon substrates can be adjusted by changing the temperatures used to form them. In this embodiment, the first and third temperatures are both higher than the second temperature, resulting in the crystallinity of the first and third silicon substrates being higher than that of the second silicon substrate.

[0060] In the process of forming the first silicon substrate, the second silicon substrate, and the third silicon substrate, the temperature is first raised to a first temperature, and the first silicon substrate is prepared at the first temperature. Then, the temperature is lowered to a second temperature, and the second silicon substrate is prepared at the second temperature. Then, the temperature is raised to a third temperature, and the third silicon substrate is prepared at the third temperature.

[0061] The relationship between the first temperature and the third temperature is not specifically limited; that is, the first temperature can be greater than, less than or equal to the third temperature.

[0062] In some embodiments, the first temperature is 600°C to 630°C. This ensures that the crystallinity of the prepared first silicon substrate meets the requirements (e.g., crystallinity of 70% to 85%).

[0063] In some embodiments, the second temperature is 550°C to 590°C. This ensures that the crystallinity of the prepared second silicon substrate meets the requirements (e.g., crystallinity less than 50%).

[0064] In some embodiments, the third temperature is 600°C to 630°C. This ensures that the crystallinity of the prepared third silicon substrate meets the requirements (e.g., crystallinity greater than 70%).

[0065] Preparing silicon substrates with high crystallinity requires high temperatures, which can easily lead to risks such as film warping and low process feasibility. In this embodiment, the crystallinity of the second silicon substrate is lower than that of the first silicon substrate, and the thickness of the second silicon substrate is greater than that of the first silicon substrate, thus avoiding risks such as film warping and ensuring process feasibility.

[0066] In addition, the thickness of the third silicon substrate can be set to be relatively small to ensure that the subsequent diffusion process can completely react the third silicon substrate into a highly doped third doped layer.

[0067] In some embodiments, the thickness of the first silicon substrate is 4 nm to 25 nm. This ensures that the first silicon substrate has a good passivation effect.

[0068] In some embodiments, the thickness of the second silicon substrate is 100nm to 220nm. This avoids risks such as film warping and ensures process feasibility.

[0069] In some embodiments, the thickness of the third silicon substrate is 10 nm to 50 nm. This ensures that the subsequent diffusion process can completely react the third silicon substrate into a highly doped third doped layer.

[0070] In some embodiments, the total thickness of the first silicon substrate, the second silicon substrate, and the third polycrystalline layer is 150 nm to 270 nm. The total thickness of the first silicon substrate and the second silicon substrate is 120 nm to 240 nm. The total thickness of the first silicon substrate and the second silicon substrate can be consistent with the thickness of the polycrystalline silicon layer in related technologies to ensure that the battery performance is not affected by the film thickness.

[0071] The longer the preparation time of the silicon substrate, the greater the thickness of the silicon substrate. The thickness of the first, second, and third silicon substrates can be adjusted by changing the preparation time. In this embodiment, the second time is longer than the first and second times, respectively, so that the thickness of the second silicon substrate is greater than the thickness of both the first and third silicon substrates.

[0072] The relationship between the first time and the third time is not specifically limited; that is, the first time can be greater than, less than or equal to the third time.

[0073] In some embodiments, the first time is 150s to 210s. This ensures that the thickness of the prepared first silicon substrate meets the requirements (e.g., a thickness of 4nm to 25nm).

[0074] In some embodiments, the second time is 2900s to 4100s. This ensures that the thickness of the prepared second silicon substrate meets the requirements (e.g., a thickness of 100nm to 220nm).

[0075] In some embodiments, the third time is 160s to 300s. This ensures that the thickness of the prepared third silicon substrate meets the requirements (e.g., a thickness of 10nm to 50nm).

[0076] As an example, in the process of forming the first silicon substrate, the reactant gas includes silane. The flow rates of silane at the furnace inlet and in the furnace are 200 sccm to 800 sccm, respectively, and the flow rate of silane at the furnace tail is 300 sccm to 1200 sccm. The pressure is 240 mTorr to 300 mTorr, the temperature is 600℃ to 630℃, and the time is 150 s to 210 s. This ensures that the crystallinity and thickness of the prepared first silicon substrate meet the requirements.

[0077] As an example, in the process of forming the second silicon substrate, the reactant gas includes silane. The flow rates of silane at the furnace inlet and in the furnace are 200 sccm to 800 sccm, respectively, and the flow rate of silane at the furnace tail is 300 sccm to 1200 sccm. The pressure is 240 mTorr to 300 mTorr, the temperature is 550℃ to 590℃, and the time is 2900 s to 4100 s. This ensures that the crystallinity and thickness of the prepared second silicon substrate meet the requirements.

[0078] As an example, in the process of forming the third silicon substrate, the reactant gas includes silane. The flow rates of silane at the furnace inlet and in the furnace are 200 sccm to 800 sccm, respectively, and the flow rate of silane at the furnace tail is 300 sccm to 1200 sccm. The pressure is 240 mTorr to 300 mTorr, the temperature is 600℃ to 630℃, and the time is 160 s to 300 s. This ensures that the crystallinity and thickness of the prepared third silicon substrate meet the requirements.

[0079] It should be noted that the low-pressure, high-temperature deposition method enables the continuous and uniform deposition of a dense silicon substrate. By adjusting the deposition temperature and time, a multi-layered, continuous variation in the crystallinity of the silicon substrate can be achieved, forming a first, second, and third silicon substrate, with the crystallinity of the first and third silicon substrates being greater than that of the second silicon substrate.

[0080] Silicon substrates with different crystallinities have significantly different effects on doping of doping sources. Combining silicon substrates with different crystallinities can effectively adjust the doping concentration of doping elements in the silicon substrate.

[0081] In some embodiments, the doping concentrations of the third doped layer, the second doped layer 4, and the first doped layer 3 decrease sequentially.

[0082] The first doped layer 3, the second doped layer 4, and the third doped layer have the same doping type, such as N-type. The doping source used in the diffusion process can include a phosphorus source, etc. The first doped layer 3 can be a doped polycrystalline silicon layer, the second doped layer 4 can be a doped microcrystalline silicon layer, and the third doped layer can be a phosphosilicate glass layer.

[0083] As an example, the first doped layer 3, the second doped layer 4, and the third doped layer are all N-type doped layers, with a phosphorus source as the doping source. Phosphorus diffusion is performed using the phosphorus source, and the third silicon substrate completely reacts to form a phosphorus-silicon glass layer. The third silicon substrate has a high crystallinity, and phosphorus diffusion enables high surface concentration doping. By adjusting the deposition parameters of the third silicon substrate, the phosphorus doping concentration and roughness can be adjusted.

[0084] The crystallinity of the second silicon substrate is less than that of the third silicon substrate, which can block the diffusion of phosphorus source, so that the concentration of phosphorus doping in the second silicon substrate is greater than that in the first silicon substrate, that is, the doping concentration of the second doped layer 4 is greater than that of the first doped layer 3.

[0085] In this embodiment, the doping concentration of the second doped layer 4 is greater than that of the first doped layer 3, which can achieve good field passivation effect and good ohmic contact, thereby improving the battery conversion efficiency.

[0086] In some embodiments, combined with Figure 2As shown, in the direction from the second doped layer 4 toward the first doped polycrystalline layer 3, the doping concentration of the second doped polycrystalline layer 4 gradually decreases.

[0087] The doping concentration of the second doped polycrystalline layer 4 can vary continuously or in a gradient manner (uniform or non-uniform gradient). The doping concentration in the second doped polycrystalline layer 4 is lower closer to the first doped layer 3 and higher further away from the first doped layer 3. The minimum doping concentration in the second doped layer 4 can be close to, but still greater than, the doping concentration of the first doped layer 3.

[0088] In this embodiment, the surface doping concentration of the second doped polycrystalline layer 4 is highest on the side opposite to the first doped polycrystalline layer 3, achieving good field passivation effect and good ohmic contact.

[0089] In some embodiments, the doping concentration of the first doped layer 3 is less than 6 × 10⁻⁶. 20 cm -3 The first doped layer 3 can have a uniform doping distribution.

[0090] In some embodiments, the doping concentration of the second doped layer 4 is 6 × 10⁻⁶. 20 cm -3 ~7×10 20 cm -3 The doping concentration of the second doped layer 4 can be 6 × 10⁻⁶. 20 cm -3 ~7×10 20 cm -3 The doping concentration of the second doped polycrystalline layer 4 on the side opposite to the first doped polycrystalline layer 3 can vary, and can approach 7 × 10⁻⁶. 20 cm -3 This achieves good field passivation and good ohmic contact.

[0091] In some embodiments, the doping concentration of the third doped layer is 9 × 10⁻⁶. 20 cm -3 ~1.5×10 21 cm -3 The third doped layer has a higher doping concentration to ensure that the second doped layer 4 has a higher doping concentration than the first doped layer 3, thus achieving good field passivation and good ohmic contact.

[0092] In some embodiments, during the phosphorus diffusion process, phosphorus diffusion is performed under conditions of 150 mBbar pressure and 860°C, and push-bonding oxidation is performed under conditions of 120 mBar pressure and 875°C.

[0093] By employing a wet etching process with hydrofluoric acid (HF) as the core reagent and combining it with an acid-base cleaning process, the third doped layer can be removed efficiently while protecting the structural integrity of the battery.

[0094] In this embodiment, the first doped layer 3 has a high crystallinity, which enables the first doped layer 3 to be composite passivated with the first dielectric layer 2, improving the passivation contact performance and preventing phosphorus atoms from expanding into the silicon substrate 1, thereby reducing the diffusion depth and improving minority carrier lifetime. Furthermore, the second doped layer 4 has a high doping concentration, achieving good field passivation and good ohmic contact, thus improving the battery conversion efficiency.

[0095] In some embodiments, the preparation method may further include: A third dielectric layer 5 is formed in the second region 12 of the silicon substrate 1; A fourth doped layer 8 is formed on the side of the third dielectric layer 5 away from the silicon substrate 1. The doping type of the fourth doped layer 8 is opposite to that of the first doped layer 3. A passivation layer 6 is formed covering the second doped layer 4, the fourth doped layer 8, and the isolation region 13; A first metal electrode 9 is formed that penetrates the passivation layer 6 and is in contact with the second doped layer 4; A second metal electrode 10 is formed that penetrates the passivation layer 6 and is in contact with the fourth doped layer 8.

[0096] In this design, the silicon substrate 1 can be an N-type silicon substrate, the first region 11 can be an N-type doped region, and the second region can be a P-type doped region. The first doped layer 3 and the second doped layer 4 can both be N-type doped, and the fourth doped layer 8 can be P-type doped.

[0097] Solar cells may include TBC cells or HTBC cells. In the case of solar cells including TBC cells, the first dielectric layer 2 and the third dielectric layer 5 are tunneling layers, the first doped layer 3 and the fourth doped layer 8 are doped polycrystalline silicon layers, and the second doped layer 4 is a doped microcrystalline silicon layer.

[0098] In the case of solar cells including HTBC cells, the first dielectric layer 2 is a tunneling layer, the first doped layer 3 is a doped polycrystalline silicon layer, the second doped layer 4 is a doped microcrystalline silicon layer, the third dielectric layer 5 is an intrinsic amorphous silicon layer or a microcrystalline silicon layer, and the fourth doped layer 8 is an amorphous doped layer or a microcrystalline doped layer.

[0099] In this embodiment, all doped film layers are disposed on the back surface, without obstructing the light-receiving surface, which maximizes the utilization of incident light, reduces optical loss, and further improves the conversion efficiency of the battery.

[0100] In some embodiments, before forming the second doped layer, the preparation method may further include: forming a second dielectric layer, the second dielectric layer being located between the first doped layer and the second doped layer.

[0101] Combination Figure 3 As shown, after the first doped layer 3 is formed, a thin film deposition process is used to form a second dielectric layer 14 on the side of the first doped layer 3 away from the first dielectric layer 2, and then a second doped layer 4 is formed on the side of the second dielectric layer 14 away from the first doped layer 3.

[0102] The first dielectric layer 2 and the second dielectric layer 14 can each be a tunneling layer. The material of the second dielectric layer 14 can include one or more of silicon oxide, silicon carbide, silicon nitride, and silicon oxynitride. The materials of the second dielectric layer 14 and the first dielectric layer 2 can be the same or different.

[0103] In this embodiment, a second dielectric layer 14 is provided between the first doped layer 3 and the second doped layer 4, which can further improve the blocking effect, reduce the depth of doped atoms (such as phosphorus atoms) expanding into the silicon substrate 1, and improve the battery conversion efficiency.

[0104] In some embodiments, the thickness of the second dielectric layer 14 is less than the thickness of the first dielectric layer 2. The thickness of the second dielectric layer 14 can be set to be thinner, which improves the barrier effect while avoiding excessive reduction in the depth of dopant atoms (such as phosphorus atoms) expanding into the silicon substrate 1, thus affecting the passivation effect.

[0105] In some embodiments, the thickness of the first dielectric layer 2 is 1.3 nm to 1.6 nm. Thus, the first dielectric layer 2 can constitute a tunneling layer to ensure that charge carriers pass through efficiently through the quantum tunneling effect and to ensure passivation.

[0106] In some embodiments, the thickness of the second dielectric layer 14 is 1 nm to 1.3 nm. Thus, reducing the thickness of the second dielectric layer 14 improves the barrier effect while avoiding excessive reduction in the depth of dopant atoms expanding into the silicon substrate 1, which would affect the passivation effect.

[0107] The steps of forming a first dielectric layer, a first silicon substrate, a second silicon substrate, and a third silicon substrate in the method for fabricating a solar cell provided in this application embodiment will be described in detail below. Steps 120 and 130 may include the following steps: (1) Start by opening the furnace door at atmospheric pressure.

[0108] (2) Enter the boat, with the time set at 240 s.

[0109] (3) Evacuate to 0 mTorr for 300 s.

[0110] (4) Heat up to the process temperature of 600 ℃ (the temperature range can be 590℃~605 ℃) for 800 s.

[0111] (5) Maintain constant temperature, keep the process temperature at 600 ℃, and maintain constant temperature for 300 s.

[0112] (6) Leak detection, the leak rate is required to be no more than 25 mTorr, the leak detection time is 60 s, and the temperature is 600 ℃; (7) Oxidation 1: The first dielectric layer is prepared by oxidation at atmospheric pressure. The pressure is 760 Torr, the temperature is 600 ℃ (the temperature range can be 590 ~ 605 ℃), the oxygen flow rate is 30000 sccm (the flow rate range can be 20000 ~ 40000 sccm), the time is 600 s (the time range can be 600 ~ 800 s), and the thickness of the tunneling SiO2 layer is 1.5 nm (the thickness range can be 1.3~1.6 nm).

[0113] (8) Oxidation 2: Oxidation continues in a sealed tube under normal pressure without oxygen supply, at a temperature of 600 ℃ and a time of 600 s (the time range can be 500 ~ 800 s).

[0114] (9) Evacuate the tube until the pressure inside the tube is 0 mTorr.

[0115] (10) Purge: Introduce N2 into the tube to purge the furnace tube and remove any O2 that may be present. The time is 60 s.

[0116] (11) Heat up to 620 ℃ (the temperature range can be 600 ~ 630 ℃) for 300 s.

[0117] (12) Maintain constant temperature at 620℃ for 100 s.

[0118] (13) Leak detection, the leak rate is required to be no more than 10 mTorr, the time is 60 s, and the temperature is 620 ℃.

[0119] (14) Pre-ventilation, pressure 260 mTorr (pressure range can be 240 ~ 300 mTorr), time 30 s, SiH4 flow rate at furnace mouth 350 sccm (flow rate range can be 200 ~ 800 sccm), 350 sccm in furnace (flow rate range can be 200 ~ 800 sccm), 1000 sccm at furnace tail (flow rate range can be 300 ~ 1200 sccm).

[0120] (15) Diffusion deposition, with pressure and flow rate consistent with step (14), time 180 s, to prepare the first silicon substrate with a thickness of 20 nm.

[0121] (16) Evacuate the tube and pass N2 through it for 60 s.

[0122] (17) Purge for 60 seconds.

[0123] (18) Cool down to the process temperature of 565 ℃ (the temperature range can be 550 ~ 590 ℃) for 1000 s.

[0124] (19) Maintain constant temperature, keep the process temperature at 565 ℃ for 200 s.

[0125] (20) Pre-ventilation, pressure 400 mTorr (pressure range can be 240 ~ 300 mTorr), time 30 s, SiH4 flow rate at furnace mouth 350 sccm (flow rate range can be 200 ~ 800 sccm), 350 sccm in furnace (flow rate range can be 200 ~ 800 sccm), 1000 sccm at furnace tail (flow rate range can be 300 ~ 1200 sccm).

[0126] (21) Diffusion deposition, with pressure and flow rate consistent with step (20), time 3500s, to prepare a second silicon substrate with a thickness of 180 nm.

[0127] (22) Evacuate the tube and pass N2 through it for 60 s.

[0128] (23) Purge for 60 seconds.

[0129] (24) Heat up and then cool down to the process temperature of 620 ℃ (range 600 ~ 630 ℃) for 600 s.

[0130] (25) Maintain constant temperature, keep the process temperature at 620 ℃ for 300 s.

[0131] (26) Pre-ventilate, with pressure and flow rate consistent with step (14), for 30 s.

[0132] (27) Diffusion deposition, with pressure and flow rate maintained in step (14), time 180 s, to prepare the third silicon substrate with a thickness of 20 nm.

[0133] (28) Evacuate the tube and pass N2 through it for 60 seconds.

[0134] (29) Purge for 60 seconds.

[0135] (30) Vacuuming, time 60 s.

[0136] (31) Vacuuming, time 60 s.

[0137] (32) The vacuum is broken in 90 seconds.

[0138] (33) Break the vacuum, time 150 s.

[0139] (34) Departure from the boat, with a time limit of 300 seconds.

[0140] (35) End, atmospheric pressure tube furnace door.

[0141] Among them, atmospheric pressure oxidation and diffusion deposition can be used as low-pressure chemical vapor deposition.

[0142] The overall structure of the solar cell prepared in this embodiment remains unchanged, and it can be prepared using existing equipment, with only the process method changed. By forming multiple silicon substrates with different crystallinities to achieve a highly doped shallow junction, phosphorus diffusion achieves high surface concentration doping while effectively preventing deep diffusion, improving minority carrier lifetime, reducing ohmic contact, and improving the conversion efficiency of the solar cell.

[0143] Accordingly, this application also provides a solar cell that can be fabricated using the solar cell fabrication method described in the above embodiments.

[0144] Figure 2 and Figure 3 This is a schematic diagram of the structure of a solar cell provided in an embodiment of this application. The solar cell may include a TBC cell or an HTBC cell. Other types of cells may also be included, but are not specifically limited here.

[0145] like Figure 2 and Figure 3 As shown, the solar cell provided in this application embodiment includes a silicon substrate 1, a first dielectric layer 2, a first doped layer 3, and a second doped layer 4.

[0146] The back side of the silicon substrate 1 includes alternating first regions 11 and second regions 12. One of the first regions 11 and the second region 12 is an N-type doped region, and the other is a P-type doped region. The doping type of the silicon substrate 1 can be either N-type or P-type. In some embodiments, the silicon substrate 1 is an N-type silicon substrate, the first region 11 is an N-type doped region, and the second region 12 is a P-type doped region. The first region 11 and the second region 12 can form a height difference, such that the first region 11 and the second region 12 are spaced apart.

[0147] The first dielectric layer 2 is located in a first region 11 of the silicon substrate 1. In some embodiments, the material of the first dielectric layer 2 may include one or more of silicon oxide, silicon carbide, silicon nitride, and silicon oxynitride.

[0148] The first doped layer 3 is located on the side of the first dielectric layer 2 facing away from the silicon substrate 1. The first doped layer 3 can be N-type, and the doping element can include phosphorus. The first doped layer 3 can be a single layer or a stacked structure. For example, the first doped layer 3 can include multiple doped sublayers stacked together.

[0149] The second doped layer 4 is located on the side of the first doped layer 3 that faces away from the first dielectric layer 2. The second doped layer 4 has the same doping type as the first doped layer 3. The doping type of the second doped layer 4 can be N-type, and the doping element of the second doped layer 4 can include phosphorus. The second doped layer 4 can be a single-layer structure or a stacked structure.

[0150] The crystallinity of the first doped layer 3 is greater than that of the second doped layer 4, and the thickness of the second doped layer 4 is greater than that of the first doped layer 3.

[0151] In this embodiment, the first doped layer 3 has a high crystallinity, which enables the first doped layer 3 to be composite passivated with the first dielectric layer 2, improving the passivation contact performance. This effectively prevents doped atoms (phosphorus atoms) from expanding into the silicon substrate 1, thereby reducing the expansion depth, increasing minority carrier lifetime, improving open-circuit voltage and short-circuit current, and thus improving battery conversion efficiency. Furthermore, doped layers with low crystallinity have higher process feasibility. In this embodiment, the thickness of the second doped layer with low crystallinity is greater than the thickness of the first doped layer with high crystallinity, avoiding risks such as film warping and ensuring process feasibility.

[0152] In some embodiments, the doping concentration of the second doped layer 4 is greater than the doping concentration of the first doped layer 3.

[0153] The second doped layer 4 has a higher doping concentration, which enables good field passivation and good ohmic contact, further improving the battery conversion efficiency.

[0154] In some embodiments, the doping concentration of the second doped layer 4 gradually decreases in the direction from the first doped layer 3 to the second doped layer 4.

[0155] The doping concentration of the second doped layer 4 can vary continuously or in a gradient manner (uniform or non-uniform gradient). The doping concentration in the second doped layer 4 is lower closer to the first doped layer 3 and higher further away from the first doped layer 3. The minimum doping concentration in the second doped layer 4 can be close to, but still greater than, the doping concentration of the first doped layer 3.

[0156] In this embodiment, the surface doping concentration of the second doped layer 4 on the side opposite to the first doped layer 3 is the highest, achieving good field passivation effect and good ohmic contact.

[0157] In some embodiments, the doping concentration of the first doped layer 3 is less than 6 × 10⁻⁶. 20 cm -3 The first doped layer 3 can have a uniform doping distribution.

[0158] In some embodiments, the doping concentration of the second doped layer 4 is 6 × 10⁻⁶. 20 cm -3 ~7×10 20 cm -3 The doping concentration of the second doped layer 4 can be 6 × 10⁻⁶. 20 cm -3 ~7×10 20 cm -3 The doping concentration of the second doped layer 4 on the side opposite to the first doped layer 3 can vary between these concentrations, and can approach 7 × 10⁻⁶. 20 cm -3 This achieves good field passivation and good ohmic contact.

[0159] In some embodiments, the crystallinity of the first doped layer 3 is 70% to 85%. The crystallinity of the first doped layer 3 can be set to be relatively large to ensure the passivation effect of the first doped layer 3, realize the composite passivation of the first doped layer 4 and the first dielectric layer 2, improve the passivation contact performance, reduce the depth of phosphorus diffusion into the silicon substrate 1, and improve minority carrier lifetime.

[0160] In some embodiments, the crystallinity of the second doped layer 4 is less than 50%. The crystallinity of the second doped layer 4 can be set to a small value to ensure carrier transport performance, and the fabrication of a polycrystalline silicon layer with low crystallinity results in low process complexity and low production cost.

[0161] In some embodiments, the thickness of the first doped layer 3 is 4 nm to 25 nm. This ensures that the first doped layer 4 has a good passivation effect.

[0162] In some embodiments, the thickness of the second doped layer is 100 nm to 220 nm. This ensures carrier transport performance.

[0163] In some embodiments, the total thickness of the first doped layer 3 and the second doped layer 4 is 120 nm to 240 nm. The total thickness of the first doped layer 3 and the second doped layer 4 can be consistent with the thickness of the doped polycrystalline silicon layer in related technologies to ensure that the battery performance is not affected by the film thickness.

[0164] In some embodiments, such as Figure 3 As shown, the solar cell also includes: The second dielectric layer 14 is located between the first doped layer 3 and the second doped layer 4.

[0165] The first dielectric layer 2 and the second dielectric layer 14 can each be a tunneling layer. The material of the second dielectric layer 14 can include one or more of silicon oxide, silicon carbide, silicon nitride, and silicon oxynitride. The materials of the second dielectric layer 14 and the first dielectric layer 2 can be the same or different.

[0166] In this embodiment, a second dielectric layer 14 is provided between the first doped layer 3 and the second doped layer 4, which can further improve the blocking effect, reduce the depth of doped atoms (such as phosphorus atoms) expanding into the silicon substrate 1, and improve the battery conversion efficiency.

[0167] In some embodiments, the thickness of the second dielectric layer 14 is less than the thickness of the first dielectric layer 2. The thickness of the second dielectric layer 14 can be set to be thinner, which improves the barrier effect while avoiding excessive reduction in the depth of dopant atoms (such as phosphorus atoms) expanding into the silicon substrate 1, thus affecting the passivation effect.

[0168] In some embodiments, the thickness of the first dielectric layer is 1.3 nm to 1.6 nm. Thus, the first dielectric layer 2 can constitute a tunneling layer to ensure that charge carriers pass through efficiently through the quantum tunneling effect and to ensure a passivation effect.

[0169] In some embodiments, the thickness of the second dielectric layer is 1 nm to 1.3 nm. Therefore, reducing the thickness of the second dielectric layer 14 improves the barrier effect while preventing excessive reduction in the depth of dopant atoms penetrating the silicon substrate 1, which would negatively impact the passivation effect.

[0170] In some embodiments, the back side of the silicon substrate 1 further includes an isolation region 13 located between the first region 11 and the second region 12. The isolation region 13 separates the first region 11 and the second region 12 to prevent leakage current caused by short circuits.

[0171] In some embodiments, the first region 11 is an N-type doped region, and the second region 12 is a P-type doped region. The width A1 of the first region 11 is smaller than the width A2 of the second region 12. The lengths of the first region 11 and the second region can be the same, such that the area of ​​the first region 11 is smaller than the area of ​​the second region 12.

[0172] This embodiment increases the area ratio of the second region 12 to improve the carrier collection capability and further improve the battery conversion efficiency.

[0173] In some embodiments, the solar cell further includes: The third dielectric layer 5 is located in the second region 12; The fourth doped layer 8 is located on the side of the third dielectric layer 5 away from the silicon substrate 1, and the doping type of the fourth doped layer 8 is opposite to that of the first doped layer 3. Passivation layer 6 covers the second doped layer 4 and the fourth doped layer 8; The first metal electrode 9 penetrates the passivation layer 6 and is in contact with the second doped layer 4; The second metal electrode 10 penetrates the passivation layer 6 and is in contact with the fourth doped layer 8.

[0174] In this design, the silicon substrate 1 can be an N-type silicon substrate, the first region 11 can be an N-type doped region, and the second region can be a P-type doped region. The first doped layer 3 and the second doped layer 4 can both be N-type doped, and the fourth doped layer 8 can be P-type doped.

[0175] Passivation layer 6 covers the second doped layer 4 and the fourth doped layer 8. Where a spacer region 13 exists between the first region 11 and the second region 12, passivation layer 6 also covers the isolation region 13 of the silicon substrate 1. Passivation layer 6 may include an aluminum oxide layer. The presence of passivation layer 6 can reduce surface defects, reduce carrier recombination during transport, and improve the passivation effect.

[0176] The solar cell may also include an antireflection layer. The antireflection layer is located on the side of the passivation layer 6 facing away from the silicon substrate 1. The antireflection layer may include silicon nitride (SiN). x ) layer, silicon oxynitride (SiO) x N y ) layer, silicon dioxide (SiO) x At least one of the following layers. It is understood that the antireflective layer can be SiO₂. x SiN x SiO x N y The antireflective layer can be a stacked layer or a single layer, and those skilled in the art can choose flexibly according to the actual application requirements. The antireflective layer can reduce light reflection, improve light absorption, and enhance the passivation effect.

[0177] The first metal electrode 9 penetrates the passivation layer 6 and the antireflection layer in the first region 11 and extends into the second doped layer 4, contacting the second doped layer 4 to reduce contact resistance and improve the electrical performance of the battery. The second metal electrode 10 penetrates the passivation layer 6 and the antireflection layer in the second region 12 and extends into the fourth doped layer 8, contacting the fourth doped layer 8 to reduce contact resistance and improve the electrical performance of the battery.

[0178] In this embodiment, all doped film layers are disposed on the back surface, without obstructing the light-receiving surface, which maximizes the utilization of incident light, reduces optical loss, and further improves the conversion efficiency of the battery.

[0179] In some embodiments, the first dielectric layer 2 and the third dielectric layer 5 are tunneling layers, the first doped layer 3 and the fourth doped layer 8 are doped polycrystalline silicon layers, and the second doped layer 4 is a doped microcrystalline silicon layer. Therefore, the solar cell can be a TBC cell.

[0180] In some embodiments, the first dielectric layer 2 is a tunneling layer, the first doped layer 3 is a doped polycrystalline silicon layer, the second doped layer 4 is a doped microcrystalline silicon layer, the third dielectric layer 5 is an intrinsic amorphous silicon layer or a microcrystalline silicon layer, and the fourth doped layer 8 is an amorphous doped layer or a microcrystalline doped layer. Thus, the solar cell can be an HTBC cell.

[0181] In some embodiments, the surface of the isolation region 13 is textured. This textured surface has a pyramidal structure. The textured surface of the isolation region 13 can improve carrier collection efficiency and enhance surface passivation.

[0182] In some embodiments, the second surface is textured, that is, the light-receiving surface of the silicon substrate 1 is textured, in order to reduce surface reflectivity and improve surface passivation effect.

[0183] In some embodiments, the surfaces of the first region 11 and the second region 12 are polished surfaces, which facilitates the formation of a good first dielectric layer 2 and a doped layer in the first region 11 and a good fourth doped layer 8 in the second region 12, thereby improving the passivation effect and the contact effect of the first metal electrode 9 and the second metal electrode 10, and thus improving the battery efficiency.

[0184] According to the solar cell of this application, a first doped layer 3 and a second doped layer 4 are provided on the side of the first dielectric layer 2 away from the silicon substrate 1, and the crystallinity of the first doped layer 3 is greater than that of the second doped layer 4. This allows the first doped layer 3 with higher crystallinity to be composite passivated with the first dielectric layer 2, thereby improving the passivation contact performance, reducing the depth of doped atoms (such as phosphorus atoms) expanding into the silicon substrate 1, improving minority carrier lifetime, and increasing open-circuit voltage and short-circuit current, thus improving the cell conversion efficiency. Furthermore, the thickness of the second doped layer 4 with lower crystallinity is greater than that of the first doped layer 3 with higher crystallinity, avoiding risks such as film warping and ensuring process feasibility.

[0185] This application also provides a photovoltaic module, including the solar cell in the above embodiments, which will not be described in detail here.

[0186] The photovoltaic module according to this application can improve the passivation contact performance of the battery, increase the battery conversion efficiency, and thus increase the power generation of the photovoltaic module.

[0187] In the description of this application, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. "First feature" and "second feature" may include one or more of the indicated feature.

[0188] In the description of this application, "A and / or B" can include any of the cases of A alone, B alone, or A and B, where A and B are merely examples and can be any technical feature connected by "and / or" in this application.

[0189] In this application, the order in which the steps are written does not imply a strict execution order and does not limit the implementation process. The specific execution order of each step should be determined by its function and possible internal logic. Unless otherwise specified, all steps in this application can be performed sequentially or randomly, preferably sequentially. For example, if the method includes steps (a) and (b), it means that the method may include steps (a) and (b) performed sequentially, or it may include steps (b) and (a) performed sequentially. For example, if the method may also include step (c), it means that step (c) can be added to the method in any order. For example, the method may include steps (a), (b), and (c), or it may include steps (a), (c), and (b), or it may include steps (c), (a), and (b), etc.

[0190] It should be noted that this application is not limited to the above-described embodiments. The above embodiments are merely examples, and any embodiments with the same structure and effect as the technical concept within the scope of this application are included in the technical scope of this application. Furthermore, various modifications that can be conceived by those skilled in the art to the embodiments, and other ways of constructing by combining some of the constituent elements of the embodiments, without departing from the spirit of this application, are also included in the scope of this application.

Claims

1. A method for preparing a solar cell, characterized in that, include: A silicon substrate is provided, the back side of which includes alternating first and second regions; A first dielectric layer is formed in the first region of the silicon substrate; A first doped layer and a second doped layer are sequentially formed on the side of the first dielectric layer away from the silicon substrate; wherein the crystallinity of the first doped layer is greater than that of the second doped layer, and the thickness of the second doped layer is greater than that of the first doped layer.

2. The method for preparing a solar cell according to claim 1, characterized in that, The step of "sequentially forming a first doped layer and a second doped layer on the side of the first dielectric layer facing away from the silicon substrate" includes: A first silicon substrate, a second silicon substrate, and a third silicon substrate are sequentially formed on the side of the first dielectric layer away from the silicon substrate; wherein the first silicon substrate is formed under a first temperature and a first time, the second silicon substrate is formed under a second temperature and a second time, and the third silicon substrate is formed under a third temperature and a third time, wherein the first temperature and the third temperature are respectively greater than the second temperature, and the second time is respectively greater than the first time and the third time. The first silicon substrate, the second silicon substrate, and the third silicon substrate are subjected to diffusion treatment to form a first doped layer, a second doped layer, and a third doped layer, respectively. Remove the third doped layer.

3. The method for preparing a solar cell according to claim 2, characterized in that, In the direction from the second doped layer toward the first doped layer, the doping concentration of the second doped layer gradually decreases; and / or, the doping concentrations of the third doped layer, the second doped layer, and the first doped layer decrease sequentially.

4. The method for preparing a solar cell according to claim 2, characterized in that, The first temperature is 600℃~630℃; and / or, The second temperature is 550℃~590℃; and / or, The third temperature is 600℃~630℃.

5. The method for preparing a solar cell according to any one of claims 2-4, characterized in that, The first time is 150s~210s; and / or, The second time is 2900s~4100s; and / or, The third time is 160s~300s.

6. A solar cell, characterized in that, The solar cell includes: A silicon substrate, the back side of which includes alternating first and second regions; A first dielectric layer is located in the first region; A first doped layer is located on the side of the first dielectric layer opposite to the silicon substrate; A second doped layer is located on the side of the first doped layer that is away from the first dielectric layer; Wherein, the crystallinity of the first doped layer is greater than that of the second doped layer, and the thickness of the second doped layer is greater than that of the first doped layer.

7. The solar cell according to claim 6, characterized in that, The doping concentration of the second doped layer is greater than that of the first doped layer.

8. The solar cell according to claim 7, characterized in that, In the direction from the second doped layer toward the first doped layer, the doping concentration of the second doped layer gradually decreases.

9. The solar cell according to claim 7, characterized in that, The doping concentration of the first doped layer is less than 6 × 10⁻⁶. 20 cm -3 ; and / or, The doping concentration of the second doped layer is 6 × 10⁻⁶. 20 cm -3 ~7×10 20 cm -3 .

10. The solar cell according to claim 6, characterized in that, The crystallinity of the first doped layer is 70%~85%; and / or, The crystallinity of the second doped layer is less than 50%.

11. The solar cell according to claim 6, characterized in that, The thickness of the first doped layer is 4 nm to 25 nm; and / or, The thickness of the second doped layer is 100 nm to 220 nm; and / or, The total thickness of the first doped layer and the second doped layer is 120nm~240nm.

12. The solar cell according to claim 6, characterized in that, The solar cell also includes: A second dielectric layer is located between the first doped layer and the second doped layer.

13. The solar cell according to claim 12, characterized in that, The thickness of the second dielectric layer is less than the thickness of the first dielectric layer.

14. The solar cell according to claim 13, characterized in that, The thickness of the first dielectric layer is 1.3 nm to 1.6 nm; and / or, The thickness of the second dielectric layer is 1 nm to 1.3 nm.

15. The solar cell according to any one of claims 6-14, characterized in that, The solar cell also includes: A third dielectric layer, wherein the third dielectric layer is located in the second region; A fourth doped layer is located on the side of the third dielectric layer away from the silicon substrate, and the doping type of the fourth doped layer is opposite to that of the first doped layer. A passivation layer covering the second doped layer and the fourth doped layer; A first metal electrode, which penetrates the passivation layer and is in contact with the second doped layer; The second metal electrode penetrates the passivation layer and is in contact with the fourth doped layer.

16. The solar cell according to claim 15, characterized in that, The first dielectric layer and the third dielectric layer are tunneling layers, the first doped layer and the fourth doped layer are doped polycrystalline silicon layers, and the second doped layer is a doped microcrystalline silicon layer.

17. The solar cell according to claim 15, characterized in that, The first dielectric layer is a tunneling layer, the first doped layer is a doped polycrystalline silicon layer, the second doped layer is a doped microcrystalline silicon layer, the third dielectric layer is an intrinsic amorphous silicon layer or a microcrystalline silicon layer, and the fourth doped layer is an amorphous doped layer or a microcrystalline doped layer.

18. The solar cell according to claim 15, characterized in that, The back side of the silicon substrate also includes an isolation region located between the first region and the second region.

19. The solar cell according to claim 15, characterized in that, The first region is an N-type doped region, the second region is a P-type doped region, and the width of the first region is smaller than the width of the second region.

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