Polycrystalline silicon etching method and semiconductor process equipment

Abstract

The invention provides a polycrystalline silicon etching method and semiconductor process equipment, relates to the technical field of semiconductor manufacturing, and is designed for solving the problem that the surface roughness is large after polycrystalline silicon is removed through dry etching. The polycrystalline silicon etching method comprises the following steps: providing a semiconductor device, wherein the semiconductor device comprises a substrate, a gate oxide layer formed on the upper surface of the substrate and a polycrystalline silicon layer formed on the upper surface of the gate oxide layer; a dry etching step for etching the polycrystalline silicon layer; and a purging step in which the purge gas comprises a hydrogen-containing gas and an inert gas. According to the method, the surface roughness after the polycrystalline silicon is removed can be reduced.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing technology, and more specifically, to a polysilicon etching method and semiconductor process equipment. Background Technology

[0002] In the process of replacing the metal gate, a dummy gate structure is usually formed first using polysilicon material. After high-temperature processes such as source / drain ion implantation and annealing, the dummy gate structure is removed by selective dry etching to form a cavity structure for filling the high-k dielectric and metal gate.

[0003] After undergoing high-temperature processes such as source / drain ion implantation and annealing, the physical and chemical properties of the top of the dummy gate structure have changed significantly, forming an amorphous and difficult-to-etch hardened layer. During the etching process, factors such as uneven reaction rates between plasma and hardened polycrystalline silicon, excessive anisotropy, and micro-loading effects often lead to increased surface roughness at the interface between the dummy gate structure and the pseudo-gate oxide layer after etching. This results in defects in the final device structure and significantly reduces device performance. Summary of the Invention

[0004] The first objective of this invention is to provide a polysilicon etching method to solve the technical problem of high surface roughness after removing polysilicon using dry etching.

[0005] The polysilicon etching method provided by this invention includes: A semiconductor device is provided, the semiconductor device comprising a substrate, a gate oxide layer formed on a surface of the substrate, and a polysilicon layer formed on a surface of the gate oxide layer; A dry etching step is performed to etch the polysilicon layer; and The purging step involves purging gases, including hydrogen-containing gases and inert gases.

[0006] Furthermore, in the dry etching step, the etching gas includes nitrogen trifluoride, wherein the flow rate of nitrogen trifluoride is 450–550 sccm.

[0007] Furthermore, in the dry etching step, the process pressure is 5 to 7 Torr.

[0008] Furthermore, in the purging step, the process pressure is 0.

[0009] Furthermore, the dry etching step includes multiple sub-etching steps, and the purging step includes multiple sub-purging steps, with the multiple sub-etching steps and the multiple sub-purging steps performed alternately.

[0010] Furthermore, in the dry etching step, a portion of the etching gas is introduced from the center of the semiconductor device, and a portion of the etching gas is introduced from the edge of the semiconductor device.

[0011] The beneficial effects of the polysilicon etching method of this invention are: In this polysilicon etching method, by adding a purging step to the dry etching step, the hydrogen-containing gas in the purging gas can be utilized. After the polysilicon layer is etched, the free radicals rapidly combine with the numerous dangling bonds exposed on its surface to form stable Si-H bonds, thereby passivating the surface activity and preventing adverse reactions between the polysilicon layer and the air or residues in the process chamber after etching. On the other hand, the inert gas in the purging gas can also be used to blow away the byproducts generated on the surface of the polysilicon layer after etching in a timely manner, reducing the adhesion of byproducts on its surface and thus reducing surface roughness.

[0012] Therefore, by adding the above-mentioned purging step after the dry etching step of the polysilicon layer, not only can the byproducts attached to the surface of the polysilicon layer after etching be blown away in time to reduce surface roughness and make the surface of the etched polysilicon layer relatively flat, avoiding damage to the underlying gate oxide layer, but also a passivation layer can be formed on the surface of the polysilicon layer after etching to prevent the surface roughness from increasing due to adverse reactions between the polysilicon layer and air or residues in the process cavity. This reduces the loss and fluctuation of the critical dimension of the effective height of the metal gate after the metal gate is replaced, effectively improving the device yield.

[0013] The second objective of this invention is to provide a semiconductor process apparatus to solve the technical problem of high surface roughness after removing polysilicon using dry etching.

[0014] The semiconductor process equipment provided by the present invention includes a process chamber, an air intake structure, an upper electrode assembly, a lower electrode assembly, and a controller. The controller includes at least one processor and at least one memory. The memory stores a computer program, and when the computer program is executed by the processor, it implements the polysilicon etching method as described above.

[0015] Furthermore, the process cavity is provided with a device fixing device and a focusing ring. The device fixing device is used to support and fix the semiconductor device. The focusing ring surrounds the device fixing device, and the focusing ring is provided with air holes on the inner surface of the device fixing device. The air intake structure includes an edge air intake channel, which is opened on the focusing ring and communicates with the air holes.

[0016] Furthermore, the number of air holes is multiple, and the multiple air holes are arranged at intervals along the circumference of the focusing ring.

[0017] Furthermore, the opening degree of the vent is adjustable.

[0018] The beneficial effects of the semiconductor process equipment of this invention are: This semiconductor process equipment can realize the above-mentioned polysilicon etching method. Accordingly, this semiconductor process equipment has all the advantages of the above-mentioned polysilicon etching method, which will not be elaborated here. Attached Figure Description

[0019] To more clearly illustrate the technical solutions in the embodiments of the present invention or related technologies, the drawings used in the description of the embodiments or related technologies will be briefly introduced below. Obviously, the drawings described below are only embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on the provided drawings without creative effort.

[0020] Figure 1 A flowchart of a polysilicon etching method provided in an embodiment of the present invention; Figure 2 This is a front cross-sectional view of a semiconductor device using the polysilicon etching method provided in this embodiment of the invention before performing a dry etching step; Figure 3 This is a front cross-sectional view of a semiconductor device using the polysilicon etching method provided in this embodiment of the invention after performing a dry etching step. Figure 4 This is a partial structural front sectional view of a semiconductor process equipment provided in an embodiment of the present invention; Figure 5 This is a top sectional view of a partial structure of a semiconductor process apparatus with a small pore opening, provided in an embodiment of the present invention. Figure 6 This is a top sectional view of a partial structure of a semiconductor process equipment with a large pore opening, provided in an embodiment of the present invention.

[0021] Explanation of reference numerals in the attached figures: 010 - Semiconductor device; 101 - Silicon oxide; 102 - Low dielectric constant dielectric layer; 103 - Polysilicon layer; 104 - Gate oxide layer; 105 - Substrate; 100 - Lower electrode assembly; 200 - Device fixing device; 300 - Focusing ring; 310 - Air hole; 400 - Air intake structure; 410 - Edge air intake channel. Detailed Implementation

[0022] As semiconductor manufacturing technology continues to evolve towards smaller technology nodes, replacing metal gate processes has become a standard technique for manufacturing high-performance transistors. Among these techniques, the step of removing the polysilicon dummy gate structure using dry etching is crucial for successful replacement. Currently, the surface roughness after etching the polysilicon dummy gate structure is relatively large. On the one hand, the rough etched surface leads to localized unevenness in the etching process. In the protruding areas, the plasma may prematurely break down the polysilicon dummy gate structure, excessively attacking and thinning the underlying protective pseudo-gate oxide layer. Any damage to the pseudo-gate oxide layer will be directly transferred to the subsequently filled high-k dielectric and metal gate, resulting in increased gate leakage current, degradation of dielectric layer reliability, and even short-circuit failure of the device. On the other hand, it also leads to inconsistent bottom heights of the cavity structure formed after the dummy gate structure is etched, resulting in uneven heights of the subsequently filled high-k dielectric and metal gate. This not only causes severe fluctuations in device electrical parameters but also significantly reduces device performance uniformity and yield.

[0023] Based on this, one related technology proposes first using chlorine, hydrogen bromide, and oxygen at a relatively high bottom power to perform dry etching on the polysilicon within the deep trench, followed by using carbon tetrafluoride and chlorine at a lower bias power to perform a near-isotropic etching reaction on the polysilicon to obtain a relatively smooth polysilicon surface. However, hydrogen bromide and chlorine are highly toxic and corrosive, posing significant safety hazards, and the use of a bottom bias voltage can easily damage the device structure.

[0024] Related technology two proposes depositing an inorganic film layer on the polycrystalline silicon surface first, and then etching the side of the inorganic film layer away from the polycrystalline silicon to reduce the surface roughness of the polycrystalline silicon and avoid damage to the polycrystalline silicon. However, this technology requires depositing an inorganic film layer on the polycrystalline silicon surface first, and then removing the inorganic film layer in a subsequent process, which is cumbersome and inefficient.

[0025] Therefore, the purpose of this invention is to provide a polysilicon etching method and semiconductor process equipment to solve the technical problem of large surface roughness after removing polysilicon by dry etching.

[0026] To make the above-mentioned objects, features, and advantages of the present invention more apparent and understandable, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.

[0027] like Figure 1 As shown, this embodiment provides a polysilicon etching method, including: Step S100: As Figure 2As shown, a semiconductor device 010 is provided, wherein the semiconductor device 010 includes a substrate 105, a gate oxide layer 104 formed on the upper surface of the substrate 105, and a polysilicon layer 103 formed on the upper surface of the gate oxide layer 104.

[0028] In the metal gate replacement process, by removing the dummy gate structure formed by the polysilicon layer 103, a cavity can be formed in the space occupied by the polysilicon layer 103, which can then be filled using a high-k dielectric and a metal gate to form the desired device structure. After the metal gate replacement process is completed, the gate oxide layer 104 can separate the upper metal gate from the lower substrate 105, preventing current from flowing between the metal gate and the substrate 105, thus providing insulation.

[0029] Please continue to refer to Figure 2 The semiconductor device 010 may also include silicon oxide 101 and a low dielectric constant dielectric layer 102, wherein the low dielectric constant dielectric layer 102 serves as a sidewall of the metal gate, which can separate the metal gate from the source / drain region; and the silicon oxide 101 can isolate adjacent transistors.

[0030] Step S200: Dry etching step to etch polysilicon layer 103.

[0031] After the dry etching step, the structure of semiconductor device 010 is as follows: Figure 3 As shown, at this point, the polysilicon layer 103 is partially removed.

[0032] In the dry etching step, the etching gas may include nitrogen trifluoride, wherein the flow rate of nitrogen trifluoride is 450–550 sccm.

[0033] During the etching of the polysilicon layer 103, the micromask effect causes the byproduct AFS (Ammonium Fluoro Silicate) to accumulate at the peaks, resulting in a slower etching rate at the peaks and a faster etching rate at the troughs, thus increasing the surface roughness after etching. Simultaneously, the shadowing effect causes charged particles to be reflected / scattered at the troughs, increasing the ion flux and further accelerating the trough etching rate.

[0034] In this embodiment, by increasing the flow rate of nitrogen trifluoride, the etching gas flux at the crest position can be increased, thereby improving the etching rate at the crest position and making the etching rate at the crest position more consistent with the etching rate at the trough position, so as to improve the problem of increased surface roughness caused by uneven etching rates at the crest and trough positions.

[0035] Preferably, in the dry etching step, the flow rate of nitrogen trifluoride is 500 sccm.

[0036] In the dry etching step, the process pressure can be 5 to 7 Torr.

[0037] By increasing the process pressure in the dry etching step, the mean free path of the etch radicals can be significantly shortened, increasing the collisional ionization probability of the etching gas and generating a higher density plasma at the same power. Furthermore, the increased collisional ionization probability of the etching gas also disperses its energy and reduces its average energy. Simultaneously, the residence time of the etching gas is increased, allowing the etch radicals to fully contact the surface of the polysilicon layer 103 and undergo an etching reaction, thus making the surface of the polysilicon layer 103 more planar.

[0038] Preferably, in the dry etching step, the process pressure is 6 Torr.

[0039] In this embodiment, during the dry etching step, the center power of the upper electrode assembly can be 1500 W; the duty cycle can be 50%; the etching gas also includes argon and hydrogen. Argon is mainly used for physical etching through ion bombardment, and the argon flow rate is 4000 sccm. Hydrogen is mainly used to improve the etching selectivity by changing the surface chemical reaction, and the hydrogen flow rate is 2500 sccm.

[0040] Step S300: Purging step, wherein the purging gas includes hydrogen-containing gas and inert gas.

[0041] By adding a purging step to the dry etching process, on the one hand, the hydrogen-containing gas in the purging gas can be utilized. After the polysilicon layer 103 is etched, the free radicals rapidly combine with the large number of dangling bonds exposed on its surface to form stable Si-H bonds, thereby passivating the surface activity and preventing adverse reactions between the polysilicon layer 103 and the air or process chamber residues after etching. On the other hand, the inert gas in the purging gas can also be used to blow away the by-products generated on the surface of the polysilicon layer 103 after etching in a timely manner, reducing the adhesion of by-products on its surface and thus reducing surface roughness.

[0042] Therefore, by adding the above-mentioned purging step after the dry etching step of the polysilicon layer 103, not only can the byproducts attached to the surface of the polysilicon layer 103 after etching be blown away in time to reduce the surface roughness and make the surface of the polysilicon layer 103 after etching relatively flat, thus avoiding damage to the gate oxide layer 104 below, but also a passivation layer can be formed on the surface of the polysilicon layer 103 after etching to prevent the surface roughness from increasing due to adverse reactions between the polysilicon layer 103 and the air or residues in the process cavity. After the metal gate is replaced, the loss and fluctuation of the critical dimension of the effective height of the metal gate can be reduced, effectively improving the device yield.

[0043] In this embodiment, the hydrogen-containing gas in the purging gas can be hydrogen gas, and this arrangement can provide a large amount of... Free radicals are used to accelerate the bonding with dangling bonds exposed on the surface of the polysilicon layer 103, thereby improving the passivation efficiency of the polysilicon layer 103. The hydrogen flow rate can be 5000 scccm.

[0044] In this embodiment, the inert gas in the purging gas can be argon, and the flow rate of argon can be 3500 sccm.

[0045] In this embodiment, the process pressure is 0 during the purging step. This setting allows the process chamber to approach a vacuum state, which not only effectively removes byproducts adhering to the surface of the polysilicon layer 103 after etching, but also improves purging efficiency and shortens process time.

[0046] During the purging step, the center power of the upper electrode assembly can be 1500 W; the duty cycle is 0; and the flow rate of nitrogen trifluoride is 0.

[0047] In this embodiment, the process time for the dry etching step can be 30 seconds, and the process time for the purging step can be 60 seconds. Specifically, the 30-second dry etching step can be performed first, followed by the 60-second purging step.

[0048] In other embodiments, the dry etching step can be decomposed into multiple sub-etching steps, and the purge step can be decomposed into multiple sub-purge steps, so that the multiple sub-etching steps and multiple sub-purge steps are performed alternately.

[0049] Specifically, taking a total time of 30 s for the dry etching step and 60 s for the purging step as an example, the dry etching step is decomposed into 10 sub-etching steps and the purging step into 10 sub-purging steps, with each sub-etching step and each sub-purging step having an equal duration. That is, each sub-etching step requires 3 s and each sub-purging step requires 6 s. During the polysilicon etching process, one sub-etching step can be executed first, followed by one sub-purging step, then another sub-etching step, and so on. After 10 sub-etching steps and 10 sub-purging steps, the etching process of the polysilicon layer 103 is completed.

[0050] In the dry etching step, some of the etching gas can be introduced from the middle of the semiconductor device 010, and some of the etching gas can be introduced from the edge of the semiconductor device 010.

[0051] By allowing the etching gas to enter from different orientations of the semiconductor device 010, on the one hand, the distribution area of ​​the etching gas can be increased to ensure the uniformity of the etching gas distribution on the surface of the semiconductor device 010 and avoid uneven local etching rates. On the other hand, the etching gas can also reach the surface of the semiconductor device 010 more quickly to ensure the etching amount when multiple sub-etching steps and multiple sub-purge steps are performed alternately.

[0052] In addition, this embodiment also provides a semiconductor process apparatus, including a process chamber, an air intake structure 400, an upper electrode assembly, a lower electrode assembly 100, and a controller. The controller includes at least one processor and at least one memory, in which a computer program is stored. When the computer program is executed by the processor, it implements the polysilicon etching method described above.

[0053] This semiconductor process equipment can realize the above-mentioned polysilicon etching method. Accordingly, this semiconductor process equipment has all the advantages of the above-mentioned polysilicon etching method, which will not be elaborated here.

[0054] For example, the controller can be a host computer or a slave computer. The controller can open the valve of the air intake structure 400 to introduce the corresponding process gas into the process chamber; the controller can also evacuate the process chamber by controlling the air extraction structure (not shown in the figure), for example, by controlling the valve opening of the air extraction structure or the speed of the air extraction pump, to control the process pressure inside the process chamber and to discharge by-products.

[0055] Specifically, the semiconductor process equipment in this application embodiment can be an ICP (Inductively Coupled Plasma) etching machine.

[0056] like Figure 4 As shown, the process cavity is provided with a device fixing device 200 and a focusing ring 300. The device fixing device 200 is used to support and fix the semiconductor device 010. The focusing ring 300 surrounds the device fixing device 200, and the focusing ring 300 is provided with an air hole 310 on its inner surface above the device fixing device 200. The air intake structure 400 includes an edge air intake channel 410, which is opened on the focusing ring 300 and is connected to the air hole 310.

[0057] With the above settings, process gases (etching gases, purging gases) can enter through the edge inlet channel 410 and flow to the edge of the semiconductor device 010 through the air holes 310 opened on the inner surface of the focusing ring 300, thereby supplying gas to the edge of the semiconductor device 010.

[0058] In this embodiment, the air intake structure 400 may further include a central air intake channel (not shown in the figure), wherein the central air intake channel is located above the semiconductor device 010 and at the center of the semiconductor device 010.

[0059] In this embodiment, the device fixing device 200 can be an electrostatic chuck.

[0060] like Figure 5 and Figure 6 As shown, in this embodiment, the focusing ring 300 has multiple air holes 310, which are arranged at intervals along the circumference of the focusing ring 300.

[0061] This configuration allows process gases to be supplied to the edges of the semiconductor device 010 from multiple locations around its circumference, which not only further improves the gas intake efficiency but also ensures the uniformity of process gas distribution.

[0062] In this embodiment, the opening degree of the vent 310 is adjustable.

[0063] This setting allows the opening of the vent 310 to be increased during the purging step. At this time, since the process pressure in the process chamber is low, the flow rate of the purging gas flowing from the edge inlet channel 410 to the semiconductor device 010 can be increased, thereby allowing as much gas in the process chamber as possible to be drawn away.

[0064] It should be noted that since the purging step does not involve RF (Radio Frequency), it can prevent plasma from entering the lower electrode assembly 100 and causing corrosion due to the large opening of the pore 310.

[0065] Specifically, an annular grid plate (not shown in the figure) can be set in the inner ring of the focusing ring 300. The annular grid plate has multiple grid holes, which are respectively set one-to-one with multiple air holes 310. The shape and size of the grid holes can match the shape and size of the air holes 310. When a larger opening of the air holes 310 is required, the annular grid plate can be rotated around the vertical axis so that each grid hole is in a position opposite to each air hole 310. The grid holes avoid the air holes 310. At this time, the opening of the air holes 310 is its opening area, and the air holes 310 reach their maximum opening. When the opening of the air holes 310 needs to be reduced, the annular grid plate can continue to rotate around the vertical axis to partially block the air holes 310 using the solid structure between two adjacent grid holes, thereby reducing the flow area of ​​the air holes 310 and thus reducing the opening of the air holes 310.

[0066] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

[0067] Finally, it should be noted that in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the term "comprising" or any other variations thereof is intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0068] In the above embodiments, descriptions of directions such as "up", "down", and "side" are based on the accompanying drawings.

[0069] The above description of the disclosed embodiments enables those skilled in the art to make or use the invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the invention. Therefore, the invention is not to be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A polysilicon etching method, characterized in that, include: A semiconductor device (010) is provided, the semiconductor device (010) including a substrate (105), a gate oxide layer (104) formed on the upper surface of the substrate (105) and a polysilicon layer (103) formed on the upper surface of the gate oxide layer (104). A dry etching step is performed to etch the polysilicon layer (103); and The purging step involves purging gases, including hydrogen-containing gases and inert gases.

2. The polysilicon etching method according to claim 1, characterized in that, In the dry etching step, the etching gas includes nitrogen trifluoride, wherein the flow rate of nitrogen trifluoride is 450–550 sccm.

3. The polysilicon etching method according to claim 1, characterized in that, In the dry etching step, the process pressure is 5 to 7 Torr.

4. The polysilicon etching method according to claim 1, characterized in that, During the purging step, the process pressure is 0.

5. The polysilicon etching method according to claim 1, characterized in that, The dry etching step includes multiple sub-etching steps, and the purging step includes multiple sub-purging steps. The multiple sub-etching steps and the multiple sub-purging steps are performed alternately.

6. The polysilicon etching method according to claim 1, characterized in that, In the dry etching step, part of the etching gas is introduced from the center of the semiconductor device (010), and part of the etching gas is introduced from the edge of the semiconductor device (010).

7. A semiconductor process apparatus, comprising a process chamber, an inlet structure (400), an upper electrode assembly, a lower electrode assembly (100), and a controller, characterized in that, The controller includes at least one processor and at least one memory, the memory storing a computer program that, when executed by the processor, implements the polysilicon etching method as described in any one of claims 1-6.

8. The semiconductor process equipment according to claim 7, characterized in that, The process cavity is provided with a device fixing device (200) and a focusing ring (300). The device fixing device (200) is used to support and fix the semiconductor device (010). The focusing ring (300) surrounds the device fixing device (200), and the focusing ring (300) is provided with an air hole (310) on the inner surface of the device fixing device (200). The air intake structure (400) includes an edge air intake channel (410), which is opened on the focusing ring (300) and communicates with the air hole (310).

9. The semiconductor process equipment according to claim 8, characterized in that, The number of vents (310) is multiple, and the multiple vents (310) are arranged at intervals along the circumference of the focusing ring (300).

10. The semiconductor process equipment according to claim 8, characterized in that, The opening degree of the vent (310) is adjustable.

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