Processing method for improving electrical uniformity of InSb wafer
By combining directional cutting, X-ray orientation, and Hall effect testing, the electrical uniformity region was accurately measured, and non-uniform regions were removed using optical identification. This solved the problem of non-uniform electrical parameters in InSb wafers and achieved a significant improvement in electrical uniformity.
Patent Information
- Application Number
- CN202511531680.4
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-10-24
- Publication Date
- 2026-02-24
AI Technical Summary
During the growth of InSb wafers, the unstable solid-liquid interface leads to non-uniform electrical parameters, especially in large-scale FPA arrays, making it difficult to control the electrical uniformity of the wafers using traditional methods.
By combining directional cutting, X-ray orientation determination, etching, and Hall effect testing, the electrical uniformity region is accurately measured. Non-uniform regions are removed using optical identification and a chamfering machine, thus achieving high electrical uniformity of the wafer.
It significantly improves the electrical uniformity of InSb wafers, increasing the proportion of the electrical uniform region from 60%-80% to 90%-100%.
Smart Images
Figure CN121568563A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of wafer processing technology, and in particular to a processing method for improving the electrical uniformity of InSb wafers. Background Technology
[0002] Indium antimonide (InSb) is a group III-V compound semiconductor material with a zincblende structure. It exhibits near-100% quantum efficiency in the 3–5 μm mid-wave infrared band and is commonly used in the fabrication of mid-wave infrared detectors. InSb focal plane arrays (FPAs), due to their mature fabrication process, have been widely applied in civilian infrared systems related to infrared detection, achieving excellent results. Future large-scale, high-performance FPAs require larger sizes and higher-quality materials, which places higher demands on the radial electrical uniformity of InSb wafers.
[0003] During InSb crystal growth, the solid-liquid interface is often curved due to the constraint of the melt isotherms in the crucible. If the crystal is rapidly lifted during growth, a small flat plane appears at the solid-liquid interface. This plane is a (111) atomic close-packed plane, called a small plane. This small plane has a rapid lateral growth rate and an effective segregation coefficient much higher than that of the non-small plane region. This results in a much higher impurity concentration in the small plane region (4 to 10 times higher than that in the non-small plane region), which is the main reason for the poor uniformity of the radial electrical parameters of InSb crystals. This makes the performance uniformity of the chips fabricated on it poor, especially unsuitable for large-scale FPA arrays. Therefore, preparing InSb wafers with appropriate and uniform impurity concentrations is the key to preparing high-performance FPAs.
[0004] InSb single crystals are typically grown using the Czochralski method. Research and testing show that when the solid-liquid interface is convex from the crystal to the melt, the planar regions in the wafer are located at the wafer center; when the solid-liquid interface is concave from the crystal to the melt, the planar regions are located at the wafer edge. A flat solid-liquid interface is an unstable state, and it is difficult to maintain a flat and stable solid-liquid interface. A slightly convex solid-liquid interface is relatively stable, but it can lead to regions with low electrical performance at the wafer edge. The size and shape of the planar regions are irregular and change with the crystal shape. When the crystal growth axis deviates from the crystal... <111> When the crystal orientation changes, the small planar regions of a single crystal along the axial direction will deviate from the center, causing the crystal to... <111> After crystal orientation slicing, the facet regions are not located at the center of the wafer. Adjusting the distribution and size of these facets can effectively regulate material uniformity. However, the solid-liquid interface is affected by factors such as temperature, pulling speed, rotation speed, and crystal orientation; even minor disturbances can produce significant deviations. Therefore, obtaining wafers with high radial electrical uniformity by controlling the smooth solid-liquid interface throughout the crystallization process is difficult. Thus, a simple and rapid method is urgently needed to remove electrically non-uniform regions from the wafer and obtain highly electrically uniform wafers. Summary of the Invention
[0005] The technical solution adopted in this invention is to improve the electrical uniformity of InSb wafers. In view of this, this invention provides a processing method for improving the electrical uniformity of InSb wafers.
[0006] The present invention provides a processing method for improving the electrical uniformity of InSb wafers, comprising: Step S1: Select an n-type low-Te-doped InSb crystal segment within a preset size range, and perform directional cutting on the crystal segment. Use an X-ray orientation instrument to determine the crystal orientation and cutting angle of the cut slice. Adjust the cutting angle and repeat the cutting operation during subsequent cutting processes until the crystal orientation of the crystal cutting surface meets the preset requirements. Cut the crystal segment into a wafer and select a test wafer from the wafer. Step S2: Etch the selected test wafer to make the wafer surface smooth. After etching, rinse with deionized water and perform low-temperature minority carrier lifetime test to determine the corresponding minority carrier lifetime distribution map. Step S3: After the test piece is divided into small pieces, the Hall effect test is performed at liquid nitrogen temperature. The obtained test data is arranged according to the position of the small pieces in the original test piece to obtain the radial electrical parameter distribution map of the sample. Step S4: Overlay the radial electrical parameter distribution map of the sample with the minority carrier lifetime distribution map to obtain the precise range of the electrical uniformity region of the InSb wafer. Select the region where the sample electrical parameters meet the requirements and the minority carrier lifetime distribution is uniform and mark it. This region is the target chamfer region of the test wafer. Step S5: Mark the chamfer range of the number of wafers adjacent to the test wafer to be the same as the range of the test wafer; Step S6: Place the wafer with the marked target chamfer area on the optical recognition stage of the chamfering machine to display the area to be chamfered; Step S7: The chamfered area is changed according to the different positions of the wafer on the positioning device so that the chamfered area accurately covers the target chamfered area. The chamfering machine is run to cut and chamfer the non-uniform area to obtain an InSb wafer with high electrical uniformity.
[0007] In one embodiment, in step S1, the thickness of the cutting disc is 500–2000 μm. An X-ray orientation instrument is used to determine the crystal orientation and angle of the cutting disc. The cutting angle is adjusted and the above operation is repeated during subsequent cutting processes until the crystal orientation of the cut surface is [value missing]. <111> ±0.1°, the crystal segment is cut into wafers, and one test wafer is selected every 10 wafers.
[0008] In one embodiment, in step S2, a low-temperature minority carrier lifetime test is performed on the etched wafer to determine the corresponding minority carrier lifetime distribution map.
[0009] In one embodiment, in step S3, the test piece is divided into 5×5mm square pieces and then Hall effect testing is performed. The radial electrical parameter distribution map of the sample is obtained based on the position of the small pieces in the original test piece.
[0010] In one embodiment, in step S5, the chamfer range of the first 5 pieces and the last 5 pieces adjacent to the test piece is marked with the same range as the test piece.
[0011] In one embodiment, in step S6, the identification system will identify the outline, shape and size of the wafer and display the area to be chamfered, place the pre-made optical positioning aid under the wafer, and the identification system will identify the outline, shape and size generated by the superposition of the wafer and the positioning device.
[0012] By adopting the above technical solution, the present invention has at least the following advantages: The method provided by this invention, compared to wafers that have not undergone rigorous screening and processing, can accurately locate the electrical uniformity region of InSb wafers and improve on-chip electrical uniformity while trimming the wafer shape. The proportion of the wafer's electrical uniformity region is increased from 60%-80% to 90%-100%. Attached Figure Description
[0013] Various other advantages and benefits will become apparent to those skilled in the art upon reading the following detailed description of preferred embodiments. The accompanying drawings are for illustrative purposes only and are not intended to limit the scope of this application. Furthermore, the same reference numerals denote the same parts throughout the drawings. In the drawings: Figure 1 This is a schematic flowchart of a processing method for improving the electrical uniformity of InSb wafers according to an embodiment of the present invention. Figure 2 This is a flowchart of another processing method for improving the electrical uniformity of InSb wafers according to an embodiment of the present invention; Figure 3 A schematic diagram illustrating the process of selecting and cooperating with a positioning device for correcting and identifying contours in an InSb wafer region with high electrical uniformity according to an embodiment of the present invention. Detailed Implementation
[0014] To further illustrate the technical means and effects of the present invention in achieving its intended purpose, the present invention will be described in detail below with reference to the accompanying drawings and preferred embodiments.
[0015] While exemplary embodiments of the invention are shown in the accompanying drawings, it should be understood that the invention can be implemented in various forms and should not be limited to the embodiments set forth herein. Rather, these embodiments are provided to enable a more thorough understanding of the invention and to fully convey its scope to those skilled in the art. The invention will now be described in detail with reference to the accompanying drawings and embodiments.
[0016] This invention provides a processing method and apparatus for improving the electrical uniformity of InSb wafers, such as... Figure 1 As shown, it includes the following steps: Step S1: Select an n-type low-Te-doped InSb crystal segment within a preset size range, and perform directional cutting on the crystal segment. Use an X-ray orientation instrument to determine the crystal orientation and cutting angle of the cut slice. Adjust the cutting angle and repeat the cutting operation during subsequent cutting processes until the crystal orientation of the crystal cutting surface meets the preset requirements. Cut the crystal segment into a wafer and select a test wafer from the wafer. Step S2: Etch the selected test wafer to make the wafer surface smooth. After etching, rinse with deionized water to determine the corresponding minority carrier lifetime distribution map. Step S3: After the test piece is divided into small pieces, the Hall effect test is performed at liquid nitrogen temperature. The obtained test data is arranged according to the position of the small pieces in the original test piece to obtain the radial electrical parameter distribution map of the sample. Step S4: Overlay the radial electrical parameter distribution map of the sample with the minority carrier lifetime distribution map to obtain the precise range of the electrical uniformity region of the InSb wafer. Select the region where the sample electrical parameters meet the requirements and the minority carrier lifetime distribution is uniform and mark it. This region is the target chamfer region of the test wafer. Step S5: Mark the chamfer range of the number of wafers adjacent to the test wafer to be the same as the range of the test wafer; Step S6: Place the wafer with the marked target chamfer area on the optical recognition stage of the chamfering machine to display the area to be chamfered; Step S7: The chamfered area is changed according to the different positions of the wafer on the positioning device so that the chamfered area accurately covers the target chamfered area. The chamfering machine is run to cut and chamfer the non-uniform area to obtain an InSb wafer with high electrical uniformity.
[0017] Specifically, in step S1, the thickness of the cut sheet is 500–2000 μm. An X-ray orientation instrument is used to determine the crystal orientation and angle of the cut sheet. During subsequent cutting, the cutting angle is adjusted, and the above operation is repeated until the crystal orientation of the cut surface is... <111> ±0.1°, the crystal segment is cut into wafers, and one test wafer is selected every 10 wafers.
[0018] Specifically, in step S2, hydrofluoric acid and nitric acid are mixed in a preset ratio and concentration to prepare a selective corrosion solution.
[0019] Specifically, in step S3, the test piece is cut into small square pieces of 5×5mm.
[0020] Specifically, in step S5, the chamfer range of the first 5 pieces and the last 5 pieces adjacent to the test piece is marked to be the same as the range of the test piece.
[0021] Specifically, in step S6, the identification system will identify the outline, shape and size of the wafer, and display the area to be chamfered. The pre-made optical positioning aid will be placed under the wafer, and the identification system will identify the outline, shape and size generated by the superposition of the wafer and the positioning device.
[0022] The following will combine Figure 2 as well as Figure 3 The method provided in this embodiment will be described in detail.
[0023] The embodiments of the present invention focus on a complete set of technical methods to improve the electrical uniformity of InSb wafers, including the selection and preparation of the wafer to be tested, accurate measurement of the electrically uniform region, and rounding and chamfering removal of the electrically non-uniform region.
[0024] Selection and preparation of the wafer to be tested: Select InSb crystal segments with a length greater than 10 cm and a diameter greater than 45 mm, grown with low-doped Te n-type growth. Use a dicing machine to orient the qualified crystal segments, with a cut thickness of 500–2000 μm. Use an X-ray orienting instrument to determine the crystal orientation and angle of the cut wafers. Adjust the cutting angle and repeat the above operation during subsequent cutting processes until the crystal orientation of the cut surface is... <111> ±0.1°. The crystal segment is cut into wafers, and then a test wafer is selected every few wafers.
[0025] Precise Measurement of the Electrically Uniform Region: To avoid the insufficient radial resolution of direct electrical uniformity testing methods like Hall effect testing and the significant measurement errors caused by surface conditions in indirect methods like minority carrier lifetime testing, this method employs a combined approach to accurately measure the electrical uniform region of the wafer. First, a selective etching solution is prepared using hydrofluoric acid and nitric acid at a specific ratio and concentration. This solution is used to etch the selected test wafer until the surface is smooth. After etching, the sample is rinsed with deionized water, and then subjected to minority carrier lifetime testing at liquid nitrogen temperature. Next, the test wafer is diced into smaller pieces, and Hall effect testing is performed at liquid nitrogen temperature to obtain the radial electrical parameter distribution map of the sample. By superimposing the radial electrical parameter distribution map obtained from the Hall effect measurement with the minority carrier lifetime distribution map, the precise range of the electrical uniform region of the InSb wafer can be obtained.
[0026] Rounding and chamfering removal of electrically non-uniform regions: A region with acceptable electrical parameters and uniform minority carrier lifetime distribution is selected and marked; this region is the pre-chamfering region of the test wafer. The chamfering range of several wafers before and after the test wafer is aligned with the marked range of the test wafer. The chamfering machine uses optical recognition to identify the wafer contour and calculates and displays the pre-chamfering region. A pre-fabricated optical positioning aid is placed below the wafer; the recognition system identifies the contour, shape, and size resulting from the superposition of the wafer and the positioning device, and calculates and displays the new pre-chamfering region. The chamfering region can be changed according to the wafer's position on the positioning device to ensure the pre-chamfering region accurately covers the marked area. After completing the above adjustments, the chamfering machine is run to round and chamfer the non-uniform region, resulting in an InSb wafer with high electrical uniformity.
[0027] For ease of understanding, the process of improving the electrical uniformity of InSb wafers using this invention is detailed below: Step 1: Select an n-type low-Te-doped InSb crystal segment of a certain length and diameter. Use a cutting machine to orient the qualified crystal segment, with a cutting blade thickness of 500–2000 μm. Use an X-ray orienter to determine the crystal orientation and angle of the cutting blade. Adjust the cutting angle and repeat the above operation during subsequent cutting processes until the crystal orientation of the crystal cutting surface is... <111> ±0.1°. The crystal segment is cut into wafers, and one test wafer is selected every 10 wafers.
[0028] Step 2: Prepare a selective etching solution by mixing hydrofluoric acid and nitric acid in a certain ratio and concentration, and use it to etch the selected test wafer to make the wafer surface smooth. After etching, rinse with deionized water and perform minority carrier lifetime test on the sample at liquid nitrogen temperature.
[0029] Step 3: After cutting the test piece into 5×5mm square pieces, perform Hall effect testing at liquid nitrogen temperature. Arrange the test data according to the position of the small pieces in the original wafer to obtain the radial electrical parameter distribution map of the sample.
[0030] Step 4: By superimposing the radial electrical parameter distribution map of the sample obtained from the Hall effect measurement with the minority carrier lifetime distribution map, the precise range of the electrical uniformity region of the InSb wafer can be obtained. Select areas where the sample electrical parameters meet the requirements and the minority carrier lifetime distribution is uniform, and mark these areas; these areas are the target chamfered areas of the test wafer.
[0031] Step 5: Make the chamfer range of the first 5 pieces and the last 5 pieces adjacent to the test piece the same as the range marked on the test piece.
[0032] Step 6: Place the wafer with the marked target chamfer area on the optical recognition stage of the chamfering machine. The recognition system will identify the wafer's outline, shape, and size, and display the area to be chamfered. Place the pre-made optical positioning aid under the wafer. The recognition system will identify the outline, shape, and size created by the superposition of the wafer and the positioning device, and display the area to be chamfered.
[0033] Step 7: Depending on the position of the wafer on the positioning device, the chamfer area can be changed to ensure that the chamfer area accurately covers the electrically uniform area of the sample marked above and meets the requirements. After running the chamfering machine to cut and chamfer the non-uniform area, a high electrically uniform InSb wafer can be obtained.
[0034] Through testing, this embodiment has at least the following advantages: Compared to wafers that have not undergone rigorous screening and processing, this method can accurately locate the electrical uniformity region of InSb wafers and improve on-chip electrical uniformity while refining the wafer shape. The proportion of the wafer's electrical uniformity region has increased from 60%-80% to 90%-100%.
[0035] The embodiments of this application have been described above with reference to the accompanying drawings. However, this application is not limited to the specific embodiments described above. The specific embodiments described above are merely illustrative and not restrictive. Those skilled in the art can make many other forms under the guidance of this application without departing from the spirit and scope of the claims. All of these forms are within the protection scope of this application.
Claims
1. A processing method for improving the electrical uniformity of InSb wafers, characterized in that, include: Step S1: Select an n-type low-Te-doped InSb crystal segment within a preset size range, and perform directional cutting on the crystal segment. Use an X-ray orientation instrument to determine the crystal orientation and cutting angle of the cut slice. Adjust the cutting angle and repeat the cutting operation during subsequent cutting processes until the crystal orientation of the crystal cutting surface meets the preset requirements. Cut the crystal segment into a wafer and select a test wafer from the wafer. Step S2: Etch the selected test wafer to make the wafer surface smooth. After etching, rinse with deionized water and perform low-temperature minority carrier lifetime test to determine the corresponding minority carrier lifetime distribution map. Step S3: After the test piece is divided into small pieces, the Hall effect test is performed at liquid nitrogen temperature. The obtained test data is arranged according to the position of the small pieces in the original test piece to obtain the radial electrical parameter distribution map of the sample. Step S4: Overlay the radial electrical parameter distribution map of the sample with the minority carrier lifetime distribution map to obtain the precise range of the electrical uniformity region of the InSb wafer. Select the region where the sample electrical parameters meet the requirements and the minority carrier lifetime distribution is uniform and mark it. This region is the target chamfer region of the test wafer. Step S5: Mark the chamfer range of the number of wafers adjacent to the test wafer to be the same as the range of the test wafer; Step S6: Place the wafer with the marked target chamfer area on the optical recognition stage of the chamfering machine to display the area to be chamfered; Step S7: The chamfered area is changed according to the different positions of the wafer on the positioning device so that the chamfered area accurately covers the target chamfered area. The chamfering machine is run to cut and chamfer the non-uniform area to obtain an InSb wafer with high electrical uniformity.
2. The processing method for improving the electrical uniformity of InSb wafers according to claim 1, characterized in that, In step S1, the thickness of the cut sheet is 500–2000 μm. An X-ray orientation instrument is used to determine the crystal orientation and angle of the cut sheet. During subsequent cutting, the cutting angle is adjusted, and the above operation is repeated until the crystal orientation of the cut surface is... <111> ±0.1°, the crystal segment is cut into wafers, and one test wafer is selected every 10 wafers.
3. The processing method for improving the electrical uniformity of InSb wafers according to claim 2, characterized in that, In step S2, a low-temperature minority carrier lifetime test is performed on the etched wafer to determine the corresponding minority carrier lifetime distribution map.
4. The processing method for improving the electrical uniformity of InSb wafers according to claim 3, characterized in that, In step S3, the test piece is divided into 5×5mm square pieces and then Hall effect testing is performed. The radial electrical parameter distribution map of the sample is obtained based on the position of the small pieces in the original test piece.
5. The processing method for improving the electrical uniformity of InSb wafers according to claim 4, characterized in that, In step S5, the chamfer range of the first 5 pieces and the last 5 pieces adjacent to the test piece is marked to be the same as the range of the test piece.
6. The processing method for improving the electrical uniformity of InSb wafers according to claim 5, characterized in that, In step S6, the identification system will identify the outline, shape and size of the wafer, and display the area to be chamfered. The pre-made optical positioning auxiliary device is placed under the wafer, and the identification system will identify the outline, shape and size generated by the superposition of the wafer and the positioning device.