Integrated circuit, integrated circuit device, and method of manufacturing integrated circuit

Abstract

The embodiment of the invention provides an integrated circuit, an integrated circuit device and a method for manufacturing the integrated circuit. An integrated circuit includes a substrate having a front side and a back side opposite the front side. The substrate includes at least one active region on the front side. The circuitry is on a front side of the substrate, and the front side metallization layer is disposed over the circuitry. The back-side metallization layer is disposed below the back side of the substrate, and the first power pickup unit is located at the first side of the circuit. The first power pickup unit is configured to conduct one or more voltages from a back-side metallization layer to the front-side metallization layer, the back-side metallization layer being electrically coupled to the at least one active region.

Description

Technical Field

[0001] The embodiments of the present invention generally relate to the semiconductor field, and more specifically, to integrated circuits, integrated circuit devices, and methods of manufacturing integrated circuits. Background Technology

[0002] Typically, integrated circuits (ICs) include a power delivery or distribution network (PDN) for supplying power to the components within the IC. Some ICs include a front-side PDN with front-side conductive traces for supplying power, while others include a rear-side PDN with rear-side conductive traces for conducting power. This power PDN may be referred to as a "super power rail" (SPR). Furthermore, some ICs include a dual-side power rail structure that incorporates both front-side and rear-side PDNs. Dual-side power rail structures can reduce the IC's area and decrease the source resistance from the power source to the IC components due to the shunting of the front and rear-side power supplies, thereby increasing circuit speed. Summary of the Invention

[0003] An embodiment of the present invention provides an integrated circuit, comprising: a substrate having a front side and a rear side opposite to the front side, the substrate including at least one active region on the front side; a circuit located on the front side of the substrate; a front metallization layer disposed above the circuit; a rear metallization layer disposed below the rear side of the substrate; and a first power pickup unit unit located on a first side of the circuit and configured to conduct one or more voltages from the rear metallization layer to the front metallization layer, the rear metallization layer being electrically coupled to the at least one active region.

[0004] Another embodiment of the present invention provides an integrated circuit device, comprising: a substrate having a front side and a rear side opposite to the front side; a circuit located on the front side of the substrate; a first front metallization layer disposed on the substrate; a rear metallization layer disposed below the rear side of the substrate; and a first power pickup unit located on a first side of the circuit, and including a power feed via, a metal-covered drain contact, and a via-to-drain contact, the via-to-drain contact being electrically connected from the rear metallization layer to the first front metallization layer.

[0005] Another embodiment of the present invention provides a method for manufacturing an integrated circuit, comprising: providing a substrate having a front side and a rear side opposite to the front side; forming an active region on the front side of the substrate; forming an epitaxial active region in the active region; forming a metal-covered drain contact electrically connected to the active region; forming a via-to-drain contact electrically connected to the metal-covered drain contact; forming a front-side metallization layer above the via-to-drain contact and electrically connected to the via-to-drain contact; and forming a rear-side metallization layer below the rear side of the substrate and electrically coupled to at least one active region of the active region, wherein transistors are formed in a circuit on the front side of the substrate, and a first power supply unit is formed on a first side of the circuit to conduct one or more voltages from the rear-side metallization layer to the front-side metallization layer. Attached Figure Description

[0006] The various aspects of the invention can be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard industrial practice, the various components are not drawn to scale. In fact, for clarity of discussion, the dimensions of the various components may be arbitrarily increased or decreased.

[0007] Figure 1 This is a schematic illustration of a device including a circuit (such as a clock unit or clock circuit) and a power pickup unit or circuit according to some embodiments.

[0008] Figure 2 This is a schematic illustration of a clock unit and a power pickup unit disposed along one side of the clock unit, according to some embodiments.

[0009] Figure 3 This is a schematic illustration of a clock unit and a first power pickup unit and a second power pickup unit disposed along opposite sides of the clock unit, according to some embodiments.

[0010] Figure 4 This is a schematic illustration of a clock unit and a first power pickup unit and a second power pickup unit that are longer than the clock unit, according to some embodiments.

[0011] Figure 5 This is a schematic illustration of a clock unit and a first power pickup unit and a second power pickup unit located on the short side of the clock unit, according to some embodiments.

[0012] Figure 6 This is a schematic illustration of a clock unit and a first power pickup unit and a second power pickup unit located on the short side of the clock unit, according to some embodiments.

[0013] Figure 7This is a schematic illustration of a clock unit and power pickup units surrounding all sides of the clock unit according to some embodiments.

[0014] Figure 8 This is a schematic diagram illustrating circuit options according to some embodiments, including a reference circuit, a single-sided power pickup unit circuit, and a two-sided or dual-sided power pickup unit line.

[0015] Figure 9 This is a schematic illustration of a device including a substrate according to some embodiments, the substrate including an N-type well active region for a power supply voltage VDD and a P-type well active region for a power supply voltage VSS.

[0016] Figure 10 Including illustrative descriptions based on some embodiments Figure 9 The diagram shows a device comprising a VB-type power pickup structure, a first front metallization layer M0, and a first rear metallization layer BMO.

[0017] Figure 11 This is an illustrative description based on some embodiments. Figure 10 The line AA in the middle is intercepted Figure 10 Cross-sectional view of the device.

[0018] Figure 12 This is a schematic illustration of a device including a clock unit located next to or adjacent to a power pickup unit, according to some embodiments.

[0019] Figure 13 This is an illustrative description based on some embodiments along... Figure 12 The cross-sectional view of the VDD power pickup unit taken from line BB in the diagram.

[0020] Figure 14 This is a schematic diagram of a device according to some embodiments, the device including an FTV power pickup structure, a first front metallization layer M0, and a first rear metallization layer BMO for conducting power supply voltage VDD.

[0021] Figure 15 This is an illustrative description based on some embodiments. Figure 14 The line CC in the middle is cut off Figure 14 Cross-sectional view of the device.

[0022] Figure 16 This is a schematic diagram of a device according to some embodiments, the device including an FTV power pickup structure, a first front metallization layer M0, and a first rear metallization layer BMO for conducting power supply voltage VSS.

[0023] Figure 17 This is an illustrative description based on some embodiments. Figure 16The line DD in the middle is cut off Figure 16 Cross-sectional view of the device.

[0024] Figure 18 This is a schematic diagram of a device according to some embodiments, the device including an FTV power pickup structure, a first front metallization layer M0, and a first rear metallization layer BMO for conducting power supply voltage VDD.

[0025] Figure 19 This is an illustrative description based on some embodiments. Figure 18 EE cut-off in the middle Figure 18 Cross-sectional view of the device.

[0026] Figure 20 This is a schematic diagram of a device according to some embodiments, the device including an FTV power pickup structure, a first front metallization layer M0, and a first rear metallization layer BMO for conducting power supply voltage VSS.

[0027] Figure 21 This is an illustrative description based on some embodiments. Figure 20 The line FF in the middle is cut off Figure 20 Cross-sectional view of the device.

[0028] Figure 22 The diagram illustrates the characteristics of the VB-type power pickup unit and the FTV-type power pickup unit according to some embodiments.

[0029] Figure 23 This is a schematic illustration of a device according to some embodiments, the device including a clock unit and a power pickup unit surrounding all sides of the clock unit.

[0030] Figure 24 These are schematic diagrams illustrating a method for manufacturing an integrated circuit according to some embodiments.

[0031] Figure 25 This is a block diagram illustrating examples of computer systems configured to provide the devices (including electronic devices and semiconductor devices) and methods of this disclosure, according to some embodiments.

[0032] Figure 26 This is a block diagram of a semiconductor device manufacturing system and its related semiconductor device manufacturing process according to some embodiments. Detailed Implementation

[0033] This invention provides numerous different embodiments or examples for implementing various features of this disclosure. Specific examples of components and arrangements are described below to simplify the invention. Of course, these are merely examples and are not intended to limit the invention. For example, in the following description, forming a first component on or over a second component may include embodiments where the first and second components are formed in direct contact, and may also include embodiments where an additional component may be formed between the first and second components, such that the first and second components are not in direct contact. Furthermore, reference numerals and / or characters may be repeated in various instances of the invention. This repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0034] Furthermore, for ease of description, spatial relative terms such as "below," "under," "lower," "above," and "upper" may be used to describe the relationship between one element or component and another (or other elements or components) as shown in the figure. In addition to the orientation shown in the figure, spatial relative terms are intended to include different orientations of the device during use or operation. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptors used herein can be interpreted accordingly.

[0035] In circuits with a dual-side power rail structure, the voltage drop between the front and rear PDNs degrades performance due to uneven power distribution and high-resistance power pickup units or circuits. For example, front-to-back power pickup units formed in metal-over-drain (MD) and epitaxial layers increase resistance.

[0036] The disclosed embodiments include pickup units or circuits that reduce current-resistance (IR) voltage drop and improve wiring resources. The disclosed embodiments include different types of power pickup structures, such as rear-side via (VB) pickup structures and feed-through-via (FTV) pickup structures. The disclosed embodiments also include different placements of pickup units or structures next to circuits or units (such as clock units). In some embodiments, the power pickup unit is located on one side of the circuit or along one side of the circuit. In some embodiments, the power pickup unit is located on two opposite sides of the circuit or along both opposite sides. In some embodiments, the power pickup unit is located on all sides of the circuit.

[0037] The disclosed embodiments include an integrated circuit comprising a substrate having at least one active region and circuitry located on the front side of the substrate. A front metallization layer is disposed above the circuitry, and a rear metallization layer is electrically coupled to at least one active region and disposed below the rear side of the substrate. A first power pickup unit is located on a first side of the circuitry and configured to conduct one or more voltages from the rear metallization layer to the front metallization layer. In some embodiments, the integrated circuit includes a second power pickup unit located on a second side of the circuitry, opposite to the first side of the circuitry, and configured to conduct one or more voltages from the rear metallization layer to the front metallization layer.

[0038] In some embodiments, the integrated circuit includes a VB, an epitaxial layer, an MD contact, and a via-to-drain (VDR) contact, wherein a rear metallization layer is electrically connected to VB, VB is electrically connected to the epitaxial layer, the MD contact is electrically connected to the VDR contact, and the VDR contact is electrically connected to the front metallization layer. This allows voltage to be conducted between the rear and front metallization layers through VB, the epitaxial layer, the MD contact, and the VDR contact. In some embodiments, the integrated circuit includes an FTV, an MD contact, and a VDR contact, wherein a rear metallization layer is electrically connected to the FTV, the FTV is electrically connected to the MD contact, and the MD contact is electrically connected to the VDR contact. This allows voltage to be conducted between the rear and front metallization layers through the FTV, the MD contact, and the VDR contact. The MD contact is also electrically connected to the epitaxial layer.

[0039] The disclosed embodiments also include a device comprising a circuit located on the front side of a substrate, a front metallization layer disposed above the substrate, and a rear metallization layer disposed below the rear side of the substrate. A power pickup unit is located on one side of the circuit. The power pickup unit includes an FTV, MD contacts, and a VDR contact, which are electrically connected from the rear metallization layer to the front metallization layer. The MD contacts are located between epitaxial layers and are not electrically connected to the epitaxial layers.

[0040] Further disclosed embodiments include a method of manufacturing an integrated circuit, the method comprising forming a substrate having a front side and a rear side opposite to the front side; forming an active region on the front side of the substrate; forming a circuit on the front side of the substrate; forming a front metallization layer on the circuit; forming a rear metallization layer below the rear side of the substrate and electrically coupling it to at least one of the active regions; and forming a power pickup unit on one side of the circuit to conduct one or more voltages from the rear metallization layer to the front metallization layer.

[0041] Figure 1This is a schematic illustration of device 40 according to some embodiments. Device 40 includes circuitry 42, such as a clock unit or clock circuit, and power pickup unit or circuitry 44. In some embodiments, device 40 includes multiple circuits 42. In some embodiments, device 40 includes multiple power pickup units 44. In some embodiments, each circuit 42 includes transistors, diodes, resistors, and / or other circuit elements constituting the circuit. In some embodiments, device 40 includes one or more semiconductors. In some embodiments, device 40 includes one or more integrated circuits.

[0042] In different layouts, device 40 may include different placements of power pickup unit 44 relative to circuit 42. In some embodiments, power pickup unit 44 is located on one side of circuit 42 or along one end of circuit 42. In some embodiments, power pickup unit 44 is located on two opposite sides of circuit 42 or along both sides of circuit 42. In some embodiments, power pickup unit 44 is located on all sides of circuit 42.

[0043] The power pickup unit 44 is configured to conduct one or more voltages (e.g., power supply voltages VDD and VSS) from the rear side of device 40 to the front side of device 40. The power pickup unit 44 reduces the wire length from the power supply to the circuit 42. Furthermore, the power pickup unit 44 reduces the IR voltage drop from the power supply to the circuit 42 and improves wiring resources. In some embodiments, the power pickup unit 44 is attached to the circuit 42. In some embodiments, the power pickup unit 44 is located near the circuit 42.

[0044] The power pickup unit 44 may include different types of power pickup structures. In some embodiments, the power pickup unit 44 includes a VB pickup structure. In some embodiments, the power pickup unit 44 includes an FTV pickup structure.

[0045] Figure 2 This is a schematic illustration of a clock unit 46 and a power pickup unit 48 disposed along one side of the clock unit 46, according to some embodiments. The power pickup unit 48 is embedded in the device, for example... Figure 1 The device 40 has a clock unit 46 located on the front side of the device. In some embodiments, the clock unit 46 is similar to circuit 42 (such as...). Figure 1 As shown). In some embodiments, the power pickup unit 48 is similar to the power pickup unit 44 (e.g., Figure 1 (As shown).

[0046] Clock unit 46 has a length L1, while power pickup unit 48 has a length L2 that is the same as the length L1 of clock unit 46. Clock unit 46 includes two long sides 50a and 50b and two short sides 52a and 52b, and power pickup unit 48 includes two long sides 54a and 54b and two short sides 56a and 56b. The long side 54b of power pickup unit 48 is adjacent to the long side 50a of clock unit 46. In other embodiments, the long side 54a of power pickup unit 48 is adjacent to the long side 50b of clock unit 46. In some embodiments, power pickup unit 48 must be at least as long as clock unit 46.

[0047] The power pickup unit 48 is configured to conduct one or more voltages, such as power supply voltages VDD and VSS, from the rear side of the device to the front side of the device. In some embodiments, the power pickup unit 48 is attached to the clock unit 46. In other embodiments, the power pickup unit 48 is located near the clock unit 46. Furthermore, in some embodiments, the power pickup unit 48 is configured to conduct one or more voltages to the clock unit 46.

[0048] The power pickup unit 48 shortens the wiring length from the power supply to the clock unit 46. In addition, the power pickup unit 44 reduces the IR voltage drop from the power supply to the clock unit 46 and improves wiring resources.

[0049] Figure 3 This is a schematic illustration of a clock unit 60 and a first power pickup unit 62 and a second power pickup unit 64 disposed along both sides of the clock unit 60, according to some embodiments. The first power pickup unit 62 is positioned along a first side of the clock unit 60, and the second power pickup unit 64 is positioned along a second side of the clock unit 60. The first side of the clock unit 60 is opposite to the second side of the clock unit 60.

[0050] Each of the first power pickup unit 62 and the second power pickup unit 64 is embedded in the device, for example... Figure 1 The device 40, and the clock unit 60 is located on the front side of the device. In some embodiments, the clock unit 60 is similar to circuit 42 (such as...). Figure 1 (As shown). In some embodiments, each of the first power pickup unit 62 and the second power pickup unit 64 is similar to the power pickup unit 44 (e.g., Figure 1 (As shown).

[0051] Clock unit 60 has a length L3, and each of the first power pickup unit 62 and the second power pickup unit 64 has the same length L4 as clock unit 60. Clock unit 60 includes two long sides 66a and 66b and two short sides 68a and 68b. First power pickup unit 62 includes two long sides 70a and 70b and two short sides 72a and 72b, and second power pickup unit 64 includes two long sides 74a and 74b and two short sides 76a and 76b. The long side 70b of first power pickup unit 62 is adjacent to the long side 66a of clock unit 60, and the long side 74a of second power pickup unit 64 is adjacent to the long side 66b of clock unit 60. In some embodiments, each of the first power pickup unit 62 and the second power pickup unit 64 must be at least as long as clock unit 60.

[0052] Each power pickup unit 62 and 64 is configured to conduct one or more voltages, such as power supply voltages VDD and VSS, from the rear side of the device to the front side of the device. In some embodiments, one or more of the first power pickup unit 62 and the second power pickup unit 64 are attached to the clock unit 60. In some embodiments, one or more of the first power pickup unit 62 and the second power pickup unit 64 are located near the clock unit 60. Furthermore, in some embodiments, one or more of the first power pickup unit 62 and the second power pickup unit 64 are configured to conduct one or more voltages to the clock unit 60.

[0053] Power pickup units 62 and 64 shorten the wiring length from the power supply to the clock unit 60. Furthermore, power pickup units 62 and 64 reduce the IR voltage drop from the power supply to the clock unit 60 and improve wiring resources.

[0054] Figure 4 This is a schematic illustration of a clock unit 80 and a first power pickup unit 82 and a second power pickup unit 84, which are longer than the clock unit 80, according to some embodiments. The first power pickup unit 82 is positioned along a first side of the clock unit 80, and the second power pickup unit 84 is positioned along a second side of the clock unit 80. The first side of the clock unit 80 is opposite to the second side of the clock unit 80.

[0055] Each of the first power pickup unit 82 and the second power pickup unit 84 is embedded in the device, for example... Figure 1 The device 40 has a clock unit 80 located on its front side. In some embodiments, the clock unit 80 is similar to circuit 42 (e.g., ...). Figure 1 (As shown). In some embodiments, each of the first power pickup unit 82 and the second power pickup unit 84 is similar to the power pickup unit 44 (e.g., Figure 1 (As shown).

[0056] Clock unit 80 has a length L5, and each of the first power pickup unit 82 and the second power pickup unit 84 has a length L6, which is greater than the length L5 of clock unit 80. Clock unit 80 includes two long sides 86a and 86b and two short sides 88a and 88b. First power pickup unit 82 includes two long sides 90a and 90b and two short sides 92a and 92b, and second power pickup unit 84 includes two long sides 94a and 94b and two short sides 96a and 96b. Long side 90b of first power pickup unit 82 is adjacent to long side 86a of clock unit 80, and long side 94a of second power pickup unit 84 is adjacent to long side 86b of clock unit 80.

[0057] Each power pickup unit 82 and 84 is configured to conduct one or more voltages, such as power supply voltages VDD and VSS, from the rear side of the device to the front side of the device. In some embodiments, one or more of the first power pickup unit 82 and the second power pickup unit 84 are attached to the clock unit 80. In some embodiments, one or more of the first power pickup unit 82 and the second power pickup unit 84 are located near the clock unit 80. Furthermore, in some embodiments, one or more of the first power pickup unit 82 and the second power pickup unit 84 are configured to conduct one or more voltages to the clock unit 80.

[0058] Power pickup units 82 and 84 reduce the wiring length from the power supply to the clock unit 80. Furthermore, power pickup units 82 and 84 reduce the IR voltage drop from the power supply to the clock unit 80 and improve wiring resources.

[0059] Figure 5 This is a schematic illustration of a clock unit 100 and a first power pickup unit 102 and a second power pickup unit 104 along the short side of the clock unit 100, according to some embodiments. The first power pickup unit 102 is positioned along a first side of the clock unit 100, and the second power pickup unit 104 is positioned along a second side of the clock unit 100. The first side of the clock unit 100 is opposite to the second side of the clock unit 100.

[0060] Each of the first power pickup unit 102 and the second power pickup unit 104 is embedded in a device, for example... Figure 1 The clock unit 100 is located on the front side of the device 40. In some embodiments, the clock unit 100 is similar to circuit 42 (e.g., ...). Figure 1 (As shown). In some embodiments, each of the first power pickup unit 102 and the second power pickup unit 104 is similar to the power pickup unit 44 (e.g., Figure 1 (As shown).

[0061] Clock unit 100 has a short side length L7, and each of the first power pickup unit 102 and the second power pickup unit 104 has a long side length L8 that is the same as the length L7 of clock unit 100. Clock unit 100 includes two long sides 106a and 106b and two short sides 108a and 108b. First power pickup unit 102 includes two long sides 110a and 110b and two short sides 112a and 112b, and second power pickup unit 104 includes two long sides 114a and 114b and two short sides 116a and 116b. The long side 110b of the first power pickup unit 102 is adjacent to the short side 108a of clock unit 100, while the long side 114a of the second power pickup unit 104 is adjacent to the short side 108b of clock unit 100. In some embodiments, each long side of the first power pickup unit 102 and the second power pickup unit 104 must be at least as long as the short side of the clock unit 100.

[0062] Each power pickup unit 102 and 104 is configured to conduct one or more voltages, such as power supply voltages VDD and VSS, from the rear side of the device to the front side of the device. In some embodiments, one or more of the first power pickup unit 102 and the second power pickup unit 104 are attached to the clock unit 100. In some embodiments, one or more of the first power pickup unit 102 and the second power pickup unit 104 are located near the clock unit 100. Furthermore, in some embodiments, one or more of the first power pickup unit 102 and the second power pickup unit 104 are configured to conduct one or more voltages to the clock unit 100.

[0063] Power pickup units 102 and 104 reduce the wiring length from the power supply to the clock unit 100. Furthermore, power pickup units 102 and 104 reduce the IR voltage drop from the power supply to the clock unit 100 and improve wiring resources.

[0064] Figure 6 This is a schematic illustration of a clock unit 120 and a first power pickup unit 122 and a second power pickup unit 124 along the short side of the clock unit 120, according to some embodiments. The first power pickup unit 122 is arranged along the first short side of the clock unit 120, and the second power pickup unit 124 is arranged along the second short side of the clock unit. The first short side and the second short side of the clock unit 120 are opposite each other.

[0065] Each of the first power pickup unit 122 and the second power pickup unit 124 is embedded in the device, for example... Figure 1 The clock unit 120 is located on the front side of the device 40. In some embodiments, the clock unit 120 is similar to circuit 42 (such as...). Figure 1(As shown). In some embodiments, each of the first power pickup unit 122 and the second power pickup unit 124 is similar to power pickup unit 44 (e.g., Figure 1 (As shown).

[0066] Clock unit 120 has a short side length L9, and each of the first power pickup unit 122 and the second power pickup unit 124 has a long side length L10 that is longer than the short side length L9 of clock unit 120. Clock unit 120 includes two long sides 126a and 126b and two short sides 128a and 128b. First power pickup unit 122 includes two long sides 130a and 130b and two short sides 132a and 132b, and second power pickup unit 124 includes two long sides 134a and 134b and two short sides 136a and 136b. The long side 130b of the first power pickup unit 122 is adjacent to the short side 128a of clock unit 120, while the long side 134a of the second power pickup unit 124 is adjacent to the short side 128b of clock unit 120.

[0067] Each power pickup unit 122 and 124 is configured to conduct one or more voltages, such as power supply voltages VDD and VSS, from the rear side of the device to the front side of the device. In some embodiments, one or more of the first power pickup unit 122 and the second power pickup unit 124 are attached to the clock unit 120. In some embodiments, one or more of the first power pickup unit 122 and the second power pickup unit 124 are located near the clock unit 120. Furthermore, in some embodiments, one or more of the first power pickup unit 122 and the second power pickup unit 124 are configured to conduct one or more voltages to the clock unit 120.

[0068] Power pickup units 122 and 124 shorten the wiring length from the power supply to the clock unit 120. In addition, power pickup units 122 and 124 reduce the IR voltage drop from the power supply to the clock unit 120 and improve wiring resources.

[0069] Figure 7 This is a schematic illustration of a clock unit 140 and a power pickup unit 142 surrounding all sides of the clock unit 140, according to some embodiments. The power pickup unit 142 is embedded in the device, for example... Figure 1 The clock unit 140 is located on the front side of the device 40. In some embodiments, the clock unit 140 is similar to circuit 42 (such as...). Figure 1 As shown). In some embodiments, the power pickup unit 142 is similar to the power pickup unit 44 (as shown). Figure 1 (As shown).

[0070] Clock unit 140 includes two long sides 146a and 146b and two short sides 148a and 148b, and power pickup unit 142 includes two long sides 150a and 150b and two short sides 152a and 152b. Power pickup unit 142 is configured to conduct one or more voltages (e.g., supply voltages VDD and VSS) from the rear side of the device to the front side of the device. In some embodiments, power pickup unit 142 is attached to clock unit 140 along the two long sides 146a and 146b and the two short sides 148a and 148b. In some embodiments, power pickup unit 142 is located near clock unit 140 along the two long sides 146a and 146b and the two short sides 148a and 148b. Furthermore, in some embodiments, power pickup unit 142 is configured to conduct one or more voltages to clock unit 140.

[0071] The power pickup unit 142 reduces the wiring length from the power supply to the clock unit 140. Furthermore, the power pickup unit 142 reduces the IR voltage drop from the power supply to the clock unit 140 and improves wiring resources.

[0072] Figure 8 This is a schematic diagram illustrating circuit option 160 according to some embodiments. Circuit option 160 includes reference circuitry 162, single-sided power pickup unit circuitry 164, and dual-sided or dual-sided power pickup unit lines 166. Each of the reference circuitry 162, single-sided power pickup unit circuitry 164, and dual-sided power pickup unit lines 166 includes circuitry 168, such as a clock unit, an FTV input (FTV-I) 170, and an FTV output (FTV-O) 172.

[0073] Reference circuit 162 includes circuit 168, FTV-I 170 on one side of circuit 168, and FTV-O 172 on the other side of circuit 168. Reference circuit 162 has a 6X input / output (I&O) cell height, a 4X input (I) cell height, and a 4X output (O) cell height. The delay of the wires is used as a reference value.

[0074] The single-sided power pickup unit circuit 164 includes a power pickup unit 174 located between circuit 168 and FTV-O 172. The single-sided power pickup unit circuit 164 has an I&O unit height of 7x, an I unit height of 5x, and an O unit height of 5x. The I&O delay is -2.5% of a reference value, the I delay is -2.2% of a reference value, and the O delay is -2.3% of a reference value. In other embodiments, the power pickup unit circuit 174 may be located between circuit 168 and FTV-I 170.

[0075] The dual-side power pickup unit circuit 166 includes a first power pickup unit 176 located between circuit 168 and FTV-I 170, and a second power pickup unit 178 located between circuit 168 and FTV-O 172. The dual-side power pickup unit circuit 166 has an I&O unit height of 8x, an I unit height of 6x, and an O unit height of 6x. The I&O delay is -3.9% of the reference value, the I delay is -3.5% of the reference value, and the O delay is -3.5% of the reference value.

[0076] Figure 9 This is a top view diagram illustrating a device 200 according to some embodiments. Device 200 includes a substrate 202, which includes an N-type well active region 204 for a power supply voltage VDD and a P-type well active region 206 for a power supply voltage VSS. Device 200 includes a rear-side metallization layer 208 for delivering power supply VDD and a rear-side metallization layer 210 for delivering power supply VSS. In some embodiments, device 200 is similar to... Figure 1 Device 40.

[0077] Power supply VDD is transmitted from the rear metallization layer 208 through power pickup units to the circuitry in device 200. Power supply VSS is conducted from the rear metallization layer 210 through one or more power pickup units to the circuitry in device 200. In some embodiments, each circuitry is similar to circuit 42 (e.g., Figure 1 As shown). In some embodiments, each power pickup unit is similar to power pickup unit 44 (e.g. Figure 1 (As shown). In some embodiments, the circuit is a clock unit.

[0078] Figure 10 and Figure 11 It is an illustrative illustration. Figure 9 The diagram of device 200 includes VB-type power pickup units or structures 220a to 220f for conducting power supplies VDD and VSS from the rear side of device 200 to the front side of device 200. VB-type power pickup structures 220a to 220f simultaneously conduct power supplies VDD and VSS from the rear side of device 200 to the front side of device 200. In some embodiments, device 200 is similar to... Figure 1 Device 40.

[0079] Figure 10 This includes, according to some embodiments, illustrative VB-type power pickup structures 220a to 220f, first front metallization layers M0 222a-222g, and first rear metallization layers BMO 208 and 210 (e.g.) Figure 9The top view (shown) shows the first front metallization layers M0 222a to 222g located above or above the VB-type power pickup structures 220a to 220f, and the first rear metallization layers BMO 208 and 210 located below or below the VB-type power pickup structures 220a to 220f. The power distribution network in the first front metallization layers M0 222a to 222g is different for power supply VDD and power supply VSS. Furthermore, the device 200 includes gate contacts 224, such as polysilicon (PO) gates or lines, and edge fingers 226, such as edge PO fingers. For clarity, the first front metallization layers M0 222a to 222g and the first rear metallization layers BMO 208 and 210 are shown respectively.

[0080] VB-type power pickup structures 220a to 220c pass through the N-type well active region 204 for power supply voltage VDD, and VB-type power pickup structures 220d to 220f pass through the P-type well active region 206 for power supply voltage VSS.

[0081] Each VB-type power pickup structure 220a to 220c includes VB contacts 228a to 228c, a P-type epitaxial active region 230, MD contacts 232a to 232c, and a VDR contact 234. A first rear-side metallization layer BMO 208 is electrically connected to and conducts power VDD to the VB contacts 228a to 228c. The VB contacts 228a to 228c are electrically connected to the P-type epitaxial active region 230. The P-type epitaxial active region 230 is electrically connected to the MD contacts 232a to 232c. The MD contacts 232a to 232c are electrically connected to the VDR contact 234. The VDR contact 234a is electrically connected to a first front-side metallization layer M0 222a for power VDD.

[0082] Each VB-type power pickup structure 220d to 220f includes VB contacts 228d to 228f, an N-type epitaxial active region 236, MD contacts 232d to 232f, and a VDR contact 238. A first rear-side metallization layer BMO 210 is electrically connected to and conducts power VSS to the VB contacts 228d to 228f. The VB contacts 228d to 228f are electrically connected to the N-type epitaxial active region 236, which is electrically connected to the MD contacts 232d to 232f. The MD contacts 232d to 232f are electrically connected to the VDR contact 238. The VDR contact 238g is electrically connected to a first front-side metallization layer MO 222g for power VSS.

[0083] Figure 11 This is an illustrative description based on some embodiments. Figure 10The image shows a cross-sectional view of device 200 taken from line AA. Device 200 includes a first front metallization layer M0222a to 222g located above or on top of VB-type power pickup structures 220b and 220e, and a first rear metallization layer BMO 208 and 210 located below or below VB-type power pickup unit structures 220b and 220V.

[0084] The VB-type power pickup structure 220b passes through the N-type well active region 204 for the power supply voltage VDD, and the VB-type power pickup structure 220e passes through the P-type well active region 206 for the power supply voltage VSS.

[0085] The VB-type power pickup structure 220b includes a VB contact 228b, a P-type epitaxial active region 230, an MD contact 232b, and a VDR contact 234. A first rear-side metallization layer BMO 208 is electrically connected to the VB contact 228b and conducts power VDD to the VB contact 228b. The VB contact 228b is electrically connected to the P-type epitaxial active region 230. The P-type epitaxial active region 230 is electrically connected to the MD contact 232b. The MD contact 232b is electrically connected to the VDR contact 234. The VDR contact 234 is electrically connected to a first front-side metallization layer M0 222a for power VDD. The power supply voltage VDD flows from the first rear metallization layer BM0 208 to the VB contact 228b, the P-type epitaxial active region 230, the MD contact 232b, the VDR contact 234, and the first front metallization layer M0 222a, and in some embodiments, to the VDD distribution network.

[0086] The VB-type power pickup structure 220e includes a VB contact 228e, an N-type epitaxial active region 236, an MD contact 232e, and a VDR contact 238. A first rear-side metallization layer BMO 210 is electrically connected to the VB contact 228e and conducts power VSS to it. The VB contact 228e is electrically connected to the N-type epitaxial active region 236. The N-type epitaxial active region 236 is electrically connected to the MD contact 232e. The MD contact 232e is electrically connected to the VDR contact 238. The VDR contact 238 is electrically connected to a first front-side metallization layer MO 222g for power VSS. The power supply voltage VSS flows to or out of the first rear metallization layer BM0 210, to the VB contact 228e, to the N-type epitaxial active region 236, to the MD contact 232e, to the VDR contact 238, to the first front metallization layer M0 222g, and in some embodiments, to the VSS distribution network.

[0087] Figure 12This is a schematic illustration of device 250 according to some embodiments, which includes a clock unit 252 located next to or adjacent to a power pickup unit 254. The clock unit 252 is located on the front side of device 250, and the power pickup unit 254 conducts power supply voltages VDD and VSS from the rear side of device 250 to the front side of device 250 and the clock unit 252. The clock unit 252 includes epitaxial active regions 256a to 256c, and the power pickup unit 254 includes epitaxial active regions 258a and 258b.

[0088] The power pickup unit 254 includes a VDD power pickup unit 260, which conducts the power supply voltage VDD from the rear side of the device 250 to the front side of the device 250 and the clock unit 252. The VDD power pickup unit 260 is a VB-type power pickup unit, which conducts the power supply voltage VDD to the first metallization layer M0, which serves as the VDD power rail 262.

[0089] The power pickup unit 254 includes VSS power pickup units 264a and 264b, which conduct the power supply voltage VSS from the rear side of device 250 to the front side of device 250 and clock unit 252. VSS power pickup units 264a and 264b conduct the power supply voltage VSS to a first metallization layer M0, which serves as the VSS power rail 266. In some embodiments, VSS power pickup units 264a and 264b are VB-type power pickup units or structures.

[0090] Device 250 includes a first metallization layer MOVDD power rail 262 and a first metallization layer MOVSS power rail 266. The first metallization layer MOVDD power rail 262 is electrically connected to a second front metallization layer M1 270, a second via 268b, and the first front metallization layer M0 serving as the clock unit VDD power rail 272 via a first via 268a. Furthermore, the first metallization layer MOVDD power rail 262 is electrically connected to another second front metallization layer M1 274, a fourth via 268d, and the first front metallization layer M0 serving as the clock unit VDD power rail 272 via a third via 268c.

[0091] The first metallization layer M0 and VSS power rail 266 are electrically connected to the second front metallization layer M1 276, the sixth through-hole 268f, and the first front metallization layer M0, which serves as the clock unit VSS power rail 278, through the fifth through-hole 268e. The first metallization layer M0 and VSS power rail 266 are electrically connected to the second front metallization layer M1 280 and the eighth through-hole 268h, which serve as the first front metallization layer M0, which serves as the clock unit VSS power rail 278, through the seventh through-hole 268g.

[0092] Figure 13 This is an illustrative description based on some embodiments along... Figure 12The image shows a cross-sectional view of the VDD power pickup unit 260 taken from line BB. The VDD power pickup unit 260 includes a first rear-side metallization layer BM0 282, a first VB 284, a second VB 286, a clock unit P-type epitaxial active region 256c, a power pickup unit P-type epitaxial active region 258a, and an MD layer 288 (also located in...). Figure 12 (See attached instructions) VDR 290 (also included) Figure 12 (As explained in the text) and the first metallization layer M0VDD power rail 262.

[0093] VDD power pickup unit 260 passes through the N- or P-well active region 292 of device 250 to conduct the power supply voltage VDD from the rear side of device 250 to the front side of device 250. The first rear-side metallization layer BMO 282 of VDD power pickup unit 260 is electrically connected to the first VB 284, the first VB 284 is electrically connected to the clock unit P-type epitaxial active region 256c and the second VB 286, and the second VB 286 is electrically connected to the power pickup unit P-type epitaxial active region 258a. The clock unit P-type epitaxial active region 256c and the power pickup unit P-type epitaxial active region 258a are electrically connected to the MD layer 288, the MD layer 288 is electrically connected to VDR 290, and the VDR 290 is electrically connected to the first metallization layer BMOVDD power rail 262.

[0094] The power supply voltage VDD flows from the first rear metallization layer BMO 282 to the first VB 284 and the clock unit P-type epitaxial active region 256c, and then to the second VB 286 and the power pickup unit P-type epitaxial active region 258a. Then, the power supply voltage VDD flows from the clock unit P-type epitaxial active region 256c and the power pickup unit P-type epitaxial active region 258a to the MD layer 288, VDR 290, and the first metallization layer MOVDD power rail 262, and in some embodiments, to the VDD power distribution network. Therefore, the power supply voltage VDD is conducted from the first rear metallization layer BMO 282 to the clock unit 252 and the power pickup unit 254 via the VDD power pickup unit 260.

[0095] Figure 14 and Figure 15 This is a schematic diagram illustrating device 300, which includes an FTV-type power pickup unit or structure 302 for conducting power supply voltage VDD from the rear side of device 300 to the front side of device 300. In some embodiments, device 300 is similar to Figure 1 Device 40.

[0096] Figure 14This is a schematic illustration of device 300 according to some embodiments. Device 300 includes an FTV power pickup structure 302, first front metallization layers MO 304a to 304g, and first rear metallization layers BMO 306 and 308 for conducting power supply voltage VDD. The first front metallization layers MO 304a to 304g are located above or on top of the FTV power pickup structure 302, and the first rear metallization layers BMO 306 and 308 are located below or beneath the FTV power pickup structure 302. The power distribution network in the first front metallization layers MO 304a to 304g is different for power supply VDD and power supply VSS. In addition, device 300 includes gate contacts 310, such as PO gates or lines, and edge fingers 312, such as edge PO fingers. For clarity, the first front metallization layers M0 304a to 304g and the first rear metallization layers BMO 306 and 308 are drawn respectively.

[0097] Device 300 includes an N-type well active region 314 having a P-type epitaxial active region 316 and a P-type well active region 318 having an N-type epitaxial active region 320. FTV power pickup structure 302 passes through the N-type well active region 314 and the P-type well active region 318 to conduct power supply voltage VDD.

[0098] The FTV power pickup structure 302 includes an FTV contact 322, MD contacts 324a and 324b, and a VDR contact 326. The first rear metallization layer BMO 306 includes a base 328 and an extension or micro-movement portion 330, the extension or micro-movement portion 330 extending away from the base 328 and below the FTV contact 322. The height of the micro-movement portion 330 is called the micro-movement distance J. The first rear metallization layer BMO 308 is recessed or recessed to avoid interference between the first rear metallization layer BMO 306 and the first power metallization layer BMO 304. An extension or micro-movement portion 330 of the first rear metallization layer BM0 306 is electrically connected to the FTV contact 322 and conducts power VDD to the FTV contact 322. The FTV contact 332 is electrically connected to the MD contacts 324a and 324b. The MD contacts are electrically connected to the VDR contact 326. The VDR contact is electrically connected to the first front metallization layer M0304a for power VDD.

[0099] Figure 15 This is an illustrative description based on some embodiments along... Figure 14 The image shows a cross-sectional view of device 300 taken from line CC. Device 300 includes a first front metallization layer M0 304a to 304g above or on top of FTV power pickup structure 302, and a first rear metallization layer BMO 306 and 308 below or under FTV power pickup unit structure 302.

[0100] The FTV power pickup structure 302 passes through the N-type well active region 314 and the P-type well active region 318. The FTV power pickup structure 302 includes an FTV contact 322, MD contacts 324a and 324b, and a VDR contact 326. An extension or micro-shift portion 330 of the first rear-side metallization layer BM0306 is electrically connected to the FTV contact 322 and conducts power VDD to the FTV contact 322. The FTV contact 322 is electrically connected to the MD contacts 324a (and MD contacts 324b), while the MD contact 324c is electrically connected to the VDR contact 326. The VDR contact 326 is electrically connected to the first front-side metallization layer MO 304a for power VDD. Furthermore, the MD contact 324a is electrically connected to the P-type epitaxial active region 316. The power supply voltage VDD flows from the first rear metallization layer BM0 306 to FTV contact 322, MD contact 324a (and MD contact 324b), VDR contact 326 and the first front metallization layer MO 304a, and in some embodiments, to the VDD distribution network.

[0101] Figure 16 and Figure 17 This is a schematic diagram illustrating device 340, which includes an FTV-type power pickup unit or structure 342 for conducting power supply voltage VSS from the rear side of device 340 to the front side of device 340. In some embodiments, device 340 is similar to Figure 1 Device 40.

[0102] Figure 16 This is a schematic illustration of device 340 according to some embodiments. Device 340 includes an FTV power pickup structure 342, first front metallization layers MO 344a to 344g, and first rear metallization layers BMO 346 and 348 for conducting power supply voltage VSS. The first front metallization layers MO 344a to 344g are located above or on top of the FTV power pickup structure 342, and the first rear metallization layers BMO 346 and 348 are located below the FTV power pickup structure 342. The power distribution network in the first front metallization layers MO 344a to 344g is different for power supply VDD and power supply VSS. In addition, device 340 includes gate contacts 350, such as PO gates or lines, and edge fingers 352, such as edge PO fingers. For clarity, the first front metallization layers M0 344a to 344g and the first rear metallization layers BMO 346 and 348 are plotted respectively.

[0103] Device 340 includes an N-type well active region 354 having a P-type epitaxial active region 356 and a P-type well active region 358 having an N-type epitaxial active region 360. The FTV power pickup structure 342 allows the power supply voltage VSS to pass through the N-type well active region 354 and the P-type well active region 358.

[0104] The FTV power pickup structure 342 includes an FTV contact 362, MD contacts 364a and 364b, and a VDR contact 366. The first rear metallization layer BMO 348 includes a base 368 and an extension or micro-movement portion 370 extending from the base 368 and below the FTV contact 362. The height of the micro-movement portion 370 is referred to as the micro-movement distance J. The first rear metallization layer BMO 346 is recessed or recessed to avoid interference between the first rear metallization layer BMO 349 and the first rear metallization layer BMO 348. An extension or micro-shifted portion 370 of the first rear metallization layer BM0 348 is electrically connected to the FTV contact 362 and conducts the power supply voltage VSS to the FTV contact 362. The FTV contact is electrically connected to the MD contacts 364a and 364b. The MD contact is electrically connected to the VDR contact 366. The VDR contact is electrically connected to the first front metallization layer MO 344g for the power supply VSS.

[0105] Figure 17 This is an illustrative description based on some embodiments. Figure 16 The image shows a cross-sectional view of device 340 taken from line DD. Device 340 includes a first front metallization layer M0 344a to 344g above or on top of FTV power pickup structure 342, and a first rear metallization layer BMO 346 and 348 below or under FTV power pickup unit structure 342.

[0106] The FTV power pickup structure 342 passes through the N-type well active region 354 and the P-type well active region 358. The FTV power pickup structure 342 includes an FTV contact 362, MD contacts 364a and 364b, and a VDR contact 366. An extension or micro-shift portion 370 of the first rear-side metallization layer BM0348 is electrically connected to the FTV contact 362 and conducts power VSS to the FTV contact 362. The FTV contact 362 is electrically connected to the MD contacts 364a (and MD contacts 364b), the MD contacts are electrically connected to the VDR contact 366, and the VDR contact 366 is electrically connected to the first front-side metallization layer MO 344g of the power VSS. Furthermore, the MD contact 364a is electrically connected to the N-type epitaxial active region 360. The power supply voltage VSS flows from the first rear metallization layer BM0 348 to FTV contact 362, MD contact 364a (and MD contact 364b), VDR contact 366 and the first front metallization layer M0 344g, and in some embodiments, to the VSS distribution network.

[0107] Figure 18 and Figure 19 This is a schematic diagram illustrating device 400, which includes an FTV-type power pickup unit or structure 402 for conducting a power supply voltage VDD from the rear side of device 400 to the front side of device 400. The FTV-type power pickup structure 402 is located in the central region of device 400, and a protrusion or micro-movement portion 430 of the first rear metallization layer BMO 406 extends into the central region to contact the FTV-type power pickup structure 402. Furthermore, a recess or indentation in the first rear metallization layer BMO 408 corresponds to the micro-movement portion 430 to avoid interference between the first rear metallization layer BMO 406 and the first power metallization layer BMO 404. The height of the micro-movement portion 430 is called the micro-movement distance J. In some embodiments, device 400 is referred to as a power pickup unit. In some embodiments, device 400 is similar to... Figure 1 Device 40.

[0108] Figure 18This is a schematic illustration of a device 400 according to some embodiments. The device 400 includes an FTV power pickup structure 402, first front metallization layers MO 404a to 404g, and first rear metallization layers BMO 406 and 408 for conducting power supply voltage VDD. The first front metallization layers MO 404a to 404g are located above or on top of the FTV power pickup structure 402, and the first rear metallization layers BMO 406 and 408 are located below or beneath the FTV power pickup structure 402. The power distribution network in the first front metallization layers MO 404a to 404g is different for power supply VDD and power supply VSS. Furthermore, the device 400 includes gate contacts 410, such as a PO gate or line, and edge fingers 412, such as edge PO fingers. For clarity, the first front metallization layers M0 404a to 404g and the first rear metallization layers BMO 406 and 408 are drawn respectively.

[0109] Device 400 includes an N-type well active region 414 having a P-type epitaxial active region 416 and a P-type well active region 418 having an N-type epitaxial active region 420. FTV power pickup structure 402 passes through the N-type well active region 414 and the P-type well active region 418 to conduct power supply voltage VDD.

[0110] The FTV power pickup structure 402 includes an FTV contact 422, an MD contact 424, and a VDR contact 426. A first rear metallization layer BMO 406 includes a base 428 and a protrusion (extension) or micro-movement portion 430 extending from the base 428 and below the FTV contact 422. The first rear metallization layer BMO 408 is recessed or recessed to avoid interference between the first rear metallization layer BMO 406 and the first rear metallization layer BMO 408. The micro-movement portion 430 of the first rear metallization layer BMO 406 is electrically connected to the FTV contact 422 and conducts power VDD to the FTV contact 422. The FTV contact 422 is electrically connected to the MD contact 424, the MD contact 424 is electrically connected to the VDR contact 426, and the VDR contact 426 is electrically connected to a first front metallization layer M0404d for power VDD. The first front metallization layer M0 404d is electrically connected to the second front metallization layer M1432 through a first via 434, and the second front metallization layer M1432 is electrically connected to the first front metallization layer M0 404a through a second via 436. In some embodiments, the first front metallization layer M0 404a is connected to the VDD PDN.

[0111] Figure 19 This is an illustrative description based on some embodiments. Figure 18The image shows a cross-sectional view of device 400 taken by line EE. Device 400 includes a first front metallization layer M0 404a to 404g above or on top of the FTV power pickup structure 402, and a first rear metallization layer BMO 406 and 408 below or below the FTV power pickup unit structure 402. Furthermore, a second front metallization layer M1 432 is located above or on top of the first front metallization layers M0 404a to 404g.

[0112] The FTV power pickup structure 402 passes through the N-type well active region 414 and the P-type well active region 418. The FTV power pickup structure 402 includes an FTV contact 422, an MD contact 424, and a VDR contact 426. An extension or micro-shift portion 430 of the first rear metallization layer BMO 406 is electrically connected to the FTV contact 422 and conducts power VDD to the FTV contact 422. The FTV contact 422 is electrically connected to the MD contact 424. The MD contact 424 is electrically connected to the VDR contact 426. The VDR contact 426 is electrically connected to the first front metallization layer MO 404d. The first front metallization layer MO 404d is electrically connected to the second front metallization layer M1 432 through a first via 434. The second front metallization layer M1 432 is electrically connected to the first front metallization layer MO 404a for power VDD through a second via 436.

[0113] The power supply voltage VDD flows from the first rear metallization layer BM0 406 to the FTV contact 422, MD contact 424, VDR contact 426, the first front metallization layer M0 404d, the first via 434, the second front metallization layer M1 432, the second via 436, and the first front metallization layer M0 404a, and in some embodiments, to the VDD distribution network.

[0114] Figure 20 and Figure 21 This diagram schematically illustrates device 440, which includes an FTV-type power pickup unit or structure 442 for conducting power supply voltage VSS from the rear side of device 440 to the front side of device 440. The FTV-type power pickup structure 442 is located in the central region of device 440, and a protrusion or micro-displacement 470 of the first rear metallization layer BMO 448 extends into the central region to contact the FTV-type power pickup structure 442. Furthermore, a recess or indentation in the first rear metallization layer BMO 446 corresponds to the micro-displacement 470 to avoid interference between the first power metallization layers BMO 444 and BMO 448. The height of the micro-displacement 470 is referred to as the micro-displacement distance J. In some embodiments, device 440 is referred to as a power pickup unit. In some embodiments, device 440 is similar to... Figure 1 Device 40.

[0115] Figure 20 This is a schematic illustration of device 440 according to some embodiments. Device 440 includes an FTV power pickup structure 442, first front metallization layers MO 444a to 444g, and first rear metallization layers BMO 446 and 448 for conducting power supply voltage VSS. The first front metallization layers MO 444a to 444g are located above or on top of the FTV power pickup structure 442, and the first rear metallization layers BMO 446 and 448 are located below or beneath the FTV power pickup structure 442. The power distribution network in the first front metallization layers MO 444a to 444g is different for power supply VDD and power supply VSS. Furthermore, device 440 includes gate contacts 450, such as a PO gate or line, and edge fingers 452, such as edge PO fingers. For clarity, the first front metallization layers M0 444a to 444g and the first rear metallization layers BMO 446 and 448 are plotted respectively.

[0116] Device 440 includes an N-type well active region 454 having a P-type epitaxial active region 456 and a P-type well active region 458 having an N-type epitaxial active region 460. FTV power pickup structure 442 passes through the N-type well active region 454 and the P-type well active region 458 to conduct power supply voltage VSS.

[0117] The FTV power pickup structure 442 includes an FTV contact 462, an MD contact 464, and a VDR contact 466. A first rear metallization layer BMO 448 includes a base 468 and a protrusion (extension) or micro-movement portion 470 extending from the base 468 and below the FTV contact 462. The first rear metallization layer BMO 446 is recessed or recessed to avoid interference between the first rear metallization layer BMO 444 and the first power metallization layer BMO 448. The micro-movement 470 of the first rear metallization layer BMO 448 is electrically connected to the FTV contact 462 and conducts power VSS to the FTV contact 462. The FTV contact 462 is electrically connected to the MD contact 464, the MD contact 464 is electrically connected to the VDR contact 466, and the VDR contact 466 is electrically connected to a first front metallization layer MO 444d for power VSS. The first front metallization layer M0 444d is electrically connected to the second front metallization layer M1 472 through a first via 474, and the second front alloy layer M1 472 is electrically connected to the first front alloy layer M0 444g through a second via 476. In some embodiments, the first front metallization layer M0 444g is connected to the VSS PDN.

[0118] Figure 21 This is an illustrative description based on some embodiments. Figure 20The image shows a cross-sectional view of device 440 taken by line FF. Device 440 includes a first front metallization layer M0 444a to 444g above or on top of the FTV power pickup structure 442, and a first rear metallization layer BMO 446 and 448 below or below the FTV power pickup unit structure 442. Furthermore, a second front metallization layer M1 472 is located above or on top of the first front metallization layers M0 444a-444g.

[0119] The FTV power pickup structure 442 passes through the N-type well active region 454 and the P-type well active region 458. The FTV power pickup structure 442 includes an FTV contact 462, an MD contact 464, and a VDR contact 466. An extension or micro-shift portion 470 of the first rear metallization layer BMO 448 is electrically connected to the FTV contact 462 and conducts power VSS to the FTV contact 462. The FTV contact 462 is electrically connected to the MD contact 464. The MD contact 464 is electrically connected to the VDR contact 466. The VDR contact 466 is electrically connected to the first front metallization layer MO 444d. The first front metallization layer MO 444d is electrically connected to the second front metallization layer M1 472 through a first via 474. The second front circuitry layer M1 472 is electrically connected to the first front metallization layer MO 444g for power VSS through a second via 476.

[0120] The power supply voltage VSS flows from the first rear metallization layer BM0 448 to the FTV contact 462, MD contact 464, VDR contact 466, the first front metallization layer M0 444d, the first via 474, the second front metallization layer M1 472, the second via 476, and the first front metallization layer M0 444g, and in some embodiments, to the VSS distribution network.

[0121] Figure 22 This is a diagram illustrating the characteristics of a VB-type power pickup unit in column 500 and an FTV-type power pickup unit in column 502 according to some embodiments. The power pickup unit characteristics include a first rear-side metallization layer BMO pattern in row 504, a power supply connected in row 506, and resistors and capacitors in row 508.

[0122] In column 500, the first rear metallization layer BMO pattern in row 504 of the VB-type power pickup unit does not have an extension or micro-shift portion for connecting to the power pickup unit. However, in column 502, the first rear metallization layer BMO pattern in row 504 of the FTV-type power pickup unit has an extension or micro-shift portion for connecting to the power pickup unit.

[0123] For the VB type power pickup unit in column 500, the power supply connected in row 506 is VDD and / or VSS, while for the FTV type power pickup unit in column 502, the power supply connected in row 506 is either VDD or VSS.

[0124] For the VB type power pickup unit in column 500, the resistance and capacitance in row 508 are higher, while for the FTV type power pickup unit in column 502, the resistance and capacitance in row 508 are lower.

[0125] Figure 23 This is a schematic illustration of device 520 according to some embodiments, which includes a clock unit 522 and a power pickup unit 524 surrounding all sides of the clock unit 522. The power pickup unit 524 is embedded in the device 520, and the clock unit 522 is located on the front side of the device 520. In some embodiments, device 520 is similar to Figure 1 Device 40. In some embodiments, clock unit 522 is similar to circuit 42 (such as...) Figure 1 As shown). In some embodiments, the power pickup unit 524 is similar to the power pickup unit 44 (as shown). Figure 1 (As shown). In some embodiments, clock unit 522 is similar to clock unit 140 (e.g., as shown). Figure 7 As shown). In some embodiments, the power pickup unit 524 is similar to the power pickup unit 142 (as shown). Figure 7 (As shown).

[0126] Clock unit 522 includes two long sides 526a and 526b and two short sides 528a and 528b, and power pickup unit 524 includes two long sides 530a and 530b and two short sides 532a and 532b. Power pickup unit 524 is configured to conduct one or more voltages (e.g., power supply voltages VDD and VSS) from the rear side of device 520 to the front side of device 520.

[0127] Power pickup unit 524 includes a plurality of VDD power pickup structures 534 that conduct power supply voltage VDD from the rear side of device 520 to the front side of device 520. The plurality of VDD power pickup structures 534 conduct power supply voltage VDD to VDD power rails 536a and 536b located on two opposing or opposite long sides 526a and 526b of clock unit 522. The VDD power pickup structures 534 conduct power supply voltage VDD to a first metallization layer M0 serving as VDD power rail 536a and a first metallization layer M0 serving as VDD power rail 536b. In some embodiments, each VDD power pickup structure 534 is similar to VDD power pickup unit 260, which conducts power supply voltage VDD from the rear side of device 250 to the front side of device 250 and clock unit 252, as... Figure 12 and Figure 13 As shown and described.

[0128] The power pickup unit 524 includes multiple VSS power pickup structures 538, which conduct the power supply voltage VSS from the rear side of the device 520 to the front side of the device 520. The multiple VSS power pickup structures 538 conduct the power supply voltage VSS to VSS power rails 540a to 540c, which are located on two opposing or opposite long sides 530a and 530b of the power pickup unit 524, and at the center of the device 520. The VSS power pickup structures 538 conduct the power supply voltage VSS to the first metallization layer M0 of the M0 VSS power rail 540a, the first metallization layer M0 of the M0 VSS power rail 540b, and the first metallization layer M0 of the M0 VSS power rail 540c. The M0 VSS power rails 540a to 540c are electrically connected to each other through a second front metallization layer M1, which is the M1 VSS power rails 542a to 542f. In this embodiment, the M1 VSS power rails 542a to 542f are electrically connected to the M0 VSS power rails 540a to 540c via through-holes 544. In some embodiments, each VSS power pickup structure 538 is similar to one or more of the VB-type power pickup structures 220a to 220f, which conduct the power supply voltage VSS from the rear side of the device 200 to the front side of the device 200, such as... Figures 9 to 11 As shown and described.

[0129] The power pickup unit 524 reduces the wiring length from power supplies VDD and VSS to clock unit 522. Furthermore, the power pickup unit 524 reduces the IR voltage drop from power supplies VDD and VSS to clock unit 522 and improves wiring resources.

[0130] Figure 24 This is a diagram illustrating a method of manufacturing an integrated circuit according to some embodiments. In step 560, the method includes providing a substrate having a front side and a rear side opposite to the front side. In some embodiments, the substrate is similar to substrate 202 (e.g., Figure 9 (As shown).

[0131] In step 562, the method includes forming an active region on the front side of the substrate, and in step 564, the method further includes forming an epitaxial active region within the active region. In some embodiments, the active region is an N-type well active region and a P-type well active region. In some embodiments, the active region is similar to well active regions 204 and 206 (e.g., Figure 11 As shown), 292 (as shown) Figure 13 As shown), 314 and 318 (as shown) Figure 15 (as shown) and 354 and 358 (as shown) Figure 17 (as shown) and 414 and 418 (as shown) Figure 19 As shown), and 454 and 458 ( Figure 21 (as shown in the figure). In some embodiments, the active region of the epitaxial layer is similar to an N-type epitaxial or P-type epitaxial active region, such as active regions 230 and 236 (as shown in the figure). Figure 11 (as shown), 256c and 258a (as shown) Figure 13 As shown), 316 and 320 (as shown) Figure 15 As shown), 356 and 360 ( Figure 17 As shown), 416 and 420 Figure 19 (as shown), and 456 and 460 ( Figure 21 (as shown in the image).

[0132] In step 566, the method includes forming an MD contact electrically connected to an active region, and in step 568, the method further includes forming a VDR contact electrically connected to the MD contact. In some embodiments, the MD contact is similar to MD contacts 232b and 232e (e.g., Figure 11 As shown), 288 (as shown) Figure 13 (as shown) and 324a (as shown) Figure 15 As shown), 364a ( Figure 17 As shown), 424 Figure 19 As shown), and 464 ( Figure 21 (as shown in the diagram). In some embodiments, the VDR contacts are similar to VDR contacts 234 and 238 (as shown in the diagram). Figure 11 As shown), 290 (as shown) Figure 13 (as shown) and 326 (as shown) Figure 15 As shown), 366 ( Figure 17 (as shown), 426 ( Figure 19 (as shown), and 466 ( Figure 21 (as shown in the image).

[0133] In step 570, the method includes forming a front-side metallization layer electrically connected to the VDR contact on the VDR contact. In step 572, the method further includes forming a rear-side metallization layer electrically coupled to at least one active region on the rear side of the substrate. A transistor is formed in a circuit on the front side of the substrate, and a first power pickup unit is formed on a first side of the circuit to conduct one or more voltages from the rear-side metallization layer to the front-side metallization layer. In some embodiments, the front-side metallization layer is similar to front-side metallization layers 222a to 222g. Figure 11 As shown), 262 ( Figure 13 As shown), 304a to 304g ( Figure 15 (as shown) and 344a to 344g ( Figure 17 As shown), 404a to 404g ( Figure 19(as shown) and 444a to 444g ( Figure 21 (As shown). In some embodiments, the rear metallization layer is similar to rear metallization layers 208 and 210 (as shown). Figure 11 As shown), 282 (as shown) Figure 13 As shown), 306 and 308 (as shown) Figure 15 (as shown) and 346 and 348 (as shown) Figure 17 (as shown) and 406 and 408 (as shown) Figure 19 As shown), and 446 and 448 ( Figure 21 (as shown in the image).

[0134] In some embodiments, the first power pickup unit is similar to power pickup unit unit 220 (e.g., Figure 11 As shown), 260 (as shown) Figure 13 (as shown) and 302 (as shown) Figure 15 As shown), 342 (as shown) Figure 17 (as shown) and 402 (as shown) Figure 19 (as shown) or 442 (as shown) Figure 21 As shown). In some embodiments, the circuit is similar to circuit 42 (as shown). Figure 1 (as shown) and / or clock unit 252 (as shown) Figure 12 (As shown).

[0135] In some embodiments, the method includes forming a second power pickup unit on a second side of the circuit opposite to a first side of the circuit to conduct one or more voltages from a rear metallization layer to a front metallization layer.

[0136] In some embodiments, the method includes forming a VB contact electrically connected to at least one active region of an epitaxial layer, wherein forming a back-side metallization layer includes electrically connecting the back-side metallization layer to the VB contact.

[0137] In some embodiments, the method includes forming an FTV electrically connected to at least one MD contact, wherein forming a rear-side metallization layer includes electrically connecting the rear-side metallization layer to the FTV. In some embodiments, the method includes forming a rear-side metallization layer including a micro-movement extension for electrical connection to the FTV.

[0138] Figure 25This is a block diagram illustrating an example of a computer system 600 according to some embodiments, configured to provide devices (including electronic devices and semiconductor devices) and methods of this disclosure. Some or all of the design, layout, and fabrication of the semiconductor devices (also referred to as semiconductor circuits) may be performed by or with the assistance of the computer system 600. Furthermore, some or all of the design, layout, and fabrication of devices, including electronic devices, may be performed by or with the assistance of the computer system 600. In some embodiments, the computer system 600 includes an electronic design automation (EDA) system. In some embodiments, the semiconductor device is an IC.

[0139] In some embodiments, system 600 is a general-purpose computing device including processor 602 and non-transient computer-readable storage medium 604. Computer-readable storage medium 604 may be encoded, for example, storing computer program code (such as executable instructions 606). Processor 602 executes instructions 606 (at least partially) to provide a design tool that implements some or all of the functionality of system 600, such as pre-layout simulation, post-layout simulation, routing, rerouting, and final fabrication layout. Additionally, fabrication tools 608 are included for further layout and physical implementation of the semiconductor device design and fabrication. In some embodiments, execution of instructions 606 by processor 602 provides (at least partially) design tools that implement some or all of the functionality of system 600. In some embodiments, system 600 includes a commercial router. In some embodiments, system 600 includes an Automated Place and Route (APR) system.

[0140] Processor 602 is electrically coupled to computer-readable storage medium 604 via bus 610 and to I / O interface 612 via bus 610. Network interface 614 is also electrically connected to processor 602 via bus 610. Network interface 614 is connected to network 616, allowing processor 602 and computer-readable storage medium 604 to be connected to external components via network 616. Processor 602 is configured to execute computer program code or instructions 606 encoded in computer-readable storage medium 604 to cause system 600 to perform some or all of its functions, such as providing the semiconductor devices and methods of this disclosure and other functions of system 600. In some embodiments, processor 602 is a central processing unit (CPU), a multiprocessor, a distributed processing system, an application-specific integrated circuit (ASIC), and / or a suitable processing unit.

[0141] In some embodiments, the computer-readable storage medium 604 is an electronic, magnetic, optical, electromagnetic, infrared, and / or semiconductor system or device. For example, the computer-readable storage medium 604 may include semiconductor or solid-state memory, magnetic tape, removable computer disk, random access memory (RAM), read-only memory (ROM), rigid disk, and / or optical disk. In some embodiments using optical disk, the computer-readable storage medium 604 may include an optical disc read-only memory (CD-ROM), an optical disc read / write memory (CD-R / W), and / or a digital video optical disc (DVD).

[0142] In some embodiments, computer-readable storage medium 604 stores computer program code or instructions 606 configured to cause system 600 to perform some or all of the functions of system 600. In some embodiments, computer-readable storage medium 604 also stores information that facilitates the performance of some or all of the functions of system 600. In some embodiments, computer-readable storage medium 604 stores a database 618, which includes one or more of a component library, a digital circuit unit library, and a database.

[0143] System 600 includes an I / O interface 612 coupled to external circuitry. In some embodiments, the I / O interface 612 includes a keyboard, keypad, mouse, trackball, trackpad, touchscreen, and / or cursor arrow keys for transmitting information and commands to processor 602.

[0144] Network interface 614 is coupled to processor 602 and allows system 600 to communicate with network 616 to which one or more other computer systems are connected. Network interface 614 may include: a wireless network interface such as Bluetooth, WIFI, WIMAX, GPRS, or WCDMA; or a wired network interface such as Ethernet, USB, or IEEE-1364. In some embodiments, some or all of the functions of system 600 may be performed in two or more systems similar to system 600.

[0145] System 600 is configured to receive information via I / O interface 612. The information received via I / O interface 612 includes one or more of the following: instructions, data, design rules, component and unit libraries, and / or other parameters for processing by processor 602. The information is transmitted to processor 602 via bus 610. Furthermore, system 600 is configured to receive information related to the user interface (UI) via I / O interface 612. This UI information can be stored as UI 620 in computer-readable storage medium 604.

[0146] In some embodiments, some or all of the functions of system 600 are implemented through a standalone software application executed by a processor. In some embodiments, some or all of the functions of system 600 are implemented in a software application as part of an additional software application. In some embodiments, some or all of the functions of system 600 are implemented as plug-ins to a software application. In some embodiments, at least one function of system 600 is implemented as a software application as part of an EDA tool. In some embodiments, some or all of the functions of system 600 are implemented as software applications used by system 600. In some embodiments, layout diagrams are generated using tools such as VIRTUOSO, available from CADENCE DESIGN SYSTEMS, Inc., or another suitable layout generation tool.

[0147] In some embodiments, wiring, layout, and other processes are implemented as functions of a program stored in a non-transitory computer-readable recording medium. Examples of non-transitory computer-readable recording media include, but are not limited to, external / removable and / or internal / built-in storage or storage units, such as one or more optical discs, such as digital video optical discs or digital multifunction optical discs (DVDs), magnetic disks, such as hard disks, semiconductor memories, such as ROM and RAM, and memory cards, etc.

[0148] As described above, embodiments of system 600 include manufacturing tools 608 for implementing manufacturing processes of system 600. For example, based on a final layout, a photomask can be generated for manufacturing semiconductor devices using manufacturing tools 608.

[0149] Combination Figure 26 Other aspects of device manufacturing were disclosed. Figure 26 This is a block diagram of a semiconductor device manufacturing system 622 and an associated semiconductor device production process according to some embodiments. In some embodiments, based on a layout diagram, the manufacturing system 622 is used to manufacture one or more semiconductor masks and / or at least one component in a semiconductor device layer.

[0150] exist Figure 26In this system, semiconductor device manufacturing system 622 includes entities such as design room 624, mask room 626, and semiconductor device manufacturing plant / foundry (“Fab”) 628, which interact in the design, development, and manufacturing cycle and / or services related to manufacturing semiconductor devices (such as those described herein). The entities in system 622 are connected via a communication network. In some embodiments, the communication network is a single network. The communication network includes wired and / or wireless communication channels. Each entity interacts with one or more other entities and provides services to one or more other entities and / or receives services from one or fewer other entities. In some embodiments, two or more of design room 624, mask room 626, and semiconductor device manufacturing plant 628 are owned by a single larger room. In some embodiments, two or more of design room 624, mask room 626, and semiconductor device manufacturing plant 628 coexist in a shared facility and use shared resources.

[0151] Design studio (or design team) 624 generates a semiconductor device design layout 630. The semiconductor device design layout 630 includes various geometric patterns or semiconductor device layouts designed for semiconductor devices. The geometric patterns correspond to patterns of metal, oxide, or semiconductor layers that constitute various components of the semiconductor structure to be manufactured. These layers combine to form various semiconductor device features. For example, a portion of the semiconductor device design layout 630 includes various semiconductor device components, such as diagonal vias, active regions or areas, gate electrodes, source electrodes, drain electrodes, metal lines, partial vias, and openings for bonding pads, which will be formed on a semiconductor substrate (such as a silicon wafer) and various material layers disposed on the semiconductor substrate. Design studio 624 implements the design process to generate the semiconductor device design layout 630. The semiconductor device design layout 630 is presented in the form of one or more data files containing geometric pattern information. For example, the semiconductor device design layout 630 can be represented in GDSII or DFII file format. In some embodiments, the design process includes one or more of analog circuit design, digital circuit design, logic circuit design, standard cell circuit design, distribution network (PDN) design including rear via design, power supply voltage rail design, reference voltage rail design, layout and routing routines, and physical layout design.

[0152] Mask chamber 626 includes data preparation 632 and mask fabrication 634. Mask chamber 626 uses a semiconductor device design layout 630 to fabricate one or more masks 636 for fabricating various layers of a semiconductor device or semiconductor structure. Mask chamber 626 performs mask data preparation 632, in which the semiconductor device design layout 630 is converted into a representative data file (RDF). Mask data preparation 632 provides the RDF to mask fabrication 634. Mask fabrication 634 includes a mask writer that converts the RDF into an image on a substrate, such as a mask (marker) 636 or a semiconductor wafer 638. The design layout 630 is manipulated by mask data preparation 632 to conform to the characteristics of the mask writer and / or the standards of the semiconductor device fabrication plant 628. Figure 26 In this embodiment, mask data preparation 632 and mask manufacturing 634 are shown as separate elements. In some embodiments, mask data preparation 632 and mask manufacturing 634 may be collectively referred to as mask data preparation.

[0153] In some embodiments, mask data preparation 632 includes optical proximity correction (OPC), which uses lithographic enhancement techniques to compensate for image errors, such as those that may be caused by diffraction, interference, other process effects, etc. OPC adjusts the semiconductor device design layout diagram 630. In some embodiments, mask data preparation 632 includes further resolution enhancement techniques (RET), such as off-axis illumination, subresolution aids, phase-shift masks, other suitable techniques, or combinations thereof. In some embodiments, inverse lithography (ILT) is also used, which treats OPC as an inverse imaging problem.

[0154] In some embodiments, mask data preparation 632 includes a mask rule checker (MRC) that uses a set of mask creation rules to check the semiconductor device design layout 630, which has already been processed in the OPC, to ensure sufficient margin to account for variability in semiconductor manufacturing processes, etc. In some embodiments, the MRC modifies the semiconductor device design layout 630 to compensate for constraints during mask fabrication 634, which may undo some modifications performed by the OPC to satisfy the mask creation rules.

[0155] In some embodiments, mask data preparation 632 includes a lithography process check (LPC), which simulates a process performed by a semiconductor device fabrication plant 628. The LPC simulates this process based on a semiconductor device design layout 630 to create a simulated fabricated device. Processing parameters in the LPC simulation may include parameters related to various processes in the semiconductor device manufacturing cycle, parameters related to the tools used to manufacture the semiconductor device, and / or other aspects of the manufacturing process. The LPC considers various factors such as spatial image contrast, depth of focus (“DOF”), mask error enhancement factor (“MEEF”), other suitable factors, and combinations thereof. In some embodiments, after the LPC has created a simulated fabricated device, if the shape of the simulated device is not close enough to meet design rules, the OPC and / or MRC are repeated to further refine the semiconductor device design layout 630.

[0156] For clarity, the above description of mask data preparation 632 has been simplified. In some embodiments, data preparation 632 includes additional features, such as modifying the logic operations (LOPs) of the semiconductor device design layout 630 according to manufacturing rules. Furthermore, the processes applied to the semiconductor device design layout 630 during data preparation 632 can be performed in various different sequences.

[0157] After mask data preparation 632 and during mask fabrication 634, a mask 636 or a set of masks 636 is fabricated based on a modified semiconductor device design layout 630. In some embodiments, mask fabrication 634 includes performing one or more photolithographic exposures based on the semiconductor device design layout 630. In some embodiments, a pattern is formed on the mask (photomask or photomask plate) 636 using a mechanism of electron beam (e-beam) or multiple electron beams based on the modified semiconductor device design layout 630. The mask 636 can be formed using various techniques. In some embodiments, a binary technique is used to form the mask 636. In some embodiments, the mask pattern includes opaque regions and transparent regions. Radiation beams, such as ultraviolet (UV) beams, used to expose an image-sensitive material layer (e.g., photoresist) coated on the wafer are blocked by the opaque regions and transmitted through the transparent regions. In one example, a binary mask version of the mask 636 includes a transparent substrate (e.g., fused silica) and an opaque material (e.g., chromium) coated in the opaque regions of the binary mask. In another example, a phase-shifting technique is used to form mask 636. In the phase-shifting mask (PSM) version of mask 636, various features in the pattern formed on the phase-shifting mask are configured to have appropriate phase differences to improve resolution and imaging quality. In various examples, the phase-shifting mask can be attenuated PSM or alternating PSM. The mask generated by mask fabrication 634 is used in various processes. For example, this mask is used in ion implantation processes to form various doped regions in semiconductor wafer 638, in etching processes to form various etched regions in semiconductor wafer 635, and / or in other suitable processes.

[0158] Semiconductor device manufacturing plant 628 includes wafer fabrication 640. Semiconductor device manufacturing plant 628 is a semiconductor device manufacturing enterprise that includes one or more manufacturing facilities for manufacturing various different semiconductor device products. In some embodiments, semiconductor device manufacturing plant 628 is a semiconductor foundry. For example, there may be one manufacturing facility for front-end line (FEOL) manufacturing of multiple semiconductor device products, a second manufacturing facility for providing BEOL manufacturing for semiconductor device interconnects and packaging, and a third manufacturing facility for providing other services for foundry operations.

[0159] Semiconductor device fabrication plant 628 uses a mask 636, fabricated by mask chamber 626, to fabricate the semiconductor structure or semiconductor device 642 of this disclosure. Therefore, semiconductor device fabrication plant 628 uses at least indirectly the semiconductor device design layout 630 to fabricate the semiconductor structure or semiconductor device 642 of this disclosure. Furthermore, semiconductor wafer 638 includes a silicon substrate or other suitable substrate on which a material layer is formed, and semiconductor wafer 638 also includes one or more of various doped regions, dielectric components, multilevel interconnects, etc. (formed in subsequent fabrication steps). In some embodiments, semiconductor wafer 638 is fabricated by semiconductor device fabrication plant 628 using mask 636 to form the semiconductor structure or semiconductor device 642 of this disclosure. In some embodiments, semiconductor device fabrication includes performing one or more photolithographic exposures at least indirectly based on semiconductor device design layout 630.

[0160] Therefore, the disclosed embodiments include power pickup structures placed at different locations next to circuits (such as clock units), and different types of power pickup mechanisms, such as VB-type power pickup structures and FTV-type power pickup mechanisms.

[0161] The disclosed embodiments include a device comprising a substrate having at least one active region and a circuit located on the front side of the substrate. A front metallization layer is disposed above the circuit, and a rear metallization layer is disposed below the rear side of the substrate. A first power pickup structure is located on one side of the circuit for conducting one or more voltages from the rear metallization layer to the front metallization layer. In some embodiments, a second power pickup structure is disposed on the other side of the circuit, opposite to one side of the circuit, for conducting the one or more voltages from the rear metallization layer to the front metallization layer.

[0162] In some embodiments, the device includes a second front metallization layer disposed above the first front metallization layer, the first via, and the second via, wherein the first front metallization layer is electrically connected to the second front metallization layer through the first via, and the third front metallization layer is electrically connected to a power rail in the first front metallization layer through the second via.

[0163] In some embodiments, the power feed via, the metal-covered drain contact, and the via-to-drain contact are electrically connected from the rear metallization layer to the first front metallization layer, but not electrically connected to the P-type epitaxial layer or the N-type epitaxial layer.

[0164] In some embodiments, the rear metallization layer includes a segment that includes a micro-movement portion for connection to the power feed via.

[0165] In some embodiments, the integrated circuit device includes a second power pickup unit located on a second side of the circuit, the second side being opposite to the first side of the circuit, and the second power pickup unit is configured to conduct a first voltage VDD or a second voltage VSS from the rear metallization layer to the front metallization layer.

[0166] In some embodiments, the power pickup structure includes a rear metallization layer electrically connected to VB, VB electrically connected to an epitaxial layer, the epitaxial layer electrically connected to an MD contact, the MD contact electrically connected to a VDR contact, and the VDR contact electrically connected to a front metallization layer. This allows the power supply voltage to be conducted from the rear metallization layer to the front metallization layer via VB, the epitaxial layer, the MD contact, and the VDR contact.

[0167] In some embodiments, the power pickup structure includes an FTV, an MD contact, and a VDR contact, wherein the rear metallization layer is electrically connected to the FTV, the FTV is electrically connected to the MD contact, and the MD contact is electrically connected to the VDR contact. This allows the power supply voltage to be conducted from the rear metallization layer to the front metallization layer through the FTV, MD contact, and VDR contact.

[0168] The disclosed embodiments also include a method of manufacturing an integrated circuit, the method comprising forming a substrate having a front side and a rear side opposite to the front side; forming an active region on the front side of the substrate; forming a circuit on the front side of the substrate; forming a front metallization layer on the circuit; forming a rear metallization layer below the rear side of the substrate and electrically coupling it to at least one of the active regions; and forming a power pickup unit on one side of the circuit to conduct one or more voltages from the rear metallization layer to the front metallization layer.

[0169] In some embodiments, the method includes forming a second power pickup unit on a second side of the circuit opposite to the first side of the circuit to conduct the one or more voltages from the rear metallization layer to the front metallization layer.

[0170] In some embodiments, the method includes: forming a rear-side via electrically connected to at least one of the active regions of the epitaxial layer, wherein forming the rear-side metallization layer includes electrically connecting the rear-side metallization layer to the rear-side via.

[0171] In some embodiments, the method includes: forming a feed via electrically connected to at least one of the metal-covered drain contacts, wherein forming the back metallization layer includes electrically connecting the back metallization layer to the feed via.

[0172] In some embodiments, forming the rear metallization layer includes forming a rear metallization segment, the rear metallization segment including a micro-movement extension for electrical connection to the power feed via.

[0173] According to some embodiments, the integrated circuit includes a substrate having a front side and a rear side opposite to the front side. The substrate includes at least one active region on the front side. A circuit is located on the front side of the substrate, with a front-side metallization layer disposed above the circuit. A rear-side metallization layer is disposed below the rear side of the substrate, and a first power pickup unit is located on a first side of the circuit. The first power pickup unit is configured to conduct one or more voltages electrically coupled from the rear-side metallization layer to the front-side metallization layer.

[0174] In some embodiments, the integrated circuit includes a second power pickup unit located on a second side of the circuit, the second side being opposite to the first side of the circuit, and configured to conduct the one or more voltages from the rear metallization layer to the front metallization layer.

[0175] In some embodiments, the one or more voltages include a first voltage VDD and a second voltage VSS.

[0176] In some embodiments, in a top view of the integrated circuit, the first side of the circuit is either the long side or the short side.

[0177] In some embodiments, the integrated circuit includes a first rear via, a P-type epitaxial layer, a first metal-covered drain contact, and a first via-to-drain contact, wherein the rear metallization layer is electrically coupled to the front metallization layer through the first rear via, the P-type epitaxial layer, the metal-covered drain contact, and the first via-to-drain contact, such that a first voltage of the one or more voltages is conducted between the rear metallization layer and the front metallization layer through the first rear via, the P-type epitaxial layer, the first metal-covered drain contact, and the first via-to-drain contact.

[0178] In some embodiments, the integrated circuit includes a second rear via, an N-type epitaxial layer, a second metal-covered drain contact, and a second via-to-drain contact, wherein the rear metallization layer is electrically coupled to the front metallization layer through the second rear via, the N-type epitaxial layer, the second metal-covered drain contact, and the second via-to-drain contact, such that a second voltage of the one or more voltages is conducted between the rear metallization layer and the front metallization layer through the second rear via, the N-type epitaxial layer, the second metal-covered drain contact, and the second via-to-drain contact.

[0179] In some embodiments, the integrated circuit includes a power feed via, a metal-covered drain contact, and a via-to-drain contact, wherein the rear metallization layer is electrically coupled to the front metallization layer through the power feed via, the metal-covered drain contact, and the via-to-drain contact, such that the voltage VDD of the one or more voltages is conducted between the rear metallization layer and the front metallization layer through the power feed via, the metal-covered drain contact, and the via-to-drain contact.

[0180] In some embodiments, the metal-covered drain contact is electrically connected to a P-type epitaxial layer, and the back metallization layer includes a segment that includes a micro-movement portion for connection to the feed via.

[0181] In some embodiments, the integrated circuit includes a power feed via, a metal-covered drain contact, and a via-to-drain contact, wherein the rear metallization layer is electrically coupled to the front metallization layer through the power feed via, the metal-covered drain contact, and the via-to-drain contact, such that the voltage VSS of the one or more voltages is conducted between the rear metallization layer and the front metallization layer through the power feed via, the metal-covered drain contact, and the via-to-drain contact.

[0182] In some embodiments, the metal-covered drain contact is electrically connected to an N-type epitaxial layer, and the back metallization layer includes a segment that includes a micro-movement portion for connection to the feed via.

[0183] The foregoing has outlined features of several embodiments to enable those skilled in the art to better understand aspects of this disclosure. Those skilled in the art should understand that they can readily use this disclosure as the basis for designing or modifying other processes and structures to achieve the same purposes and / or advantages as the embodiments described herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of this disclosure, and that they can be modified, substituted, and altered in various ways without departing from the spirit and scope of this disclosure.

Claims

1. An integrated circuit, comprising: A substrate having a front side and a rear side opposite to the front side, the substrate including at least one active region on the front side; The circuit is located on the front side of the substrate; A front metallization layer is disposed above the circuit. A rear metallization layer is disposed on the rear side below the substrate; as well as A first power pickup unit is located on a first side of the circuit and is configured to conduct one or more voltages from the rear metallization layer to the front metallization layer, the rear metallization layer being electrically coupled to the at least one active region.

2. The integrated circuit of claim 1, further comprising a second power pickup unit located on a second side of the circuit, the second side being opposite to the first side of the circuit, and configured to conduct the one or more voltages from the rear metallization layer to the front metallization layer.

3. The integrated circuit according to claim 1, wherein, The one or more voltages include a first voltage VDD and a second voltage VSS.

4. The integrated circuit according to claim 1, wherein, In the top view of the integrated circuit, the first side of the circuit is either the long side or the short side.

5. An integrated circuit device, comprising: A substrate having a front side and a rear side opposite to the front side; The circuit is located on the front side of the substrate; A first front-side metallization layer is disposed on the substrate; A rear metallization layer is disposed on the rear side below the substrate; as well as The first power pickup unit is located on the first side of the circuit and includes a power feed via, a metal-covered drain contact, and a via-to-drain contact, wherein the via-to-drain contact is electrically connected from the rear metallization layer to the first front metallization layer.

6. The integrated circuit device of claim 5, comprising a second power pickup unit located on a second side of the circuit, the second side being opposite to the first side of the circuit, and the second power pickup unit being configured to conduct a first voltage VDD or a second voltage VSS from the rear metallization layer to the front metallization layer.

7. A method for manufacturing an integrated circuit, comprising: A substrate having a front side and a rear side opposite to the front side is provided; An active region is formed on the front side of the substrate; An epitaxial active region is formed in the active region; A metal-covered drain contact is formed that is electrically connected to the active region; A through-hole is formed that is electrically connected to the metal-covered drain contact to the drain contact; A front metallization layer is formed above the via-to-drain contact and electrically connected to the via-to-drain contact; as well as A rear-side metallization layer is formed below the rear side of the substrate and electrically coupled to at least one active region of the active region, wherein a transistor is formed in the circuit on the front side of the substrate, and a first power supply unit is formed on a first side of the circuit to conduct one or more voltages from the rear-side metallization layer to the front-side metallization layer.

8. The method of claim 7, comprising: A second power pickup unit is formed on a second side of the circuit opposite to the first side of the circuit to conduct the one or more voltages from the rear metallization layer to the front metallization layer.

9. The method according to claim 7, comprising: Forming a rear-side via electrically connected to at least one of the active regions of the epitaxial layer, wherein forming the rear-side metallization layer includes electrically connecting the rear-side metallization layer to the rear-side via.

10. The method of claim 7, comprising: Forming a feed via electrically connected to at least one of the metal-covered drain contacts, wherein forming the rear metallization layer includes electrically connecting the rear metallization layer to the feed via.

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