Integrated circuit device, integrated circuit structure and method of manufacturing integrated circuit

Abstract

A first interconnect structure is formed over a first side of a substrate. The first interconnect structure includes a plurality of first interconnect layers embedded in the first dielectric structure. One of the first interconnect layers includes a landing pad having a mesh structure. A second interconnect structure is formed over a second side of the substrate opposite the first side. The second interconnect structure includes a plurality of second interconnect layers embedded in a second dielectric structure. A recess is formed that extends through the second dielectric structure and the substrate, and partially through the first dielectric structure. The recess exposes at least a portion of the landing pad. Through-substrate vias (TSVs) are formed by filling the recess with one or more conductive materials. Embodiments of the invention provide an integrated circuit device, an integrated circuit structure, and a method of manufacturing an integrated circuit.

Description

Technical Field

[0001] Embodiments of this application relate to integrated circuit devices, integrated circuit structures, and methods of manufacturing integrated circuits. Background Technology

[0002] The semiconductor integrated circuit (IC) industry has experienced rapid growth. Technological advancements in IC materials and design have resulted in several generations of ICs, each with smaller and more complex circuitry than the previous one. In the course of IC development, functional density (i.e., the number of interconnect devices per chip area) has typically increased, while geometry (i.e., the smallest component (or wire) that can be produced using manufacturing processes) has decreased. This scaling down process usually yields benefits through increased production efficiency and reduced associated costs.

[0003] However, as semiconductor manufacturing progresses to more advanced technology nodes, additional manufacturing challenges may arise. For example, current implementations of landing pads for through-substrate vias (TSVs) can lead to excessive wafer warpage and / or stress, which in turn can cause performance degradation or even failure. Therefore, better TSV landing pads are needed. Summary of the Invention

[0004] One aspect of the present invention relates to an IC device. The IC device includes a substrate. The IC device includes a through-substrate via (TSV) extending vertically through the substrate. The IC device includes an interconnect structure disposed above a first side of the substrate. The interconnect structure includes a plurality of interconnect layers. A first interconnect layer of the plurality of interconnect layers includes landing pads on which the TSV rests. The landing pads have a mesh structure in at least one of a cross-sectional side view or a planar top view.

[0005] Another aspect of the present invention relates to a structure. The structure includes a substrate. The structure includes a first interconnect structure disposed over a first side of the substrate. The structure includes a second interconnect structure disposed over a second side of the substrate opposite to the first side. The structure includes a through-substrate via (TSV) extending vertically through the substrate and at least partially through the first and second interconnect structures. At least one of the first or second interconnect structure includes a landing pad physically extending to the TSV. The landing pad includes a plurality of conductive segments spaced apart from each other in a planar top view and a cross-sectional side view.

[0006] Another aspect of the present invention relates to a method. A first interconnect structure is formed over a first side of a substrate. The first interconnect structure includes a plurality of first interconnect layers embedded in a first dielectric structure. One of the first interconnect layers includes a landing pad having a mesh structure. A second interconnect structure is formed over a second side of the substrate opposite to the first side. The second interconnect structure includes a plurality of second interconnect layers embedded in a second dielectric structure. A recess is formed extending through the second dielectric structure and the substrate, and partially through the first dielectric structure. The recess exposes at least a portion of the landing pad. A through-substrate via (TSV) is formed by filling the recess with one or more conductive materials. Attached Figure Description

[0007] The various aspects of the invention will be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard industry practice, the components are not drawn to scale. In fact, the dimensions of the components may be arbitrarily increased or decreased for clarity of discussion. It should also be emphasized that the drawings illustrate only typical embodiments of the invention and should not be construed as limiting the scope, as the invention can be readily applied to other embodiments as well.

[0008] Figure 1A This is a schematic perspective view of a semiconductor device;

[0009] Figure 1B This is a schematic top view of a semiconductor device;

[0010] Figure 1C This is a schematic cross-sectional side view of a semiconductor device;

[0011] Figures 2-12 Various cross-sectional side views of a portion of an IC device according to an embodiment of the present invention are shown;

[0012] Figure 13A and Figure 14A Various planar top views of a portion of an IC device according to an embodiment of the present invention are shown;

[0013] Figure 13B and Figure 14B Various cross-sectional side views of a portion of an IC device according to an embodiment of the present invention are shown;

[0014] Figures 15A-15F Various planar top views of a portion of an IC device according to an embodiment of the present invention are shown;

[0015] Figure 16 The original IC design layout and the modified IC design layout of a portion of an IC device according to an embodiment of the present invention are shown;

[0016] Figure 17A flowchart illustrating a method for manufacturing an IC device according to an embodiment of the present invention is shown;

[0017] Figure 18 An integrated circuit manufacturing system according to various aspects of the present invention is shown. Detailed Implementation

[0018] The following disclosure provides numerous different embodiments or examples for implementing various features of the invention. Specific examples of components and arrangements are described below to simplify the invention. Of course, these are merely examples and are not intended to limit the invention. For example, in the following description, forming a first component above or on a second component can include embodiments where the first and second components are in direct contact, and can also include embodiments where an additional component can be formed between the first and second components, thereby allowing the first and second components to not be in direct contact. Furthermore, reference numerals and / or letters may be repeated in various examples. This repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0019] Additionally, reference numerals and / or letters may be repeated in various instances of this invention. This repetition is for simplification and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed. Furthermore, in the following invention, forming on, connecting to, and / or coupling to another component can include embodiments where the components are formed in direct contact, or embodiments where additional components can be formed between the components, thereby allowing the components to not be in direct contact. Additionally, terms of spatial relative position, such as “lower,” “upper,” “horizontal,” “vertical,” “above,” “under,” “below,” “upward,” “downward,” “top,” “bottom,” etc., and their derivatives (e.g., “horizontally,” “downward,” “upward,” etc.), are used to facilitate the disclosure of the relationship between one component and another. Spatial relative terms are intended to cover different orientations of the device, including components. Furthermore, when numbers or ranges of numbers are described using terms such as “about,” “approximately,” etc., these terms are intended to cover numbers that fall within a reasonable range of the described number, such as within + / - 10% of the described number or other values ​​understood by those skilled in the art. For example, the term “about 5 nm” covers a size range from 4.5 nm to 5.5 nm.

[0020] This invention generally relates to improved designs for landing pads used in through-substrate vias (TSVs), and more specifically, to TSV landing pads with a mesh structure that helps reduce stress and / or wafer warpage. More specifically, TSVs are used to provide electrical connections in integrated circuit (IC) packages. Conductive landing pads are implemented to provide landing space to the TSV, providing both electrical connections and mechanical support. For convenience, current TSV landing pads are typically implemented as solid metal blocks. Unfortunately, this solid block design for TSV landing pads may have a metal pattern density greater than optimal, which can lead to wafer warpage and / or excessive stress. Furthermore, TSV landing pads with a solid block design may experience excessive thermal expansion and / or contraction, which can further exacerbate wafer warpage and / or stress.

[0021] To address the problems discussed above, this invention implements the TSV landing pads as a mesh structure. For example, in some embodiments, the invention may implement the TSV as multiple metal segments spaced apart from each other in certain cross-sectional side views and / or planar top views, rather than implementing the TSV landing pads as solid metal blocks. The mesh structure of the TSV landing pads described herein may also require various geometric designs and / or shapes in the planar top view, such that the metal pattern density corresponding to the TSV landing pads is not 100% (as is already the case for solid block designs of TSV landing pads), but within a predetermined range of less than 100% (e.g., 20% to 80%). This mesh structure design for TSV landing pads can allow for reduced stress and / or better tolerances related to thermal expansion and / or contraction, which may result in reduced wafer warpage and / or stress. Consequently, the performance and / or yield of IC devices can be improved.

[0022] Now refer to Figure 1- Figure 18 The various aspects of the invention will be discussed in more detail. More specifically, Figures 1A-1C The basic structure of an exemplary transistor device that can be implemented in an IC device will be described. Figures 2-12 Various cross-sectional side views of a portion of an IC device according to an embodiment of the present invention are shown at different manufacturing stages. Figures 13A-14A Various planar top views of the TSV landing pads are shown. Figures 13B-14B Various cross-sectional side views of the TSV landing pads according to embodiments of the present invention are shown. Figures 15A-15F The IC design layout of the TSV landing pad mesh structure according to various embodiments of the present invention is shown. Figure 16 The process of modifying the original IC design layout to generate a modified IC design layout corresponding to the TSV landing pads is illustrated according to an embodiment of the present invention. Figure 17A flowchart illustrating a method for manufacturing an IC device according to an embodiment of the present invention is shown. Figure 18 An integrated circuit manufacturing system according to various aspects of the present invention is shown.

[0023] Now for reference Figure 1A and Figure 1B The figures show a three-dimensional perspective view and a top view of a portion of an integrated circuit (IC) device 90. The IC device 90 may be an intermediate device or a portion thereof manufactured during IC processing, and may include: static random access memory (SRAM) and / or other logic circuitry; passive components, such as resistors, capacitors, and inductors; and active components, such as p-type FETs (PFETs), n-type FETs (NFETs), FinFETs, metal-oxide-semiconductor field-effect transistors (MOSFETs), complementary metal-oxide-semiconductor (CMOS) transistors, bipolar transistors, high-voltage transistors, high-frequency transistors, and / or other memory cells.

[0024] exist Figure 1A and Figure 1B In the example shown, IC device 90 is a three-dimensional fin FET (FinFET) device. In this context, a FinFET device is a fin field-effect transistor device that has recently become increasingly popular in the semiconductor industry because it offers several advantages compared to traditional metal-oxide-semiconductor field-effect transistor (MOSFET) devices (e.g., "planar" transistor devices). These advantages may include better chip area efficiency, improved carrier mobility, and manufacturing processes compatible with those of planar devices. Therefore, it may be desirable to use FinFET devices in the design of integrated circuit (IC) chips, for part or all of an IC chip.

[0025] refer to Figure 1AThe IC device 90 includes a substrate 110. The substrate 110 may include: a basic (single-element) semiconductor, such as silicon, germanium, and / or other suitable materials; a compound semiconductor, such as silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, indium antimonide, and / or other suitable materials; an alloy semiconductor, such as SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, GaInAsP, and / or other suitable materials. The substrate 110 may be a single-layer material with a uniform composition. Alternatively, the substrate 110 may include multiple material layers with similar or different compositions suitable for IC device fabrication. In one example, the substrate 110 may be a silicon-on-insulator (SOI) substrate having a semiconductor silicon layer formed on a silicon oxide layer. In another example, the substrate 110 may include a conductive layer, a semiconductor layer, a dielectric layer, other layers, or combinations thereof. Various doped regions, such as source / drain regions, may be formed in or on the substrate 110. Depending on the design requirements, the doped region can be doped with an n-type dopant such as phosphorus or arsenic, and / or a p-type dopant such as boron. The doped region can be formed directly on the substrate 110 in a p-well structure, an n-well structure, a double-well structure, or using a bump structure. The doped region can be formed by implantation of doped atoms, in-situ doped epitaxial growth, and / or other suitable techniques.

[0026] A three-dimensional active region comprising a nanostructure 170 is formed on a substrate 110. The active region is an elongated fin-like structure protruding upward beyond the substrate 110. Hereinafter, the protruding structure 120 may be interchangeably referred to as fin structure 120. The fin structure 120 may be fabricated using a suitable process including photolithography and etching processes. The photolithography process may include: forming a photoresist layer on the substrate 110, exposing the photoresist to a pattern, performing a post-exposure baking process, and developing the photoresist to form a mask element (not shown) including a resist. The mask element is then used to etch recesses into the substrate 110, leaving the fin structure 120 on the substrate 110. The etching process may include dry etching, wet etching, reactive ion etching (RIE), and / or other suitable processes. In some embodiments, the fin structure 120 may be formed by a dual patterning or multiple patterning process. Typically, dual patterning or multiple patterning processes combine photolithography and self-alignment processes, allowing the creation of patterns with, for example, smaller pitches compared to those achievable using a single direct photolithography process. As an example, a layer can be formed on top of the substrate and patterned using a photolithography process. Spacers are then formed next to the patterned layer using a self-aligned process. The layer is then removed, and the remaining spacers or mandrels can then be used to pattern the fin 120.

[0027] The IC device 90 also includes source / drain components 122 formed over the fin structure 120. The source / drain components 122 may include an epitaxial layer epitaxially grown on the fin structure 120. The IC device 90 also includes an isolation structure 130 formed over the substrate 110. The isolation structure 130 electrically isolates various components of the IC device 90. The isolation structure 130 may include silicon oxide, silicon nitride, silicon oxynitride, fluorine-doped silicate glass (FSG), low-k dielectric materials, and / or other suitable materials. In some embodiments, the isolation structure 130 may include shallow trench isolation (STI) components. In one embodiment, the isolation structure 130 is formed by etching trenches in the substrate 110 during the formation of the fin structure 120. The trenches can then be filled using the isolation materials described above, followed by a chemical mechanical planarization (CMP) process. Other isolation structures, such as field oxides, localized oxidation of silicon (LOCOS), and / or other suitable structures, may also be implemented as the isolation structure 130. Alternatively, the isolation structure 130 may include a multilayer structure, for example, having one or more thermal oxide pad layers.

[0028] IC device 90 also includes a gate structure 140 formed over fin structure 120 and bonded to fin structure 120 on three sides of the channel region of each fin 120. Gate structure 140 may be a dummy gate structure (e.g., comprising an oxide gate dielectric and a polysilicon gate electrode), or it may be an HKMG structure comprising a high-k gate dielectric and a metal gate electrode, wherein the HKMG structure is formed by replacing the dummy gate structure. Although not depicted herein, gate structure 140 may include additional material layers, such as an interface layer, capping layer, other suitable layers, or combinations thereof, over fin structure 120.

[0029] refer to Figure 1B Multiple fin structures 120 are oriented longitudinally along the X direction, and multiple gate structures 140 are oriented longitudinally along the Y direction, i.e., substantially perpendicular to the fin structures 120. In many embodiments, the IC device 90 includes additional components, such as gate spacers disposed along the sidewalls of the gate structures 140, a hard mask layer disposed above the gate structures 140, and many other components.

[0030] Figure 1C A schematic cross-sectional side view of a portion of an IC device 5 manufactured according to an embodiment of the present invention is shown, wherein the IC device 5 is a gate-all-around (GAA) device, which may be referred to below as GAA device 5. It should be understood that in some embodiments the GAA device 5 may be an NFET, or in other embodiments it may be a PFET.

[0031] refer to Figure 1CThe cross-sectional view of GAA device 5 is taken along the XZ plane, where the X direction (and...) Figure 1A The X direction is the same as the horizontal direction, and the Z direction is the same as the horizontal direction. Figure 1A The Z-direction is the same in both directions, and is perpendicular to the direction. The GAA device 5 includes a fin structure 10, which may be similar to the fin structure 120 discussed above. In some embodiments, the fin structure 10 includes silicon. The GAA device 5 includes a source / drain component 20, which may be similar to the source / drain component 122 discussed above. In embodiments where the GAA device 5 is an NFET, the source / drain component 20 includes silicon-phosphorus (SiP). In embodiments where the GAA device 5 is a PFET, the source / drain component 20 includes silicon-germanium (SiGe).

[0032] GAA device 5 includes multiple channels, such as Figure 1C The channels 30-33 shown are illustrated. Each of the channels 30-33 comprises a semiconductor material, such as silicon or a silicon compound. The channels 30-33 are nanostructures (e.g., having dimensions in the range of several nanometers) and may also each have an elongated shape and extend along the X-direction. In some embodiments, the channels 30-33 may each have a nanowire shape, a nanosheet shape, a nanotube shape, etc. The cross-sectional profile of the nanowire, nanosheet, or nanotube may be circular / circular, square, rectangular, hexagonal, elliptical, or a combination thereof.

[0033] In some embodiments, the lengths of channels 30-33 (e.g., measured along the X direction) may be different from each other. For example, the length of channel 30 may be less than the length of channel 31, the length of channel 31 may be less than the length of channel 32, and the length of channel 32 may be less than the length of channel 33. In some embodiments, each of channels 30-33 may not have a uniform thickness.

[0034] In some embodiments, the spacing (e.g., measured along the Z direction) between channels 30-33 (each channel from its adjacent channel) is in the range of about 2 nanometers (nm) to about 12 nm. In some embodiments, the thickness (e.g., measured along the Z direction) of each of channels 30-33 is in the range of about 2 nm to about 5 nm. In some embodiments, the width (e.g., measured along the Z direction) of each of channels 30-33 is in the range of about 2 nm to about 5 nm. Figure 1A (Measured in the Y direction) in the range of approximately 15 nm to approximately 150 nm. Multiple interface layers (IL) 40 can also be formed on the upper and lower surfaces of the channels 30-33.

[0035] The GAA device 5 also includes a gate structure disposed above and between channels 30-33. The gate structure may include a gate dielectric layer 50. In some embodiments, the gate dielectric layer 50 includes a high-k gate dielectric. The gate structure also includes one or more work-function metal layers 60. In embodiments where the GAA device 5 is an NFET, the one or more work-function metal layers 60 include N-type work-function metal layers such as TiAlC. In embodiments where the GAA device 5 is a PFET, the one or more work-function metal layers 60 include P-type work-function metal layers such as TiN.

[0036] The gate structure also includes fill metal 80. In the portion of the gate structure formed above channels 30-33, fill metal 80 is formed above one or more function metal layers 60. One or more function metal layers 60 are U-shaped and surround the fill metal 80, and gate dielectric layer 50 is also U-shaped and surrounds one or more function metal layers 60. In the portion of the gate structure formed between channels 30-33, fill metal 80 is circumferentially surrounded by one or more function metal layers 60 (in the cross-sectional view), and then one or more function metal layers 60 are circumferentially surrounded by gate dielectric layer 50. It should be understood that the gate structure may also include an adhesive layer formed between one or more function metal layers 60 and fill metal 80 to increase adhesion. However, for simplicity, such an adhesive layer is not specifically shown herein.

[0037] The GAA device 5 also includes a gate spacer 90 and an internal spacer 95 disposed on the sidewalls of the gate dielectric layer 50. The internal spacer 95 is also disposed between channels 30-33. The gate spacer and the internal spacer 95 may include a dielectric material, such as a low-k material such as SiOCN, SiON, SiN, or SiOC.

[0038] The GAA device 5 also includes a source / drain contact 96 formed above the source / drain component 20. The source / drain contact 96 may include a conductive material, such as cobalt, copper, aluminum, tungsten, or a combination thereof. The source / drain contact 96 is surrounded by barrier layers, such as barrier layers 97A and 97B, which help prevent or reduce material diffusion from and into the source / drain contact 96. In some embodiments, barrier layer 97A comprises TiN, and barrier layer 97B comprises SiN. A silicide layer 98 may also be formed between the source / drain component 20 and the source / drain contact 96 to reduce the source / drain contact resistance. The silicide layer 98 may comprise a metal silicide material, such as cobalt silicide in some embodiments.

[0039] GAA device 5 also includes interlayer dielectric (ILD) 99. ILD 99 provides electrical isolation between the various components of GAA device 5, such as between the gate structure and the source / drain contacts 96.

[0040] GAA devices can also offer advantages such as better chip area efficiency and improved carrier mobility. Thus, advanced IC chips can also be implemented using GAA devices. However, it should be understood that the present invention is not limited to any particular number of devices or device regions, nor to any particular device configuration, unless otherwise required. For example, although FinFET devices or GAA devices have been described as potential transistors that can be used to implement IC chips or portions thereof, the concepts of the present invention, discussed in more detail below, can also be applied to implementing IC chips using planar FET devices.

[0041] Figures 2-12 This is a series of cross-sectional side views illustrating a manufacturing process for fabricating TSV landing pads with a mesh structure according to an embodiment of the present invention. The cross-sectional side views are taken along the YZ plane, which is defined by the horizontal Y direction and the vertical Z direction. Reference Figure 2 The IC device 200 shown herein includes a portion of a wafer. In the illustrated embodiment, the IC device 200 includes a substrate 210, which may be an embodiment of the substrate 110 discussed above. For example, the substrate 210 may include a basic semiconductor (e.g., silicon or germanium), a compound semiconductor (e.g., silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, or indium antimonide), or an alloy semiconductor (e.g., SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, or GaInAsP). In some embodiments, the substrate 210 may also be a single-layer material with a uniform composition, or may include multiple material layers with similar or different compositions suitable for IC device fabrication (e.g., a silicon-on-insulator (SOI) substrate having a semiconductor silicon layer formed on a silicon oxide layer). References above Figures 1A-1C The transistors discussed, such as FinFET devices or GAA devices, can be formed in or on substrate 210 to form various types of circuits. However, for simplicity, such circuits are not specifically shown herein.

[0042] Substrate 210 has two opposing sides: side 220 (which may be referred to as the "front side") and side 221 (which may be referred to as the "back side"). In interconnect structure formation process 235, interconnect structure 230 is formed over side 220 of substrate 210. In this regard, interconnect structure 230 may be a multilayer interconnect (MLI) structure, which includes multiple interconnect layers (e.g., M0 to M...). yThe interconnect layers include multiple conductive vias that interconnect the various interconnect layers together. The interconnect layers may include multiple metal lines, which can be implemented as elongated conductive strips. The metal lines are configured to route electrical signals, and metal lines from different interconnect layers are interconnected through conductive vias. Figure 2 As shown, the metal wires and conductive vias are embedded in the dielectric material 240 of the interconnect structure 230, which provides proper electrical isolation for the metal wires and / or conductive vias.

[0043] In various embodiments, dielectric material 240 may also be formed using silicon oxide, silicon oxynitride, silicon nitride, silicon carbide, or a low-k dielectric material having a dielectric constant lower than that of silicon oxide (e.g., less than about 3.9). As a non-limiting example, low-k dielectric materials may include black diamond (a registered trademark of Applied Materials), carbon-containing low-k dielectric materials, hydrogen silsesquioxane (HSQ), methyl silsesquioxane (MSQ), etc. These dielectric materials may be formed via one or more deposition processes of interconnect structure formation process 235. In various embodiments, a damascene process (e.g., a dual damascene process) may be used as part of interconnect structure formation process 235 to form metal lines and conductive vias. In various embodiments, the metal lines and / or conductive vias may include copper on a diffusion barrier layer. The diffusion barrier layer may be formed of titanium, titanium nitride, tantalum, tantalum nitride, etc.

[0044] According to various aspects of the invention, the topmost (e.g., the one furthest from the substrate 210) interconnect layer M y A subset of the metal lines can be specifically configured to implement TSV landing pads 250 with a mesh structure. Figure 2 In a cross-sectional side view, this mesh structure itself appears to consist of multiple metal line segments horizontally spaced apart from each other along the Y direction, with the gaps between the metal lines filled by portions of dielectric material 240. This mesh structure of the TSV landing pad 250 can provide benefits related to wafer warpage and / or stress. For example, the mesh structure allows for a more uniform distribution and / or reduction of stress associated with the TSV landing pad 250, which may result in reduced wafer warpage. Additionally, since the TSV landing pad 250 is not a single metal block, each conductive element for the TSV landing pad 250 has more space to contract and / or expand in response to different thermal conditions, which can also reduce wafer warpage. In some embodiments, the mesh structure is configured such that the metal pattern density of the TSV landing pad 250 is in the range of about 20% to about 80%. This range is specifically configured so that the TSV landing pad 250 can achieve the potential benefits associated with stress reduction and more flexible thermal shrinkage / expansion, while still being able to handle its intended function of providing electrical connection and mechanical support for the TSV (which will be formed in a later process).

[0045] Please note that the TSV landing pad 250 may be located in a region of the interconnect structure 230 away from the “main region” 260, where most (if not all) of the metal traces and conductive vias may be located for electrical wiring purposes. In other words, there may be no metal traces or conductive vias of the interconnect structure 230 between the TSV landing pad 250 and the substrate 210. That is, a portion of the dielectric material 240 (rather than any conductive element of the interconnect layer of the interconnect structure 230) lies directly beneath the TSV landing pad 250. This allows the TSV (formed in a later manufacturing stage) to extend through the portion of the dielectric material 240 located between the TSV landing pad 250 and the substrate 210 without accidentally short-circuiting to another conductive element.

[0046] Now for reference Figure 3 A substrate thinning process 300 is applied to the IC device 200 from side 221. In some embodiments, the substrate thinning process 300 may include a mechanical polishing process and a chemical thinning process. For example, during the mechanical polishing process, a significant amount of substrate material may first be removed from the substrate 210. Subsequently, the chemical thinning process may apply etching chemicals to the side 221 of the substrate 210 to further reduce the thickness of the substrate 210. As a result of the substrate thinning process 300, the thickness of the substrate 210 along the vertical Z-direction is significantly reduced. For example, in some embodiments, the substrate 210 may have a thickness on the order of several micrometers (or tens of micrometers) when the substrate thinning process 300 is completed.

[0047] Now for reference Figure 4 The IC device 200 shown is flipped vertically along the Z direction, causing sides 220 and 221 to switch. In other words, in Figure 4 In this configuration, interconnect structure 230 is now disposed beneath substrate 210. Note that the vertical flipping of IC device 200 can also be performed before substrate thinning process 300. In any case, interconnect structure 330 is formed above sidewall 221 of substrate 210 via interconnect structure forming process 335. Similar to interconnect structure 230, interconnect structure 330 can also be an MLI structure, comprising multiple interconnect layers (e.g., BMO to BMO). z1 The interconnect layers and conductive vias are also embedded in a dielectric material 340, which may have a material composition substantially similar to that of the dielectric material 240 discussed above.

[0048] Now for reference Figure 5One or more etching processes 360 can be performed to etch the recess 370, which extends vertically through the interconnect structure 330 and substrate 210 in the IC device 200, and partially through the interconnect structure 230. For example, one or more etching processes 360 may include a dry etching process in some embodiments and a wet etching process in other embodiments. One or more etching processes 360 can be performed until the TSV landing pad 250 is reached. In other words, one or more etching processes 360 can be configured to etch the recess 370 on the interconnect layer M. y There is etch selectivity between the IC device 200 and the remaining materials, including dielectric materials 240 / 340 and substrate 210. For example, one or more etching processes 360 can be configured to etch interconnect layers M at a higher speed than the etched interconnect layers M. y The material (e.g., one or more metallic materials) etches away the dielectric material 340 / 240 and the substrate 210 at a much faster rate, and once the material reaching the interconnect layer M is detected... y Then it can stop. In this way, the interconnect layer M y It can be used as an etch stop layer. When one or more etch processes are completed at 360°, the interconnect layer M... y The surface is exposed to the side 221 through the recess 370. The recess 370 may also be referred to as a TSV groove because it will be filled with TSV in a subsequent process.

[0049] Now for reference Figure 6 A TSV formation process 390 is performed to form a TSV 400 in a recess 370. For example, the TSV formation process 390 may include one or more deposition processes, such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), etc. The deposition process deposits one or more conductive materials in the recess 370. For example, the deposition process may first deposit a barrier layer to partially fill the recess 370, wherein the barrier layer may be deposited to physically contact the TSV landing pad 250. Subsequently, an electroplating process may be performed as part of the TSV formation process 390 to completely fill the recess 370 using a metallic material such as copper. The metallic material may be formed on the barrier layer. During this manufacturing stage, the TSV 400 extends through the interconnect structure 330 (e.g., perpendicularly through the dielectric material 340), through the substrate 210, and partially through the interconnect structure 230 (e.g., perpendicularly through the dielectric material 240).

[0050] Now for reference Figure 7 Perform interconnect layer formation process 420 to form interconnect layer BM Z2This serves as the top layer in the interconnect layer of the interconnect structure 330. The interconnect layer formation process 420 may include a deposition process to be applied over the TSV 400 and over the rest of the interconnect structure 330 (e.g., on the BM). Z1 An additional amount of dielectric material 340 is deposited above the layer. Subsequently, a dual damascene process can be performed to etch trenches in the dielectric material 340 and fill the etched trenches with a conductive material to form conductive pads 450, and a BM connecting the conductive pads 450 to the interconnect structure 330. Z1 Conductive vias 451 for layer interconnection. For example... Figure 7 As shown in the cross-sectional side view, the bottom surface of the conductive pad 450 extends to the top surface of the TSV 400. In other words, the conductive pad 450 is in physical (and electrical) contact with the TSV 400. Since the bottom surface of the TSV 400 extends to the top surface of the TSV landing pad 250—for example, the TSV 400 is in physical and electrical contact with the TSV landing pad 250—it can be said that the TSV 400 electrically couples the conductive pad 450 and the TSV landing pad 250 together, which also means that an electrical connection can also be established between the interconnect structure 230 and the interconnect structure 330.

[0051] Please note that since conductive pad 450 is in physical contact with TSV 400, conductive pad 450 can be considered as another landing pad for TSV 400, and it can be interchangeably referred to as a landing pad. Figure 7 In the embodiment shown, the conductive pad 450 has a solid block configuration: it can be a single piece of metal extending to the “main region” 460 of the interconnect structure 330, where most (if not all) of the metal lines and conductive vias of the interconnect structure 330 are located for electrical wiring purposes. However, in other embodiments, the conductive pad 450 may also employ a mesh structure similar to the TSV landing pad 250.

[0052] To illustrate, in Figure 8 In the alternative embodiments shown, the conductive pad 450 can be implemented similarly to the TSV landing pad 250. For example, similar to the TSV landing pad 250, the conductive pad 450 is no longer a single solid metal block, but consists of multiple conductive strips (e.g., each conductive strip is an interconnect layer BM). Z2 Different metal wire segments), these conductive strips are separated from each other by multiple gaps along the Y direction (these gaps are filled with dielectric material 340).

[0053] It should also be understood that the TSV landing pad 250 does not need to be formed in the bottommost interconnect layer of the interconnect structure 230, and / or the conductive pad 450 does not need to be formed in the topmost interconnect layer of the interconnect structure 330. In other embodiments, additional conductive pads, which may also have a mesh structure, may be implemented above the conductive pad 450 and / or below the TSV landing pad 250.

[0054] Figure 9 This alternative embodiment of the invention is shown. Figure 9 In some embodiments, the interconnect structure 230 may further include a structure located at M y M "below" the interconnect layer y+1 The interconnect layer is positioned further away from the substrate 210 compared to the other interconnect layers of the interconnect structure 230. y+1 The interconnect layer includes conductive pads 470, which also have a mesh structure. For example, the mesh structure of the conductive pads 470 can be similar to that of the TSV landing pads 250, as it includes multiple conductive strips spaced apart from each other along the Y direction. The conductive pads 470 are electrically coupled to the TSV landing pads 250 through multiple conductive vias 480. For example, each conductive strip (e.g., a metal wire) of the conductive pads 470 is connected to a corresponding conductive strip of the TSV landing pads 250 through a different conductive via.

[0055] It should be understood that M y+1 The interconnect layer (including conductive pads 470) is formed prior to the formation of the TSV 400 (e.g., prior to the formation of the recess 370). Advantageously, the conductive pads 470 can be used as an additional etch stop layer. For example, even if the etching of the recess 370 is too aggressive, extending to M... y Beyond the TSV landing pad 250 of the interconnect layer, it can still be located in M. y+1 The conductive pads on the interconnect layer stop at point 470.

[0056] Regardless of the implementation Figure 9 The embodiments are still Figure 10 In all embodiments, additional manufacturing processes can be implemented to complete the fabrication of IC device 200. For example, IC device 200 can be bonded to or otherwise connected to another IC die via side 220. In some embodiments, the other IC die may be a die substantially identical to the IC die of IC device 200. In other embodiments, the IC die may have a different function than IC device 200. Side 221 of IC device 200 may also be bonded to a carrier or may have conductive bumps formed to further provide electrical connections between IC device 200 and other external devices.

[0057] Figures 10-12This is an enlarged cross-sectional side view corresponding to a portion of IC device 200, illustrating the different stages of TSV formation. More specifically, the enlarged view corresponds to... Figure 5 The portion of the IC device covered by the dashed box includes the bottom of the recess 370 and the TSV landing pad 250. Now refer to... Figure 10 Manufacturing stage and Figure 5 The stage shown is the same, that is, after the recess 370 has been etched, but before the TSV 400 has been formed to fill the recess 370. For simplicity, Figure 10 The TSV landing pad 250 shown includes four distinct conductive segments 250A, 250B, 250C, and 250D as part of a mesh structure. However, it should be understood that in other embodiments, the TSV landing pad 250 may include more or fewer conductive segments than four such conductive segments 250A-250D.

[0058] According to one aspect of the invention, the etching of the recess 370 is specifically configured such that the upper surface of some conductive segments is partially, but not completely, exposed. For example, conductive segment 250A has an upper surface consisting of portions 500 and 501, wherein portion 501 is exposed by the recess 370, while portion 500 is not exposed through the recess 370 but is covered by a portion of the dielectric material 240. Alternatively, the etching of the recess 370 is configured such that the upper right corner (i.e., the corner facing the recess 370) is exposed, but the upper left corner (i.e., the corner facing away from the recess 370) is covered by the dielectric material 240. Similarly, conductive segment 250D has a portion 502 of the upper surface exposed by the recess 370, and a portion 503 of the upper surface not exposed but covered by a portion of the dielectric material 240, meaning that the upper left corner of conductive segment 250D is exposed, while the upper right corner of conductive segment 250D is covered by the dielectric material 240.

[0059] The configuration of the recess 370 discussed above also results in differences in its lateral dimensions at different depth levels. For example, the bottom of the recess 370 has a lateral dimension 520 along the Y direction, measured from the right edge of conductive segment 250A to the left edge of conductive segment 250D. Meanwhile, the portion of the recess 370 located above conductive segments 250A-250D has a lateral dimension 521 along the Y direction, measured between the two edges of the dielectric material 240. The lateral dimension 521 is larger than the lateral dimension 520, which is an inherent consequence of the fact that conductive segments 250A and 250D each laterally protrude beyond the edges of the dielectric material 240 in a direction toward the center of the recess 370.

[0060] The configuration of the recess 370 discussed above provides certain benefits. For example, it reduces the likelihood of bubbles or voids becoming trapped in the TSV 400 that will form in subsequent manufacturing stages. More details are now available with reference to... Figure 11 A deposition process 390A (as part of a TSV formation process 390) is performed to deposit a barrier layer 400A in the recess 370. The barrier layer 400A is formed on a portion 501 of the upper surface of the conductive segment 250A and on the exposed right edge surface of the conductive segment 250A. The barrier layer 400A is also deposited on a portion of the bottom surface of the dielectric material 240 disposed between the conductive segments 250A and 250B. Because the gap 540 laterally separating the conductive segments 250A and 250B is relatively wide, the barrier layer 400A can be deposited with good gap-filling properties, and the likelihood of bubbles or voids getting trapped beneath the barrier layer 400A is low.

[0061] In contrast, if the recess 370 is not configured as discussed above, the sidewall of the dielectric material 240 (i.e., the edge defining the left edge of the recess 370) will be located on the left or right side of the conductive section 250A. Assuming such a sidewall of the dielectric material 240 is located on the right side of the conductive section 250A (meaning the entire upper surface of the conductive section 250A is covered by the dielectric material 250), then the resulting gap 540 between the sidewall of the dielectric material 240 and the left sidewall of the conductive section 250B will be smaller (i.e., narrower along the Y direction). A smaller gap 540 may lead to gap filling problems, potentially causing bubbles or voids to become trapped below or inside the barrier layer 400A. Similarly, assuming the sidewalls of dielectric material 240 are located on the left side of conductive segment 250A (meaning the entire upper surface of conductive segment 250A is exposed to recess 370), the resulting gap between the sidewalls of dielectric material 240 and the left sidewall of conductive segment 250A could also be very small (i.e., very narrow along the Y direction). Such a small gap 540 could also lead to gap filling problems and cause bubbles or voids to become trapped below or inside barrier layer 400A. This invention avoids these potential problems by carefully configuring recess 370 to expose only a portion, rather than all, of the upper surfaces of conductive segments 250A and 250D. This improves the gap filling performance of barrier layer 400A and reduces the likelihood of bubbles or voids being trapped by barrier layer 400A. Consequently, device performance can be improved.

[0062] Now for reference Figure 12An electroplating process 390B (as part of the TSV formation process 390) is performed to form a conductive material 400B in the recess 370 as the remainder of the TSV 400. In some embodiments, the conductive material 400B comprises copper, but other types of conductive materials may be implemented in alternative embodiments. The conductive material 400B is formed on a barrier layer 400A. In some embodiments, the barrier layer 400A and the conductive material 400B may be formed above the upper surface of the dielectric material 240, and a planarization process such as chemical mechanical polishing (CMP) may be performed to remove excess portions of the conductive material 400B and the barrier layer 400A formed on the upper surface of the dielectric material 240, so that the resulting TSV 400 and dielectric material 140 may have substantially coplanar upper surfaces, for example, as Figure 6 As shown in the image.

[0063] Figure 13A and Figure 13B A plan view and a cross-sectional side view of a portion of an IC device 200 including a TSV 400 and a TSV landing pad 250 according to an embodiment of the present invention are shown. More specifically, Figure 13A The top view corresponds to the horizontal plane defined by the X direction and the Y direction perpendicular to the X direction. Figure 13B The cross-sectional side view corresponds to a vertical plane defined by the Y direction and the Z direction, which is orthogonal to the horizontal XY plane. Figure 13B The cross-sectional side view is along Figure 13A It is cut by the section line A-A' in the middle.

[0064] exist Figures 13A-13B In the embodiment shown, five conductive segments 250A, 250B, 250C, 250D, and 250F are used to implement the TSV landing pad 250. These conductive segments are from M y Metal lines of the interconnect layer. These conductive segments 250A-250F each extend horizontally along the X direction and are spaced apart from each other along the Y direction. Thus, a mesh structure is formed through the conductive segments 250A-250F. This mesh structure is formed with a pattern density between approximately 20% and approximately 80%. In this regard, the pattern density of the mesh structure can be defined as the amount of area of ​​the conductive segments 250A-250E (e.g., in a top view) divided by the total area of ​​the TSV landing pads 250, which includes the gaps between the conductive segments 250A-250E (e.g., occupied by dielectric material 240). Figure 13BIn the cross-sectional side view, this pattern density can be defined by dividing the sum of the lateral dimensions of the conductive segments 250A-250E by the total lateral dimension of the TSV landing pad 250, which again includes the gaps (e.g., gap 550, etc.) separating the conductive segments 250A-250E along the Y direction. As discussed above, this range of pattern densities is specifically configured to allow the TSV landing pad 250 to achieve the potential benefits associated with stress reduction and more flexible thermal contraction / expansion, while still being able to perform its intended function of providing electrical connection and mechanical support for the TSV 400.

[0065] It should also be noted that, as mentioned above... Figures 10-12 The TSV 400 discussed is formed on a portion rather than all of the upper surface of some conductive sections 250A and 250E, which helps to minimize the formation of bubbles or voids within the TSV 400.

[0066] Figure 14A and Figure 14B A plan view and a cross-sectional side view of a portion of an IC device 200 including a TSV 400 and a TSV landing pad 250, according to another embodiment of the present invention, are shown respectively. Similar to... Figures 13A-13B , Figure 14A The top view corresponds to the horizontal plane defined by the X direction and the Y direction perpendicular to the X direction. Figure 14B The cross-sectional side view corresponds to a vertical plane defined by the Y direction and the Z direction, which is orthogonal to the horizontal XY plane. Figure 14B The cross-sectional side view is along Figure 14A It is cut by the section line A-A' in the middle.

[0067] Similar to the above references Figures 13A-13B The embodiments discussed, Figures 14A-14B The embodiments also include TSV landing pads 250, which use M y The interconnect layer is implemented using five conductive segments 250A-250F, forming a mesh structure. However, with Figures 13A-13B The implementation methods are different. Figures 14A-14B The embodiments also include M y+1 Interconnect layer, which is located along the Z direction at M y "Below" the interconnect layer (e.g., located below M) y The interconnect layer is located further away from the substrate 210. In other words, Figures 14A-14B The embodiments are similar to those discussed above. Figure 9 In the embodiment, because M y+1The interconnect layer includes conductive pads 470, which also have a mesh structure. The conductive pads 470 include multiple conductive segments 470A-470E, which are electrically and physically connected to conductive segments 250A-250E via multiple conductive vias 480A-480E, respectively. (See above reference.) Figure 9 The conductive pad 470 discussed above can be used as an additional etch stop layer for etching the recess 370 (see above reference). Figure 5 (As discussed). In some embodiments, the conductive pad 470 may also have a pattern density in the range of about 20% to about 80%, which is configured to reduce stress and have better thermal shrinkage / expansion flexibility, while still allowing the conductive pad 470 to be used as an etch stop layer and to provide electrical connection and mechanical support for the TSV400.

[0068] Figures 15A-15F Different top views of various embodiments of the mesh structure design are shown in plan view. In some embodiments, Figures 15A-15F The mesh structure design shown corresponds to an IC design layout file, which may include a Graphical Design System (GDS) file in binary database file format. Such a GDS file can specify the geometry or pattern of microelectronic components such as gates, source / drains, dielectric components, metal lines, vias, etc. In this case, the GDS file may show the geometry or pattern of TSV 400 and TSV landing pad 250. Figures 15A-15F In the various embodiments shown, M y The metal lines of the interconnect layer are configured to form TSV landing pads 250, which are not solid in plan view, but have a mesh structure including various gaps, holes, openings, etc. Figures 15A-15F A common feature in all designs of the TSV landing pads 250 shown is that each TSV landing pad 250 includes a perimeter 600 having a rectangular shape in the plan view. The perimeter 600 may also be referred to as the outer ring because it surrounds or circumferentially surrounds the rest of the TSV landing pad 250 in the plan view and can define the boundary of the TSV landing pad 250.

[0069] One reason the perimeter 600 is implemented as a rectangular shape in the plan view is that this shape improves the routing flexibility of the TSV landing pad 250. For example, the TSV landing pad 250 may need to be electrically connected to other IC components, and the rectangular shape of the perimeter 600 allows for easier establishment of these electrical connections. For example, the rectangular shape of the perimeter 600 can avoid potential jogging problems when establishing these electrical connections. However, it should be understood that the rectangular shape of the perimeter 600 is not necessary unless otherwise required, and in other embodiments, the TSV landing pad 250 may have a non-rectangular perimeter.

[0070] Now for reference Figure 16 This illustrates a process for modifying the IC design layout according to an embodiment of the present invention. For example, Figure 16 A plan view of the original IC design layout 700 and the modified IC design layout 710 is shown. In some embodiments, the original IC design layout 700 and the modified IC design layout 710 may each be in the form of a GDS file. The original IC design layout 700 may be an IC design layout generated by (or received from) an IC design company. Figure 16 As shown, the original IC design layout 700 may include TSV 400 and TSV landing pads 750 as solid blocks, for example formed on M y A rectangular metal block in the interconnect layer. For simplicity and / or convenience, IC design companies may have generated such an IC design layout, and / or have not considered the problems of such a solid block for the TSV landing pad 750 (e.g., stress due to thermal expansion / contraction and / or wafer warping).

[0071] According to various aspects of the present invention, an IC manufacturing entity (e.g., a semiconductor foundry) can receive an original IC design layout 700 and modify it to generate a modified IC design layout 710. For example, the TSV landing pad 750 is modified from a solid metal block to the TSV landing pad 250 discussed above, which has multiple conductive segments 250A-250E (e.g., as M...). y The TSV 400 itself may not require modification. As discussed above, this mesh structure of the TSV landing pads 250 mitigates issues related to wafer warpage and / or stress. It should be understood that... Figure 16 The specific mesh structure shown is merely a non-limiting example of the modified IC design layout 710. In other embodiments, other suitable mesh structures (e.g., the one shown in Figure 15) may be implemented for the TSV landing pad 250 as part of the modified IC design layout.

[0072] Figure 17This is a flowchart of a method 800 for manufacturing an IC device according to various aspects of the present invention. Method 800 includes step 810 for forming a first interconnect structure over a first side of a substrate. The first interconnect structure includes a plurality of first interconnect layers embedded in a first dielectric structure. One of the first interconnect layers includes a landing pad having a mesh structure. In some embodiments, the mesh structure is a first mesh structure, and another of the first interconnect layers includes a second mesh structure. The second mesh structure is electrically coupled to the first mesh structure through a plurality of conductive vias in the first interconnect structure. In some embodiments, the first interconnect structure is formed such that the landing pad has a rectangular boundary in a planar top view.

[0073] Method 800 includes step 820 for forming a second interconnect structure over a second side of a substrate opposite to the first side. The second interconnect structure includes a plurality of second interconnect layers embedded in a second dielectric structure.

[0074] Method 800 includes step 830 for forming a recess extending through the second dielectric structure and the substrate, and partially through the first dielectric structure. The recess exposes at least a portion of a landing pad. In some embodiments, the recess is formed such that a first lateral dimension of the bottom of the recess is smaller than a second lateral dimension of the remainder of the recess. In some embodiments, in a cross-sectional side view, the landing pad includes a plurality of conductive segments, and the recess is formed by partially exposing the upper surface of at least a subset of the conductive segments in the cross-sectional side view.

[0075] Method 800 includes step 840 for forming a through-substrate via (TSV) by filling the recess with one or more conductive materials.

[0076] It should be understood that method 800 may include further steps performed before, during, or after steps 810-840. For example, method 800 may include steps performed after forming the first interconnect structure but before forming the second interconnect structure. Such steps may include reducing the thickness of the substrate from the second side. After reducing the substrate thickness, the second interconnect structure is formed on the second side of the substrate. As another example, method 800 may include steps performed after forming the TSV. Such steps may include forming conductive pads as the top layer in the second interconnect layer. The conductive pads are formed to physically contact the TSV from the second side. In some embodiments, the conductive pads are formed to have a mesh structure. For simplicity, other additional steps are not discussed in detail herein.

[0077] Figure 18An integrated circuit manufacturing system 900 according to an embodiment of the present invention is shown, which can be used to manufacture IC structure 200 and / or IC chip assembly 200A. The manufacturing system 900 includes multiple entities 902, 904, 906, 908, 910, 912, 914, 916, ..., N connected via a communication network 918. The network 918 can be a single network, or it can be various different networks, such as intranets and the Internet, and can include both wired and wireless communication channels.

[0078] In one embodiment, entity 902 represents a service system for manufacturing collaboration; entity 904 represents a user, such as a product engineer monitoring a product of interest; entity 906 represents an engineer, such as a processing engineer controlling processes and related formulations, or an equipment engineer monitoring or adjusting the conditions and settings of processing tools; entity 908 represents a metrology tool for IC testing and measurement; entity 910 represents a semiconductor processing tool, such as a processing tool for implementing the various deposition processes discussed above; entity 912 represents a virtual metrology module associated with processing tool 910; entity 914 represents an advanced processing control module associated with processing tool 910 and other processing tools; and entity 916 represents a sampling module associated with processing tool 910.

[0079] Each entity can interact with other entities and can provide integrated circuit manufacturing, processing control, and / or computing capabilities to other entities, and / or receive these capabilities from other entities. Each entity may also include one or more computer systems for implementing computation and performing automation. For example, the advanced processing control module of entity 914 may include multiple computer hardware components with coded software instructions. The computer hardware may include hard disk drives, flash drives, CD-ROMs, RAM memory, display devices (e.g., monitors), and input / output devices (e.g., mice and keyboards). The software instructions can be written in any suitable programming language and can be designed to perform specific tasks.

[0080] The integrated circuit manufacturing system 900 enables interaction between entities for the purposes of integrated circuit (IC) manufacturing and advanced processing control of IC manufacturing. In one embodiment, advanced processing control includes adjusting processing conditions, settings, and / or recipes of a processing tool applicable to a relevant wafer based on metrological results.

[0081] In another embodiment, metrological results are measured from a subset of the processed wafers based on an optimal sampling rate determined based on process quality and / or product quality. In yet another embodiment, metrological results are measured from selected fields and points of a subset of the processed wafers based on an optimal sampling field / point determined based on various characteristics of process quality and / or product quality.

[0082] One of the capabilities provided by the IC Manufacturing System 900 is the ability to enable collaboration and information access in areas such as design, engineering, fabrication, metrology, and advanced process control. Another capability offered by the IC Manufacturing System 900 is the integration of systems between equipment, such as metrology tools and processing tools. This integration allows equipment to coordinate its activities. For example, integrating metrology tools and processing tools allows manufacturing information to be more effectively integrated into the manufacturing process or APC module, and enables the acquisition of wafer data from online or field measurements using metrology tools integrated into the relevant processing tools.

[0083] In summary, the present invention relates to implementing TSV landing pads with a mesh structure rather than a solid block structure. For example, such a mesh structure may include multiple conductive strips (e.g., metal lines from interconnect layers of an interconnect structure) spaced apart from each other in a plan view or cross-sectional side view. By implementing such a mesh structure for the TSV landing pads, embodiments of the present invention provide advantages over conventional devices. However, it should be understood that other embodiments may provide additional advantages, and not all advantages need to be disclosed herein, and specific advantages are not required to apply to all embodiments. For example, advantages may include reduced wafer warpage and / or stress. In this regard, solid block TSV landing pads may experience excessive thermal expansion and / or contraction relative to other devices, especially as IC device dimensions continue to shrink. Excessive thermal expansion and / or contraction can lead to wafer warpage, which is undesirable. Additionally, solid block TSV landing pads may exert excessive stress on nearby components, which is also undesirable. The present invention overcomes these problems by implementing the TSV landing pads as a mesh structure rather than a solid block. This mesh structure provides space for the individual components of the TSV-mounted pads to expand or contract under different thermal conditions, which can reduce wafer warpage. Additionally, this mesh structure can reduce the amount of stress applied to nearby components, which is also beneficial. Other advantages include compatibility with existing manufacturing processes, ease of implementation, and low cost.

[0084] One aspect of the present invention relates to an IC device. The IC device includes a substrate. The IC device includes a through-substrate via (TSV) extending vertically through the substrate. The IC device includes an interconnect structure disposed above a first side of the substrate. The interconnect structure includes a plurality of interconnect layers. A first interconnect layer of the plurality of interconnect layers includes landing pads on which the TSV rests. The landing pads have a mesh structure in at least one of a cross-sectional side view or a planar top view.

[0085] In some embodiments, in a cross-sectional side view or a plan view, the first interconnect layer includes a plurality of conductive segments spaced apart from each other by a plurality of gaps. In some embodiments, in a cross-sectional side view: the first conductive segment of the plurality of conductive segments has a flat surface facing the substrate; and a through-substrate via lands on a portion, but not all, of the flat surface of the first conductive segment. In some embodiments, in a plan view, the perimeter of the landing pads includes a rectangular ring. In some embodiments, the first interconnect layer is configured to be further away from the substrate than the remaining interconnect layers. In some embodiments, the plurality of interconnect layers further include a second interconnect layer located further away from the substrate than the first interconnect layer; the second interconnect layer includes conductive pads having a mesh structure in a cross-sectional side view or a plan view; and the landing pads of the first interconnect layer and the conductive pads of the second interconnect layer are interconnected together by a plurality of conductive vias. In some embodiments, the interconnect structure is the first interconnect structure; the semiconductor device further includes a second interconnect structure disposed above a second side of the substrate opposite to the first side; and a through-substrate via extends at least partially through and is electrically coupled to the second interconnect structure. In some embodiments, the second interconnect structure includes a plurality of additional interconnect layers; and the second interconnect layer is physically bonded to one of the plurality of additional interconnect layers through a substrate via. In some embodiments, the landing pad of the first interconnect layer is a first landing pad; the second interconnect layer includes a second landing pad having a further mesh structure; and the second interconnect layer is physically connected to the second landing pad through a substrate via.

[0086] Another aspect of the invention relates to a structure. The structure includes a substrate. The structure includes a first interconnect structure disposed over a first side of the substrate. The structure includes a second interconnect structure disposed over a second side of the substrate opposite to the first side. The structure includes a through-substrate via (TSV) extending vertically through the substrate and at least partially through the first and second interconnect structures. At least one of the first or second interconnect structure includes a landing pad physically extending to the TSV. The landing pad includes a plurality of conductive segments spaced apart from each other in a planar top view and a cross-sectional side view.

[0087] In some embodiments, the landing pads have rectangular boundaries in a planar top view. In some embodiments, the first interconnect structure and the second interconnect structure each include a dielectric material; and in a cross-sectional side view, the upper surface of at least one of the conductive segments of the landing pads is in direct contact with the through-substrate via and the dielectric material.

[0088] Another aspect of the invention relates to a method. A first interconnect structure is formed over a first side of a substrate. The first interconnect structure includes a plurality of first interconnect layers embedded in a first dielectric structure. One of the first interconnect layers includes a landing pad having a mesh structure. A second interconnect structure is formed over a second side of the substrate opposite to the first side. The second interconnect structure includes a plurality of second interconnect layers embedded in a second dielectric structure. A recess is formed extending through the second dielectric structure and the substrate, and partially through the first dielectric structure. The recess exposes at least a portion of the landing pad. A through-substrate via (TSV) is formed by filling the recess with one or more conductive materials.

[0089] In some embodiments, the method further includes: reducing the thickness of the substrate from a second side after forming the first interconnect structure but before forming the second interconnect structure, wherein the second interconnect structure is formed on the second side of the substrate after the substrate thickness is reduced. In some embodiments, the method further includes: forming a conductive pad as the top layer of the second interconnect layer after forming a through-substrate via, wherein the conductive pad is formed to physically contact the through-substrate via from the second side. In some embodiments, the conductive pad is formed to have a mesh structure. In some embodiments, the mesh structure is a first mesh structure; another of the first interconnect layers includes a second mesh structure; and the second mesh structure is electrically coupled to the first mesh structure through a plurality of conductive vias of the first interconnect structure. In some embodiments, the first interconnect structure is formed such that the landing pad has a rectangular boundary in a planar top view. In some embodiments, the recess is formed such that a first lateral dimension of the bottom of the recess is smaller than a second lateral dimension of the remainder of the recess. In some embodiments, in a cross-sectional side view, the landing pad includes a plurality of conductive segments; and the recess is formed by partially exposing the upper surface of at least a subset of the conductive segments in the cross-sectional side view.

[0090] The foregoing has outlined features of several embodiments to enable those skilled in the art to better understand various aspects of this disclosure. Those skilled in the art should understand that they can readily use this disclosure as a basis for designing or modifying other processes and structures for performing the same or similar purposes and / or achieving the same or similar advantages as this disclosure. Those skilled in the art should also recognize that such equivalent structures do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and modifications can be made without departing from the spirit and scope of this disclosure.

Claims

1. An integrated circuit device, comprising: Substrate; Through-substrate via (TSV) extending vertically through the substrate; and An interconnect structure is disposed above a first side of the substrate; in: The interconnect structure includes multiple interconnect layers; The first interconnect layer of the plurality of interconnect layers includes a landing pad on which the through-substrate via rests; and The landing pads have a mesh structure in at least one of the cross-sectional side view or the planar top view.

2. The integrated circuit device according to claim 1, wherein, In the cross-sectional side view or the planar top view, the first interconnect layer includes a plurality of conductive segments separated from each other by a plurality of gaps.

3. The integrated circuit device according to claim 2, wherein, In the cross-sectional side view: The first conductive segment of the plurality of conductive segments has a flat surface facing the substrate; and The through-substrate via is located on a portion, not all, of the flat surface of the first conductive section.

4. The integrated circuit device according to claim 1, wherein, In the plan view, the perimeter of the landing pad includes a rectangular ring.

5. The integrated circuit device according to claim 1, wherein, The first interconnect layer is positioned further away from the substrate than the other interconnect layers.

6. The integrated circuit device according to claim 1, wherein: The plurality of interconnect layers further includes a second interconnect layer located further away from the substrate than the first interconnect layer; The second interconnect layer includes conductive pads having the mesh structure in the cross-sectional side view or the planar top view; and The landing pads of the first interconnect layer and the conductive pads of the second interconnect layer are interconnected together through a plurality of conductive vias.

7. The integrated circuit device according to claim 1, wherein: The interconnection structure is the first interconnection structure; The semiconductor device further includes a second interconnect structure disposed above a second side of the substrate opposite to the first side; and The through-substrate via extends at least partially through and is electrically coupled to the second interconnect structure.

8. The integrated circuit device according to claim 7, wherein: The second interconnect structure includes multiple additional interconnect layers; and The through-substrate via is physically bonded to a second interconnect layer among the additional plurality of interconnect layers.

9. Types of integrated circuit structures, including: Substrate; A first interconnect structure is disposed above a first side of the substrate; A second interconnect structure is disposed above a second side of the substrate opposite to the first side; and Through-substrate vias (TSVs) extend vertically through the substrate and at least partially through the first interconnect structure and the second interconnect structure; in: At least one of the first interconnect structure or the second interconnect structure includes a landing pad that physically extends to the through-substrate via; and The landing pads comprise multiple conductive segments spaced apart from each other in a plan view and a cross-sectional side view.

10. A method for manufacturing an integrated circuit, comprising: A first interconnect structure is formed above a first side of a substrate, wherein the first interconnect structure includes a plurality of first interconnect layers embedded in a first dielectric structure, and wherein one of the first interconnect layers includes a landing pad having a mesh structure. A second interconnect structure is formed over a second side of the substrate opposite to the first side, wherein the second interconnect structure includes a plurality of second interconnect layers embedded in a second dielectric structure; A recess is formed extending through the second dielectric structure and the substrate, and partially through the first dielectric structure, wherein the recess exposes at least a portion of the landing pad; and Through-substrate vias (TSVs) are formed by filling the recesses with one or more conductive materials.

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