Lead frame assembly of semiconductor device
By using an improved lead frame assembly with a design that integrates continuous lead portions with the wafer connection portion, the problem of increased connection resistance in semiconductor devices is solved, resulting in reduced resistance and improved current handling capability.
Patent Information
- Application Number
- CN202511765381.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Priority Date
- 2019-07-03
- Filing Date
- 2020-07-03
- Publication Date
- 2026-02-24
AI Technical Summary
The existing lead frame arrangement of semiconductor devices leads to an increase in the connection resistance between the semiconductor wafer and the external leads, especially in clip-on packages, resulting in increased device resistance, such as increased drain-source on-resistance in MOSFET semiconductor devices.
An improved lead frame assembly is employed, comprising a continuous lead portion and a clamp-type frame structure. The continuous lead portion is integrally formed with the wafer interconnect portion and is designed to extend across the width of the wafer interconnect portion. It also contacts the carrier through a bend, maximizing the operating current and minimizing the spread resistance.
This reduces the operating resistance of semiconductor devices, such as Rdson, without significantly increasing inductance, thereby improving current handling capability and the reliability of electrical connections.
Smart Images
Figure CN121568581A_ABST
Abstract
Description
[0001] This application is a divisional application of patent application No. 2020106308331, filed on July 3, 2020, entitled "Leader Frame Assembly for Semiconductor Device". Technical Field
[0002] This disclosure relates to lead frame assemblies for semiconductor devices. Specifically, this disclosure relates to clip frame structures for semiconductor devices, semiconductor devices including the clip frame structure, and related methods of manufacturing the semiconductor device. Background Technology
[0003] In semiconductor devices, clip-bonded packages are commonly used as leadframe arrangements to enable connections from the semiconductor wafer to external contacts of the device. Compared to traditional wirebonded packages, clip-bonded packages offer several advantages. For example, in automotive applications, clip-bonded packages are often used for mechanically robust and reliable electrical connections to semiconductor wafers. Furthermore, conductive clip-bonded materials can have increased thermal mass compared to wirebonded materials, thus serving as heat sinks for semiconductor wafers.
[0004] Existing known lead frame arrangements for semiconductor devices (e.g., Figure 1a and 1b The type shown leads to an increase in the connection resistance between the semiconductor wafer and the external leads. For example... Figure 1a and Figure 1b As shown, the semiconductor device 100 includes a semiconductor wafer 104 mounted on wafer pads 106. A clamping member 102 electrically connects contact terminals on the top surface of the semiconductor wafer 104 to external leads 108. Figure 1b As shown, a solder joint 110 is used to electrically connect and mechanically bond the clip-on component to the external lead 108. This solder joint 110 results in increased connection resistance, which can lead to increased device resistance. For example, in a MOSFET semiconductor device where the clip-on component is the source connection, this increased resistance can result in increased drain-source on-resistance R. dson Increase. Summary of the Invention
[0005] Various example embodiments address problems such as those described above, which become apparent from the following disclosure regarding improvements to the lead frame arrangement of semiconductor devices.
[0006] In some exemplary embodiments, aspects of this disclosure relate to semiconductor devices including improved lead frame arrangements and methods of manufacturing such semiconductor devices.
[0007] According to an embodiment, a lead frame assembly for a semiconductor device is provided, the lead frame assembly including: a wafer attachment structure and a clamping frame structure, the clamping frame structure including: a wafer connection portion configured to contact a contact terminal on the top side of a semiconductor wafer; and a continuous lead portion extending along the wafer connection portion; wherein the continuous lead portion is integrally formed with the wafer connection portion.
[0008] A continuous lead portion can be a merged lead portion that substantially extends across the width of the wafer interconnect portion. The continuous lead portion can be configured and arranged to maximize the operating current of the clamp-on frame structure and minimize the extended resistance of the clamp-on frame structure. The continuous lead portion may include one or more bends configured and arranged to allow the lead portion to contact the carrier. The continuous lead portion may also include multiple lead ends.
[0009] A semiconductor device is also provided, which includes a lead frame assembly according to an embodiment.
[0010] According to an embodiment, a method for manufacturing a semiconductor device is also provided, the method comprising: providing a lead frame assembly; mounting a semiconductor wafer on a wafer attachment structure of the lead frame assembly; providing a clamping frame structure including: a wafer connection portion configured to contact a contact terminal on a top side of the semiconductor wafer; and a continuous lead portion extending along the wafer connection portion; wherein the continuous lead portion is integrally formed with the wafer connection portion.
[0011] The continuous lead portion can be a merged lead portion and can be formed as a width extension substantially across the wafer interconnect portion. The continuous lead portion can be constructed and arranged to maximize the operating current of the clamp frame structure and minimize the extended resistance of the clamp frame structure. Attached Figure Description
[0012] To provide a detailed understanding of the features of this disclosure, reference has been made to embodiments, some of which are illustrated in the accompanying drawings. However, it should be noted that the drawings illustrate only typical embodiments and should not be construed as limiting the scope of this disclosure. The drawings are intended to facilitate understanding of this disclosure and are not necessarily drawn to scale. The advantages of the claimed subject matter will become apparent to those skilled in the art upon reading this specification in conjunction with the accompanying drawings, in which the same reference numerals are used to denote the same elements, and in the drawings:
[0013] Figure 1a A perspective view of a known lead frame arrangement is shown;
[0014] Figure 1bA side view of a known lead frame arrangement is shown;
[0015] Figure 2a A perspective view of the lead frame arrangement according to an embodiment is shown;
[0016] Figure 2b A side view of the lead frame arrangement according to an embodiment is shown;
[0017] Figure 3 A perspective view of the lead frame arrangement according to an embodiment is shown;
[0018] Figure 4 A perspective view of a clip arrangement according to an embodiment is shown.
[0019] Figure 5 A perspective view of a semiconductor device according to an embodiment is shown;
[0020] Figure 6 A top view of a semiconductor device according to an embodiment is shown; and
[0021] Figures 7a to 7h The process steps for manufacturing a semiconductor device according to an embodiment are shown. Detailed Implementation
[0022] In general, Figure 2a and Figure 2b A semiconductor device 200, prior to molding and including a leadframe assembly 202, is shown according to an embodiment. The semiconductor device 200 typically includes a wafer attachment structure 204 and a clamping frame structure 206 forming the leadframe assembly 202, and a semiconductor wafer 208 attached to both the wafer attachment structure 204 and the clamping frame structure 206.
[0023] A wafer attachment structure 204 is typically arranged to mount a semiconductor wafer 208 thereon and to provide support for a clamping frame structure 206. Additionally, the wafer attachment structure 204 can provide contact with the back or bottom of the semiconductor wafer 208, depending on the arrangement of the contact terminals (e.g., source, gate, or drain) of the semiconductor wafer 208. The wafer attachment structure 204 is typically formed of a metallic conductive material such as copper. In this way, the wafer attachment structure 204 can provide bottom external leads 203, such as drain contacts or tabs, for the contact terminals arranged on the back or bottom of the semiconductor wafer 208. The bottom external leads 203 can extend outside the molding package material of the semiconductor device 200 to form heat sink tabs to the bottom of the semiconductor wafer 208, for example... Figure 5 As shown.
[0024] Semiconductor wafer 208 is fixedly disposed on wafer attachment structure 204, and clamp frame structure 206 is fixedly connected to semiconductor wafer 208 and wafer attachment structure 204. Figure 2a and Figure 2b In one embodiment, the clip-on frame structure 206 is formed of two different but integrally formed portions (i.e., the wafer connection portion 210 and the lead portion 212). The wafer connection portion 210 may be generally rectangular in shape, and / or the dimensions of the wafer connection portion 210 may be set such that they substantially correspond to the dimensions of the contact terminals on the top side of the semiconductor wafer 208 to which the wafer connection portion 210 is attached.
[0025] As described above, the bottom or back contact terminals of the semiconductor wafer 208 can be securely attached to the wafer attachment structure 204. The semiconductor wafer 208 can be securely attached to and electrically connected to the wafer attachment structure 204 via the bottom contact terminals (not shown) using any suitable bonding material such as solder or conductive adhesive. The wafer connection portion of the clip-on frame structure 206 is securely attached to the contact terminals arranged on the top side of the semiconductor wafer 208 using a suitable bonding material such as solder or conductive adhesive.
[0026] Lead portion 212 is a continuous and merged portion extending from die connection portion 210. Lead portion 212 is continuous to form a substantially elongated member extending away from die connection portion 210 and along the width of die connection portion 210. In this way, lead portion 212 has a continuous width W and can be viewed as a merged member, i.e., the lead portion 212 has no branching or multiple finger-like lead members, and the merged member extends substantially along the width of die connection portion 210. Lead portion 212 is arranged as a "gull wing" lead, having one or more angles or bends to allow the lead portion to contact the PCB. The continuous and merged lead portion 212 can be arranged as a plate-like member with appropriate gull wing bends formed therein.
[0027] The dimensions of the lead portion 212 can be configured to align with or correspond to the coverage area of a contact on a PCB (not shown). By maximizing the width W of the lead portion 212, and thus its volume (assuming the length and thickness of the lead portion 212 are constant), the current handling capability of the clamp frame structure 206 and the semiconductor device 200 in terms of the maximum permissible operating current (e.g., drain-source current) can be maximized. Similarly, the arrangement discussed above will minimize the spread resistance of the clamp frame structure 206, thereby reducing the on-resistance of the semiconductor device 200.
[0028] By arranging the lead portions in this manner, the package resistance of the lead frame assembly 202 can be reduced, thereby reducing the operating resistance of the semiconductor device 200, for example, R. dson However, the above arrangement does not significantly increase the inductance of the lead frame assembly 202. For example, according to an embodiment, the resistance of the clip-on frame structure can be 0.34717 mΩ and the inductance can be 1.9718 nH. For a known arrangement, the resistance of the clip-on frame structure can be 0.49792 mΩ and the inductance can be 1.9898 nH.
[0029] Then, using molding material 216 (e.g., as shown in the image) Figure 5 (As shown) packaged semiconductor wafer 208 and clamp frame structure 206. Lead portion 212 and bottom external lead 203 protrude through molding compound 216 to allow lead portion 212 and bottom external lead 203 to contact an external carrier such as a PCB.
[0030] The clip-on frame structure 206 is typically formed from a single monolithic metal sheet (e.g., copper) that is formed or stamped to produce the desired structure. In this way, the wafer connection portion 210 and the lead portion 212 of the clip-on frame structure 206 can have equal thicknesses. The choice of metal is entirely up to those skilled in the art and can be selected based on the electrical characteristics required for the lead frame assembly of the semiconductor device 200.
[0031] Figure 3 and Figure 4 Another embodiment of the lead frame assembly 202 is shown. (This is related to the above regarding...) Figure 2a and Figure 2b The arrangement is consistent with the above. Figure 3 and Figure 4 The arrangement typically includes a wafer attachment structure 204 and a clamp frame structure 206 forming a lead frame assembly 202, and a semiconductor wafer 208 attached to both the wafer attachment structure 204 and the clamp frame structure 206.
[0032] Figure 3 and Figure 4 The arrangement also includes a plurality of optional slots or holes 220 formed through the wafer connection portion 210 and the bottom external lead 203. The slots or holes 220 serve as anchoring or locking points for the molding compound 216 and allow for improved adhesion or attachment of the molding compound 216 to the lead frame assembly 202. Improved adhesion of the molding compound can reduce stress and package cracking during the lead forming process (i.e., cutting and bending the wafer connection portion 210 and / or the bottom external lead 203 after molding).
[0033] Additionally, an optional slot or hole 221 formed through the wafer connection portion 210 extends transversely to or longitudinally across the wafer connection portion 210. This allows for both stress relief and solder protection.
[0034] In terms of stress relief, the holes or trenches 221 formed in the wafer interconnect portion 210 reduce the surface-dispersed stress across the wafer interconnect portion 210, since the wafer interconnect portion 210 is attached to terminals disposed on the top surface of the semiconductor wafer. In other words, the holes or trenches 221 distort the stress caused by the wafer interconnect portion 210, preventing stress from propagating across the wafer interconnect portion 210. Regarding solder protection, the holes or trenches 221 allow gases to escape from beneath the wafer interconnect portion 210 during solder reflow.
[0035] Optional slots or holes 212 can also be incorporated into the lead portion 212 to prevent the lead from springing back due to the elastic recovery of the metal after lead formation. This also makes the lead more flexible during board-level temperature cycling, which can prevent the solder joints between the lead and the PCB from breaking or cracking.
[0036] Figure 3 , Figure 4 and Figure 5 The arrangement also shows one or more optional lead ends 224 disposed at one end of the lead portion 212 away from the die connection portion 210. The lead ends 224 and the lead portion 212 may include one or more bends 230 between the die connection portion 210 and the end of the lead end 224, such that the lead is formed as a so-called "gull-wing" lead. The lead ends 224 can be arranged according to any standard lead geometry required for the coverage area of the contacts on the PCB. For example, the lead geometry may be a Small Outline Integrated Circuit (SOIC) (e.g., SO8, SO14, SO16) or any other suitable package shape.
[0037] According to an embodiment, the clip-on frame structure 206 can form a source connection to the source terminal on the top side of the semiconductor wafer 208. Lead 218 can form a gate connection to the gate terminal also formed on the top side of the semiconductor wafer 208. Bottom external lead 203 can form a drain connection to the drain terminal formed on the back side of the semiconductor wafer 106. In this respect, the semiconductor wafer 106 can be a field-effect transistor.
[0038] Similarly, the semiconductor wafer 208 can be a bipolar junction transistor. The clip-on frame structure 206 can form a collector connection to the collector terminal on the top side of the semiconductor wafer 208. The lead 218 can form a base connection to the base terminal also formed on the top side of the semiconductor wafer 208. The bottom external lead 203 can form a emitter connection to the emitter terminal formed on the back side of the semiconductor wafer 208.
[0039] Figure 6 A slot or hole 220 is shown arranged in the bottom outer lead 203 for securing the molding compound 216 to the bottom outer lead 203, thereby allowing improved bonding or attachment of the molding compound 216 to the bottom outer lead 203.
[0040] Figures 7a to 7h The process flow steps for manufacturing a semiconductor device according to an embodiment are shown.
[0041] like Figure 7a As shown, a wafer attachment structure 204 is provided having a bottom external lead 203 extending therefrom. The wafer attachment structure 204 and the bottom external lead 203 can be formed of any suitable conductive material such as copper. Figure 7a The arrangement shows a single chip attachment structure 204; however, those skilled in the art will understand that multiple chip attachment structures can be arranged in a strip or matrix manner.
[0042] In the next step, such as Figure 7b As shown, wafer attachment material 215 is dispensed onto wafer attachment structure 204. Wafer attachment material 215 is arranged to securely mount semiconductor wafer 208 to wafer attachment material 215, such as... Figure 7c As shown. The wafer attachment material 215 can be any suitable adhesive material, such as solder or conductive adhesive.
[0043] After placing the semiconductor chip 208, as Figure 7d As shown, contact terminal attachment material is applied to the top-side contacts of the semiconductor wafer 208 for electrical and mechanical connection between the clamp frame structure 206 and the semiconductor wafer 208, such as... Figure 7d As shown. Wafer attachment material can be applied by any suitable process, such as adhesive or solder printing or dispensing.
[0044] Once the semiconductor wafer 208 is placed on the wafer attachment structure 204, contact terminal attachment material 214 is arranged on one or more top contacts of the semiconductor wafer 208. Then, a clip-on frame structure 206 can be arranged on the contact terminals, such as... Figure 7e As shown. Although Figure 7eThe arrangement shown depicts a single clip-on frame structure 206 disposed on a semiconductor wafer 208; however, those skilled in the art will understand that multiple such clip-on frame structures can be arranged as stripes or matrices corresponding to multiple wafer attachment structures, each wafer attachment structure having a semiconductor wafer disposed thereon. After attaching the clip-on frame structure 206, the assembly undergoes solder reflow to solidify the wafer attachment material and contact terminal attachment material. After reflow, the assembly can be encapsulated in a mold material 216, such as... Figure 7f As shown.
[0045] like Figure 7g As shown, the lead end 224 is formed by trimming the lead portion 212 and bending the lead to form a gull-wing arrangement. Figure 7h In this process, the bottom outer lead 203 is trimmed to complete the process.
[0046] Specific and preferred aspects of the invention are set forth in the appended independent claims. Combinations of features from the dependent and / or independent claims may be appropriately combined, and not limited to those described in the claims.
[0047] The scope of this disclosure includes any novel feature or combination of features explicitly or implicitly disclosed herein, or any generalization thereof, whether or not it relates to the claimed invention or alleviates any or all the problems solved by the invention. The applicant hereby declares that new claims may be made for these features in the course of implementing this application or any such further application derived therefrom. In particular, with reference to the appended claims, features of dependent claims may be combined with features of independent claims, and features of individual independent claims may be combined in any suitable manner rather than solely in the specific combinations listed in the claims.
[0048] Features described in the context of a single embodiment may also be provided in combination in a single embodiment. Conversely, for the sake of brevity, the various features described in the context of a single embodiment may also be provided individually or in any suitable sub-combination.
[0049] The term "comprising" does not exclude other elements or steps, and the terms "a" or "an" do not exclude multiple. Reference numerals in the claims should not be construed as limiting the scope of the claims.
Claims
1. A lead frame assembly for a semiconductor device, the lead frame assembly comprising: A wafer attachment structure (204) and a clamping frame structure (206), the clamping frame structure comprising: The wafer connection portion (210) is configured to contact the top side of a contact terminal or a semiconductor wafer (208); and A continuous lead portion (212) extends along the wafer connection portion (210); The continuous lead portion (212) is integrally formed with the wafer connection portion (210); The continuous lead portion (212) is a merged lead portion that extends substantially across the width of the wafer connection portion (210). The wafer connection portion (210) includes one or more second holes (221), which extend longitudinally across or through the wafer connection portion (210). The continuous lead portion (212) is characterized in that it includes one or more first holes or slots (220) arranged to serve as anchor points or locking points for the molding compound, and wherein the continuous lead portion (212) includes one or more third holes or slots (222) arranged to prevent the continuous lead portion (212) from springing back.
2. The lead frame assembly according to claim 1, wherein, The continuous lead portion includes one or more bends located within the continuous lead portion and configured and arranged to allow the lead portion to contact the carrier.
3. The lead frame assembly according to claims 1 to 2, wherein, The continuous lead portion also includes multiple lead ends.
4. A semiconductor device comprising the lead frame assembly of claims 1 to 3, having a semiconductor chip device mounted on the wafer attachment structure.
5. A method for manufacturing a semiconductor device, the method comprising: Provide lead frame components; The semiconductor wafer (208) is mounted on the wafer attachment structure (204) of the lead frame assembly; A clamp-type frame structure is provided, the clamp-type frame structure comprising: The wafer connection portion (210) is configured to contact a contact terminal on the top side of the semiconductor wafer (208); and A continuous lead portion (212) extends along the wafer connection portion; wherein the continuous lead portion (212) is integrally formed with the wafer connection portion (210); The continuous lead portion (212) is a merged lead portion and is formed to extend substantially across the width of the wafer connection portion (210). Further, one or more first holes or slots (220) are provided within the continuous lead portion (212), the one or more first holes or slots (220) being arranged to serve as anchor points or locking points for the molding compound; A second hole or a plurality of second holes (221) is further provided in the wafer connection portion (210), the second hole or the plurality of second holes (221) extending longitudinally through the wafer connection portion (210) or across the wafer connection portion (210); One or more third holes or third slots (222) are further provided within the continuous lead portion (212), the one or more third holes or third slots (222) being arranged to prevent the continuous lead portion (212) from bouncing back.
6. The method of claim 5, wherein one or more bends are formed in the continuous lead portion to allow the lead portion to contact the carrier.