Adaptive local conditioning management based on processing circuitry for state detection in integrated circuit (IC) chips

Abstract

An adjustment management circuit is configured to receive an adjustment request from at least one state detection circuit, generate and store adjustment suggestions in each clock cycle based on the received adjustment request, and generate an adjustment control signal to adjust activity of a processing circuit based on recent and stored adjustment suggestions. The adjustment request may be based on measurements of electrical, thermal, and / or active states in the processing circuit monitored by the LAM circuit, and the measured states may be caused by activity of the processing circuit. The regulation management circuitry may provide a local, dynamic, low latency response to mitigate damage that may be caused by the measured local state of the processing circuitry while waiting for a response from the power management hierarchy. In some examples, the adjustment suggestions generated in each cycle may affect the adjustment control signal for multiple subsequent cycles.

Description

Priority application

[0001] This application claims priority to U.S. Patent Application Serial No. 18 / 339,461, filed June 22, 2023, entitled “Adaptive Local Throttle Management of Processing Circuits Based on Determinated States in an Integrated Circuit (IC) Chip,” the entire contents of which are incorporated herein by reference.

[0002] This application also claims priority to U.S. Patent Application Serial No. 18 / 623,192, filed April 1, 2024, entitled “Adaptive Local Throttle Management of Processing Circuits Based on Detected States in an Integrated Circuit (IC) Chip” (a continuation of U.S. Patent Application Serial No. 18 / 339,461), the entire contents of which are incorporated herein by reference. background I. Technical Field This disclosure relates to processor-based systems (e.g., central processing unit (CPU)-based systems, graphics processing unit (GPU)-based systems, or neural network processing unit (NPU)-based systems), and more specifically, to power distribution management of circuits in processor-based systems.

[0003] II. Background Technology Microprocessors, also known as processing units (PUs), perform computational tasks in a wide variety of applications. One type of conventional microprocessor or PU is the Central Processing Unit (CPU). Another type of microprocessor or PU is a dedicated processing unit called a Graphics Processing Unit (GPU). GPUs are designed with dedicated hardware to accelerate the rendering of graphics and video data to be displayed. GPUs can be implemented as integrated components of a general-purpose CPU or as discrete hardware components separate from the CPU. Other examples of PUs can include neural network processing units or neural processing units (NPUs). A CPU is configured to execute software instructions that cause the processor to fetch data from locations in memory and use the fetched data to perform one or more processor operations.

[0004] A Processing Unit (PU) is included in a computer system that includes other supporting processing devices (circuitets) accessed as part of performing computational operations within the computer system. Examples of these other supporting processing devices include memory, input / output (I / O) devices, secondary memory, modems, video processors, and associated interface circuitry. The PU and supporting processing devices in a computer system are collectively referred to as processing devices. Processing devices in a processor-based system may be provided in separate ICs on separate IC chips or may be aggregated in a larger IC (such as a System-on-Chip (SoC) IC), where some or all of these processing devices are integrated into the same IC chip. For example, an SoC IC chip may include a PU comprising multiple processor cores and supporting processing devices such as a memory system including cache memory and a memory controller for controlling access to external memory, I / O interfaces, a power management system, etc. SoCs may be particularly advantageous for applications where the available area of ​​a computer system (e.g., a mobile computing device such as a cellular device) is limited. To manage the power allocated to the processing devices, the SoC may also include a power management system comprising one or more power rails within the SoC that supply power to its components. Detached power management integrated circuits (PMICs), which can be located off-chip or on-chip within a System-on-a-Chip (SoC), can independently control the power supplied to power rails. An SoC can be designed to have multiple distinct power rails distributed throughout the SoC to provide power to various clusters of processing devices for their operation. For example, depending on the SoC design, all processor cores within the SoC may be coupled to a common power rail for power supply, while supporting processing devices may be powered by separate power rails within the SoC. Summary of the Invention

[0005] The aspects disclosed herein include adaptive local activity regulation based on the measurement states of processing circuitry within an integrated circuit (IC) chip. Related methods for regulating local activity within the IC chip are also disclosed. The IC chip includes a processor and integrated supporting processing devices for the processor (e.g., network nodes, memory controllers, internal memory, input / output (I / O) interface circuitry, etc.). For example, the processor may be a central processing unit (CPU), a graphics processing unit (GPU), or a neural network processing unit (NPU), wherein the processor includes multiple processing units (PUs) and / or processor cores. The processor-based system can be provided as a system-on-a-chip (SoC) including the processor and the integrated supporting processing devices for the PUs. As an example, the SoC can be employed in smaller mobile devices (e.g., cellular phones, laptops) and enterprise systems such as server chips in computer servers. The IC chip may also include a hierarchical power management system configured to control the power consumption of the processor-based system at both local and centralized levels to achieve desired performance within the IC chip's total power budget. The hierarchical power management system can be configured to control power consumption by controlling the power levels (e.g., by controlling voltage levels) at one or more power rails in the IC chip that provide power to the PU and the integrated supporting processing device. For example, the hierarchical power management system can be configured to provide additional power to certain power rails supplying power to devices with higher current demands to achieve higher performance, while providing less power to other power rails to keep the overall power within the power and / or thermal limits of the IC chip. The hierarchical power management system can also be configured to control power consumption by adjusting the performance (e.g., frequency) of the processing device in the processor-based system, thereby regulating (i.e., reducing, maintaining, or increasing) its current demand and thus regulating its power consumption. Note that, as used herein, regulation can mean taking action that reduces or increases a parameter that affects power and thus results in a corresponding decrease or increase in power consumption.

[0006] This hierarchical power management system is configured to regulate the performance of the processing device in the processor-based system because the level of processing activity in the processing device within the SoC can vary based on workload conditions. Some power rails in the SoC may experience increased current demands. It is desirable that this current demand does not exceed the maximum current limit of its respective power rail. Even if the higher current demand on a power rail is within its maximum current limit, the increased activity of the processing device in the SoC can still produce a sharp increase in current demand from its power rail, known as a "di / dt" event. This di / dt event can cause voltage decay in that power rail, thus adversely affecting the performance of the processing device powered by such a power rail. Furthermore, even if the higher current demand on a power rail is within its maximum current limit, the higher current demand can still increase the overall power consumption of the SoC. The processing device can have a maximum rated power to operate appropriately and / or not affect performance in an undesirable manner. The higher current demand from the processing device can also generate excessive heat. Therefore, the maximum rated power of the SoC can be based in part on the SoC's ability to dissipate the heat generated by the processing device during its operation.

[0007] In an exemplary aspect, the hierarchical power management system may include local area management (LAM) circuitry distributed throughout the IC chip, each LAM circuitry associated with one or more processing devices within the IC chip. The LAM circuitry may be configured to generate power events associated with monitored processing devices (also referred to as “monitored processing circuitry”) within the IC chip, representing power consumption associated with the monitored processing device. These power events may be reported from a local area within the IC chip performing a power assessment of a specific monitored processing device to centralized power assessment and limiting (PEL) circuitry within the hierarchical power management system. The PEL circuitry may be configured to assess and control (i.e., regulate) the power in the processor-based system within the IC chip to achieve desired performance within the overall power budget of the IC chip. The PEL circuitry may determine how to regulate the power based on the received power events. For example, the power event may be associated with a power consumption assessment, and if the assessed power consumption exceeds the power limits of the IC chip or adversely affects performance, the power event may be considered a power regulation recommendation for regulating the power in the IC chip.

[0008] The activity of the processing device in an IC chip can affect its steady-state current demand (i) and current transients (di / dt), and thus its power consumption. Because the die area of ​​an IC chip can be larger due to the integration of the power supply unit (PU) with the integrated supporting processing device, there can be a significant delay between the PEL circuit receiving a power event regarding the power consumption of the monitored processing device and the PEL circuit responding by adjusting the power in the IC chip to regulate power consumption. For example, this delay can cause the device in the IC chip to temporarily continue consuming excessive power before the power management circuitry has time to react, leading to thermal and / or power problems (e.g., di / dt issues, voltage decay, overheating) or permanent damage.

[0009] In this regard, additionally or alternatively, the processor-based system includes regulation management circuitry configured to receive regulation requests from one or more state detection circuits, generate and store regulation recommendations in each clock cycle based on the received regulation requests, and generate regulation control signals based on the most recent and stored regulation recommendations to regulate the activity of the processing circuitry. The regulation request may be based on measurements of electrical, thermal, and / or activity states in the processing circuitry monitored by LAM circuitry, and these measured states may be caused by the activity of the processing circuitry. The regulation management circuitry can provide a local, dynamic, low-latency response to mitigate potential damage from measured local states of the processing circuitry, for example, while waiting for a response from the power management layer. In some examples, the regulation recommendations generated in each cycle may influence the regulation control signals in multiple subsequent cycles. In other examples, the generated regulation recommendations may replace stored regulation recommendations.

[0010] In this regard, in one exemplary aspect, an integrated circuit (IC) chip including a processor-based system is disclosed. The processor-based system includes processing circuitry operating in response to a clock signal and at least one state detection circuitry configured to generate at least one adjustment request based on one or more measurements of at least one state of the processing circuitry. The processor-based system further includes adjustment management circuitry including an adjustment request merging circuitry configured to receive the at least one adjustment request from the at least one state detection circuitry and generate an adjustment proposal based on the at least one adjustment request in each cycle of the clock signal. The adjustment management circuitry further includes a plurality of adjustment proposal registers, each configured to sequentially: receive the adjustment proposal generated in the adjustment request merging circuitry in a first cycle of the clock signal and store the received adjustment proposal in a first plurality of consecutive cycles of the clock signal after the first cycle. The processor-based system further includes a regulation suggestion aggregation circuit and a regulation control circuit. The regulation suggestion aggregation circuit is configured to generate a regulation result based on the regulation suggestion stored in the plurality of regulation suggestion registers. The regulation control circuit is configured to receive the regulation result and generate a regulation control signal in each cycle of the clock signal to selectively regulate the activity of the processing circuit.

[0011] In another exemplary aspect, a method for regulating the activity of processing circuitry in a processor-based system is disclosed. The method includes operating the processing circuitry in response to a clock signal, generating at least one regulation request in at least one state detection circuitry based on one or more measurements of at least one state of the processing circuitry, and generating regulation recommendations based on the at least one regulation request in each cycle of the clock signal during the first plurality of consecutive cycles of the clock signal. The method includes storing the regulation recommendations generated in the first plurality of consecutive cycles of the clock signal in a plurality of regulation recommendation registers, generating a regulation result based on the regulation recommendations stored in the plurality of regulation recommendation registers, and generating a regulation control signal in each cycle of the clock signal to regulate the activity of the processing circuitry based on the regulation control signal. Attached Figure Description

[0012] Figure 1 This is a schematic diagram of an exemplary processor-based system in the form of an exemplary system-on-a-chip (SoC) in an integrated circuit (IC) chip.

[0013] Figure 2 yes Figure 1 The example logic diagram of a processor-based system illustrates processing circuitry and other supporting devices communicatively coupled to an internal communication network, as well as an optional hierarchical power management system configured to perform power assessment and power consumption regulation.

[0014] Figure 3 This is a top view of an exemplary physical layout of a semiconductor die (“die”), which is Figure 1 The SoC in the processor-based system-on-a-chip (SoC) exemplifies the physical layout of different brick regions and the devices physically existing in such different brick regions, and is coded with flags indicating which separate power rails from which devices are powered by power from a hierarchical power management system.

[0015] Figure 4 This is an example of... Figure 1 An example of a power rail driven by a corresponding power management IC (PMIC) in a processor-based system is assigned to a device in the processor-based system to supply power to such a device.

[0016] Figure 5 yes Figure 1 Another top view of a processor-based system in an IC chip illustrates a Local Area Management (LAM) circuit, a Regional Activity Management (RAM) circuit, and a Power Assessment and Limitation (PEL) circuit as part of a hierarchical power management system. The hierarchical power management system is configured to locally monitor the activity of devices in the processor-based system to assess and regulate their power consumption and report active power events related to the assessed power consumption to the PEL circuit. The PEL circuit is configured to collect active power events related to the power consumption of the monitored processing devices and adjust the power in the IC chip accordingly.

[0017] Figure 6 It is possible Figure 1 A schematic diagram of an exemplary three (3) level hierarchical power management system provided in a processor-based system in an IC chip, wherein the three (3) level hierarchical power management system may include: a first local level LAM circuit configured to perform local device monitoring and power consumption regulation and report active power events regarding the power consumption of the monitored processing device; a second intermediate level RAM circuit configured to receive and aggregate local active power events; and a third centralized level PEL circuit configured to collect aggregated active power events regarding the power consumption of the monitored processing device and adjust the power in the IC chip accordingly.

[0018] Figure 7 It is possible Figure 1A schematic diagram of an exemplary two (2) level hierarchical power management system provided in a processor-based system in an IC chip, wherein the two (2) level hierarchical power management system may include: a first local level LAM circuit configured to perform local device monitoring and power consumption regulation; and a second centralized level PEL circuit configured to collect aggregated active power events regarding the power consumption of the monitored processing device and adjust the power in the IC chip accordingly.

[0019] Figure 8 This is an example Figure 6 The flowchart illustrates an exemplary procedure for a hierarchical power management system for a processor-based system, which locally monitors and adjusts the power consumption of the monitored processing device and reports active power events related to the monitored power consumption to a PEL circuit in a hierarchical manner. The PEL circuit is configured to adjust the power consumption in the processor-based system in response to the received power events.

[0020] Figure 9A This is an example that can be provided in Figure 6 A schematic diagram of an exemplary di / dt circuit in the LAM circuit of a hierarchical power management system, wherein the di / dt circuit is configured to collect activity samples of the devices monitored by the LAM circuit and correlate the activity samples to evaluate the current and generate an evaluated current sample in a specified time window, which can then be used to determine the slope of the rate of change (di / dt) of the current consumed by the monitored processing device to determine whether the power consumption of the monitored processing device should be regulated by the LAM circuit.

[0021] Figure 9B This is an example of... Figure 9A The graph of an exemplary current sample collected by the di / dt circuit in the image is plotted as it changes over time to determine the rate of change (di / dt) of current consumed by the monitored processing device.

[0022] Figure 10 This is a logic diagram of an exemplary PEL circuit that can be provided in a hierarchical power management system for a processor-based system, and exemplifies exemplary components for: receiving power events, decoding the received power events in a tracking circuit, and merging the tracked power events to generate a power limiting management response to regulate power consumption in the processor-based system in response to the received power events.

[0023] Figure 11 This is a logic diagram of an exemplary regulation management circuit in a processor-based system, illustrating exemplary components for receiving regulation requests based on the measured state of the processing circuit and generating regulation control signals to regulate processing activities in the processing circuit to dynamically respond to the detected state of the processor-based system.

[0024] Figure 12 This is a logic diagram of an exemplary state detection circuit used to generate an adjustment request in each cycle of a clock signal to dynamically respond to state changes caused by activity in the processing circuit.

[0025] Figures 13A to 13C This is an example used in Figure 11 The logic diagram of the data movement in the three-cycle sequence in the regulation suggestion register that generates the regulation control signal in the regulation suggestion aggregation circuit.

[0026] Figure 14 This is a flowchart illustrating an exemplary program for receiving adjustment requests and generating adjustment control signals based on the measurement state of the processing circuitry to adjust processing activities in the processing circuitry, thereby dynamically responding to the detection state of the processor-based system, including but not limited to... Figure 11 and Figures 13A to 13C The regulation and management circuit in it.

[0027] Figure 15 This is a block diagram of another exemplary processor-based system, which includes a regulation management circuit configured to receive regulation requests based on measurement states of the processing circuitry and to generate regulation control signals to regulate processing activities in the processing circuitry, thereby dynamically responding to the detection states of the processor-based system, including but not limited to... Figure 11 and Figures 13A to 13C The regulation and management circuit in it.

[0028] Figure 16 This is a block diagram of an exemplary wireless communication device including a radio frequency (RF) component. The RF component may include conditioning management circuitry configured to receive conditioning requests based on measurement states of processing circuitry and to generate conditioning control signals to regulate processing activities in the processing circuitry, thereby dynamically responding to the detection states of a processor-based system, including but not limited to... Figure 11 and Figures 13A to 13C The regulation and management circuit in it. Detailed Implementation

[0029] Several exemplary aspects of this disclosure will now be described with reference to the accompanying drawings. The word “exemplary” is used herein to mean “serving as an example, instance, or illustration.” Any aspect described herein as “exemplary” is not necessarily to be construed as preferred or advantageous over other aspects.

[0030] The aspects disclosed herein may include, as appropriate, hierarchical power assessment and regulation in processor-based systems within integrated circuit (IC) chips. Related power management and power regulation methods are also disclosed. The IC chip includes a processor and integrated supporting processing devices for the processor (e.g., network nodes, memory controllers, internal memory, input / output (I / O) interface circuitry, etc.). For example, the processor may be a central processing unit (CPU), a graphics processing unit (GPU), or a neural network processing unit (NPU), wherein the processor includes multiple processing units (PUs) and / or processor cores. The processor-based system can be provided as a system-on-a-chip (SoC) including the processor and the integrated supporting processing devices for the PUs. As an example, the SoC may be used in smaller mobile devices (e.g., cell phones, laptops) and in enterprise systems such as server chips in computer servers. The IC chip may also include a hierarchical power management system configured to control the power consumption of the processor-based system at both local and centralized levels to achieve desired performance within the IC chip's total power budget. This hierarchical power management system can be configured to control power consumption by controlling the power levels (e.g., voltage levels) allocated at one or more power rails in the IC chip, which provide power to the PU and the integrated supporting processing device. For example, the hierarchical power management system can be configured to provide additional power to certain power rails supplying power to devices with higher current demands to achieve higher performance, while providing less power to other power rails to keep the overall power within the power and / or thermal limits of the IC chip. The hierarchical power management system can also be configured to control power consumption by adjusting the performance (e.g., frequency) of the processing device in the processor-based system, thereby regulating (i.e., reducing, maintaining, or increasing) its current demand and thus regulating its power consumption. Note that, as used herein, regulation can mean taking action that reduces or increases a parameter that affects power and thus results in a corresponding decrease or increase in power consumption.

[0031] In an exemplary aspect, the hierarchical power management system may include local area management (LAM) circuitry distributed throughout the IC chip, each LAM circuitry associated with one or more processing devices within the IC chip. The LAM circuitry may be configured to generate power events associated with its monitored processing device within the IC chip, representing power consumption associated with the monitored processing device. These power events may be reported from the local area within the IC chip performing a power assessment of the specific monitored processing device to centralized power assessment and limiting (PEL) circuitry within the hierarchical power management system. The PEL circuitry is configured to assess and control (i.e., regulate) the power in the processor-based system within the IC chip to achieve desired performance within the overall power budget of the IC chip. The PEL circuitry may determine how to regulate the power based on the received power events. For example, the power event may be associated with a power consumption assessment, and if the assessed power consumption exceeds the power limits of the IC chip or adversely affects performance, the power event may be considered a power regulation recommendation for regulating the power in the IC chip.

[0032] The activity of the processing devices in an IC chip can affect its steady-state and transient current demands (e.g., current flow rate variations known as "di / dt"), and thus power consumption. Because the die area of ​​an IC chip can be larger due to the integration of processing units with integrated support processing devices, there can be a significant delay between the PEL circuit receiving a power event regarding the power consumption of the monitored processing device and the PEL circuit responding by adjusting the power in the IC chip to regulate power consumption. For example, this delay can cause the device in the IC chip to temporarily continue consuming excessive power before the power management circuitry has time to react, which can lead to performance problems (e.g., di / dt issues, voltage decay, overheating).

[0033] Additionally or alternatively, a processor-based system includes an exemplary regulation management circuit configured to receive regulation requests from one or more state detection circuits, generate and store regulation recommendations in each clock cycle based on the received regulation requests, and generate regulation control signals based on the most recent and stored regulation recommendations to regulate the activity of the processing circuitry. The regulation request may be based on measurements of electrical, thermal, and / or activity states monitored by the processing circuitry or by LAM circuitry, and these measured states may be caused by the activity of the processing circuitry. The regulation management circuitry can provide a local, dynamic, low-latency response to mitigate potential damage from measured local states of the processing circuitry while awaiting a response from the power management layer. In some examples, the regulation recommendations generated in each cycle will influence the regulation control signals in multiple subsequent cycles. In other examples, the generated regulation recommendations may replace stored regulation recommendations.

[0034] In this regard, Figure 1 This is a schematic diagram of an exemplary processor-based system 100 in the form of an exemplary system-on-a-chip (SoC) 102 within an integrated circuit (IC) chip 104. Optionally, a hierarchical power management system may be provided. The SoC 102 can be used in smaller mobile devices (e.g., cell phones, laptops) as well as in enterprise systems such as server chips in computer servers. First, regarding... Figure 1 Describe a processor-based system 100, and then in the following Figure 2 The description begins here of an exemplary hierarchical power management system that can be provided in a processor-based system 100 to evaluate and regulate power consumption in an IC chip 104.

[0035] refer to Figure 1The processor-based system 100 is provided in a single semiconductor die 106 and integrated into a single IC chip 104. The processor-based system 100 includes multiple processing unit (PU) clusters 108(0)-108(N), which are examples of processing devices 110 within the processor-based system 100. Each PU in the PU clusters 108(0)-108(N) may include one or more processor cores 112(0)-112(N), each configured to execute instructions (e.g., software, firmware) to perform tasks known to the processor. For example, the PU clusters 108(0)-108(N) may be a central processing unit (CPU) cluster, wherein one or more processor cores of the processor cores 112(0)-112(N) include CPUs and / or a graphics processing unit (GPU) cluster, wherein one or more processor cores of the processor cores 112(0)-112(N) include GPUs. The processor-based system 100 includes an internal communication network 114 to execute desired processing requests and associated processing tasks. This internal communication network facilitates communication paths between the PU clusters 108(0)-108(N) and other supporting processing devices, which are also considered processing devices. The PU clusters 108(0)-108(N) are communicatively coupled to the internal communication network 114. The internal communication network 114 may be a coherent communication bus providing a structure within the processor-based system 100. The internal communication network 114 may be a network structure typically composed of network nodes and their communication lines, wire networks, and / or communication channels, providing reliable communication paths between the different PU clusters 108(0)-108(N) and the supporting processing devices 110. Network nodes are circuits such as interconnect switches and routers that provide and receive data on the communication paths between the different PU clusters 108(0)-108(N) and the supporting processing devices 110. The architecture provided by the internal communication network 114 also includes a wire network or communication channel that allows different processing devices in the processor-based system 100 to communicate with each other at high speed and exchange data.

[0036] For example, such as Figure 1 As shown, the processor-based system 100 also includes an internal cache memory 116 and memory controllers (MC) 118(0)-118(M) as other types of processing devices 110 that provide access to memory. Figure 1The cache memory 116 shown is a shared cache memory that is communicatively coupled to an internal communication network 114 and accessible by the PU clusters 108(0)-108(N) via the internal communication network 114. The processor-based system 100 may also include private cache memories and / or private shared cache memories, which are integrated or privately accessible by one or more of the respective PU clusters 108(0)-108(N) without access to such private cache memories and / or private shared cache memories via the internal communication network 114. Memory controllers 118(0)-118(M) are communicatively coupled to the internal communication network 114 in the IC chip 104. Memory controllers 118(0)-118(M) provide the PU clusters 108(0)-108(N) with access to the memory for storing and capturing data to perform processing tasks. For example, memory controllers 118(0)-118(M) can be coupled to external memory of IC chip 104 or internal memory integrated in IC chip 104.

[0037] For example Figure 1 As shown, the processor-based system 100 in this example also includes I / O interface circuitry 120(0)-120(X) as another example of the processing device 110 also communicatively coupled to an internal communication network 114. The I / O interface circuitry 120(0)-120(X) provides access to I / O devices, which may be internal to and integrated into the IC chip 104 or external to the IC chip 104. For example, the I / O interface circuitry 120(0)-120(X) may be a peripheral component interconnect (PCI) interface circuitry used to connect I / O hardware devices to the processor-based system, such as... Figure 1 The processor-based system 100 allows high-speed data transfer between the device and the PU clusters 108(0)-108(N) in the processor-based system 100.

[0038] For example Figure 1 As shown, the processor-based system 100 in this example also includes socket-to-socket (S2S) interface circuitry 122(0)-122(Y) as another example of the processing device 110 also communicatively coupled to the internal communication network 114. The S2S interface circuitry 122(0)-122(Y) allows the processor-based system 100 to couple to another separate processor-based system (which may be similar to...) in a socket-to-socket connection. Figure 1 (The processor-based system 100 in the example). Figure 1The processor-based system 100 shown may be a first CPU motherboard system that can be communicatively coupled to another processor-based system for communication via an internal communication network 114 and coupled S2S interface circuits 122(0)-122(Y).

[0039] For example Figure 1 As shown, the processor-based system 100 in this example also includes additional interface (I / F) circuitry 127(0)-127(Z) as another example of the processing device 110 also communicatively coupled to the internal communication network 114. Interface circuitry 127(0)-127(Z) can provide additional external communication interfaces to the SoC 102, which is configured to provide communication interfaces according to desired standards or protocols. For example, interface circuitry 127(0)-127(Z) can be PCIe interface circuitry configured to support PCIe communication with the SoC 102.

[0040] Therefore, in Figure 1 In the processor-based system 100, an internal communication network 114 enables different processing devices (such as PU clusters 108(0)-108(N) and their processor cores 112(0)-112(N), cache memory, memory controllers 118(0)-118(M), I / O interface circuits 120(0)-120(X), and / or S2S interface circuits 122(0)-122(Y)) to work together efficiently. The architecture provided by the internal communication network 114 is designed to provide high-bandwidth, low-latency, and high-efficiency data routing between the different processing devices of the processor-based system 100.

[0041] In addition, such as Figure 1As shown and described in more detail below, the processor-based system 100 may also include a hierarchical power management system 124. In this example, the hierarchical power management system 124 is integrated into the same IC chip 104, which includes the PU clusters 108(0)-108(N) and the internal communication network 114, and is located on the same die 106. The hierarchical power management system 124 may be configured to control the power consumption of the processor-based system 100 by controlling the power consumption of some or all of the processing devices 110 in the IC chip 104. The hierarchical power management system 124 may be configured to manage power consumption to achieve desired performance within the overall power budget of the IC chip 104. For example, the processor-based system 100 may have an overall power budget based on the IC chip 104's ability to dissipate heat generated by the operation of the processor-based system 100. The processor-based system 100 may also have an overall power budget based on current limits of power rails in the IC chip 104. The power budget of the processor-based system 100 may also be based on power supply limits of the power source supplying the processor-based system 100. Therefore, the hierarchical power management system 124 can be configured to control power consumption by controlling the power level (e.g., voltage level) at one or more power rails in the IC chip 104 that supply power to the processing device 110, or by controlling the operating frequency. For example, the hierarchical power management system 124 can be configured to supply additional power to some power rails to supply power to devices with higher current requirements for higher performance, while providing less power to other power rails to keep the overall power within the power and / or thermal limits of the IC chip 104. For example, the hierarchical power management system 124 can be configured to communicate with or include the power management integrated circuit (PMIC) chip 125 (which may be on-chip or off-chip of the SoC 120) to practically cause the power supplied to certain power rails to be adjusted.

[0042] Furthermore, as discussed in more detail below, the hierarchical power management system 124 can also be configured to control the power consumption in the processor-based system 100 by adjusting the performance (e.g., frequency and / or voltage) of the processing device 110 in the processor-based system 100. This, in turn, regulates (i.e., reduces, maintains, or increases) the current demand of such processing device 110, and thus regulates its power consumption in the IC chip 104. Regulation can generally refer to any measure that affects (i.e., reduces, maintains, or increases) power consumption (e.g., modifies the clock frequency and / or supply voltage). According to the power equation P = cf V 2In the processor-based system 100, the timing circuit in the processing device 110 has a performance related to power (P) based on frequency (f), where "c" is the capacitor and "V" is the voltage. Therefore, reducing the frequency of the timing circuit in the processing device 110 of the processor-based system 100 also reduces its power consumption.

[0043] Figure 2 yes Figure 1 An exemplary logic diagram of a processor-based system 100 illustrates a processing device 110 communicatively coupled to an internal communication network 114. According to aspects of this disclosure, a hierarchical power management system 124 may be provided to control power consumption in an IC chip 104. Figure 1 and Figure 2 Common components in the processor-based system 100 are shown by common component numbers and therefore will not be described again. The IC chip 104 may also include a target device 200 that controls power, which may include the processing device 110 and other circuitry described below. As will be discussed in more detail below, the hierarchical power management system 124 is configured to regulate the power to the target device 200 and the processing device 110, thereby regulating the power consumption in the IC chip 104.

[0044] For example Figure 2As shown, the hierarchical power management system 124 may include centralized power assessment and limiting (PEL) circuitry 126, configured to assess power consumption in IC chip 104 and take action to limit or regulate power consumption in IC chip 104. In this example, PEL circuitry 126 may be provided as part of a power management integrated circuit (PMIC) 125 integrated into IC chip 104. PEL circuitry 126 may communicate such power regulation requests to, for example, a power management controller (PMC) 128, which is configured to control the power supplied by voltage rails in IC chip 104. Regulating power consumption may include increasing power (e.g., increasing the voltage to the power rail) to increase power consumption for performance enhancement and decreasing power (e.g., decreasing the voltage to the power rail) to decrease power consumption. The hierarchical power management system 124 may be configured to assess power consumption in IC chip 104 by receiving power events 130 that provide information reported to it from devices at lower hierarchical levels in IC chip 104, which provide an indirect indication of power consumption. For example, IC chip 104 may have one or more temperature sensors 132 configured to report thermal power events 130(1) to PEL circuit 126 to provide a temperature indication in IC chip 104, which can then be correlated with the power consumption of processor-based system 100 in IC chip 104. As another example, IC chip 104 may have one or more telemetry sensors 134 (e.g., current sensors) configured to detect telemetry power events 130(2) and report them to PEL circuit 126 to provide a telemetry information indication in IC chip 104, which can then be correlated with the power consumption of processor-based system 100 in IC chip 104.

[0045] The power consumption of the processing device 110 in the processor-based system 100 can cause power consumption in the IC chip 104. Therefore, a method is also needed for the PEL circuit 126 in the hierarchical power management system 124 to receive a direct indication of the power consumption of the processing device 110. The PEL circuit 126 can then use this information to assess the power consumption in the IC chip 104 and use this information to appropriately adjust the power consumption in the IC chip 104. In this regard, as... Figure 2 As shown, the hierarchical power management system 124 may also include Local Area Management (LAM) circuitry 136, each LAM circuitry being associated with one or more processing devices 110 within the IC chip 104. The LAM circuitry 136 may be placed at various locations within the IC chip 104, including corners of the IC chip 104 where power assessment and power limiting may be required. For example, LAM circuitry 136(1)(0)-136(1)(N) may be associated with one or more PU clusters in PU clusters 108(0)-108(N), such as... Figure 2As shown. As another example, LAM circuits 136(2)-136(5), 136(6)(0)-136(6)(X) may also be associated with one or more of the following: memory controller 118, internal communication network 114 (e.g., structure), one or more I / O interface circuits in I / O interface circuit 120, one or more S2S circuits in S2S circuit 122 and / or one or more interface circuits 127(0)-127(Z). Each LAM circuit 136(2)-136(5), 136(6)(0)-136(6)(X) is configured to monitor activities associated with its associated processing device 110 (as monitored processing device 110), and then generate corresponding activity power events 138(1)(0)-138(1)(N), 138(2)-138(5), 138(6)(0)-138(6)(Z) (referred to herein individually, in part, or collectively as “activity power event 138”), which are directly or indirectly communicated to PEL circuit 126. Activity power events 138(1)(0)-138(1)(N), 138(2)-138(5), 138(6)(0)-138(6)(Z) contain information related to the power consumption of the corresponding monitored processing device 110. For example, activity power events 138(1)(0)-138(1)(N), 138(2)-138(5), 138(6)(0)-138(6)(Z) may contain processing activity information or power consumption information, which are generated by the corresponding LAM circuits 136(1)(0)-136(1)(N), 136(2)-136(5), 136(6)(0)-136(6)(X) based on the processing activity of their monitored processing device 110 to evaluate the power consumption of their monitored processing device 110.

[0046] In either case, in this manner, active power event 138 can be reported from a local area in IC chip 104 (where a power assessment for a specific monitored processing device 110 is performed) to centralized PEL circuitry 126. PEL circuitry 126 can then be configured to use the received active power event 138 and / or other power events 130 to assess and control (i.e., regulate) the power in the processor-based system 100 within IC chip 104 to achieve desired performance within the total power budget of IC chip 104. For example, active power event 138, associated with a power consumption assessment of processing device 110, can essentially be considered a power regulation recommendation to PEL circuitry 126 if the assessed power consumption exceeds the power limit of IC chip 104 or negatively impacts performance in an undesirable manner, causing PEL circuitry 126 to regulate the power in IC chip 104.

[0047] The PEL circuit 126 is configured to receive an active power event 138 relating to the activity of an individual processing device 110 in the processor-based system 100. This also allows the PEL circuit 126 to regulate power consumption for certain local processing devices 110 (which are responsible for power consumption increases). This allows the PEL circuit 126 to regulate power differentially, as opposed to regulating power on a power rail or otherwise in the IC chip 104 that affects the power delivered to the larger set of processing devices 110 as a whole. For example, as discussed in more detail below, the PEL circuit 126 may be configured to use the received active power event 138 to perform performance tuning of the processing devices 110 in the processor-based system 100 to regulate their power consumption. The PEL circuit 126 may be configured to generate a power limiting management response 140, which will be communicated to certain LAM circuits 136 in the processor-based system 100 to limit the performance of their monitored processing devices 110.

[0048] Performance tuning of the processing device 110 in the processor-based system 100 can be accomplished in various ways to regulate its power consumption. For example, as discussed in more detail below, performance tuning can be achieved by the PEL circuit 126 generating a throughput-tuning power limit management response 140, the destination of which is the LAM circuit 136(3) associated with the internal communication network 114. The LAM circuit 136(3) can be configured to regulate the throughput of communication traffic in the internal communication network 114, such as at a specific network node in the internal communication network 114, thereby regulating the current demand in the internal communication network 114 and thus regulating its power consumption. Throughput tuning can be limited to certain areas or network nodes in the internal communication network 114. In another example, as discussed in more detail below, performance tuning in the processor-based system 100 can be achieved by the PEL circuit 126 generating a clock-tuning power limit management response 140, causing a clock circuit (which can clock one or more processing devices in the processing device 110) to regulate the speed (i.e., clock frequency) of certain clock-controlled processing devices 110. The clock regulation of processing device 110 adjusts its current demand, thereby regulating its power consumption. In another example, as discussed in more detail below, performance regulation in processor-based system 100 can be achieved by adjusting or changing the power state of the monitored processing device 110 to regulate its performance and thus its power consumption.

[0049] Figure 3 yes Figure 1 The diagram includes a top view of an exemplary physical layout of a semiconductor die (“die”) 102 of an IC chip 104 in a processor-based system 100, further exemplary details of the physical layout of a hierarchical power management system 124, and an exemplary organization of power rails provided in the processor-based system 100.

[0050] like Figure 3 As shown, IC chip 104 has a physical layout including a central tile (CTILE), a west tile (WTILE), an east tile (ETILE), a south tile (STILE), a north tile (NTILE), and an A tile (ATILE). A tile is a smaller segment of a semiconductor die that has been processed in the wafer fabrication process and contains a collection of IC components. In this example, the central tile (CTILE) includes PU clusters 108(0)-108(N), shown as NCC0-NCC19. Different numbers of processor cores can be provided in different PU clusters 108(0)-108(N), i.e., NCC0-NCC19. In this example, PU clusters 108(0)-108(N), i.e., NCC0-NCC19, are all powered by the same power rail 300(1). The central tile (CTILE) in this example also includes an internal communication network 114, which is shown by multiple central network nodes FABC00-FABC65. Network nodes FABC00 to FABC65 are circuits that generate a network structure (“structure”) for communication paths between different PU clusters 108(0)-108(N) and supporting processing device 110. In this example, network nodes FABC00-FABC65 are powered by a second power rail 300(2). Network nodes FABC00 to FABC65 are circuits that may include interconnect switches and / or routers that provide a reliable network structure that provides and receives data on an internal communication network 104 between different PU clusters 108(0)-108(N) and supporting processing device 110. The central brick CTILE in this example also includes system-level cache memories 116(0)-116(7) powered by a third power rail 300(3) to provide a shared cache memory 116 for PU clusters 108(0)-108(N), i.e., NCC0-NCC19. System-level cache memories 116(0)-116(7) are organized in different quadrants adjacent to and coupled to the corresponding memory circuits DDR0-DDR7, which include corresponding memory controllers 118(0)-118(7) and memories 304(0)-304(7) (e.g., dynamic data random access memory (DDR) circuitry) in the west tile WTILE, to provide, for example, an interleaved memory scheme. Memory circuits DDR0-DDR7 may be powered by another separate fourth power rail 300(4). Memory circuits DDR0-DDR7 are also communicatively coupled to an internal communication network 114 via corresponding network nodes FABC00-FABC05.

[0051] Continue to refer to Figure 3In this example, the central tile CTILE also includes system-level cache memories 116(8)-116(15), which are also powered by a third power rail 300(3) to provide additional shared cache memory 116 to the PU clusters 108(0)-108(N), i.e., NCC0-NCC19. The system-level cache memories 116(8)-116(15) can be organized into different quadrants adjacent to the corresponding memory circuits DDR8-DDR15, which include corresponding memory controllers 118(8)-118(15) and coupled memories 304(8)-304(15) (e.g., DDR circuits) in the east tile ETILE to provide, for example, an interleaved memory scheme. The memory circuits DDR8-DDR15 are also shown as being powered by the same fourth power rail 300(4) that powers the memory circuits DDR0-DDR7 in the west tile WTILE. The memory circuits DDR8-DDR15 are also communicatively coupled to the internal communication network 114 via corresponding network nodes FABC60-FABC65.

[0052] Continue to refer to Figure 3 In this example, the central tile CTILE of IC chip 104 includes request node circuits FABS00, FABS40, FABN57, and FABN47, which are coupled to the internal communication network 114 to provide network interfaces between the I / O interface circuits 120(0)-120(3) and 120(4)-120(7) in the corresponding south tile STILE and north tile NTILE and the internal communication network 114. The request node circuits FABS00, FABS40, FABN57, and FABN47 manage traffic requests from the I / O interface circuits 120(0)-120(3) and 120(4)-120(7) to the internal communication network 114 and vice versa. In this example, the request node circuits FABS00, FABS40, FABN57, FABN47 and the I / O interface circuits 120(0)-120(3), 120(4)-120(7) are powered by the fifth power rail 300(5).

[0053] Continue to refer to Figure 3 In this example, the A-brick in IC chip 104 includes PEL circuit 126 and PMC 128 in the hierarchical power management system 124.

[0054] Therefore, as Figure 3As shown, the processing device 110 in the processor-based system 100 of IC chip 104 is powered by a series of different power rails 300(1)-300(5). Therefore, the PEL circuit 126 in the hierarchical power management system 124 has resolution for each of these different power rails 300(1)-300(5), wherein the voltage on these power rails 300(1)-300(5) is changed based on power events 130, 138, thereby regulating the power consumption in IC chip 104. Note that each power rail 300(1)-300(5) may actually include one or more power rails.

[0055] Figure 4 Table 400 illustrates exemplary assignments of power management circuits AK0 to AK5 in the PMIC 125 of a processor-based system 100 to devices in the processor-based system 100 for supplying power to such devices. Power management circuits AK0-AK5 may be responsible for controlling one or more different power rails 300(1)-300(5), such as... Figure 3 As shown, power is supplied to various components. Multiple devices in the processor-based system 100 can be coupled to the same power rails 300(1)-300(5) to receive power. For example, as Figure 4 As shown, in this example, PU clusters NCC19, 18, 15, and 14 are powered by the power rail controlled by power management circuit AK0; PU clusters NCC11-10 are powered by the power rail controlled by power management circuit AK1; PU clusters NCC2, 3, 6, and 7 are powered by the power rail controlled by power management circuit AK2; PU clusters NCC0, 1, 4, and 5 are powered by the power rail controlled by power management circuit AK3; PU clusters NCC9-8 are powered by the power rail controlled by power management circuit AK4; and PU clusters NCC12, 13, 16, and 17 are powered by the power rail controlled by power management circuit AK5. Similarly, as... Figure 4 As shown, a single device in the processor-based system 100 can be coupled to more than one power rail to receive power. For example, the power supplied to the logic circuit (SoC_Logic) can be controlled by multiple power management circuits AK1-AK4. The cache memory 116 can be powered from the power rails controlled by the power management circuits AK0-AK5. Different memory controllers 118 are shown as being powered by the power rails controlled by the power management circuits AK0-AK5. The I / O interface circuits 120(0)-120(3) are shown as being powered by the power rails controlled by separate corresponding power management circuits AK3, AK2, AK5, and AK0.

[0056] Figure 5 yes Figure 1Another top view of the processor-based system 100 in IC chip 104 illustrates the Local Area Management (LAM) circuitry 136 and PEL circuitry 126 as part of a hierarchical power management system 124. (See above regarding...) Figure 2 As discussed, the LAM circuit 136 can be configured to locally monitor the activity of the PU clusters 108(0)-108(N) in the processing device 110, such as the processor-based system 100, to assess and regulate their power consumption, and report the activity power events 138 regarding the assessed power consumption to the PEL circuit 126. The processor-based system 100 in this example includes a clock circuit 506 that generates a clock signal 508 to clock the PU clusters 108(0)-108(N), thereby controlling the speed of the PU clusters 108(0)-108(N). The PEL circuit 126 is configured to collect the activity power events 138 regarding the power consumption of the monitored processing device 110, and in response, issue a power limit management response 140 to regulate the power consumption in the IC chip 104.

[0057] like Figure 5 As shown, multiple LAM circuits 136(3) are distributed in the central brick CTILE and associated with corresponding network nodes 500 (as processing devices 110) in the internal communication network 114. For example, the internal communication network 114 may be as follows: Figure 5 The mesh network shown. The internal communication network 114 is capable of routing communication traffic from the PU clusters 108(0)-108(N) through different network nodes 500 based on the performance and traffic characteristics of the internal communication network 114. In this way, the throughput of the internal communication network 114 is not limited by any single network node 500. The processor-based system 100 in this example includes a clock circuit 510 that generates a clock signal 512 to clock the network nodes 500, thereby controlling the speed of the internal communication network 114. The clock circuit 510 is another example of the target device 200 in the IC chip 104. As will be discussed in more detail below, the LAM circuit 136(3) associated with the network nodes 500 in the internal communication network 114 is configured to sample the processing activities of the separately assigned network nodes 500 to generate multiple activity samples. The LAM circuit 136(3) is then configured to evaluate the power consumption of the assigned network node 500 based on the activity samples of its assigned network node 500, so as to generate an activity power event 138 based on the evaluated power consumption of the corresponding network node 500.

[0058] In addition, such as Figure 5As shown, in this example, the hierarchical power management system 124 may also include regional activity management (RAM) circuitry 502(3) configured to monitor the activity of the internal communication network 114. RAM circuitry 502(3) may be located in specific areas of the internal communication network 114 and each is assigned to and coupled to a subset of LAM circuitry 136(3). RAM circuitry 502(3) may be intermediate power management circuitry in the hierarchical power management system 124. RAM circuitry 502(3) may be coupled to PEL circuitry 126 via a second communication network 504. RAM circuitry 502(3) may be communicatively and hierarchically located between LAM circuitry 136(3) and centralized PEL circuitry 126. In some examples, RAM circuitry 502(3) is configured to receive and aggregate activity power events 138 reported by the assigned LAM circuitry 136(3) regarding the activity of its monitored network node 500. Next, RAM circuit 502(3) can aggregate such active power events 138 and report the aggregated active power events to PEL circuit 126 so that PEL circuit 126 can determine how to regulate the power consumption of network node 500 to achieve the desired overall performance of the internal communication network 114 while keeping the power consumption within the desired limits. In response to determining that the power consumption of network node 500 exceeds the desired limits, PEL circuit 126 can communicate a power limiting management response 140 back to the given RAM circuit 502(3) to perform throughput regulation of the given network node 500. For example, as discussed in more detail below, RAM circuit 502(3) can be configured to regulate the throughput of the given network node 500 by selectively enabling and disabling communication traffic through network node 500.

[0059] Similarly, as Figure 5 As shown, in this example, multiple LAM circuits 136(2) are allocated in the west tile (WTILE) and the east tile (ETILE) and associated with the corresponding memory circuits DDR0-DDR7, DDR8-DDR15 (as processing device 110). Also, as discussed in more detail below, the LAM circuits 136(2) associated with the memory circuits DDR0-DDR7, DDR8-DDR15 are configured to sample the processing activity of the respective assigned memory circuits DDR0-DDR7, DDR8-DDR15 to generate multiple activity samples. The LAM circuits 136(2) are then configured to evaluate the power consumption of the assigned memory circuits DDR0-DDR7, DDR8-DDR15 based on the activity samples of their assigned network nodes 500, to generate an activity power event 138 based on such evaluated power consumption of the corresponding memory circuits DDR0-DDR7, DDR8-DDR15.

[0060] In addition, such as Figure 5As shown, in this example, the hierarchical power management system 124 also includes regional RAM circuits 502(2) configured to monitor the activity of memory circuits DDR0-DDR7 and DDR8-DDR15. RAM circuits 502(2) are located in specific regions of memory circuits DDR0-DDR7 and DDR8-DDR15 and are each assigned to and coupled to a subset of LAM circuits 136(2). RAM circuits 502(2) are communicatively and hierarchically located between LAM circuits 136(2) and centralized PEL circuits 126. RAM circuits 502(2) are coupled to PEL circuits 126 via a second communication network 504. RAM circuits 502(2) are configured to receive and aggregate active power events 138 reported by the assigned LAM circuits 136(2) regarding the activity of their monitored memory circuits DDR0-DDR7 and DDR8-DDR15. Next, RAM circuit 502(2) can aggregate such active power events 138 and report the aggregated active power events to PEL circuit 126 so that PEL circuit 126 can determine how to regulate the power consumption of memory circuits DDR0-DDR7, DDR8-DDR15 to achieve the desired overall performance of memory circuits DDR0-DDR7, DDR8-DDR15 while keeping power consumption within desired limits. In response to determining that the power consumption of memory circuits DDR0-DDR7, DDR8-DDR15 exceeds the desired limit, PEL circuit 126 can communicate a power limit management response 140 back to the given RAM circuit 502(2) to perform throughput and / or performance regulation of the given memory circuits DDR0-DDR7, DDR8-DDR15. For example, as discussed in more detail below, RAM circuit 502(2) can be configured to regulate the throughput and / or performance of the given memory circuits DDR0-DDR7, DDR8-DDR15 by selectively enabling and disabling memory access requests / responses to memory circuits DDR0-DDR7, DDR8-DDR15.

[0061] Similarly, as Figure 5As shown, in this example, the hierarchical power management system 124 also includes regional RAM circuits 502(4) configured to monitor the activity of I / O interface circuits 120(0)-120(7). RAM circuits 502(4) are located in specific areas of the I / O interface circuits 120(0)-120(7) and are each assigned to and coupled to a subset of LAM circuits 136(4), as shown. RAM circuits 502(4) are communicatively and hierarchically located between LAM circuits 136(4) and centralized PEL circuits 126. RAM circuits 502(4) are coupled to PEL circuits 126 via a second communication network 504. RAM circuits 502(4) are configured to receive and aggregate activity power events 138 reported by the assigned LAM circuits 136(4) regarding the activity of their monitored I / O interface circuits 120(0)-120(7). Next, RAM circuit 502(4) can aggregate such active power events 138 and report the aggregated active power events to PEL circuit 126 so that PEL circuit 126 can determine how to regulate the power consumption of I / O interface circuits 120(0)-120(7) to achieve the desired overall performance of I / O interface circuits 120(0)-120(7) while keeping power consumption within the desired limits. In response to determining that the power consumption of I / O interface circuits 120(0)-120(7) exceeds the desired limit, PEL circuit 126 can communicate a power limit management response 140 back to the given RAM circuit 502(4) to perform throughput and / or performance regulation of the given I / O interface circuits 120(0)-120(7). For example, as discussed in more detail below, RAM circuit 502(4) can be configured to regulate the throughput and / or performance of a given I / O interface circuit 120(0)-120(7) by selectively enabling and disabling access requests / responses to I / O interface circuits 120(0)-120(7).

[0062] If back Figure 2As shown, LAM circuits 136(1)(0)-136(1)(N) can also be associated with each PU cluster 108(0)-108(N) in the processor-based system 100 to sample activity therein, thereby evaluating power consumption in the respective PU cluster 108(0)-108(N). LAM circuits 136(1)(0)-136(1)(N) can be configured to generate active power events 138, including evaluated power consumption in response to RAM circuits 502, which then aggregate such active power events 138 to PEL circuits 126. RAM circuits 502 assigned to a subset of LAM circuits 136(1)(0)-136(1)(N) are coupled to PEL circuits 126 via a second communication network 504. In response, PEL circuits 126 can generate power limiting management responses 140 to regulate the performance of PU clusters 108(0)-108(N).

[0063] For example Figure 2 As shown, the LAM circuit 136(5) can also be associated with each of the S2S interface circuits 122(0)-122(Y) in the processor-based system 100 to sample the activity therein, thereby evaluating the power consumption in the respective S2S interface circuits 122(0)-122(Y). The LAM circuit 136(5) can be configured to generate active power events 138, including evaluated power consumption in response to the RAM circuit 502, which then aggregates such active power events 138 to the PEL circuit 126. The RAM circuits 502 assigned to a subset of the LAM circuit 136(5) are coupled to the PEL circuit 126 via a second communication network 504. In response, the PEL circuit 126 can generate a power limiting management response 140 to regulate the performance of the S2S interface circuits 122(0)-122(Y).

[0064] If back Figure 2 As shown, LAM circuits 136(6)(0)-136(6)(X) can also be associated with respective interface circuits 127(0)-127(Z) in the processor-based system 100 to sample their activity and evaluate the power consumption in the corresponding interface circuits 127(0)-127(Z). LAM circuits 136(6)(0)-136(6)(X) can be configured to generate active power events 138, including evaluated power consumption in response to RAM circuits 502, which then aggregate such active power events 138 to PEL circuits 126. RAM circuits 502 assigned to a subset of LAM circuits 136(6)(0)-136(6)(X) are coupled to PEL circuits 126 via a second communication network 504. In response, PEL circuits 126 can generate power limiting management responses 140 to regulate the performance of interface circuits 127(0)-127(Z).

[0065] In this example, any of the RAM circuits 502, 502(2)-504(4) discussed above may also include circuitry that functionally serves as LAM circuitry for the assigned processing device 110. In this regard, any of the RAM circuits 502, 502(2)-504(4) may also be configured to sample the processing activity of its respective assigned processing device 110 to generate multiple activity samples for such processing device 110. Such RAM circuits 502, 502(2)-504(4) may be configured to evaluate the power consumption of their assigned processing device 110 based on the activity samples of their assigned processing device 110, to generate aggregated activity power events based on this evaluated power consumption of the respective processing device 110 and other received activity power events 138 from its coupled LAM circuits 136(1)(0)-(1)(N), 136(2)-136(5), 136(6)(0)-136(6)(X).

[0066] Please note that in any of the examples above, RAM circuit 502 is optional for any processing device in monitored processing device 110, and its corresponding LAM circuits 136(1)-136(6) can be configured to directly transmit active power event 138 to PEL circuit 126.

[0067] Figure 6 This example can be provided as Figures 1 to 3 and Figure 5 A schematic diagram of additional exemplary details of the three (3) level hierarchical power management system 624 of the processor-based system 100 in the IC chip 104. Figure 6 Hierarchical power management system 624 and Figures 1 to 3 and Figure 5 The components in the hierarchical power management system 124 are shown with the same component number. In this regard, Figure 6 An example is a single LAM circuit 136 communicatively coupled to a single RAM circuit 502 (which is coupled to PEL circuit 126). However, note that this is for simplicity. Figure 6 of examples. exist Figure 6In the hierarchical power management system 624, there may be multiple RAM circuits 502 communicatively coupled to PEL circuit 126. There may also be multiple LAM circuits 136 communicatively coupled to each of the multiple RAM circuits 502. The following discussion of exemplary operation of LAM circuits 136 and RAM circuits 502 also applies to any number of LAM circuits 136 and RAM circuits 502 included in a processor-based system, including LAM circuits 136(1)(0)-(1)(N), 136(2)-136(5), 136(6)(1)-136(6)(X) and RAM circuits 502, 502(2)-502(4).

[0068] refer to Figure 6 In this example, the LAM circuit 136 is configured to sample the processing activity of the assigned, monitored processing device 110 in each period of a given local time window, as received activity samples 600. The LAM circuit 136 periodically samples the activity of its monitored processing device 110 within the local time window, representing the activity of the assigned, monitored processing device 110 within this local time window. In this example, the LAM circuit 136 is configured to correlate the received activity samples 600 with the power consumption of the processing device 110 for the given local time window. The LAM circuit 136 includes an accumulation circuit 602 configured to accumulate the evaluated power consumption based on the received activity samples 600 sampled within the given local time window to generate an evaluated current demand 604 for the monitored processing device 110 for the local time window. The evaluated current demand 604 is an evaluation of the accumulated current measurement (i.e., power consumption) reported by the assigned processing device 110 within the local time window. Next, the accumulator circuit 602 provides an evaluation current demand 604 (a time-varying current demand) for each local time window of the active power event 606 generated on the second communication network 504, thereby representing the evaluation power consumption of the monitored processing device 110 transmitted to the RAM circuit 502 assigned to the LAM circuit 136. The accumulator circuit 602 may repeat the same procedure for subsequent local time windows to accumulate the evaluation power consumption of the received active samples 600 during the local time window, thereby generating the next evaluation current demand 604 for the monitored processing device 110.

[0069] Continue to refer to Figure 6The RAM circuit 502 may include an aggregation circuit 608 configured to aggregate received active power events 606 from its coupled LAM circuit 136 into a generated aggregated active power event 138. The RAM circuit 502 may then be configured to transmit the aggregated active power event 138 to the PEL circuit 126 over a second communication network 504. Note that in this example, the RAM circuit 502 also includes its own LAM circuit 136R, which may similarly... Figure 6 The LAM circuit 136 is configured in the middle. In this regard, the LAM circuit 136R can be configured to sample the processing activity 600R of the assigned processing device 110 into multiple activity samples 600R. The LAM circuit 136R can periodically sample the processing activity 600R of the assigned processing device 110 to generate multiple activity samples within a given local time window, representing the activity of the assigned, monitored processing device 110. The LAM circuit 136R is configured to determine the current rate and / or current rate variation (i.e., di / dt) of the current supplied to the assigned processing device 110 and represented by the received multiple activity samples 600R. The LAM circuit 136R can be programmed to correlate processing activity with power consumption to evaluate the power consumption of the monitored processing device 110 within a local time window. Next, the LAM circuit 136R can be configured to generate an active power event 606 representing the evaluation power consumption of the monitored processing device 110, which is then transmitted to the aggregation circuit 608 of the RAM circuit 502 to aggregate into an aggregated active power event 138.

[0070] Continue to refer to Figure 6The PEL circuit 126 can be configured to receive aggregated active power events 138 from one or more RAM circuits 502 included in the hierarchical power management system 624. In this example, the PEL circuit 126 includes a decoding circuit 610 configured to decode the received aggregated active power events 138 into decoded active power events 611, which are routed to corresponding activity tracker circuits 612(1)-612(T) associated with the monitored processing device 110 in the processor-based system 100. The PEL circuit 126 may also include other energy tracker circuits (not shown) associated with other power events (e.g., temperature, attenuation detection) that may also affect how the PEL circuit 126 determines how to regulate power. The activity tracker circuits 612(1)-612(T) can be configured to aggregate the associated active power events 138 for the assigned monitored processing device 110 to determine whether the power consumption of the monitored processing device 110 exceeds a defined threshold current flow rate / current flow rate change (di / dt). The activity tracker circuits 612(1)-612(T) may each include a power limiting management strategy configured to generate corresponding power regulation recommendations 614(1)-614(T) for use by the PEL circuit 126 to determine how to regulate the distributed power and / or performance of the monitored processing device 110, thereby regulating power consumption.

[0071] Continue to refer to Figure 6 The PEL circuit 126 also includes a merging circuit 616 that merges power regulation recommendations 614(1)-614(T) for individual monitored processing devices 110 into merged power regulation recommendations 618(1)-618(Q). The merged power regulation recommendations 618(1)-618(Q) are provided to the corresponding assigned target circuits 620(1)-620(Q). Each target circuit 620(1)-620(Q) is associated with a different target device 200 in the processor-based system 100, wherein the PEL circuit 126 may issue power limiting management responses 140(1)-140(Q) to limit the power consumption of such target devices 200. Target devices 200 are devices in the IC chip 104 whose operational controls (e.g., operating voltage, frequency, workload) can affect the power consumption in the IC chip 104. Target devices in the IC chip 104 may include not only processing devices 110 in the processor-based system 100. For example, target devices 200 may include, for example, devices such as... Figure 3The power rails 300(1)-300(5) shown and / or any processing device in the processing device 110 of the processor-based system 100. The PEL circuit 126 can be programmed to map (e.g., via firmware, electronic fuses, etc.) the combined power regulation recommendations 618(1)-618(Q) to a specific target device 200, and thus to target circuits 620(1)-620(Q), such devices or circuits may not be directly associated with each other. For example, it may be desirable for the PEL circuit 126 to regulate the power consumption of the I / O interface circuits 120(0)-120(X) not only by regulating the power consumption of the I / O interface circuits 120(0)-120(X), but also by regulating the power consumption of the PU clusters 108(0)-108(N) that may affect the power consumption of the I / O interface circuits 120(0)-120(X). In this manner, the combined power regulation recommendations 618(1)-618(Q) and / or other power events related to power issues and power consumption in IC chip 104 can be mapped in PEL circuit 126 to be associated with different target devices 200 for power consumption regulation. The combined circuit 616 can be programmed as a "many-to-many mapping" to be associated with different power limit management responses within IC chip 104 in a desired manner, thereby providing greater flexibility in managing power consumption in IC chip 104 while still achieving the desired performance. In this way, the power regulation management behavior of PEL circuit 126 can be configured and modified even after IC chip 104 has been deployed in the application.

[0072] Continue to refer to Figure 6 Each of the target circuits 620(1)-620(Q) may be configured to determine whether the power consumption of the associated target device 200 in the processor-based system 100 should be adjusted based on the combined power adjustment recommendation 618(1)-618(Q) provided to the target circuits 620(1)-620(Q). Each of the target circuits 620(1)-620(Q) may include a finite state machine (FSM) circuit 622(1)-622(Q) configured to analyze the corresponding received combined power adjustment recommendation 618(1)-618(Q) to determine whether the power consumption of the associated target device 200 should be adjusted. If the FSM circuits 622(1)-622(Q) determine that the power consumption of the associated target device 200 in the processor-based system 100 should be adjusted, the FSM circuits 622(1)-622(Q) cause the associated power limit command generation circuits 625(1)-625(Q) to generate power limit management responses 140(1)-140(Q) such that the power consumption of the target device 200 is associated with the power limit management response 140(1)-140(Q), thereby limiting the power consumption.

[0073] For example, if target circuits 620(1)-620(Q) are assigned to target device 200 on power rails 300(1)-300(5), then target circuits 620(1)-620(Q) can be configured to determine how to regulate the voltage on the associated power rails 300(1)-300(5) to control the power consumption of processing device 110 powered by such power rails 300(1)-300(5). Corresponding power limit command generation circuits 625(1)-625(Q) can be configured to generate performance-adjusting power limit management responses 140(1)-140(Q) such that the voltage supplied to the associated power rails 300(1)-300(5) is regulated, thereby controlling the power consumption of processing device 110 powered by such associated power rails 300(1)-300(5).

[0074] In another example, if target circuits 620(1)-620(Q) are assigned to target device 200 such as internal communication network 114, then target circuits 620(1)-620(Q) can be configured to determine how to regulate the performance of internal communication network 114, thereby controlling the power consumption of internal communication network 114. For example, to regulate the throughput performance of internal communication network 114, target device 200 can be a clock circuit 506 configured to clock internal communication network 114. Figure 5 Clock circuit 506 is another example of target device 200 in IC chip 104. Target circuits 620(1)-620(Q) can be determined by clock circuit 506. Figure 5 The frequency of the generated clock signal 508 is adjusted to generate clock adjustment power limit management responses 140(1)-140(Q). The clock adjustment power limit management responses 140(1)-140(Q) can adjust the clock signal 508, which in turn will adjust the speed and throughput performance of the internal communication network 114, and thus adjust its power consumption and / or the power consumption of other circuits clocked by the clock signal 508.

[0075] In another example, if target circuits 620(1)-620(Q) are assigned to target device 200 (as PU clusters 108(0)-108(N) or any other processing device 110), then target circuits 620(1)-620(Q) can be configured to determine how to regulate the performance of internal communication network 114, thereby controlling the power consumption of internal communication network 114. For example, to regulate the performance of PU clusters 108(0)-108(N) or other processing devices 110, target device 200 may be clock circuit 506 ( Figure 5The target circuit 620(1)-620(Q) is configured to clock the PU clusters 108(0)-108(N). The target circuit 620(1)-620(Q) determines the adjustment frequency of the clock signal 508 generated by the clock circuit 506 to generate the performance power limit management response 140(1)-140(Q). The clock adjustment power limit management response 140(1)-140(Q) will cause the clock signal 508 to be adjusted, which in turn will adjust the performance of the PU clusters 108(0)-108(N) or other processing devices 110.

[0076] like Figure 6 As shown, in this example, in order to convey the power limiting management responses 140(1)-140(Q) generated by the PEL circuit 126 to achieve power regulation of the target device 200 in the processor-based system 100, the power limiting management responses 140(1)-140(Q) are conveyed to the target device 200 in the processor-based system 100. For the target device 200 of the monitored processing device 110 monitored by the LAM circuit 136 or the RAM circuit 502, the PEL circuit 126 may be configured to convey the associated power limiting management responses 140(1)-140(Q) to the RAM circuit 502. In this example, RAM circuit 502 includes command processor 626 configured to receive power limit management responses 140(1)-140(Q), process the power limit management responses 140(1)-140(Q) to identify the LAM circuit 136 to which it is communicating, which is actually implementing the power regulation requested in the received power limit management responses 140(1)-140(Q). In this example, RAM circuit 502 includes limit command engine circuit 628 configured to generate a local power limit management response 630 directed to LAM circuit 136, which can implement the power regulation requested in the received power limit management responses 140(1)-140(Q). Note that if the local power limit management response 630 refers to regulating the power consumption of multiple processing devices 110 monitored by the multiple LAM circuits 136 associated with RAM circuit 502, the limit command engine circuit 628 can address the local power limit management response 630 to the multiple LAM circuits 136. Also note that in this example, if RAM circuit 502 includes LAM circuit 136R and RAM circuit 502 is monitoring processing device 110 (which is the target device 200 to be regulated), then the local power limit management response 630 generated by limit command engine circuit 628 is directed to LAM circuit 136R.

[0077] Continue to refer to Figure 6In response to the LAM circuit 136 receiving a partial power limit management response 630, the power limit management decoder and sequencer circuit 632 can process the received partial power limit management response 630. The power limit management decoder and sequencer circuit 632 can be configured to determine a power regulation response to be applied to the monitored processing device 110 based on the partial power limit management response 630. In this regard, the power limit management decoder and sequencer circuit 632 can be configured to generate a partial regulation signal 634, thereby causing power consumption in the monitoring processing device 110 to be regulated. For example, the power limit management decoder and sequencer circuit 632 can be configured to generate a series of partial regulation signals 634, thereby continuously adjusting the power consumption of the monitored processing device 110 associated with its LAM circuit 136 upwards or downwards.

[0078] Please note that a communication delay occurs in the sequence of operations and communications described above regarding the LAM circuit 136 transmitting the active power event 606 to the RAM circuit 502 and the RAM circuit 502 transmitting the aggregated active power event 138 to the PEL circuit 126. There is a delay between the generation of the active sample 600 sampling the power consumption in the processing device 110 in the LAM circuit 136 and the reporting and receiving of the associated aggregated active power event 138 in the PEL circuit 126. This delay can be particularly large for IC chips 104 with large areas, such as those comprising many PU clusters 108(0)-108(N) and other processing devices 110 in a processor-based system 100. Once PEL circuit 126 receives and processes the associated aggregated power event 138 to generate associated power limit management responses 140(1)-140(Q), the power consumed by the monitored processing device 110 may have exceeded the expected power limit in an undesirable manner and / or for an undesirable duration, potentially causing power consumption in IC chip 104 to exceed the designed power limit. Furthermore, transient current demands of the monitored processing device 110 may cause di / dt events or voltage decay events, which could lead to performance problems and / or malfunctions that PEL circuit 126 may not be able to resolve in a timely manner.

[0079] To mitigate the delay in PEL circuit 126 receiving aggregate active power events 138 associated with monitored processing devices 110 in the processor-based system 100 (which could affect power consumption regulation within the processor-based system 100), each of the LAM circuits 136, 136R can also be configured to directly regulate the performance of the associated monitored processing device 110, thereby regulating its current demands and, consequently, its power consumption. This gives PEL circuit 126 more time to receive and process aggregate active power events 138 to determine how power consumption in the processor-based system 100 should be regulated to achieve desired overall performance while keeping power consumption within desired limits. Subsequently, in this manner, LAM circuits 136, 136R can mitigate power issues more promptly by locally regulating the power consumption of their specific monitored processing device 110 at the device level (without needing to regulate the performance of other processing devices 110). LAM circuits 136, 136R can be configured to locally and continuously monitor and regulate power consumption in their monitored processing device 110, coexisting with PEL circuit 126 generating power limiting management response 140 to limit the power consumption of target device 200 in processor-based system 100.

[0080] In this regard, such as Figure 6As shown, the LAM circuit 136 in this example includes a di / dt circuit 636 to track the rate of change of power consumption of the processing device 110 for local power consumption regulation of the monitored processing device 110. In this regard, the di / dt circuit 636 may be configured to receive, in each local time window, an evaluation current demand 604 of the activity of the processing device 110 sampled by the LAM circuit 136 from the accumulator circuit 602. For each received ingress evaluation current demand 604 (e.g., for a given local time window), the di / dt circuit 636 may be configured to use one or more previously received evaluation current demands 604 received in the previous local time window for the previous evaluation current demand 604 to generate a next summed current demand 638 (from the accumulator circuit 602) of such ingress evaluation current demands 604 in the next local time window. In this way, the next summed current demand 638 is a continuous summation of the evaluation current demands 604 for the processing device 110 within consecutive local time windows. The di / dt circuit 636 can provide the next aggregate current demand 638 to the application processor 640, which in turn provides a determined next current flow rate 642 based on the next aggregate current demand 638 to the regulating FSM circuit 644. The regulating FSM circuit 644 can be configured to continuously determine whether the next current flow rate 642 of the assigned processing device 110 exceeds a threshold current flow rate or current flow rate change configured in the LAM circuit 136 for the monitored processing device 110. In response to determining that the next current flow rate 642 of the assigned processing device 110 exceeds the threshold current flow rate, the regulating FSM circuit 644 is configured to generate a local regulation signal 634 to regulate the power consumption of the monitored processing device 110.

[0081] In this manner, the LAM circuit 136 can be configured to continuously monitor the in-process current flow rate of its monitored processing device 110, thereby enabling localized adjustment of the power consumption of the monitored processing device 110. In this manner, the LAM circuit 136 can be configured to respond to power consumption issues (such as di / dt events and voltage decay) caused by the current demand of the monitored processing device 110 more quickly than the PEL circuit 126 can respond.

[0082] As an example, if the processing device 110 monitored by LAM circuit 136 is a network node 500 of an internal communication network 114, the local adjustment signal 634 generated by LAM circuit 136 may be throughput adjustment to selectively enable and disable communication flows in network node 500 to adjust its throughput, and thus adjust its power consumption. As another example, if the processing device 110 monitored by LAM circuit 136 is a PU cluster 108(0)-108(N) or other processing device 110, the local adjustment signal 634 generated by LAM circuit 136 may be performance adjustment to selectively adjust the performance or workload of the monitored PU cluster 108(0)-108(N) or other processing device 110 to adjust its performance, and thus adjust its power consumption.

[0083] Please note that the sampling of processing activity discussed herein can be accomplished by determining or sampling quantities associated with the transient activity of the monitored processing device 110. For example, the workload performed by the monitored processing device 100 can be determined or detected as an indirect method of determining transient activity that can be associated with evaluating current or power consumption. As another example, the activity of the monitored processing device 110 can be determined by sensing the temperature at a temperature sensor associated with the processing device 110. As another example, voltage decay at the processing device 110 can be sensed to determine a sample of activity. Similarly, other quantities can be used to sample activity. As an example, processing activity can be sampled using entry interrupts, status registers, interrupt queue states, or signals indicating whether the processing device is busy or idle at the processing device.

[0084] Please note that the component for performing local adjustment by means of LAM circuit 136 may also be provided in LAM circuit 136R in RAM circuit 502, so that LAM circuit 136R may also be configured to locally adjust monitored processing device 110.

[0085] Please note, Figure 1 The hierarchical power management system 124 provided in the IC chip 104 for the processor-based system 100 is not limited to Figure 6 The three (3) level hierarchical power management system 624. For example, Figure 7 It can be provided as Figures 1 to 3 and Figure 5 A schematic diagram of a tiered power management system 724 replacing the tiered power management system 124 in the processor-based system 100 of the IC chip 104. (Except for) Figure 7 The hierarchical power management system 724 in the middle does not include the intermediate RAM circuit 502. Figure 7 The hierarchical power management system 724 is similar to Figure 6The hierarchical power management system 624 is included. The LAM circuit 136 can be configured to provide active power events 606 directly to the PEL circuit 126 for processing. Figure 7 Hierarchical power management system 724 and Figures 1 to 3 and Figure 5 Common components among the hierarchical power management systems 124 are shown with the same component number and are not described again.

[0086] Similarly, as discussed herein, PEL circuit 126 is specified to receive active power event 606 from LAM circuit 136. This reception of active power event 606 may be directly from LAM circuit 136 to PEL circuit 126, or indirectly from one or more intermediate circuits (including RAM circuit 502). For example, as discussed above, active power event 606 generated by LAM circuit 136 may be indirectly reported to PEL circuit 126 as part of aggregated active power event 138 generated by RAM circuit 502 and reported to PEL circuit 126, as part of the received active power event 606.

[0087] Figure 8 This is an example Figures 1 to 3 and Figures 5 to 7 The flowchart illustrates an exemplary procedure 800 in which the LAM circuit 136 and / or RAM circuit 502 in the hierarchical power management systems 124, 624, and 724 locally monitor and regulate the power consumption of the monitored processing device 110. The procedure 800 also includes hierarchically reporting active power events 606, 138 related to the power consumption monitored by the LAM circuit 136 and / or RAM circuit 502, in order to regulate the power consumption in the processor-based system 100 in response to the received active power events 606, 138. Figure 8 The program 800 is discussed using the hierarchical power management systems 624 and 724 as examples.

[0088] In this regard, such as Figure 8 As shown, the first step in procedure 800 may be to sample the processing activity of the assigned processing device 110 among the plurality of processing devices 110 coupled to at least one of the plurality of power rails 300(1)-300(5) to generate a plurality of activity samples 600. Figure 8 (See box 802 in the original text). The next step in procedure 800 may be to determine the current flow rate 642 of the assigned processing device 110 based on multiple activity samples 600. Figure 8 (See box 804 in the document). The next step in procedure 800 may be to determine whether the current flow rate 642 of the assigned processing device 110 exceeds the defined threshold current flow rate. Figure 8(See box 806 in the original text). The next step in procedure 800 may be to adjust the processing activity of the assigned processing device 110 to regulate its power consumption in response to determining that the current flow rate 642 of the assigned processing device 110 exceeds the threshold current flow rate. Figure 8 (See box 808 in the original text). In addition to and / or parallel to steps 804-808, another step in procedure 800 may be to evaluate the power consumption of the assigned processing device 110 based on multiple active samples 600. Figure 8 (See box 810 in the original text). The next step in procedure 800 may be to generate active power events 606, 138 based on the evaluated power consumption of the assigned processing device 110. Figure 8 (See box 812 in the document). The next step in procedure 800 can be to receive multiple power events based on active power events 606, 138. Figure 8 (See box 814 in the original text). The next step in program 800 may be to generate a power limit management response 140 based on the received multiple active power events 606, 138 to regulate the power consumption in IC chip 104. Figure 8 (Box 816 in the middle).

[0089] Figure 9A This is an example Figure 6 The diagram illustrates exemplary details of the di / dt circuit 636 and the regulating FSM circuit 644 in the LAM circuit 136 shown. Such circuitry is used to collect the received evaluation current demand 604 of the processing activity of the monitored processing device 110 within a local time window and to determine whether the current flow rate and / or current flow rate variation of the monitored processing device 110 exceeds a threshold current flow rate. This information is used by the LAM circuit 136 to determine whether its monitored processing device 110 should... Figure 6 The previously discussed local adjustment is performed by the assigned LAM circuit 136.

[0090] In this regard, such as Figure 9A As shown, the di / dt circuit 636 is configured to receive the next evaluation current demand 604 generated by the LAM circuit 136 for each local time window, as... Figure 6The di / dt circuit 636, as discussed, includes multiple latching circuits 900(1)-900(4), which are clock-controlled circuits (e.g., flip-flops) and configured to store incoming next evaluation current requirements 604 and previously received evaluation current requirements 604P(1)-604P(3). Latching circuit 900(1) stores the next incoming evaluation current requirement 604. Then, the next incoming evaluation current requirement 604 stored in latching circuit 900(1) and the previously received evaluation current requirements 604P(1)-604P(3) stored in latching circuits 900(1)-900(3) are shifted to the next corresponding latching circuit 900(2)-900(4) for each newly received incoming evaluation current requirement 604 representing a local time window. For each incoming evaluation current demand 604 representing a local time window, the incoming evaluation current demand 604 and the previous evaluation current demands 604P(1)-640P(3) are provided to the corresponding summing circuits 902(1)-902(4). The summing circuits 902(1)-902(3) subtract the incoming evaluation current demand 604 from the corresponding previous evaluation current demands 604P(1)-604P(3) to generate the incoming evaluation current demand 604 and the corresponding evaluation current demands 604P(1)-604P(3) with the corresponding current flow rate (i.e., current flow rate change) di_dt_1, di_dt_2, di_dt_3 of the local time window, as discussed below. Therefore, the determined current flow rate changes di_dt_1, di_dt_2, and di_dt_3 represent the rate of change of current flow rate or current demand, and thus represent the rate of change of power consumption of the monitored processing device 110 between the local time window when it receives the current demand 604 being evaluated and the previous local time window of the corresponding previous current demand 604P(1)-604P(3). di_dt_1 is the current or current flow rate change between the corresponding current demand 604 and 604P(1). di_dt_2 is the current or current flow rate change between the corresponding current demand 604 and 604P(2). di_dt3 is the current or current flow rate change between the corresponding current demand 604 and 604P(3).

[0091] Continue to refer to Figure 9ANext, such current flow rate changes di_dt_1, di_dt_2, and di_dt_3 can be provided to the multiplexing circuit 904, which can selectively provide one of the current flow rate changes di_dt_1, di_dt_2, and di_dt_3 as the next current flow rate 642 to the comparator circuit 906 in the regulating FSM circuit 644, as discussed below. The selected current flow rate changes di_dt_1, di_dt_2, and di_dt_3 provided to the multiplexing circuit 904 as the next current flow rate 642 can be based on the local time window selection signal sel_di_dt_window to select the local time window to be compared with each current flow rate. This gives the di / dt circuit 636 the flexibility to be programmed to select the local time window to be compared with the evaluation current demand 604P(1) and 604P(2) entering the evaluation current demand 604. For example, Figure 9B This is an example of... Figure 9A The exemplary input and evaluation current requirements 604, 604P(1)-604P(3) collected by the di / dt circuit 636 in the diagram 920 are plotted as varying with local time windows, showing how the input and evaluation current requirements 604 and 604P(1)-604P(3) can be subtracted to generate the input evaluation current requirement 604 and the evaluation current requirement 604P(1)-604P(3) with respect to the corresponding current flow rate changes di_dt_1, di_dt_2, di_dt_3 of their respective local time windows twN, twN-1, twN-2, twN-3. The duration of the local time window is known. Therefore, the current flow rate changes di_dt_1, di_dt_2, and di_dt_3 represent the changes in current demand that occur between the current demand 604 entering the current evaluation window and the corresponding previously evaluated current demand 604P(1)-604P(3) due to the difference in their local time windows. Current flow rate curve 922 represents the current flow rate of the processing device 110 during the local time windows twN-3, twN-2, twN-1, and twN. For example... Figure 9B As shown, the slope of the current flow rate curve 922 at each of the local time windows twN-3, twN-2, twN-1, and twN changes based on the changes in current demand or current flow rate demand of the processing device 110 between the local time windows twN-3, twN-2, twN-1, and twN. Figure 9B show Figure 9AThe di / dt circuit 636 in the middle is used to generate the current flow rate variations di_dt_1, di_dt_2, di_dt_3, which represent the changes in current demand that occur in the current window entering the evaluation current demand 604 and the corresponding previously evaluated current demands 604P(1)-604P(3) as their local time windows twN-3, twN-2, twN-1, and twN differ. This can be used to provide the current flow rate 642 of the processing device 110 for determining local power consumption regulation.

[0092] The selected next current flow rate 642 is provided by the di / dt circuit 636 to the comparator circuit 906 in the regulating FSM circuit 644. The regulating FSM circuit 644 can be configured to generate a local adjustment signal 634 based on whether the selected next current flow rate 642 (based on the selection of current flow rate changes di_dt_1, di_dt_2, di_dt_3) exceeds a threshold current flow rate (which may include threshold current flow rate changes) for the monitored processing device 110, thereby regulating the power consumption of the monitored processing device 110. The threshold current flow rate for the monitored processing device 110 can be obtained from the current flow rate register 908. The current flow rate register 908 can be programmed using the threshold current flow rate of the monitored processing device 110. For example, the current flow rate register 908 can be programmed with different threshold current flow rates (e.g., lowest level, level 1, level 2, highest level), so that the comparator circuit 906 can generate a local adjustment signal 634 for power consumption adjustment at different levels based on a comparison between the selected next current flow rate 642 (based on the selection of current flow rate changes di_dt_1, di_dt_2, di_dt_3) and the threshold current flow rate obtained from the current flow rate register 908.

[0093] Please note that when discussing current velocity in this article, it also means current flow and represents current (I) (e.g., the transfer of charge (q) over time (t) (q / t)) or the change in current velocity (e.g., the change in current over time (di / dt)). A given change in current velocity (di / dt) is determined based on a given current velocity (I / t).

[0094] The above Figures 1 to 3 and Figures 5 to 7 The components in the hierarchical power management systems 124, 624, and 724 can be provided in different specific implementations. For example, Figure 10 It can be Figures 1 to 3 and Figures 5 to 7 A logic diagram of another exemplary LAM circuit 1000 provided in any LAM circuit of LAM circuit 126 in the hierarchical power management systems 124, 624, and 724. Figure 10 PEL circuit 1026 and Figures 1 to 3 and Figures 5 to 7 Common components among the PEL circuits 126 in the hierarchical power management systems 124, 624, and 724 are shown with the same component number.

[0095] In the above Figures 1 to 3 and Figures 5 to 7 Another example of components in the hierarchical power management systems 124, 624, and 724, Figure 10 The PEL circuit 1026 is configured to receive aggregated active power events 138(1)-138(5) from one or more RAM circuits 502. The PEL circuit 1026 may be... Figures 1 to 3 and Figures 5 to 7 The PEL circuit 126 provided in the hierarchical power management systems 124, 624, and 724 is shown in this example. In this example, the PEL circuit 126 includes a decoding circuit 610 configured to decode received aggregated active power events 138(1)-138(5) into corresponding activity tracker circuits 612(1)-612(T), as previously described. The PEL circuit 1026 in this example also includes energy tracker circuits 1000(1)-1000(E) associated with energy power events 1002, such as PMIC telemetry power event 1002(1), temperature event 1002(2), and voltage decay detection event 1002(3) (all of which are examples of inactive power events), which can also influence the PEL circuit 126 to determine how to regulate power. The PEL circuit 1026 in this example also includes maximum average power (MAP) tracker circuits 1004(1)-1004(B), which are circuit trackers that track the total power consumed in the SoC 120 according to a defined maximum power consumption limit. Similar to the activity tracker circuits 612(1)-612(T), the energy tracker circuits 1000(1)-1000(E) and the MAP tracker circuits 1004(1)-1004(B) are configured to track corresponding energy power events 1002(1)-1002(3) and / or aggregate activity power events 138(1)-138(5) to determine whether there is a factor that depends on the power consumption exceeding a defined power (e.g., current) threshold / limit.

[0096] Each of the energy tracker circuits 1000(1)-1000(E) may include a corresponding data aggregator circuit 1016(1)-1016(E) configured to aggregate received energy power events 1002 into corresponding aggregated energy power events 1018(1)-1018(E). Each of the activity tracker circuits 1000(1)-1000(E) may also include a corresponding data aggregator circuit 1020(1)-1020(T) configured to aggregate received energy power events into corresponding aggregated energy power events 1022(1)-1022(T). Each of the MAP tracker circuits 1004(1)-1004(B) may also include a corresponding data aggregator circuit 1024(1)-1024(T) configured to aggregate received energy power events into corresponding aggregated MAP power events 1027(1)-1027(T). In this example, the energy tracker circuits 1000(1)-1000(E), the activity tracker circuits 612(1)-612(T), and the MAP tracker circuits 1004(1)-1004(B) each include a corresponding energy power limitation management strategy circuit 1006, an activity power limitation management strategy circuit 1008, and a MAP power limitation management strategy circuit 1010, which are configured to generate corresponding energy power adjustment recommendations 1012, activity power adjustment recommendations 614, and MAP power adjustment recommendations 1014. Such generated corresponding energy power adjustment recommendations 1012, activity power adjustment recommendations 614, and MAP power adjustment recommendations 1014 can be based on corresponding received aggregated energy power events 1018(1)-1018(E), aggregated activity power events 1022(1)-1022(T), and aggregated MAP power events 1027(1)-1027(B) for processing by the PEL circuit 126 to determine how to adjust the power consumption in the IC chip 104.

[0097] Continue to refer to Figure 10The energy tracker circuit 1000(1)-1000(E), the activity tracker circuit 612(1)-612(T) and the MAP tracker circuit 1004(1)-1004(B) are configured to compare the power consumption indicated by the corresponding aggregated energy power event 1018(1)-1018(E), aggregated activity power event 1022(1)-1022(T) and aggregated MAP power event 1027(1)-1027(B) with the corresponding energy power limit management strategy circuit 1006, activity power limit management strategy circuit 1008 and MAP power limit management strategy circuit 1010, the energy tracker circuit 1000(1)-1000(E), the activity tracker circuit 612(1)-612(T) and the MAP tracker circuit 1004(1)-1004(B). Next, the energy tracker circuits 1000(1)-1000(E), the activity tracker circuits 612(1)-612(T) and the MAP tracker circuits 1004(1)-1004(B) can be configured to generate corresponding energy power regulation recommendations 1012, activity power regulation recommendations 614 and MAP power regulation recommendations 1014 based on the power consumption indicated by the corresponding aggregated power events 1018(1)-1018(E), 1022(1)-1022(T) and 1027(1)-1027(B) and the comparison with the corresponding power limit management strategy circuits 1006, 1008 and 1010. For example, the energy power limit management strategy circuit 1006, the activity power limit management strategy circuit 1008, and the MAP limit management strategy circuit 1010 may each have a corresponding critical power limit, which is compared with the corresponding aggregated power events 1018(1)-1018(E), 1022(1)-1022(T), and 1027(1)-1027(B) to determine the corresponding power regulation recommendations 1012, 614, and 1014.

[0098] Continue to refer to Figure 10The PEL circuit 1026 also includes a merging circuit 616 that merges the energy power regulation recommendation 1012, the corresponding active power regulation recommendation 614, and the MAP power regulation recommendation 1014 into merged power regulation recommendations 618(1)-618(6). The merged power regulation recommendations 618(1)-618(6) are provided to the corresponding assigned target circuits 620(1)-620(6). Note that each merged power regulation recommendation 618(1)-618(6) may be affected by each power regulation recommendation from the energy power regulation recommendation 1012, the corresponding active power regulation recommendation 614, and the MAP power regulation recommendation 1014. Each target circuit 620(1)-620(6) is associated with a different target device 200 in the processor-based system 100, wherein the PEL circuit 1026 may issue power limiting management responses 140(1)-140(6) to limit the power consumption of this target device 200.

[0099] The target device 200 may include interface circuits 127(1)-127(Z) which may be regulated by a power limiting management response 140(1) transmitted to RAM circuit 502(6) and / or LAM circuit 136(6) (such circuits are configured to regulate power consumption in such interface circuits 127(1)-127(Z)). The target device 200 may include PU clusters 108(0)-108(N) which may be regulated by a power limiting management response 140(2) transmitted to RAM circuit 502(1) and / or LAM circuit 136(1) (such circuits are configured to regulate power consumption in such PU clusters 108(0)-108(N)). The target device 200 may include an internal communication network 114, which may be regulated by a power limiting management response 140(3) transmitted to RAM circuitry 502(3) and / or LAM circuitry 136(3) (such circuitry is configured to regulate power consumption in such internal communication network 114). The target device 200 may include memory controllers 118(0)-118(M), which may be regulated by a power limiting management response 140(4) transmitted to RAM circuitry 502(2) and / or LAM circuitry 136(2) (such circuitry is configured to regulate power consumption in such memory controllers 118(0)-118(M)). The target device 200 may include I / O interface circuitry 120(0)-120(X), which may be regulated by a power limiting management response 140(5) transmitted to RAM circuitry 502(4) and / or LAM circuitry 136(4) (such circuitry is configured to regulate power consumption in such I / O interface circuitry 120(0)-120(X)). The target device 200 may include S2S interface circuitry 122(0)-122(Y), which may be regulated by a power limiting management response 140(6) transmitted to RAM circuitry 502(5) and / or LAM circuitry 136(5) (such circuitry is configured to regulate power consumption in such S2S interface circuitry 122(0)-122(Y)).

[0100] The merging circuit 616 in the PEL circuit 1026 can be programmed to map (e.g., via firmware, electronic fuses, etc.) the merged power regulation recommendations 618(1)-618(6) to a specific target device 200, and thus to target circuits 620(1)-620(6), which may not be directly associated with each other. In this way, the merged power regulation recommendations 618(1)-618(6) related to power issues and power consumption in the IC chip 104 can be mapped in the PEL circuit 1026 to be associated with different target devices 200 for power consumption regulation. The merging circuit 616 can be programmed as a "many-to-many mapping" to be associated with different power limit management responses within the IC chip 104 in a desired manner, thereby providing greater flexibility in managing power consumption in the IC chip 104 while still achieving the desired performance. In this way, the power regulation management behavior of the PEL circuit 1026 can be configured and changed even after the IC chip 104 has been deployed in the application.

[0101] Continue to refer to Figure 10 Each of the target circuits 620(1)-620(6) can be configured to determine whether the power consumption of the associated target device 200 in the processor-based system 100 should be adjusted based on the combined power adjustment recommendation 618(1)-618(6) provided to the target circuits 620(1)-620(6). Each of the target circuits 620(1)-620(6) can be configured to analyze the corresponding received combined power adjustment recommendation 618(1)-618(6) to determine whether the power consumption of the associated target device 200 should be adjusted. If the target circuits 620(1)-620(Q) determine that the power consumption of the associated target device 200 in the processor-based system 100 should be adjusted, the target circuits 620(1)-620(Q) cause the generation of associated power limit management responses 140(1)-140(6) and communicate them to the corresponding RAM circuits 502(1)-502(6) and / or LAM circuits 136(1)-136(6) such that the power consumption of the target device 200 associated with the power limit management response 140(1)-140(Q) is limited.

[0102] Such as the above Figures 1 to 3 and Figures 5 to 7 The components in the hierarchical power management systems 124, 624, and 724 can be provided in different specific implementations. For example, Figure 11 It can be Figures 1 to 3 and Figures 5 to 7 A logic diagram of another exemplary regulation management circuit 1100 that is an alternative to the regulation FSM circuit 644 provided in the hierarchical power management systems 124, 624, 724. Figure 11 The regulation and management circuit 1100 in the middle and Figures 1 to 3 and Figures 5 to 7 Common components among the regulating FSM circuits 644 in the hierarchical power management systems 124, 624, and 724 are shown with the same component number.

[0103] Figure 11 The display adjustment management circuit 1100 is configured to receive an adjustment request 1102 from at least one status detection circuit 1104 and generate an adjustment control signal 1106. The adjustment control signal can selectively adjust according to... Figure 1 The activity of the monitored processing device 110 in the processor-based system 100 of the integrated circuit (IC) chip 104. In the example, the regulation management circuit 1100 may be configured to generate regulation control signals to selectively regulate Figure 2 The activity of the monitored processing device 110 in one of the LAM circuits 136 in the LAM circuit. That is, one or more LAM circuits in LAM circuit 136 may include regulation management circuitry 1100. Based on one or more measurements of the state of the processor-based system 100 detected or sensed by at least one state detection circuit 1104, regulation management circuitry 1100 may regulate (e.g., selectively reduce within a configurable range) the activity of the monitored processing device 110 (the one or more measured states are at least partially dependent on this). While this disclosure presents an example of the disclosed regulation management circuitry included in one or more LAM circuits, this disclosure is not limited thereto. Rather, any IC chip including a processor-based system (which includes processing circuitry that operates in response to a clock signal) may include management circuitry, such as the regulation management circuitry 1100 according to this disclosure.

[0104] Activities in the monitored processing device 110 (e.g., circuit switching) can have a variety of direct and indirect effects, which can lead to performance degradation and / or even potentially physical damage to the processor-based system 100. Certain measurement states that may be caused by such activities (e.g., in the LAM circuit 136) may include, for example, peak power consumption, average power consumption, peak voltage, average voltage, peak current, average current, rate of change of current or voltage, temperature, and firmware-measurable activities. In response to a measurement of one or more of these states, the regulation management circuit 1100 may react dynamically at a local level to avoid or mitigate any negative impact from the measurement state. For example, the regulation management circuit 1100 may react dynamically at a local level without waiting for the delay of a reaction through the hierarchy of the power management system 124 (e.g., through RAM circuit 502 and PEL circuit 126). Specifically, the regulation management circuit 1100 may modify the regulation control signal 1106 (which may be a local regulation signal 634) to affect the activity within a local time window or immediately (e.g., in the next cycle of the clock signal CLK).

[0105] A clock signal CLK is used to trigger switching in the regulation and management circuit 1100 and in the monitored processing device 110 and other circuits. In some examples, the clock signal CLK may be a clock signal 508 that clocks the PU clusters 108(1)-108(N) and / or a clock signal 512 that clocks the network node 500 (as discussed above).

[0106] In this regard, adjustment requests 1102 can be received from multiple state detection circuits 1104, each requesting a change in the activity of the monitored processing device 110. At least one state detection circuit 1104 can measure different states among those described above or other states not explicitly mentioned herein, and additionally or alternatively, can measure the same state (e.g., temperature) at different locations. Adjustment requests 1102 are received in an adjustment request merging circuit 1108, which generates an adjustment recommendation 1110 based on at least one adjustment request 1102. An adjustment recommendation 1110 can be generated in each cycle when at least one adjustment request 1102 is received from at least one state detection circuit 1104. However, there may be certain cycles of the clock signal CLK in which no adjustment request 1102 is received in the adjustment request merging circuit 1108. In such cycles, no adjustment recommendation 1110 is generated.

[0107] In some examples, regulation requests 1102 can be provided from hierarchical logic to locally regulate the circuitry. For example, regulation management circuitry may be included in one of the LAM circuits within LAM circuitry 136, such as... Figure 5 As shown, it is a subset of the LAM circuit 136 coupled to one of the RAM circuits in RAM circuit 502(3) and can receive adjustment requests 1102 from RAM circuit 502(3). Further note that the various sources of adjustment requests 1102 may be asynchronous, so adjustment requests 1102 may be received randomly and may only be received occasionally from any of the sources (e.g., status detection circuit 1104).

[0108] The regulation management circuit 1100 may also include a distribution circuit 1124 (which will be explained more fully below) that transmits the regulation suggestion 1110 as one of a plurality of decoded regulation suggestions 1126(1)-1126(X).

[0109] The regulation management circuit 1100 includes a plurality of regulation suggestion registers (“TR registers”) 1112(1)-1112(X), each of which is configured to receive, in one cycle of the clock signal CLK, a decoded regulation suggestion 1126(1)-1126(X) generated in the regulation request merging circuit 1108 and forwarded by the distribution circuit 1124. Each of the TR registers 1112(1)-1112(X) stores at least a portion of a corresponding regulation suggestion 1126(1)-1126(X) in multiple (X) consecutive cycles of the clock signal CLK. The adjustment suggestion registers 1112(1)-1112(X) can receive adjustment suggestions 1126(1)-1126(X) in turn or in a cyclical order, wherein the first adjustment suggestion 1126(1) is received in the first TR register 1112(1) of the plurality of TR registers in the first cycle of the clock signal CLK, the second adjustment suggestion 1126(2) can be received in the second TR register 1112(2) of the plurality of TR registers in the next cycle of the clock signal CLK, and so on. Alternatively, since, as noted above, the adjustment request merging circuit 1108 may not receive any adjustment request 1102 and generate adjustment suggestion 1110 in every cycle, there may be some cycles of the clock signal CLK in which no new adjustment suggestion 1110 is loaded into any TR register 1112(1)-1112(X). In the example where regulation suggestion 1126(X) is stored in TR register 1112(X), the distribution circuit 1124 will return to the starting point in the next cycle and send the next regulation suggestion 1110 from the regulation merging request circuit 1108 as regulation suggestion 1126(1), which will be received in TR register 1112(1).

[0110] TR register 1112 is, for example, a shift register that shifts out one bit of adjustment proposals 1126(1)-1126(X) per cycle. As an example, the first TR register 1112(1) continues to store at least a portion of the first adjustment proposal 1126(1) over the plurality of (X) cycles, the number corresponding to the number of bits (X) in the adjustment proposal 1126(1) as further explained below. After the plurality of (X) cycles, the last bit of the adjustment proposal 1126(1) is shifted out. In the next cycle, a new adjustment proposal 1126(1) is received and stored in the first TR register 1112(1); or if adjustment request 1102 is not received in adjustment request merging circuit 1108, adjustment proposal 1110 may or may not be generated. For example, adjustment proposal 1110 may be indicated, for example, by a valid signal (not shown). If adjustment suggestion 1110 is not generated, corresponding adjustment suggestions 1126(1)-1126(X) may not be provided to TR register 1112(1). Therefore, one or more TR registers in TR registers 1112(1)-1112(X) may contain only zeros "0", which have been shifted to the leftmost bit, and will not cause any reduction in activity. If adjustment request 1102 is not received within X consecutive cycles of the clock signal CLK, all TR registers will be empty and no adjustment will occur.

[0111] If at least one adjustment request 1102 is received in each cycle, the multiple TR registers 1112(1)-1112(X) will each store a different number of bits of the adjustment proposal 1126(1)-1126(X). The following is based on... Figures 13A to 13C The example description in [the document] provides further details on the operation adjustment suggestion register 112.

[0112] Return to reference Figure 11 The regulation management circuit 1100 also includes a regulation suggestion aggregation circuit 1114 (“TR aggregation circuit 1114”), which generates a regulation result 1116 based on regulation suggestions 1126(1)-1126(X). In this regard, the regulation result 1116 is an aggregation of all the regulation suggestions 1110 from the previous X cycles. In some examples, the X cycles may correspond to a local time window of the LAM circuit 136. In some examples, as referenced... Figures 13A to 13C To explain further in detail, the adjustment suggestion aggregation circuit 1114 can generate the adjustment result 1116 by performing a logical OR operation on specific bit positions of each adjustment suggestion register in the adjustment suggestion registers 1112(1)-1112(X). However, other methods can also be used in the adjustment suggestion aggregation circuit 1114 to aggregate the adjustment suggestions 1126(1)-1126(X) from the previous X cycles.

[0113] The regulation management circuit 1100 also includes a regulation control circuit 1118 that receives a regulation result 1116 (e.g., in each cycle of the clock signal CLK) and generates a regulation control signal 1106 to selectively regulate activity in the monitored processing device 110. In some examples, the regulation control circuit 1118 may generate the regulation control signal 1106 (e.g., only) from the regulation result 1116. In some examples, in addition to receiving the regulation result 1116 from the regulation suggestion aggregation circuit 1114 in each cycle of the clock signal CLK, the regulation control circuit 1118 may also receive the most recently generated regulation suggestion from the regulation suggestion 1110 generated in the regulation request merging circuit 1108, or from the regulation suggestions 1126(1)-1126(X) from the distribution circuit 1124. In such an example, the regulation control circuit 1118 can generate the regulation control signal 1106 based on the regulation result 1116 received in the current cycle and the regulation proposals 1126(1)-1126(X) received in any of the X previous cycles of the clock signal CLK. In an example where no regulation request is received within X consecutive cycles, all TR registers 1112(1)-1112(X) will contain 0 (zero), the regulation result 1116 will be "0", and thus the regulation control signal 1106 will not request regulation. For a more detailed description, see the following reference. Figure 11 For operation of the provided regulation and management circuit 1100, please refer to the following: Figure 12 A detailed description of the status detection circuit 1200 is provided.

[0114] Figure 12 This is a logic diagram of the state detection circuit 1200, which generates adjustment requests at the frequency of each cycle in the clock signal CLK to dynamically respond to state changes caused by activity in the processing circuit 110. The state detection circuit 1200 is... Figure 11 An example of the state detection circuit 1104. The state detection circuit 1200 can be... Figure 6 An alternative circuit to the di / dt circuit 636 in the system 100, which is used to track the rate of change of current. In this example, measurement 1202 is an indication of current flow in the system 100 based on the activity of the monitored processing device 110 in the LAM circuit 136. In some examples, measurement 1202 is a measurement of the current supplied to the monitored processing device 110. Measurement 1202 may be provided by the state detection circuit 1200 at a frequency of, for example, per cycle of the clock signal CLK. Figure 6 The accumulator circuit 602 in the middle performs sampling. In some examples, the current flow measurement 1202 can be... Figure 6 The total current requirement is 604.

[0115] In each cycle of the clock signal CLK, the state detection circuit 1104 may receive measurement 1202 and store measurement 1202 in the first entry 1204(1) of a plurality of entries 1204(1)-1204(X) of the shift register 1206, which may be any suitable type of storage circuit. Entries 1204(1)-1204(X) store or contain measurements 1208(1)-1208(X), which are measurements 1202 received in X previous cycles of the clock signal CLK. In response to the clock signal CLK (e.g., its rising or falling edge), measurement 1202 is stored in the first entry 1204(1). Furthermore, in response to the clock signal CLK, measurement 1208(1) (e.g., measurement 1202 received in the immediately preceding cycle) is shifted in the direction toward the last entry 1204(X) into entry 1204(2). Similarly, measurement 1208(2) is shifted from the second entry 1204(2) to the third entry 1204(3), measurement 1208(X-1) is shifted from the entry 1204(X-1) to the entry 1204(X), and measurement 1208(X) is shifted out of shift register 1206.

[0116] Determining the rate of change of current involves generating measurements 1202 and 1210 of measurements 1208(1)-1208(X-1), corresponding to a first window 1212 over X periods, and generating measurements 1208(1)-1208(X) of measurements 1208(1)-1208(X), corresponding to a second window 1216 over X periods. Window 1216 overlaps with window 1212 over X-1 periods, and the first and 1210 are compared with the second and 1214. The number X and the number of overlapping periods of windows 1212 and 1216 can be programmable.

[0117] In this example (where X=8), the first and 1210 and the second and 1214 are determined (summed) in summing circuits SUM1 and SUM2, respectively. Therefore, the first and 1210 determined in summing circuit SUM1 are the sum of the measurements 1202 received in the current cycle and the measurements 1208(1)-1208(7) of the states stored in all (except the last entry 1204(8)) of entries 1204(1)-1204(7) in shift register 1206. The second and 1214 determined in summing circuit SUM2 are the sum of measurements 1208(1)-1208(8) in entries 1204(1)-1204(8) of shift register. The first and 1210 and the second and 1214 are based on X-1 overlapping cycles, which are compared in each cycle. In this regard, the state detection circuit 1104 can dynamically respond to single-cycle changes in current and enable the regulation management circuit 1100 to respond in the next cycle.

[0118] In the above example, the number of cycles in windows 1212 and 1216 is equal to the number X of entries 1204(1)-1204(X). In some examples, the number W of cycles in windows 1212 and 1216 can be configurable up to a maximum of X. In other words, although there are X entries 1204(1)-1204(X) in register 1206, the first and 1210 can be the sum of measurements 1202 and 1208(1)-1208(M-1), and the second and 1214 can be the sum of measurements 1208(1)-1208(M), where the number M is configurable up to X.

[0119] The state detection circuit 1104 may include an adjustment request generation circuit 1218 that compares a first sum of 1210 with a second sum of 1214 and generates an adjustment request 1220 based on the first sum of 1210 and the second sum of 1214. In some examples, the adjustment request generation circuit 1218 generates the adjustment request 1220 based on the difference between the first sum of 1210 and the second sum of 1214. In some examples, additionally or alternatively, the request 1220 is based on the magnitude of the first sum of 1210 and the second sum of 1214. In this example, performing the comparison of the first sum of 1210 with the second sum of 1214 includes determining a difference 1222 between the first sum of 1210 and the second sum of 1214 by subtraction in the adjustment request generation circuit 1218, and generating the adjustment request 1220 based on this difference 1222. In this regard, the adjustment request 1220 may increase in response to the difference 1222 being a large positive number indicating a significant increase in current. In such examples, an increase in adjustment request 1220 corresponds to a request to reduce activity in the monitored processing device 110. In some examples, if the difference 1222 is a positive number exceeding a first threshold, the adjustment request may increase incrementally. A difference 1222 exceeding a second threshold may result in a larger increase. The thresholds may be configurable. In another example, if the second and 1214 are greater than the first and 1210, resulting in a negative difference 1222, the threshold request 1220 may decrease.

[0120] The adjustment request 1220 can be increased or decreased because the adjustment request 1220 generated in each of at least one state detection circuit (such as state detection circuit 1200) includes an adjustment value having one of a plurality of (V) adjustment values ​​within a range including more than two adjustment values ​​(which may be, for example, four, eight, or more). Although not shown, for example, a LAM circuit (such as LAM circuit 136) may include adjustment value range configuration circuitry for configuring the adjustment value range. Figure 11 The number of V adjustment values ​​within the adjustment value range generated in each of the at least one state detection circuit 1104 in the adjustment request 1220.

[0121] As an example, in response to determining that the current is decreasing and / or decreasing at a rate exceeding a rate threshold, or in response to determining that both the first and 1210 and the second and 1214 are below the rate threshold, a lower value in the range of adjustment values ​​can be generated to generate an adjustment request 1220. For example, if the number of adjustment values ​​V in the range of adjustment values ​​is eight (8), the adjustment request 1220 can be indicated as any of 0 / 8, 1 / 8, 2 / 8, and 7 / 8, where 0 / 8 does not request any reduction or adjustment of the activity in the monitored processing device 110, and 7 / 8 is the strongest or most restrictive request to reduce or stop the activity in the monitored processing device 110. The adjustment request 1220 can be a request to restrict the activity in the monitored processing device 110 in the first number of cycles in the second number of cycles. In the example above, the adjustment request 2 / 8 requests that the activity in the monitored processing device 110 be paused for two (2) cycles within a local time window of eight (8) cycles of the clock signal CLK. In some examples, such as when there is little or no activity in the processing circuit 110, a valid adjustment request 1220 may not be generated.

[0122] Figure 12 The state detection circuit 1200 in the circuit is designed to detect the rate of change of current (e.g., current flow or current level) and whether this change exceeds a threshold, but Figure 11 The state detection circuit 1104 can be used to detect other states, such as voltage, peak power, peak current, average voltage, average current, average power, temperature, or changes in activity that can be measured by an activity measurement algorithm that can be implemented in firmware (e.g., circuitry implementing instructions in an algorithm). In such an alternative example, measurement 1202 would be a measurement of this state.

[0123] Return to reference Figure 11 The above example of adjustment request 1220 with eight (8) adjustment value ranges is used to provide for the state detection circuit 1104 (which may be Figure 12 A more detailed description of the state detection circuit 1200 in the circuit.

[0124] As pointed out above, Figure 11 The adjustment request merging circuit 1108 receives an adjustment request 1102 from one of the state detection circuits 1104 (which may be...) Figure 12 The adjustment request 1220 in the document is used as the first adjustment request 1102. See reference [link / reference]. Figure 12As described, the state detection circuit 1200 generates an adjustment request 1220 in each cycle of the clock signal CLK, enabling a dynamic response to changes in the measured state of the LAM circuit 136 within a single cycle of the clock signal CLK. In some examples, the adjustment request merging circuit 1108 also receives a second adjustment request 1120 from the second state detection circuit 1122 and may receive the second adjustment request 1120 at a lower frequency than each cycle of the clock signal CLK. In this regard, while the state detection circuit 1200 may generate an adjustment request 1102 per cycle, another type of state detection circuit 1104 (e.g., the second state detection circuit 1122) may generate the second adjustment request 1120 only under certain conditions or at a lower frequency. Such conditions may include exceeding a threshold or an event detected by the second state detection circuit 1122. In some examples, adjustment requests may be received periodically (e.g., every 4 or 8 cycles) or randomly.

[0125] During the period when the second adjustment request 1120 is received from the second state detection circuit 1122, the adjustment request merging circuit 1108 generates an adjustment suggestion 1110 based on both the first adjustment request 1102 and the second adjustment request 1120.

[0126] In each cycle of the clock signal CLK where the second adjustment request 1120 is not received from the second state detection circuit 1122, the adjustment request merging circuit 1108 may generate an adjustment suggestion 1110 based solely on the first adjustment request 1102 from the first state detection circuit 1104. In some examples, in addition to receiving the adjustment request 1102 from the first state detection circuit 1104, multiple state detection circuits (not shown) also provide adjustment requests 1102 in each cycle of the clock signal CLK. In such examples, the adjustment request merging circuit 1108 may generate adjustment suggestions 1126(1)-1126(X) based on the first adjustment request 1102 from the first state detection circuit 1104 and other adjustment requests received in the same cycle.

[0127] In other examples, in addition to the first adjustment request 1102 from the first state detection circuit 1104, the adjustment request merging circuit 1108 may also generate an adjustment suggestion 1110 based on the last (e.g., most recently received) second adjustment request 1120 from the second state detection circuit 1122. In such examples, the adjustment request merging circuit 1108 may include circuitry for storing the last received second adjustment request 1120 and generating the adjustment suggestion 1110 based on the last stored adjustment value of the second adjustment request 1120 and / or other adjustment requests not received in each cycle. The adjustment request merging circuit 1108 may determine whether adjustment request 1102 or second adjustment request 1120 is received in a given cycle based, for example, a valid signal (not shown) activated during the cycle in which adjustment request 1102 is provided.

[0128] Further reference Figure 12 The above discussion focused on an example of a regulation request 1220 with eight (8) possible values. As is known in the art, eight possible values ​​can be encoded using three binary signals (bits). Therefore, regulation request 1220 and Figure 11 The first adjustment request 1102 and the second adjustment request 1120 can be received as three-bit binary values ​​(e.g., from "000" to "111"). The adjustment suggestion 1110 generated by the adjustment request merging circuit 1108 can have the same granularity level as the adjustment request 1102 (e.g., range of values), and therefore can also be represented by the same number of bits (e.g., 3 in this case). In other words, the adjustment suggestion 1110 is generated with a number of V possible values. However, the adjustment suggestion 1110 generated in each cycle is stored in the adjustment suggestion registers 1112(1)-1112(X) in a decoded form including V bits, where a number of bits set to "1" correspond to the value of the adjustment suggestion 1110, as explained below. In this regard, the distribution circuit 1124 is configured such that the self-adjustment request merging circuit 1108 receives the adjustment suggestion 1110, decodes the adjustment suggestion 1110, and stores the adjustment suggestion 1110 (e.g., in decoded format) in the appropriate adjustment suggestion register in the adjustment suggestion registers 1112(1)-1112(X).

[0129] In operation, the V possible values ​​(e.g., 0 / 8, 1 / 8, ..., 7 / 8) in the adjustment recommendation 1110 are interpreted in the adjustment management circuit 1100 as the ratio of inactive cycles to active cycles of the monitored processing device 110. In other words, the adjustment recommendation is a recommendation for the number of “inactive cycles” out of a total of V cycles within a local time window (e.g., V cycles). Various methods are possible for allocating “inactive cycles” within the V cycles of the local time window. For example, the adjustment recommendation 1110 with the value “4 / 8” (indicating 4 inactive cycles out of 8 cycles) can be implemented as alternating between active and inactive every other cycle within the local time window. Alternatively, the “4 / 8” adjustment recommendation can be implemented as repeatedly alternating between two consecutive active cycles and two consecutive inactive cycles. In the alternative adopted herein, the adjustment recommendation is implemented using the number of inactive cycles followed by the number of active cycles. In other words, in the example of a "4 / 8" adjustment suggestion, adjustment suggestion 1110 will remain inactive for four cycles followed by four active cycles for the monitored processing circuit 110. Therefore, in this example, the coded adjustment suggestion 1110, provided to the allocation circuit 1124 in binary form of "011", is decoded and provided as V bit values ​​of "00001111" to the adjustment suggestion registers 1112(1)-1112(X), where each bit corresponds to a cycle in the clock signal CLK. In this example, the bits in the decoded adjustment suggestion 1110 correspond from right to left to the cycles in time order. Each bit in the multi-bit value is a suggestion of "inactivity" ("1") or "activity" ("0") for the corresponding cycle out of V (e.g., eight) cycles.

[0130] The distribution circuit 1124 decodes the adjustment suggestion 1110 and stores it in decoded form in the appropriate adjustment suggestion registers of the adjustment suggestion registers 1112(1)-1112(X) in a sequential order, as discussed above. The sequence of storing the adjustment suggestion 1110 in the adjustment suggestion registers 1112(1)-1112(X) is... Figures 13A to 13C The example shown further explains this. Figures 13A to 13C In the example shown, at least one adjustment request 1102 is received from one or more state detection circuits in state detection circuit 1104 in each cycle.

[0131] Adjustment suggestion registers 1300(1)-1300(8) are related to Figure 11The example is consistent with the example of adjustment suggestion register 1112, where adjustment request 1102 has a range of V=8 possible adjustment values, which results in adjustment suggestion 1110 having eight possible values, which further results in adjustment suggestion registers 1300(1)-1300(8) each being used to store eight bits of adjustment suggestion 1110 in decoded form. As explained below, the number (8) of adjustment suggestion registers 1300(1)-1300(8) in this example is equal to the number of bits in adjustment suggestion registers 1112(1)-1112(X). The adjustment suggestion aggregation circuit 1306 is Figure 11 Example of adjustment suggestion for aggregation circuit 1114.

[0132] Figures 13A to 13C The contents of adjustment suggestion registers 1300(1)-1300(X) are illustrated in the example where X=8, during consecutive cycles of the clock signal CLK. For simplicity, the term "adjustment suggestion register" may be abbreviated as "TR register" in this example. In this example, each TR register in TR registers 1300(1)-1300(8) operates as a shift register, where each bit in the 8-bit adjustment suggestion 1302(1)-1302(8) is shifted one bit position in a first direction (e.g., to the right) during each cycle of the clock signal CLK. Adjustment suggestions 1302(1)-1302(8) are... Figure 11 The adjustment suggestions are 1126(1)-1126(8). The right-hand bits 1304(1)-1304(8) of the TR registers 1300(1)-1300(8) are provided to the adjustment suggestion aggregation circuit 1306, which corresponds to the adjustment suggestion aggregation circuit 1114. The adjustment suggestion aggregation circuit 1306 generates the corresponding adjustment suggestion suggestions. Figure 1 The adjustment result 1310 is the adjustment result of adjustment result 1116. In this example, adjustment result 1310 is based on the right-hand bits 1304(1)-1304(8) of each of the adjustment suggestion registers 1300(1)-1300(8). In some examples, adjustment suggestion aggregation circuit 1114 is implemented as a logic OR circuit that outputs "1" if any of the right-hand bits 1304(1)-1304(8) is "1".

[0133] In each cycle, the right-hand bits 1304(1)-1304(8) are shifted out and discarded. Similarly, in each cycle of the clock signal CLK, the distribution circuit 1124 provides the most recently generated adjustment proposal from adjustment proposals 1302(1)-1302(8) in decoded form to the appropriate TR register in TR registers 1300(1)-1300(8), while the other (7) registers (i.e., registers containing at least two bits) shift their stored adjustment proposals 1302(1)-1302(8) to the right. Thus, in any given cycle of the clock signal CLK, TR registers 1300(1)-1300(8) will have 8, 7, 6, 5, 4, 3, 2, and 1 remaining bits of adjustment proposals 1302(1)-1302(8), respectively, but not necessarily in this order.

[0134] Figure 13A This shows the states of TR registers 1300(1)-1300(3) and 1300(8) in TR registers 1300(1)-1300(8) during the first cycle. In the most recent cycle of the clock signal CLK, adjustment suggestion 1302(1) is stored in TR register 1300(1) in decoded form. Conversely, TR register 1300(2) contains only one remaining bit, which will be shifted out in the next cycle. Since one bit is shifted out in each cycle, Figure 13A The instruction adjustment suggestion 1302(2) is initially stored in the TR register 1300(2) seven (7) cycles ago, and the TR register 1300(2) will be available for storing adjustment suggestion 1302(2) in the next cycle. The TR registers 1300(3)-1300(8) have a number of remaining bits that increase in the order of storing adjustment suggestion 1302(3)-1302(8).

[0135] Figure 13B Example: TR registers 1300(1)-1300(8) immediately following the clock signal CLK Figure 13A The state in the second cycle following the first cycle is shown. As shown, the adjustment suggestions 1302(1)-1302(8) stored in TR registers 1300(1)-1300(8) have been shifted one bit to the right, except for TR register 1300(2), which stores the adjustment suggestion 1302(2) received from the self-allocation circuit 1124 in the previous cycle. TR register 1300(3) stores only one remaining bit of adjustment suggestion 1302(3), which can be used to store the next adjustment suggestion 1302(3).

[0136] Figure 13C Example: TR registers 1300(1)-1300(8) immediately following Figure 13BThe state in the third cycle following the second cycle is shown. The adjustment suggestions 1302(1)-1302(8) in each of the TR registers stored in TR registers 1300(1)-1300(8) have been shifted one bit to the right again, except for TR register 1300(3), which stores Figure 13B The adjustment recommendation 1302(3) generated during the period shown is illustrated.

[0137] The adjustment suggestion aggregation circuit 1306 generates the adjustment result 1310 based on the right-hand bits 1304(1)-1304(8) in the TR registers 1300(1)-1300(8). Therefore, in Figures 13A to 13C In each of the diagrams, the adjustment suggestion aggregation circuit 1306 will be based on the right bits 1304(1)-1304(8) (in Figures 13A to 13C The clock signal CLK shown has at least one "OR" operation ("1") in each cycle to generate an adjustment result 1310 of "1". In this regard, each adjustment suggestion in adjustment suggestions 1302(1)-1302(8) can affect the adjustment result 1310 for up to eight cycles of the clock signal CLK. However, for example, the state measured in the LAM circuit may change significantly (e.g., improve) in less than eight cycles, making the performance degradation requested many cycles ago unnecessary and unnecessarily degrading the performance.

[0138] In this regard, return Figure 11 The regulation management circuit 1100 may provide regulation suggestions 1110 from regulation request merging circuit 1108 or distribution circuit 1124 to the regulation control circuit 1118. The regulation control circuit 1118 may employ algorithms, state machines, or other circuitry to identify cases where the control signal 1106 is determined by the regulation suggestion 1110 generated in the current cycle rather than by the regulation result 1116. That is, the regulation result 1116 may be determined by one of the regulation suggestions 1126(1)-1126(8) generated eight cycles ago, but the most recently generated regulation suggestion 1110 is a better indication of the current dynamic conditions. Therefore, the regulation control circuit 1118 may determine whether to replace the regulation result 1116 and generate the regulation control signal 1106 based on the regulation suggestion 1110. This determination may be based on the change of the regulation suggestion 1110 from the previous one or two cycles to the current cycle.

[0139] For example, in response to a change in adjustment recommendation 1110 from a maximum value in the first cycle (e.g., 7 / 8 in the example above) to a minimum value in the second cycle immediately following the first cycle (e.g., 0 / 8), adjustment control circuit 1118 may generate adjustment control signal 1106 based on the minimum value in the second cycle rather than based on adjustment result 1116, because adjustment (e.g., reduction) of the activity of monitored processing device 110 appears no longer necessary. Alternatively, in response to a change in adjustment recommendation 1110 from a maximum value (e.g., 7 / 8) or second-largest value (e.g., 6 / 8) in the range of the first cycle to a minimum value (e.g., 0 / 8) or second-smallest value (e.g., 1 / 8) in the next cycle, adjustment control circuit 1118 may generate adjustment control signal 1106 based on adjustment recommendation 1110 in the next cycle.

[0140] As an alternative, to avoid responding too quickly to a lower adjustment request, it may be preferable to ensure that the adjustment recommendation 1110 remains low for at least two cycles. Therefore, in response to the transition of the adjustment recommendation 1110 from its maximum value (e.g., 7 / 8) in the first cycle of the clock signal CLK to its minimum value (e.g., 0 / 8) in the second cycle (e.g., immediately following the first cycle) and remaining at its minimum value in the third cycle (e.g., immediately following the second cycle), the adjustment control circuit 1118 may generate an adjustment control signal 1106 based on the adjustment recommendation 1110 (at its minimum value) in the third cycle.

[0141] In response to the adjustment control signal 1106 having an activity status indication (such as binary "0") in the first cycle, the monitored processing device 110 may be active in the next cycle of the clock signal CLK, or there may be an additional delay cycle. In response to the adjustment control signal 1106 having an inactivity status indication (such as binary "1") in the first cycle, the processing circuit 110 will be inactive in the next cycle (or thereafter) of the clock signal CLK. As an example, the adjustment control signal 1106 may be an input to a clock gating circuit (not shown) for gating the clock signal CLK or another clock signal provided to the monitored processing device 110 of the LAM circuit 136.

[0142] Figure 14This is a flowchart illustrating a method 1400 for regulating activities in a processor-based system 100, including operating a processing circuit 110 in response to a clock signal CLK (block 1402) and receiving a measurement 1202 of at least one state of the processing circuit 110 (block 1404). The method includes generating at least one regulation request 1102 based on the measurement 1202 of at least one state (block 1406) and generating a regulation suggestion 1110 based on the at least one regulation request 1102 in each cycle of the clock signal CLK (block 1408). The method further includes storing adjustment suggestions 1126(1)-1126(X) in a plurality of adjustment suggestion registers 1112(1)-1112(X) based on adjustment suggestions 1110 generated in consecutive cycles of the clock signal CLK (box 1410), and generating an adjustment result 1116 based on the adjustment suggestions 1126(1)-1126(X) stored in the plurality of adjustment suggestion registers 1112(1)-1112(X) (box 1412). The method also includes generating an adjustment control signal 1106 in each cycle of the clock signal CLK to adjust the activity of the processing circuit 110 (box 1414).

[0143] A regulation management circuit, configurable in an IC chip for a processor-based integrated system, is configured to monitor the state of local processing circuitry to receive at least one regulation request from at least one state detection circuit and to generate regulation suggestions in each cycle of a clock signal for the local processing circuitry. The regulation management circuit includes, but is not limited to, […]. Figures 11 to 14 The regulation and management circuitry, components, and methods shown herein, and in accordance with any aspect disclosed herein, can be provided in or integrated into any processor-based device. Examples not intended to be limiting include: set-top boxes, entertainment units, navigation devices, communication devices, fixed location data units, mobile location data units, Global Positioning System (GPS) devices, mobile phones, cellular phones, smartphones, Session Initiation Protocol (SIP) phones, tablet computers, phablets, servers, computers, portable computers, mobile computing devices, laptop computers, wearable computing devices (e.g., smartwatches, health or fitness trackers, glasses, etc.), desktop computers, personal digital assistants (PDAs), monitors, computer monitors, televisions, tuners, radios, satellite radios, music players, digital music players, portable music players, digital video players, video players, digital video disc (DVD) players, portable digital video players, automobiles, vehicle components, avionics systems, drones, and multirotor aircraft.

[0144] Figure 15This is a block diagram of another exemplary processor-based system, which includes a regulation management circuit configured to monitor the state of a local processing circuit to receive at least one regulation request from at least one state detection circuit and to generate a regulation proposal in each cycle of a clock signal for the local processing circuit.

[0145] In this example, the processor-based system 1500 may be formed within an IC chip 1502 and as a system-on-a-chip (SoC) 1504. The processor-based system 1500 includes a central processing unit (CPU) 1506, which includes one or more processors 1508, which may also be referred to as CPU cores or processor cores. The CPU 1506 may have a cache memory 1510 coupled to the CPU 1506 for fast access to temporarily stored data. The CPU 1506 is coupled to a system bus 1512 and may be coupled to master and slave devices included in the processor-based system 1500. As is well known, the CPU 1506 communicates with these other devices by exchanging address, control, and data information via the system bus 1512. For example, the CPU 1506 may communicate a bus transaction request to a memory controller 1514, which is an example of a slave device. Figure 15 Not illustrated, but multiple system buses 1512 may be provided, each of which constitutes a different architecture.

[0146] Other master and slave devices can be connected to system bus 1512. For example... Figure 15 As illustrated, these devices may include a memory system 1516, one or more input devices 1520, one or more output devices 1522, one or more network interface devices 1524, and one or more display controllers 1526. The memory system includes a memory controller 1514 and a memory array 1518. Input devices 1520 may include any type of input device, including but not limited to input keys, switches, voice processors, etc. Output devices 1522 may include any type of output device, including but not limited to audio, video, other visual indicators, etc. Network interface devices 1524 may be any device configured to allow data exchange to and from network 1528. Network 1528 may be any type of network, including but not limited to wired or wireless networks, private or public networks, local area networks (LANs), wireless local area networks (WLANs), wide area networks (WANs), and Bluetooth. ™ Networks and the Internet. The network interface device 1524 can be configured to support any type of communication protocol desired.

[0147] CPU 1506 can also be configured to access display controller 126 via system bus 1512 to control information transmitted to one or more displays 1530. Display controller 1526 transmits information to be displayed to display 1530 via one or more video processors 1532, which process the information to be displayed into a format suitable for display 1530. Display 1530 may include any type of display, including but not limited to cathode ray tube (CRT), liquid crystal display (LCD), plasma display, light-emitting diode (LED) display, etc.

[0148] IC chip 1502 also includes regulation management circuitry 1534, which includes state detection circuitry 1536 as part of processor-based system 1538. As an example, regulation management circuitry 1536 may be... Figures 11 to 13C The regulation management circuit 1100 is included. The processor-based system 1538 may include one or more LAM circuits 1540(1)-1140(6) associated with one or more of the processor 1508, cache memory 1510, memory controller 1514, network interface device 1524, display controller 1526, and / or system bus 1512, configured to monitor activity associated with such processing devices and report activity power events related to the activity of such devices within the hierarchical power management system 1538. As an example, the LAM circuits 1540(1)-1140(6) may be… Figures 1 to 3 , Figures 5 to 7 and Figure 10 The hierarchical power management systems 124, 624, and 724 in A contain LAM circuits 136 and 136R.

[0149] Figure 16 An exemplary wireless communication device 1600 may include a processor-based system 1602. The processor-based system includes regulation management circuitry configured to detect or receive measurements of the state of local processing circuitry and adjust its power consumption dynamically in response to the detected state of the processor-based system. Figures 11 to 13C The regulation and management circuit 1100 in the middle.

[0150] like Figure 16As shown, the wireless communication device 1600 includes an RF transceiver 1604 and a data processor 1606. The RF transceiver 1604 and / or the data processor 1606 may include corresponding hierarchical power management systems 1602(1), 1602(2), configured to locally monitor the activity of devices in a processor-based system to locally assess and regulate their power consumption, and to report active power events related to power consumption assessment to a centralized PEL circuit. The centralized PEL circuit is configured to collect active power events related to the power consumption of the monitored processing device and, in response, regulate the power in an IC chip, including but not limited to hierarchical power management systems 164, 624, 724 and their in-system configurations. Figures 1 to 3 , Figures 5 to 7 and Figures 9A to 10 An example component in [the document / reference].

[0151] The components in the RF transceiver 1604 and / or data processor 1606 may be distributed among multiple different chips 1603(1), 1603(2). The data processor 1606 may include memory for storing data and program code. The RF transceiver 1604 includes a transmitter 1608 and a receiver 1610 supporting bidirectional communication. Generally, the wireless communication device 1600 may include any number of transmitters 1608 and / or receivers 1610 for any number of communication systems and frequency bands. All or part of the RF transceiver 1604 may be implemented on one or more analog ICs, RF ICs, mixed-signal ICs, etc.

[0152] The transmitter 1608 or receiver 1610 can be implemented using either a superheterodyne architecture or a direct conversion architecture. In a superheterodyne architecture, the signal undergoes multi-stage frequency conversion between RF and baseband. For example, for receiver 1610, the signal is converted from RF to intermediate frequency (IF) in one stage and then from IF to baseband in another stage. In a direct conversion architecture, the signal is converted between RF and baseband in a single stage. Superheterodyne and direct conversion architectures can use different circuit blocks and / or have different requirements. Figure 16 In the wireless communication device 1600, the transmitter 1608 and receiver 1610 are implemented using a direct frequency conversion architecture.

[0153] In the transmission path, data processor 1606 processes the data to be transmitted and provides I and Q analog output signals to transmitter 1608. In the exemplary wireless communication device 1600, data processor 1606 includes digital-to-analog converters (DACs) 1612(1) and 1612(2) to convert the digital signals generated by data processor 1606 into I and Q analog output signals (e.g., I and Q output currents) for further processing.

[0154] Within transmitter 1608, low-pass filters 1614(1) and 1614(2) filter the I and Q analog output signals, respectively, to remove unwanted signals caused by the previous digital-to-analog conversion. Amplifiers (AMPs) 1616(1) and 1616(2) amplify the signals from low-pass filters 1614(1) and 1614(2), respectively, and provide I and Q baseband signals. Upconverter 1618 upconverts the I and Q baseband signals using the I and Q TX LO signals from transmit (TX) local oscillator (LO) signal generator 1622 via mixers 1620(1) and 1620(2) to provide upconverted signal 1624. Filter 1626 filters the upconverted signal 1624 to remove unwanted signals caused by upconversion and noise in the receive band. Power amplifier (PA) 1628 amplifies the up-converted signal 1624 from filter 1626 to obtain the desired output power level and provide a transmit RF signal. The transmit RF signal is routed through duplexer or switch 1630 and transmitted via antenna 1632.

[0155] In the receiving path, antenna 1632 receives signals transmitted by the base station and provides the received RF signal, which is routed through duplexer or switch 1630 and provided to low-noise amplifier (LNA) 1634. Duplexer or switch 1630 is designed to operate using a specific receive (RX) to TX duplexer frequency separation, such that the RX signal is isolated from the TX signal. The received RF signal is amplified by LNA 1634 and filtered by filter 1636 to obtain the desired RF input signal. Downconversion mixers 1638(1) and 1638(2) mix the output of filter 1636 with the I and Q RX LO signals (i.e., LO_I and LO_Q) from RX LO signal generator 1640 to generate I and Q baseband signals. The I and Q baseband signals are amplified by AMPs 1642(1) and 1642(2) and further filtered by low-pass filters 1644(1) and 1644(2) to obtain I and Q analog input signals, which are provided to data processor 1606. In this example, data processor 1606 includes analog-to-digital converters (ADCs) 1646(1) and 1646(2) to convert the analog input signals into digital signals to be further processed by data processor 1606.

[0156] exist Figure 16In the wireless communication device 1600, a TX LO signal generator 1622 generates I and Q TXLO signals for up-conversion, while an RX LO signal generator 1640 generates I and Q RX LO signals for down-conversion. Each LO signal is a periodic signal with a specific base frequency. A TX phase-locked loop (PLL) circuit 1648 receives timing information from a data processor 1606 and generates control signals for adjusting the frequency and / or phase of the TX LO signals from the TX LO signal generator 1622. Similarly, an RX PLL circuit 1650 receives timing information from a data processor 1606 and generates control signals for adjusting the frequency and / or phase of the RX LO signals from the RX LO signal generator 1640.

[0157] Those skilled in the art will further understand that the various exemplary logic blocks, modules, circuits, and algorithms described in connection with the aspects disclosed herein can be implemented as electronic hardware, instructions stored in memory, or in another computer-readable medium, wherein any such instructions are executed by a processor or other processing device or a combination of both. As an example, the devices and components described herein can be employed in any circuit, hardware component, integrated circuit (IC), or IC chip. The memory disclosed herein can be of any type and size and can be configured to store any type of information desired. To clearly illustrate this interchangeability, the functionality of the various exemplary components, blocks, modules, circuits, and steps has been generally described above. How such functionality is implemented depends on the specific application, design choices, and / or design constraints imposed on the overall system. Those skilled in the art may implement the described functionality in different ways for each specific application, but such specific implementation decisions should not be construed as departing from the scope of this disclosure.

[0158] The various exemplary logic blocks, modules, and circuits described in conjunction with the aspects disclosed herein may be implemented or executed using a processor, digital signal processor (DSP), application-specific integrated circuit (ASIC), field-programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic unit, discrete hardware component, or any combination thereof, designed to perform the functions described herein. The processor may be a microprocessor, but in alternative embodiments, it may be any conventional processor, controller, microcontroller, or state machine. The processor may also be implemented as a combination of computing devices (e.g., a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors cooperating with a DSP core, or any other such configuration).

[0159] The aspects disclosed herein can be embodied in hardware and instructions stored in the hardware, and can reside in, for example, random access memory (RAM), flash memory, read-only memory (ROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), registers, hard disks, removable disks, CD-ROMs, or any other form of computer-readable medium known in the art. An exemplary storage medium is coupled to a processor such that the processor can read information from and write information to the storage medium. Alternatively, the storage medium may be integral with the processor. The processor and storage medium may reside in an ASIC. The ASIC may reside in a remote station. Alternatively, the processor and storage medium may reside as discrete components in a remote station, base station, or server.

[0160] It should also be noted that the operational steps described in any of the exemplary aspects of this document are described for the purpose of providing examples and discussion. The described operations may be performed in many different orders other than the order illustrated. Furthermore, the operations described in a single operational step may actually be performed in multiple different steps. Additionally, one or more operational steps discussed in the exemplary aspects may be combined. It will be understood that, as will be apparent to those skilled in the art, many different modifications may be made to the operational steps illustrated in the flowcharts. Those skilled in the art will also understand that any of a variety of different techniques and arts can be used to represent information and signals. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be mentioned throughout the above description may be represented by voltage, current, electromagnetic waves, magnetic fields or magnetic particles, light fields or optical particles, or any combination thereof.

[0161] It should also be noted that the operational steps described in any of the exemplary aspects of this document are described for the purpose of providing examples and discussion. The described operations may be performed in many different orders other than the order illustrated. Furthermore, the operations described in a single operational step may actually be performed in multiple different steps. Additionally, one or more operational steps discussed in the exemplary aspects may be combined. It will be understood that, as will be apparent to those skilled in the art, many different modifications may be made to the operational steps illustrated in the flowcharts. Those skilled in the art will also understand that any of a variety of different techniques and arts can be used to represent information and signals. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be mentioned throughout the above description may be represented by voltage, current, electromagnetic waves, magnetic fields or magnetic particles, light fields or optical particles, or any combination thereof.

[0162] The prior description of this disclosure is provided to enable any person skilled in the art to make or use this disclosure. Various modifications to this disclosure will be apparent to those skilled in the art, and the general principles defined herein can be applied to other variations. Therefore, this disclosure is not intended to be limited to the examples and designs described herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

[0163] Specific implementation examples are described in the following numbered clauses: 1. An integrated circuit (IC) chip, the integrated circuit chip comprising a processor-based system, the processor-based system comprising: Processing circuitry that operates in response to a clock signal; At least one state detection circuit, the at least one state detection circuit being configured to generate at least one adjustment request based on one or more measurements of at least one state of the processing circuit; and Regulation management circuit, the regulation management circuit includes: A regulation request merging circuit is configured to receive at least one regulation request from at least one state detection circuit and generate a regulation suggestion based on the at least one regulation request in each cycle of the clock signal; Multiple adjustment suggestion registers, each configured sequentially: Receive the adjustment suggestion generated in the adjustment request merging circuit during the first cycle of the clock signal; and The received adjustment suggestions are stored in the first plurality of consecutive cycles of the clock signal following the first cycle; A regulation suggestion aggregation circuit, configured to generate a regulation result based on the regulation suggestions stored in the plurality of regulation suggestion registers; and An adjustment control circuit is configured to receive the adjustment result and generate an adjustment control signal in each cycle of the clock signal to selectively adjust the activity of the processing circuit.

[0164] 2. The IC chip according to Clause 1, wherein the adjustment request generated in each of the at least one state detection circuit includes an adjustment value having one of a first number of adjustment values ​​within a range of adjustment values ​​including more than two adjustment values.

[0165] 3. The IC chip according to Clause 1 or Clause 2, wherein the adjustment request includes a request to limit the activity of the processing circuitry in a second number of cycles within a first number of cycles of the clock signal.

[0166] 4. The IC chip according to any one of Clauses 1 to 3, the IC chip further comprising an adjustment value range configuration circuit configured to determine a first number of adjustment values ​​within the adjustment value range of the adjustment request generated in each of the at least one state detection circuit.

[0167] 5. The IC chip according to any one of Clauses 1 to 4, wherein the adjustment request merging circuit is configured as follows: In each cycle of the clock signal, a first adjustment request is received from the first state detection circuit in the at least one state detection circuit; and A second adjustment request is received from a second state detection circuit in the at least one state detection circuit at a frequency lower than that of each cycle of the clock signal.

[0168] 6. The IC chip according to any one of Clauses 1 to 5, wherein the adjustment request merging circuit is further configured to: In each cycle in which the second adjustment request is not received from the second state detection circuit in the at least one state detection circuit, the adjustment suggestion is generated based on the last adjustment request received from the second state detection circuit in the at least one state detection circuit.

[0169] 7. The IC chip according to any one of Clauses 1 to 6, wherein the adjustment request merging circuit is further configured to: In a second cycle in which the adjustment request is not received from the second state detection circuit in the at least one state detection circuit, the adjustment suggestion is generated solely based on the adjustment request received from the at least one state detection circuit in the second cycle, the adjustment request including the first adjustment request.

[0170] 8. An IC chip according to any one of Clauses 1 to 7, wherein each of the plurality of adjustment suggestion registers is configured to store the adjustment suggestion as a multi-bit value, wherein each bit of the multi-bit value corresponds to a period of the clock signal.

[0171] 9. The IC chip according to Clause 8, wherein each of the plurality of adjustment suggestion registers includes a shift register, the shift register being further configured to shift the plurality of bit values ​​by one bit in a first direction in each cycle of the clock signal.

[0172] 10. The IC chip according to any one of Clauses 1 to 9, wherein the regulation management circuitry is further configured to store the generated regulation proposal in one of the plurality of regulation proposal registers in each cycle of the clock signal, such that only one remaining bit of the shifted multi-bit value of the stored regulation proposal is stored.

[0173] 11. An IC chip according to any one of Clauses 1 to 10, wherein the first number of the plurality of adjustment recommendation registers is equal to the second number of bits in each of the plurality of adjustment recommendation registers.

[0174] 12. The IC chip according to any one of Clauses 8 to 11, wherein the adjustment suggestion aggregation circuit is further configured to generate the adjustment result based on a bit of one of the multiple bit values ​​stored in each of the plurality of adjustment suggestion registers.

[0175] 13. The IC chip according to Clause 12, wherein the adjustment suggestion aggregation circuit is further configured to generate the adjustment result based on a logical OR operation of one bit of the multiple bit values ​​stored in each of the plurality of adjustment suggestion registers.

[0176] 14. The IC chip according to any one of Clauses 1 to 13, wherein the regulation control circuit is further configured to generate the regulation control signal from the regulation result.

[0177] 15. The IC chip according to any one of Clauses 1 to 14, wherein the regulation control circuit is further configured to: Receive the adjustment suggestion generated in the adjustment request merging circuit; and The adjustment control signal is generated based on the adjustment result or the adjustment suggestion received in multiple previous cycles of the clock signal.

[0178] 16. An IC chip according to any one of Clauses 8 to 15, wherein: The proposed adjustment values ​​are within a range from a maximum to a minimum, where the maximum value is configured to reduce the activity of the processing circuitry for a maximum number of cycles, and the minimum value is configured to reduce the activity of the processing circuitry for a minimum number of cycles; and The adjustment control circuit is further configured to generate the adjustment control signal based on the minimum value in the next cycle in response to a change in the adjustment suggestion from the maximum value in the first cycle of the clock signal to the minimum value in the next cycle of the clock signal.

[0179] 17. An IC chip according to any one of Clauses 8 to 16, wherein: The proposed adjustment values ​​are within a range from a maximum to a minimum, where the maximum value is configured to reduce the activity of the processing circuitry for a maximum number of cycles, and the minimum value is configured to reduce the activity of the processing circuitry for a minimum number of cycles; and The adjustment control circuit is further configured to generate the adjustment control signal based on the adjustment suggestion in the next cycle in response to a change in the adjustment suggestion from one of the maximum and second maximum values ​​in the first cycle of the clock signal to one of the minimum and second minimum values ​​in the next cycle of the clock signal.

[0180] 18. An IC chip according to any one of Clauses 8 to 17, wherein: The proposed adjustment values ​​are within a range from a maximum to a minimum, where the maximum value is configured to reduce the activity of the processing circuitry for a maximum number of cycles, and the minimum value is configured to reduce the activity of the processing circuitry for a minimum number of cycles; and The adjustment control circuit is further configured to generate the adjustment control signal based on the adjustment suggestion in the third cycle in response to the transition of the adjustment suggestion from the maximum value in the first cycle of the clock signal to the minimum value in the second cycle of the clock signal and to maintain the minimum value in the third cycle of the clock signal.

[0181] 19. An IC chip according to any one of Clauses 1 to 18, wherein: The adjustment control signal has one of an active state indication and an inactive state indication; In response to the adjustment control signal having the activity state indication in the second cycle, the processing circuit is active in the third cycle following the second cycle; and In response to the inactivity indication of the adjustment control signal in the third cycle, the processing circuit is inactive in the fourth cycle following the third cycle.

[0182] 20. An IC chip according to any one of Clauses 1 to 19, wherein the at least one state detection circuit comprises a plurality of entries, wherein the at least one state detection circuit is further configured to: Receive the state measurement; The state measurement is stored in the first entry of the first plurality of entries in the shift register; The state measurement stored in each of the first plurality of entries is shifted in a first direction from the first entry toward the last entry; Generate a first sum of the received state measurement and the state measurements stored in all entries of the shift register except for the last entry; Generate a second sum of the stored state measurements from all entries in the shift register; Compare the first sum with the second sum; and The adjustment request is generated based on the difference between the first sum and the second sum.

[0183] 21. An IC chip according to any one of Clauses 1 to 20, wherein the state measurement includes the measurement of the current supplied to the processing circuit.

[0184] 22. The IC chip according to any one of Clauses 20 to 21, wherein the first number of consecutive cycles of the clock signal storing the state measurement are configurable.

[0185] 23. An IC chip according to any one of Clauses 20 to 22, wherein the state measurement includes a measurement of voltage, peak power, peak current, average voltage, average current, temperature, and an activity measured using an activity measurement algorithm.

[0186] 24. An IC chip according to any one of Clauses 20 to 23, said IC chip being integrated into a device selected from the group consisting of: set-top boxes; entertainment units; navigation devices; communication devices; fixed location data units; mobile location data units; global positioning system (GPS) devices; mobile phones; cellular phones; smartphones; session initiation protocol (SIP) phones; tablet computers; tablet phones; servers; computers; portable computers; mobile computing devices; wearable computing devices; desktop computers; personal digital assistants (PDAs); monitors; computer monitors; televisions; tuners; radios; satellite radios; music players; digital music players; portable music players; digital video players; video players; digital video disc (DVD) players; portable digital video players; automobiles; vehicle components; avionics systems; unmanned aerial vehicles; and multirotor aircraft.

[0187] 25. A method for regulating activity in processing circuitry of a processor-based system, the method comprising: The processing circuit operates in response to a clock signal; In at least one state detection circuit, at least one adjustment request is generated based on one or more measurements of at least one state of the processing circuit; In each cycle of the clock signal, in the first plurality of consecutive cycles of the clock signal, an adjustment suggestion is generated based on the at least one adjustment request; The adjustment suggestions generated in the first plurality of consecutive cycles of the clock signal are stored in a plurality of adjustment suggestion registers; The adjustment result is generated based on the adjustment recommendations stored in the plurality of adjustment recommendation registers; and An adjustment control signal is generated in each cycle of the clock signal to adjust the activity of the processing circuit based on the adjustment control signal.

[0188] 26. The method according to Clause 25, wherein generating the adjustment request includes generating an adjustment value within a range comprising more than two adjustment values.

[0189] 27. The method according to Clause 25 or Clause 26, wherein generating the adjustment request includes generating a request to reduce the activity of the processing circuitry in a first plurality of cycles during a second plurality of cycles of the clock signal.

[0190] 28. The method according to any one of Clauses 25 to 27, the method further comprising determining, based on a range of adjustment value configuration circuitry, a plurality of possible adjustment values ​​for the adjustment request generated in each of at least one state detection circuitry.

[0191] 29. The method according to any one of Clauses 25 to 28, wherein the method further comprises: In the first state detection circuit of the at least one state detection circuit, a first adjustment request is generated in each cycle of the clock signal; and In the second state detection circuit of the at least one state detection circuit, a second adjustment request is generated at a frequency lower than that of each cycle of the clock signal.

[0192] 30. The method according to Clause 29, wherein the method further comprises: In each cycle in which the second adjustment request is not received from the second state detection circuit in the at least one state detection circuit, the adjustment suggestion is generated based on the last second adjustment request received from the second state detection circuit in the at least one state detection circuit.

[0193] 31. The method described pursuant to Clause 29 or Clause 30, wherein the method further comprises: In each cycle in which the adjustment request is not received from the second state detection circuit in the at least one state detection circuit, the adjustment suggestion is generated based on the adjustment request received from the at least one state detection circuit, the adjustment request including the first adjustment request.

[0194] 32. The method according to any one of Clauses 25 to 31, wherein the method further comprises: The adjustment suggestion is stored as a multi-bit value in each of the plurality of adjustment suggestion registers, wherein each bit of the multi-bit value corresponds to the period of the clock signal.

[0195] 33. The method according to Clause 32, the method further comprising shifting the multi-bit value in each of the plurality of adjustment suggestion registers by one bit in a first direction during each cycle of the clock signal.

[0196] 34. The method according to Clause 33, the method further comprising storing the generated adjustment suggestion in one of the plurality of adjustment suggestion registers in each cycle of the clock signal, the adjustment suggestion register having only one remaining bit of a shifted multi-bit value of the stored adjustment suggestion.

[0197] 35. The method according to any one of Clauses 32 to 34, the method further comprising generating the adjustment result based on a bit of one of the multiple bit values ​​stored in each of the plurality of adjustment recommendation registers.

[0198] 36. The IC chip according to Clause 35, the IC chip further comprising generating the adjustment result based on a logical OR operation of one bit of the plurality of bit values ​​stored in each of the plurality of adjustment suggestion registers.

[0199] 37. The method according to any one of Clauses 25 to 36, the method further comprising generating the regulation control signal from the regulation result.

[0200] 38. The method according to any one of Clauses 25 to 37, the method further comprising, in each cycle of the clock signal: Receive the adjustment suggestion generated in the adjustment request merging circuit; and The adjustment control signal is generated based on the adjustment results and the adjustment suggestions received in multiple cycles of the clock signal.

[0201] 39. The method according to any one of Clauses 32 to 36, wherein the multi-bit value of the adjustment recommendation is in a range from a maximum value to a minimum value, the maximum value corresponding to reducing the activity of the processing circuit in a maximum number of cycles, and the minimum value corresponding to reducing the activity of the processing circuit in a minimum number of cycles, the method further comprising: In response to the adjustment suggestion shifting from the maximum value in the first cycle of the clock signal to the minimum value in the next cycle of the clock signal, the adjustment control signal is generated based on the minimum value.

[0202] 40. The method according to Clause 39, wherein the method further comprises: In response to the adjustment suggestion shifting from one of the maximum and second-largest values ​​in the first cycle of the clock signal to one of the minimum and second-smallest values ​​in the next cycle of the clock signal, the adjustment control signal is generated based on the adjustment suggestion.

[0203] 41. The method according to Clause 39, wherein the method further comprises: In response to the adjustment suggestion to transition from the maximum value in the first cycle of the clock signal to the minimum value in the next cycle of the clock signal and to maintain the minimum value in the current cycle of the clock signal, the adjustment control signal is generated based on the minimum value.

[0204] 42. An IC chip according to any one of Clauses 25 to 41, wherein the adjustment control signal has one of an active state indication and an inactive state indication, the method further comprising: In response to the adjustment control signal having the activity state indication in the second cycle, the processing circuit is activated in the second cycle; and In response to the inactivity indication of the adjustment control signal in the third cycle, the processing circuit is deactivated in the third cycle.

[0205] 43. The method according to any one of Clauses 25 to 42, wherein measuring the state of the processor-based system in each cycle of the clock signal further comprises: The measurement depends on the state of activity of the processing circuit; The state measurement received in each of the first number (X) consecutive cycles of the clock signal; Generate the state measurement in the current cycle and the first sum of the state measurements stored in the previous second number (X-1) consecutive cycles of the clock signal; Generate a second sum of the state measurements stored in the first number (X) consecutive cycles of the clock signal; Compare the first sum with the second sum; and The adjustment request is generated based on the difference between the first sum and the second sum.

[0206] 44. The method according to any one of Clauses 25 to 42, wherein measuring the state includes measuring the current supplied to the processing circuit.

[0207] 45. The method according to any one of Clauses 25 to 44, wherein measuring the state includes measuring voltage, peak power, peak current, average voltage, average current, temperature, and activities measured using an active measurement algorithm.

[0208] 46. ​​An apparatus comprising components configured to perform the method according to any one of clauses 25 to 45.

[0209] 47. A computer program comprising instructions for causing an integrated circuit (IC) chip to perform the steps of the method according to any one of claims 25 to 45.

Claims

1. An integrated circuit (IC) chip, the integrated circuit chip comprising a processor-based system, the processor-based system comprising: Processing circuitry that operates in response to a clock signal; At least one state detection circuit, the at least one state detection circuit being configured to generate at least one adjustment request based on one or more measurements of at least one state of the processing circuit; as well as Regulation management circuit, the regulation management circuit includes: A regulation request merging circuit is configured to receive at least one regulation request from at least one state detection circuit and generate a regulation suggestion based on the at least one regulation request in each cycle of the clock signal; Multiple adjustment suggestion registers, each configured sequentially: Receive the adjustment suggestion generated in the adjustment request merging circuit during the first cycle of the clock signal; and The received adjustment suggestions are stored in the first plurality of consecutive cycles of the clock signal following the first cycle; A regulation suggestion aggregation circuit, configured to generate a regulation result based on the regulation suggestions stored in the plurality of regulation suggestion registers; and An adjustment control circuit is configured to receive the adjustment result and generate an adjustment control signal in each cycle of the clock signal to selectively adjust the activity of the processing circuit.

2. The IC chip of claim 1, wherein the adjustment request generated in each of the at least one state detection circuit includes an adjustment value, the adjustment value having one of a first number of adjustment values ​​within a range of adjustment values ​​including more than two adjustment values.

3. The IC chip of claim 2, wherein the adjustment request includes a request to limit the activity of the processing circuit in a second number of cycles within a first number of cycles of the clock signal.

4. The IC chip according to claim 2, the IC chip further comprising an adjustment value range configuration circuit, the adjustment value range configuration circuit being configured to determine a first number of adjustment values ​​within the adjustment value range of the adjustment request generated in each of the at least one state detection circuit.

5. The IC chip according to claim 1, wherein the adjustment request merging circuit is configured as follows: A first adjustment request is received from a first state detection circuit in the at least one state detection circuit during each cycle of the clock signal; and A second adjustment request is received from a second state detection circuit in the at least one state detection circuit at a frequency lower than that of each cycle of the clock signal.

6. The IC chip according to claim 5, wherein the adjustment request merging circuit is further configured to: In each cycle in which the second adjustment request is not received from the second state detection circuit in the at least one state detection circuit, the adjustment suggestion is generated based on the last adjustment request received from the second state detection circuit in the at least one state detection circuit.

7. The IC chip according to claim 5, wherein the adjustment request merging circuit is further configured to: In a second cycle in which the adjustment request is not received from the second state detection circuit in the at least one state detection circuit, the adjustment suggestion is generated solely based on the adjustment request received from the at least one state detection circuit in the second cycle, the adjustment request including the first adjustment request.

8. The IC chip of claim 1, wherein each of the plurality of adjustment suggestion registers is configured to store the adjustment suggestion as a multi-bit value, wherein each bit of the multi-bit value corresponds to the period of the clock signal.

9. The IC chip of claim 8, wherein each of the plurality of adjustment suggestion registers includes a shift register, the shift register being further configured to shift the plurality of bit values ​​by one bit in a first direction in each cycle of the clock signal.

10. The IC chip of claim 9, wherein the regulation management circuit is further configured to store the generated regulation suggestion in one of the plurality of regulation suggestion registers in each cycle of the clock signal, thereby storing only the remaining bit of the shifted multi-bit value of the stored regulation suggestion.

11. The IC chip of claim 8, wherein the first number of the plurality of adjustment suggestion registers is equal to the second number of bits in each of the plurality of adjustment suggestion registers.

12. The IC chip of claim 8, wherein the adjustment suggestion aggregation circuit is further configured to generate the adjustment result based on a bit of one of the multiple bit values ​​stored in each of the plurality of adjustment suggestion registers.

13. The IC chip of claim 12, wherein the adjustment suggestion aggregation circuit is further configured to generate the adjustment result based on a logical OR operation of one bit of the multiple bit values ​​stored in each of the plurality of adjustment suggestion registers.

14. The IC chip of claim 1, wherein the adjustment control circuit is further configured to generate the adjustment control signal from the adjustment result.

15. The IC chip of claim 1, wherein the adjustment control circuit is further configured to: Receive the adjustment suggestion generated in the adjustment request merging circuit; and The adjustment control signal is generated based on the adjustment result or the adjustment suggestion received in multiple previous cycles of the clock signal.

16. The IC chip according to claim 8, wherein: The proposed adjustment values ​​are in the range from a maximum value to a minimum value, wherein the maximum value is configured to reduce the activity of the processing circuit for a maximum number of cycles, and the minimum value is configured to reduce the activity of the processing circuit for a minimum number of cycles. as well as The adjustment control circuit is further configured to generate the adjustment control signal based on the minimum value in the next cycle in response to a change in the adjustment suggestion from the maximum value in the first cycle of the clock signal to the minimum value in the next cycle of the clock signal.

17. The IC chip according to claim 8, wherein: The proposed adjustment values ​​are in the range from a maximum value to a minimum value, wherein the maximum value is configured to reduce the activity of the processing circuit for a maximum number of cycles, and the minimum value is configured to reduce the activity of the processing circuit for a minimum number of cycles. as well as The adjustment control circuit is further configured to generate the adjustment control signal based on the adjustment suggestion in the next cycle in response to a change in the adjustment suggestion from one of the maximum and second maximum values ​​in the first cycle of the clock signal to one of the minimum and second minimum values ​​in the next cycle of the clock signal.

18. The IC chip according to claim 8, wherein: The proposed adjustment values ​​are in the range from a maximum value to a minimum value, wherein the maximum value is configured to reduce the activity of the processing circuit for a maximum number of cycles, and the minimum value is configured to reduce the activity of the processing circuit for a minimum number of cycles. as well as The adjustment control circuit is further configured to generate the adjustment control signal based on the adjustment suggestion in the third cycle in response to the transition of the adjustment suggestion from the maximum value in the first cycle of the clock signal to the minimum value in the second cycle of the clock signal and to maintain the minimum value in the third cycle of the clock signal.

19. The IC chip according to claim 1, wherein: The adjustment control signal has one of an active state indication and an inactive state indication; In response to the adjustment control signal having the activity state indication in the second cycle, the processing circuit is active in the third cycle following the second cycle; as well as In response to the inactivity indication of the adjustment control signal in the third cycle, the processing circuit is inactive in the fourth cycle following the third cycle.

20. The IC chip of claim 1, wherein the at least one state detection circuit comprises a plurality of entries, wherein the at least one state detection circuit is further configured to: Receive the state measurement; The state measurement is stored in the first entry of the first plurality of entries in the shift register; The state measurement stored in each of the first plurality of entries is shifted in a first direction from the first entry toward the last entry; Generate a first sum of the received state measurement and the state measurements stored in all entries of the shift register except for the last entry; Generate a second sum of the stored state measurements from all entries in the shift register; Compare the first sum with the second sum; as well as The adjustment request is generated based on the difference between the first sum and the second sum.

21. The IC chip of claim 16, wherein the state measurement includes the measurement of the current supplied to the processing circuit.

22. The IC chip of claim 16, wherein the first number of consecutive cycles storing the clock signal of the state measurement is configurable.

23. The IC chip of claim 1, wherein the state measurement includes a measurement of voltage, peak power, peak current, average voltage, average current, temperature, and an activity measured using an activity measurement algorithm.

24. The IC chip of claim 1, wherein the IC chip is integrated into a device selected from the group consisting of: set-top boxes; entertainment units; navigation devices; communication devices; fixed location data units; mobile location data units; global positioning system (GPS) devices; mobile phones; cellular phones; smartphones; session initiation protocol (SIP) phones; tablet computers; tablet phones; servers; computers; portable computers; mobile computing devices; wearable computing devices; desktop computers; personal digital assistants (PDAs); monitors; computer monitors; televisions; tuners; radios; satellite radios; music players; digital music players; portable music players; digital video players; video players; digital video disc (DVD) players; portable digital video players; automobiles; vehicle components; avionics systems; unmanned aerial vehicles; and multi-rotor aircraft.

25. A method for regulating activity in processing circuitry of a processor-based system, the method comprising: The processing circuit operates in response to a clock signal; In at least one state detection circuit, at least one adjustment request is generated based on one or more measurements of at least one state of the processing circuit; In each cycle of the clock signal, in the first plurality of consecutive cycles of the clock signal, an adjustment suggestion is generated based on the at least one adjustment request; The adjustment suggestions generated in the first plurality of consecutive cycles of the clock signal are stored in a plurality of adjustment suggestion registers; The adjustment result is generated based on the adjustment recommendations stored in the plurality of adjustment recommendation registers; as well as An adjustment control signal is generated in each cycle of the clock signal to adjust the activity of the processing circuit based on the adjustment control signal.

26. The method of claim 25, wherein generating the adjustment request comprises generating an adjustment value within a range including more than two adjustment values.

27. The method of claim 26, wherein generating the adjustment request comprises generating a request to reduce the activity of the processing circuitry in a first plurality of cycles during a second plurality of cycles of the clock signal.

28. The method of claim 26, the method further comprising determining, based on an adjustment value range configuration circuit, a plurality of possible adjustment values ​​for the adjustment request generated in each of the at least one state detection circuit.

29. The method of claim 25, further comprising: In the first state detection circuit of the at least one state detection circuit, a first adjustment request is generated in each cycle of the clock signal; as well as In the second state detection circuit of the at least one state detection circuit, a second adjustment request is generated at a frequency lower than that of each cycle of the clock signal.

30. The method of claim 29, further comprising: In each cycle in which the second adjustment request is not received from the second state detection circuit in the at least one state detection circuit, the adjustment suggestion is generated based on the last second adjustment request received from the second state detection circuit in the at least one state detection circuit.

31. The method according to claim 29, wherein the method further comprises: In each cycle in which the adjustment request is not received from the second state detection circuit in the at least one state detection circuit, the adjustment suggestion is generated based on the adjustment request received from the at least one state detection circuit, the adjustment request including the first adjustment request.

32. The method of claim 25, further comprising: The adjustment suggestion is stored as a multi-bit value in each of the plurality of adjustment suggestion registers, wherein each bit of the multi-bit value corresponds to the period of the clock signal.

33. The method of claim 32, further comprising shifting the plurality of bit values ​​in each of the plurality of adjustment suggestion registers by one bit in a first direction during each cycle of the clock signal.

34. The method of claim 33, further comprising storing the generated adjustment suggestion in one of the plurality of adjustment suggestion registers in each cycle of the clock signal, the adjustment suggestion register having only one remaining bit of a shifted multi-bit value of the stored adjustment suggestion.

35. The method of claim 33, further comprising generating the adjustment result based on a bit of one of the plurality of bit values ​​stored in each of the plurality of adjustment recommendation registers.

36. The IC chip of claim 35, further comprising generating the adjustment result based on a logical OR operation of one bit of the plurality of bit values ​​stored in each of the plurality of adjustment suggestion registers.

37. The method of claim 25, further comprising generating the adjustment control signal from the adjustment result.

38. The method of claim 25, further comprising, in each cycle of the clock signal: Receive the adjustment suggestion generated in the adjustment request merging circuit; and The adjustment control signal is generated based on the adjustment results and the adjustment suggestions received in multiple cycles of the clock signal.

39. The method of claim 31, wherein the multi-bit value of the adjustment suggestion is in a range from a maximum value to a minimum value, the maximum value corresponding to reducing the activity of the processing circuit in a maximum number of cycles, and the minimum value corresponding to reducing the activity of the processing circuit in a minimum number of cycles, the method further comprising: In response to the adjustment suggestion shifting from the maximum value in the first cycle of the clock signal to the minimum value in the next cycle of the clock signal, the adjustment control signal is generated based on the minimum value.

40. The method of claim 39, further comprising: In response to the adjustment suggestion shifting from one of the maximum and second-largest values ​​in the first cycle of the clock signal to one of the minimum and second-smallest values ​​in the next cycle of the clock signal, the adjustment control signal is generated based on the adjustment suggestion.

41. The method of claim 37, further comprising: In response to the adjustment suggestion to transition from the maximum value in the first cycle of the clock signal to the minimum value in the next cycle of the clock signal and to maintain the minimum value in the current cycle of the clock signal, the adjustment control signal is generated based on the minimum value.

42. The IC chip of claim 37, wherein the adjustment control signal has one of an active state indication and an inactive state indication, the method further comprising: In response to the adjustment control signal having the activity status indication in the second cycle, the processing circuit is activated in the second cycle; as well as In response to the inactivity indication of the adjustment control signal in the third cycle, the processing circuit is deactivated in the third cycle.

43. The method according to claim 25, wherein, Measuring the state of the processor-based system in each cycle of the clock signal further includes: The measurement depends on the state of activity of the processing circuit; The state measurement received in each of the first number (X) consecutive cycles of the clock signal; Generate the state measurement in the current cycle and the first sum of the state measurements stored in the previous second number (X-1) consecutive cycles of the clock signal; Generate a second sum of the state measurements stored in the first number (X) consecutive cycles of the clock signal; Compare the first sum with the second sum; and The adjustment request is generated based on the difference between the first sum and the second sum.

44. The method of claim 39, wherein measuring the state includes measuring the current supplied to the processing circuit.

45. The method of claim 25, wherein measuring the state comprises measuring voltage, peak power, peak current, average voltage, average current, temperature, and activities measured using an activity measurement algorithm.

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