Topology result code for Crifford circuits

Abstract

A method (50) of applying a Crifford circuit to a correction fault in a qubit register (12) of a quantum computer (10) includes receiving (52) circuit data defining the Crifford circuit; receiving (56) additional data identifying one or more measurements for each of a plurality of faces (48) belonging to the lattice (44); issuing (58) a result code based on the circuit data, the result code comprising a series of result checks, each result check corresponding to an expected error syndrome for application of the Crifford circuit to the qubit register; and issuing (60) a topology result code based on the circuit data, the additional data and the result code, the topology result code comprising a series of check operators that support quantum error correction via a topology decoder, thereby enabling fault correction in the application of the Crifford circuit to the quantum bit register.

Description

Background Technology

[0001] A quantum computer is a physical machine configured to perform logical operations based on quantum mechanical phenomena. Such logical operations can include, for example, mathematical calculations. Current interest in quantum computing technology stems from analyses demonstrating that, when applied to specific types of problems, a properly configured quantum computer can outperform any available non-quantum computer in terms of computational efficiency. These problems include computer modeling of natural and synthetic quantum systems, integer factorization, data search, and function optimization applied to systems of linear equations and machine learning. Summary of the Invention

[0002] One aspect of this disclosure relates to a method for correcting faults in a qubit register of a quantum computer using a Clifford circuit. The method includes: (a) receiving circuit data defining the Clifford circuit; (b) receiving additional data identifying one or more measurements belonging to each of a plurality of faces of a lattice; (c) issuing a result code based on the circuit data, the result code including a series of result checks, each result check corresponding to an expected error syndrome for the application of the Clifford circuit to the qubit register; and (d) issuing a topological result code based on the circuit data, the additional data, and the result code, the topological result code including a series of check operators supporting quantum error correction via a topology decoder, thereby achieving fault correction in the application of the Clifford circuit to the qubit register.

[0003] Another aspect of this disclosure relates to a computer system operatively coupled to a quantum computer. The computer system includes a processor and a computer memory operatively coupled to the processor, the computer memory having instructions that cause the processor to correct faults in a qubit register of a Clifford circuit applied to the quantum computer. The instructions include (a) instructions for receiving circuit data defining the Clifford circuit, (b) instructions for receiving additional data identifying one or more measurements belonging to each of a plurality of faces of a lattice, (c) instructions for issuing a result code based on the circuit data, the result code including a series of result checks, each result check corresponding to an expected error checker for the application of the Clifford circuit to the qubit register, and (d) instructions for issuing a topological result code based on the circuit data, the additional data, and the result code, the topological result code including a series of check operators supporting quantum error correction via a topology decoder, thereby achieving fault correction in the application of the Clifford circuit to the qubit register.

[0004] This summary is provided to present a simplified version of the selected concepts further described in the detailed embodiments. This summary is not intended to identify key or essential features of the claimed subject matter, nor is it intended to limit the scope of the claimed subject matter. The claimed subject matter is not limited to the implementation of solutions to any or all the shortcomings pointed out in any part of this disclosure. Attached Figure Description

[0005] Figure 1 Various aspects of an example quantum computer are shown.

[0006] Figure 2 The image shows a Bloch sphere, which graphically represents the quantum state of a qubit in a quantum computer.

[0007] Figure 3 Aspects of example signal waveforms for implementing quantum gate operations or measurements in a quantum computer are shown.

[0008] Figure 4 This is a schematic diagram of a lattice for a physical quantum bit in a non-restrictive example.

[0009] Figure 5 This is a diagram illustrating an example algorithm for generating code inspection that can be used in conjunction with a topology decoder.

[0010] Figure 6 It is Figure 5 The algorithm transforms the shortened code inspection into a concise time sequence, illustrated in the example flow diagram.

[0011] Figure 7 This paper illustrates aspects of an example method for correcting one or more faults in a quantum computer's qubit register using a Clifford circuit.

[0012] Figure 8 It shows the applicability Figure 5 Algorithm, Figure 6 process and Figure 7 Examples of methods in various aspects of classic computer systems. Detailed Implementation

[0013] 1. Overview As described in further detail in this paper, [Reference 1] proposes an end-to-end process for detecting and correcting faults in Clifford circuits. The limitation of this process is that its implementation is either a difficult-to-construct lookup table decoder or an LDPC decoder that results in significant runtime costs. An extension of the [Reference 1] process is presented here, compatible with topology decoders such as minimum-weight perfect matching and joint lookup, which are efficient in both construction and execution. More specifically, this extension enables topology code implementations, including surface codes and Floquet codes, to perform automated decoder construction.

[0014] 2. Quantum Computer Architecture To provide context for quantum error correction via topological result code, some aspects of an example quantum computer architecture will first be described. Now turning to the accompanying figures, Figure 1 Aspects of an example quantum computer 10 configured to perform quantum logic operations (see below) are shown. While conventional computer memory contains digital data in the form of bit arrays and performs bit-by-bit logic operations, quantum computers contain data in the form of qubit arrays and perform quantum mechanical operations on the qubits to implement the desired logic. Therefore, Figure 1 The quantum computer 10 includes a set of qubit registers 12—for example, a state register 12S and an auxiliary register 12A. Each qubit register includes a series of qubits 14. The number of qubits in the qubit registers is not particularly limited, but can be determined based on the complexity of the quantum logic to be implemented by the quantum computer.

[0015] Depending on the architecture required for the quantum computer 10, the qubits 14 of the qubit register 12 can take various forms. As a non-limiting example, each qubit may include: a superconducting Josephson junction, a trapped ion, an atomic trap coupled to a high-fine-grained cavity, atoms or molecules confined within a fullerene, ions or neutral-doped atoms confined within a main lattice, quantum dots exhibiting discrete spatial or spin-electronic states, electron-hole pairs in a semiconductor junction entrained via an electrostatic trap, coupled quantum wire pairs, atomic nuclei addressable by magnetic resonance, free electrons in helium, molecular magnets, or metalloid carbon nanospheres. The qubits can be implemented in multiple processing states corresponding to different light propagation modes via linear optical elements (e.g., mirrors, beam splitters, and phase shifters), and in states accumulated within a Bose-Einstein condensate. More broadly, each qubit 14 can include any particle or particle system that can exist in two or more discrete quantum states that can be measured and manipulated experimentally.

[0016] Figure 2 This is a diagram of Bloch Sphere 16, which provides a graphical representation of some quantum mechanical aspects of a single qubit 14. In this specification, the north and south poles of the Bloch Sphere correspond to the standard basis vectors, respectively. and For example, the spin up and spin down states of electrons or other fermions. The point set on the surface of the Bloch sphere contains all possible pure states of a qubit. The interior point corresponds to all possible mixed states. The mixed states of a given qubit may arise from decoherence, which may occur due to undesirable coupling with the external degrees of freedom.

[0017] Return now Figure 1The quantum computer 10 includes a controller 18. The controller may include at least one processor 20 and associated computer memory 22. The processor 20 may be operatively coupled to peripheral components, such as network components, to enable remote operation of the quantum computer. The processor 20 may take the form of a central processing unit (CPU), a graphics processing unit (GPU), etc. Therefore, the controller 18 may include classical electronic components. The terms “classical” and “non-quantum” as used herein apply to any component that can be accurately modeled without considering the quantum state of any individual particle. For example, classical electronic components include integrated, microlithographically etched transistors, resistors, and capacitors. The computer memory 22 may be configured to have program instructions 24 that cause the processor 20 to perform any function or process of the controller 18. The computer memory may also be configured to have additional data 26. In some examples, the data 26 may include a register of classical control bits 28 that influence the operation of the quantum computer during runtime—for example, to provide classical control inputs to one or more quantum gate operations. In an example where the qubit register 12 is a cryogenic or ultra-cryogenic device, the controller 18 may include control components that can operate at cryogenic or ultra-cryogenic temperatures—for example, a field-programmable gate array (FPGA) operating at 77K. In such an example, the cryogenic control components may be operatively coupled to interface components that can operate at normal temperatures.

[0018] The controller 18 of the quantum computer 10 is configured to receive multiple inputs 30 and provide multiple outputs 32. The inputs and outputs may each include digital lines and / or analog lines. At least some of the inputs and outputs may be data lines through which data is provided to and / or extracted from the quantum computer. Other inputs may include control lines through which the operation of the quantum computer can be adjusted or otherwise controlled.

[0019] Controller 18 is operatively coupled to qubit register 12 via quantum interface 34. The quantum interface is configured to exchange data (solid line) bidirectionally with the controller. The quantum interface is also configured to exchange signals associated with the data (dashed line) bidirectionally with the qubit register. Depending on the physical implementation of qubit 14, such signals may include electrical, magnetic, and / or optical signals. Through the signals transmitted via the quantum interface, the controller can query and otherwise influence the quantum states stored in any, some, or all of the qubit registers, as defined by the collective quantum states of the qubits therein. For this purpose, the quantum interface includes a qubit writer 36 and a qubit reader 38. The qubit writer is configured to output a signal to one or more qubits of the qubit register based on the write data received from the controller. The qubit reader is configured to sense the signal from one or more qubits of the qubit register and output read data to the controller based on that signal. The read data received from the qubit reader, in some examples, may be an estimate of observables in a measurement of the quantum states stored in the qubit register. In summary, controller 18 and interface 34 can be referred to as a "control system".

[0020] In some examples, a properly configured signal from the qubit writer 36 can physically interact with one or more qubits 14 of the qubit register 12 to trigger a measurement of a quantum state stored in one or more qubits. The qubit reader 38 can then sense the resulting signal emitted by the one or more qubits according to the measurement and can provide read data corresponding to the resulting signal to the controller 18. In other words, the qubit reader can be configured to output an estimate of one or more observables reflecting the quantum state of one or more qubits of the qubit register based on the received signal and provide that estimate to the controller 18. In a non-limiting example, the qubit writer can provide appropriate voltage pulses or pulse sequences to the electrodes of one or more qubits based on data from the controller to initiate a measurement. In short, the qubit reader can sense photon emission from one or more qubits and can assert the corresponding digital voltage level on the quantum interface line to the controller. Generally, any measurement of a quantum mechanical state is performed by an operator corresponding to the observable to be measured. Defined; the result of measurement It is guaranteed to be One of the allowed eigenvalues. In quantum computer 10, Statistically, it is related to the state of the qubit register before the measurement, but it is not uniquely determined by the state of the qubit register.

[0021] Based on appropriate inputs from controller 18, quantum interface 34 can be configured to implement one or more quantum logic gates to operate on quantum states stored in qubit register 12. The term "state vector" as used herein refers to the quantum states stored in a series of qubits 14S of the state register 12S of quantum computer 10. While the functionality of each type of logic gate in a classical computer system is described by a corresponding truth table, the functionality of each type of quantum gate is described by a corresponding operator matrix. The operator matrix operates (i.e., multiplies) on the complex vector representing the qubit register state and implements a specified rotation of that vector in Hilbert space.

[0022] For example, the Hadamard gate H is defined by the following formula:

[0023] The H-gate acts on a single qubit; the H-gate controls the ground state. Mapped to and will Therefore, the H-gate creates a superposition of states that, when measured, exhibit... or The probabilities are equal.

[0024] Phase gate Defined by the following formula:

[0025] Gate retains ground state Unchanged, but will Mapped to Therefore, measurement or The probability is not changed by the gate, but the phase of the quantum state of the qubit is shifted. This is equivalent to... Figure 2 Bloch Rotate 90 degrees along the latitude circle.

[0026] Some quantum gates operate on two or more qubits. For example, the SWAP gate operates on two different qubits and swaps their values. This gate is defined by the following equation:

[0027] A "Clifford gate" is a quantum gate belonging to the Clifford group—a group of quantum gates that influences the permutations of the Pauli operator. For In the case of qubits, Pauli operators form a group.

[0028] in It is a single-qubit Pauli matrix. The Clifford group is then defined as the unitary operator group of the normalized Pauli group.

[0029] The aforementioned list of quantum gates and associated operator matrices is non-exhaustive and is provided for illustrative purposes only. Other quantum gates include, as a non-limiting example, examples. Door, Door, and Door, Door, Additional phase-shifting door, Door, controlled Door, under control Doors and Controlled The gate, as well as the Toffoli gate, the Fredkin gate, the Ising gate, and the Deutsch gate.

[0030] continue Figure 1 Appropriately configured signals from the qubit writer 36 of the quantum interface 34 can physically interact with one or more qubits 14 of the qubit register 12 to assert any desired quantum gate operation. As described above, the desired quantum gate operation includes, specifically, a rotation of a complex vector representing the state of the qubit register. In some examples, to achieve the desired rotation... A quantum bit writer can write qubits for a predetermined duration. Apply a predetermined signal level In some examples, such as Figure 3 As shown, multiple signal levels can be applied over multiple consecutive or otherwise correlated durations to assert quantum gate operations on one or more qubits of a qubit register. Typically, each signal level... and each duration These are control parameters that can be adjusted by appropriate programming of the controller 18.

[0031] The terms "quantum circuit" and "quantum algorithm" used in this document are used to describe predetermined sequences of basic quantum gate and / or measurement operations that can be executed by the quantum computer 10. For example, a quantum circuit can be used to transition the quantum states of the qubit register 12 to implement classical or non-basic quantum gate operations or apply density operators. In some examples, a quantum circuit can be used to implement predefined operations. This operation can be incorporated into complex operation sequences. To ensure the adjoint operation, [the following is omitted as it is not explicitly stated]. one input qubit Mapped to One output or auxiliary qubit Quantum circuits can be defined as quantum circuits that... Quantum gates that operate on qubits .in this case, It can be configured to enable The input qubits remain unchanged, but the XOR operation will change the result. The result, combined with auxiliary qubits, makes .

[0032] Implicit in this description is that each qubit 14 of any qubit register 12 can be queried via quantum interface 34 to confidently reveal the standard basis vectors characterizing the quantum state of that qubit. or However, in some implementations, the measurement of the quantum state of a physical qubit can be erroneous. Therefore, any qubit 14 can be implemented as a logical qubit, which comprises a set of physical qubits measured according to an error-correcting quantum algorithm or circuit that reveals the quantum state of the logical qubit with a confidence level above a threshold.

[0033] 3. Topology result code Due to the inherent difficulty of isolating qubits from their noisy environment, the reliable execution of large-scale quantum algorithms will almost certainly require the use of quantum error correction. Quantum error-correcting circuits consist of a set of measurements, the parity of which is predetermined in the absence of errors. Thus, these sets of measurements correspond to code checks that can be used to identify and correct errors. For a wide range of quantum circuits, the so-called "result code" can be efficiently found [Reference 1].

[0034] However, a major challenge is mapping violations in code checks back to corresponding causal errors—i.e., decoding. The general decoding problem is NP-hard [Reference 2]. [Reference 1] proposes a sparsification algorithm to identify low-weight checks in the resulting code that can be used to efficiently construct a so-called LDPC decoder. Unfortunately, current LDPC decoders for quantum codes are slow, making them difficult or unusable at scale. Furthermore, these decoders generally perform poorly for topological quantum codes.

[0035] The decoder based on Minimum Weighted Perfect Matching (MWPM) [Reference 3] and the Joint Search (UF) algorithm [Reference 4] offer significantly optimized running time and can be used for popular and practical quantum codes, including surface codes [Reference 3] and Flokai codes [Reference 5][Reference 6]. However, these topological decoders require corresponding code checks to satisfy additional constraints, not just low weights. In particular, the natural structure of a topological decoder is where each circuit fault violates only two code checks. The sparsity algorithm [Reference 1] cannot guarantee adherence to this structure.

[0036] Some of the terms used in this disclosure may be referenced. Figure 4 Visualization Figure 4 This is a schematic diagram of the lattice 40 of physical qubit 14. Consistent with the description in Section 1, each physical qubit is stored in a quantum computer (e.g., in...). Figure 1 The collective quantum state in the qubit register 12 contributes one degree of freedom. In some examples, each degree of freedom is a spin-1 / 2 degree of freedom, such as... Figure 2 The block sphere represents the structure. In lattice 40, each physical qubit 14 is mapped to a corresponding vertex 42 of the planar figure 44. The structure and properties of the planar figure can be understood in the context of graph theory, which is familiar to those skilled in the art. In the example shown, lattice 40 is a square lattice; however, this feature is not strictly necessary, as lattices with non-square geometries are also contemplated. In planar figure 44, edges 46 intersect at the set of vertices 42, and a set of faces 48 is also defined. In topological error-correcting quantum codes, the stabilizer operator... A i For each vertex i The physical qubits are manipulated. Additionally, the stabilizer operator... B i Define each face j The physical qubits are used for manipulation. The "stabilizer space" of topological error-correcting quantum codes is where the operators... A and B Each operator is reduced to a vector space of identity operators. For toroidal topological error-corrected quantum codes (as a non-restrictive example), the stabilizer space is four-dimensional and therefore capable of representing two logical qubits of quantum information. In general, each circuit fault will shift the quantum state of lattice 40 out of the stabilizer space, thereby generating an operator. A and / or B Unlike the identity operator, this involves vertices and faces. The position of this anomaly operator on lattice 40 defines the "checksum" of the topological error-correcting quantum code, which can be used for error correction. For additional information, interested readers can refer to the extensive literature on topological error-correcting quantum codes.

[0037] Figure 5 This is a diagram of the code for Example Algorithm 1, which generates checks that can be used in conjunction with a topological decoder. The high-level idea is to leverage the lattice structure by searching for the code along a timeline of the lattice planes. For each plane, there exists a corresponding shortened result code. The search for the shortened code is converted into a concise temporal order (defined below).

[0038] For input circuits based on topological codes, such as toroidal codes or Flocai codes, the output of Algorithm 1 is a set of checks that can be used to construct a topological decoder. Each check corresponds to a vertex in the graph. Each possible fault in the circuit is detected by a subset of the checks. This subset of checks corresponds to an edge or hyperedge in the graph. If each fault is detected by two or fewer checks, the graph has no hyperedges and can be directly used by the MWPM or UF decoder. Otherwise, hyperedges can be converted into edges in some other way—for example, as described in [Reference 7].

[0039] Figure 6 This is a diagram illustrating Example Flow 2, which transforms the inspection of shortened code into a concise chronological order, obtained through a series of row operations. First, the inspection matrix is ​​represented as a simplified row echelon. Since Algorithm 1 sorts the columns chronologically, it establishes a unique starting point for each inspection. The remaining task is to transform each row so that it has a unique ending point and minimizes the total duration. In each iteration, the row with the latest ending point is identified. If multiple rows have the same ending point, the bottom row is selected and used to reduce the ending points of the remaining rows, making them more "concise." Then, the weight of the selected row is reduced if possible.

[0040] In addition to the circuit, Algorithm 1 requires an input to identify the measurement belonging to each face of the lattice. The choice of lattice depends on the quantum error-correcting code derived from the circuit. For example, surface codes correspond to square lattices, and cell codes correspond to hexagonal lattices. In some examples, this input can be provided by the user. However, in other examples, the faces can be inferred programmatically from the circuit. For some circuits, the face inference is direct. For example, a CNOT-based checksum extraction circuit for surface codes designates some qubits as data qubits and some qubits as auxiliary qubits. The coordinates of each auxiliary qubit correspond to the center of a face. The entire face is then defined by a CNOT gate supported by that center. For circuits consisting of one- and two-qubit measurements, such as those for Flokai codes, the plane embedding can be computed and used to identify these faces.

[0041] Some circuits, even those based on topological codes, may contain non-local checks within a lattice plane, or checks that do not belong to a lattice plane. For example, this can occur in circuits that prepare and measure logical operators for codes. Such global checks can interfere with the construction and performance of the topological decoder.

[0042] Some variations of Algorithm 1 consider this scenario. One option is to retain only those checks whose duration is below a certain cutoff value. For a typical checker extraction circuit that repeatedly applies a constant-depth circuit, the cutoff value would be proportional to the depth of the repeated sub-circuit. Another option is to modify line 8, which adds all unique checks obtained for a given face. In other examples, a suitable algorithm could only add checks that are not yet in the set. Those checks across the span. This is computationally more expensive, but ensures that a non-local check appears at most once in the set of checks.

[0043] Figure 7 Aspects of an example method 50 for correcting one or more faults in a qubit register of a quantum computer using Clifford circuits are illustrated. Generally, each Clifford circuit suitable for this method includes one or more Clifford gates and may also include one or more Pauli measurements.

[0044] At point 52 of method 50, the classical computer receives circuit data defining the Clifford circuit. At point 54, the classical computer selects a lattice based on the Clifford circuit and the desired type of quantum error-correcting code. For example, a square lattice can be selected when a surface code is required, or a hexagonal lattice can be selected when a cellular code is required. Operationally, the classical computer can make a decision about the lattice based on the circuit data received at point 52.

[0045] At point 56, the classical computer receives additional data identifying one or more measurements belonging to each of the multiple faces of the lattice. At point 58, the classical computer issues a result code based on the circuit data. The result code consists of a series of result checks, each corresponding to an expected error checker for the application of the Clifford circuit to the qubit register. Typically, the result code issued at point 58 is an arbitrary-based result code; it is not necessarily so at this stage of the process. Topology The resulting code may not be suitable for downstream topology decoding.

[0046] At point 60, the classical computer emits a topological result code based on circuit data, additional data, and the result code. The topological result code includes a series of checking operators that support quantum error correction via a topological decoder. In this way, method 50 enables fault correction in applications using Clifford circuits with qubit registers. In some examples, the topological result code may include a surface code; in others, it may include a Flokai code. Other types of topological result codes are also envisioned. Generally, each fault exposed and corrected in method 50 violates only two result checks of the topological result code, according to the topological decoding.

[0047] More specifically, when issuing the topological result code, the classical computer accumulates result checks along multiple timelines of multiple faces of the lattice at point 62. For each face of the lattice, the classical computer computes the shortened result code corresponding to that face at point 64. At point 66, the classical computer transforms (e.g., reorders) the multiple result checks of the shortened result code into a concise temporal order. In some examples, the concise temporal order is an order that reduces the overlap between result checks. In some examples, the concise temporal order is an order that reduces the duration of one or more result checks.

[0048] Method 50 allows for many variations and extensions. For example, the result code corresponding to the circuit may include at least one result check that is nonlocal within a plane of the lattice or is not part of any plane of the lattice. In some examples, the method can address this by retaining only result checks whose duration is below a predetermined threshold. In a more specific variation of the method, the Clifford circuit may be a checker extraction circuit, where sub-circuits of constant depth are repeatedly applied. Here, the threshold may be proportional to the constant depth. In other examples, where the result code includes result checks that are nonlocal within a plane of the lattice or are not part of any plane of the lattice, only those result checks that are not within the existing span of the accumulation set are accumulated—for example, line 8 of Algorithm 1.

[0049] Continuing with method 50, at position 68, the classical computer constructs a topology decoder for the topology result code. Generally, the topology decoder can be constructed based on the circuit data received at position 62. In some examples, the topology decoder is also constructed based on additional data received at position 64. At position 70, the topology decoder decodes the execution result of the topology result code to correct one or more faults in the application of the Clifford circuit to the qubit register. In some examples, the topology decoder is a minimum-weight perfect match or joint search decoder.

[0050] 4. References, Classic Computer Descriptions, and Conclusions Interested readers may refer to the following references, which are incorporated herein by reference for all purposes: [Reference 1] Nicolas Delfosse and Adam Paetznick, “Spacetime codes of Clifford circuits” (2023).

[0051] [Reference 2] Elwyn Berlekamp, ​​Robert McEliece, and Henk Van Tilborg, “On the inherent intractability of certain coding problems (corresp.)” IEEE Transactions on Information Theory 24:3, 384-386 (1978).

[0052] [Reference 3] Eric Dennis, Alexei Kitaev, Andrew Landahl, and John Preskill, “Topological quantum memory” Journal of Mathematical Physics Mathematical Physics 43:9, 4452-4505 (2002).

[0053] [Reference 4] Nicolas Delfosse and Naomi H. Nickerson, “Almost-linear time decoding algorithm for topological codes” quantum (Quantum) 5,595 (2021).

[0054] [Reference 5] Matthew B. Hastings and Jeongwan Haah, “Dynamically generated logical qubits” Quantum 5,564 (2021).

[0055] [Reference 6] Jeongwan Haah and Matthew B. Hastings, “Boundaries for the Honeycomb Code” Quantum ,693 (Apr 2022).

[0056] [Reference 7] Nicolas Delfosse, Adam Paetznick, Jeongwan Haah, Matthew Hastings and Marcus Silva, “Splitting decoder for quantum codes”.

[0057] The methods described herein can be bound to a computer system with one or more computing devices. Such methods and processes can be implemented as applications or services, application programming interfaces (APIs), libraries, and / or other computer program products.

[0058] Figure 8 A schematic diagram is provided of a classic computer 94 configured to provide some or all of the functions of the classic computer systems disclosed herein. The classic computer 94 may take the form of a personal computer, an application server computer, or any other computing device.

[0059] The classic computer 94 includes a logic system 96 and a computer memory system 98. The classic computer 94 may optionally include a display system 100, an input system 102, a network system 104, and / or other systems not shown in the figures.

[0060] The logical system 96 includes one or more physical devices configured to execute instructions. For example, the logical system may be configured to execute instructions that are part of the construction of at least one operating system (OS), application, service, and / or other program. The logical system may include at least one hardware processor (e.g., a microprocessor, central processing unit, central processing unit (CPU), and / or graphics processing unit (GPU)) configured to execute software instructions. Additionally or alternatively, the logical system may include at least one hardware or firmware device configured to execute hardware or firmware instructions. The processor of the logical system may be single-core or multi-core, and the instructions executed thereon may be configured for sequential, parallel, and / or distributed processing. The various components of the logical system may optionally be distributed among two or more separate devices that can be remotely located and / or configured for coordinated processing. Aspects of the logical system may be virtualized and executed by remotely accessible, networked computing devices configured for cloud computing.

[0061] Computer memory system 98 includes at least one physical device configured to temporarily and / or permanently store computer system information, such as data and instructions executable by logic system 96. When the computer memory system includes two or more devices, the devices can be located in the same location or remotely. Computer memory system 98 may include at least one volatile, non-volatile, dynamic, static, read / write, read-only, random access, sequential access, location-addressable, file-addressable, and / or content-addressable computer memory device. Computer memory system 98 may include at least one removable and / or built-in computer memory device. The state of computer memory system 98 can be changed—for example, to store different data—when the logic system executes instructions.

[0062] Various aspects of the logic system 96 and the computer memory system 98 can be integrated together into one or more hardware logic components. Any such hardware logic component may include, for example, at least one application-specific integrated circuit (PASIC / ASIC), application-specific standard product (PSSP / ASSP), system-on-a-chip (SOC), or complex programmable logic device (CPLD).

[0063] The logical system 96 and the computer memory system 98 can cooperate to instantiate one or more logical machines or engines. As used herein, the terms "machine" and "engine" each collectively refer to a combination of cooperating hardware, firmware, software, instructions, and / or any other components that provide functionality to the computer system. In other words, machines and engines are never abstract ideas and always have tangible forms. A machine or engine can be instantiated by a single computing device, or a machine or engine can include two or more sub-components instantiated by two or more different computing devices. In some implementations, a machine or engine includes a local component (e.g., a software application executed by the computer system processor) that cooperates with a remote component (e.g., a cloud computing service provided by a network of one or more server computer systems). The software and / or other instructions that give a particular machine or engine its functionality may optionally be stored as one or more unexecuted modules on one or more computer memory devices.

[0064] The machines and engines can be implemented using any suitable combination of machine learning (ML) and artificial intelligence (AI) techniques. Non-limiting examples of techniques that can be combined in the implementation of one or more machines include support vector machines, multilayer neural networks, convolutional neural networks (e.g., spatial convolutional networks for processing images and / or videos, and / or any other suitable convolutional neural networks configured to perform feature convolution and pooling across one or more temporal and / or spatial dimensions), recurrent neural networks (e.g., long short-term memory networks), associative memories (e.g., lookup tables, hash tables, Bloom filters, neural Turing machines, and / or neural random access memories), unsupervised spatial methods and / or clustering methods (e.g., nearest neighbor algorithms, topological data analysis, and / or k-means clustering), and / or graphical models (e.g., (hidden) Markov models, Markov random fields, (hidden) conditional random fields, and / or AI knowledge bases).

[0065] When included, display system 100 can be used to present a visual representation of data stored in computer memory system 98. In some examples, the visual representation may take the form of a graphical user interface (GUI). The display system may include one or more display devices utilizing virtually any type of technology. In some implementations, the display system may include one or more virtual, augmented, or mixed reality displays.

[0066] When included, input system 102 may include or interface with one or more input devices. Input devices may include sensor devices or user input devices. Examples of user input devices include a keyboard, mouse, or touchscreen.

[0067] When included, network system 104 can be configured to communicatively couple classic computer 94 to one or more other computer systems. The network system may include wired and / or wireless communication devices compatible with one or more different communication protocols. The network system can be configured to communicate via personal area networks, local area networks, and / or wide area networks.

[0068] In summary, one aspect of this disclosure relates to a method for correcting faults in a qubit register of a quantum computer using a Clifford circuit, the method comprising: (a) receiving circuit data defining the Clifford circuit; (b) receiving additional data identifying one or more measurements belonging to each of a plurality of faces of a lattice; (c) issuing a result code based on the circuit data, the result code comprising a series of result checks, each result check corresponding to an expected error checker for the application of the Clifford circuit to the qubit register; and (d) issuing a topological result code based on the circuit data, the additional data, and the result code, the topological result code comprising a series of check operators supported by a topology decoder for quantum error correction, thereby achieving fault correction in the application of the Clifford circuit to the qubit register.

[0069] In some implementations, the topological result code includes surface codes or Flokai codes. In some implementations, a fault is one of multiple faults, and each fault violates only two result checks. In some implementations, the method also includes selecting the lattice based on the class of the Clifford circuit and the quantum error-correcting code. In some implementations, the result code includes result checks that are non-local within a plane of the lattice or do not belong to any plane of the lattice, and the method also includes retaining the result check only if the duration of the result check is less than a predetermined threshold. In some implementations, the Clifford circuit is a checker extraction circuit in which sub-circuits of constant depth are repeatedly applied, and the threshold is proportional to the constant depth. In some implementations, issuing the topological result code includes accumulating result checks along multiple timelines in multiple planes of the lattice, and for each of the multiple planes of the lattice: calculating a shortened result code corresponding to that plane; and converting the multiple result checks of the shortened result code into a temporal order that reduces the overlap between result checks and / or the duration of one or more result checks in the result checks. In some implementations, the result code includes result checks that are nonlocal within a plane of the lattice or do not belong to any plane of the lattice, and only those result checks that are not within the existing span of the accumulation set are accumulated. In some implementations, the Clifford circuit includes one or more Clifford gates. In some implementations, the Clifford circuit includes one or more Pauli measurements. In some implementations, the method further includes: constructing a topology decoder for the topology result code; and decoding the execution result of the topology result code via the topology decoder to correct for faults in the application of the Clifford circuit to the qubit register. In some implementations, the topology decoder is a minimum-weight perfect-match or joint-lookup decoder. In some implementations, the topology decoder is constructed based on circuit data.

[0070] Another aspect of this disclosure relates to a computer system operatively coupled to a quantum computer, the computer system including a processor; and a computer memory operatively coupled to the processor having instructions that cause the processor to correct faults in a qubit register of a Clifford circuit applied to the quantum computer. The instructions include: (a) instructions for receiving circuit data defining the Clifford circuit; (b) instructions for receiving additional data identifying one or more measurements belonging to each of a plurality of faces of a lattice; (c) instructions for issuing a result code based on the circuit data, the result code including a series of result checks, each result check corresponding to an expected error checker for the application of the Clifford circuit to the qubit register; and (d) instructions for issuing a topological result code based on the circuit data, the additional data, and the result code, the topological result code including a series of check operators supporting quantum error correction via a topology decoder, thereby enabling fault correction in the application of the Clifford circuit to the qubit register.

[0071] In some implementations, the instructions also include instructions for selecting the lattice based on the class of the Clifford circuit and the quantum error-correcting code. In some implementations, issuing the topological result code involves accumulating result checks along multiple timelines on multiple faces of the lattice, and for each face of the lattice: calculating a shortened result code corresponding to that face; and converting the multiple result checks of the shortened result code into a temporal order that reduces overlap between result checks and / or the duration of one or more result checks in the result checks. In some implementations, the instructions also include instructions for constructing a topological decoder for the topological result code; and decoding the execution result of the topological result code via the topological decoder to correct faults in the application of the Clifford circuit to the qubit register. In some implementations, the topological decoder is a minimum-weight perfect-match or joint-lookup decoder. In some implementations, the topological decoder is constructed based on circuit data.

[0072] Another aspect of this disclosure relates to a method for correcting faults in a qubit register of a quantum computer using a Clifford circuit. The method includes: (a) receiving circuit data defining the Clifford circuit; (b) receiving additional data identifying one or more measurements belonging to each of a plurality of faces of a lattice; (c) issuing a result code based on the circuit data, the result code including a series of result checks, each result check corresponding to an expected error checker for the application of the Clifford circuit to the qubit register; and (d) issuing a topological result code based on the circuit data, the additional data, and the result code, the topological result code including a series of check operators supporting quantum error correction via a topology decoder, thereby enabling fault correction in the application of the Clifford circuit to the qubit register, and issuing the topological result code includes accumulating result checks along a plurality of timelines along the plurality of faces of the lattice, and for each of the plurality of faces of the lattice, calculating a shortened result code corresponding to that face, and converting the plurality of result checks of the shortened result code into a temporal order that reduces overlap between result checks and / or the duration of one or more result checks in the result checks.

[0073] This disclosure is presented by way of example and with reference to the accompanying drawings. Components, process steps, and other elements that may be substantially the same are identified and described in a coordinated manner with minimal repetition in one or more drawings. However, it should be noted that the elements identified in a coordinated manner may also differ to some extent. It will be further noted that the drawings are schematic and are generally not drawn to scale. Rather, the various drawing scales, aspect ratios, and numbers of components shown in the figures may be intentionally distorted to make certain features or relationships easier to see. Unless otherwise stated, the curves shown in the drawings are theoretical.

[0074] It should be understood that the configurations and / or methods described herein are exemplary in nature, and these particular embodiments or examples should not be considered limiting, as many variations are possible. The specific routines or methods described herein may represent one or more of any number of processing strategies. Therefore, the various actions shown and / or described may be performed in the order shown and / or described, in a different order, in parallel, or omitted. Similarly, the order of the above processes may be changed. In this spirit, the phrase "at least in part based on" is intended to remind the reader that the functional and / or conditional logic shown herein neither requires nor excludes suitable additional logic performed in combination with the shown logic to provide additional benefits.

[0075] The subject matter of this disclosure includes all novel and non-obvious combinations and sub-combinations of the various processes, systems and configurations disclosed herein, as well as any and all equivalents thereof.

Claims

1. A method (50) for correcting faults in a qubit register (12) of a quantum computer (10) using a Clifford circuit, the method comprising: Receive (52) the circuit data defining the Clifford circuit; Receive (56) additional data, which identifies one or more measurements belonging to each of the multiple faces (48) of the lattice (44); Based on the circuit data, a result code (58) is issued, the result code comprising a series of result checks, each result check corresponding to an expected error checker for the application of the Clifford circuit to the qubit register; as well as Based on the circuit data, the additional data, and the result code, a (60) topology result code is issued, which includes a series of checking operators that support quantum error correction via a topology decoder, thereby enabling fault correction in the application of the Clifford circuit to the qubit register.

2. The method according to claim 1, wherein the topology result code includes surface code or Flokai code.

3. The method of claim 1, wherein the fault is one of a plurality of faults, and wherein each fault violates only two result checks.

4. The method of claim 1, further comprising selecting a lattice based on the type of the Clifford circuit and the quantum error-correcting code.

5. The method of claim 1, wherein the result code includes a result check that is non-local within a plane of the lattice or does not belong to any plane of the lattice, and the method further includes retaining the result check only if the duration of the result check is less than a predetermined threshold.

6. The method of claim 5, wherein the Clifford circuit is a checksum extraction circuit in which a sub-circuit of constant depth is repeatedly applied, and wherein the threshold is proportional to the constant depth.

7. The method of claim 1, wherein issuing the topology result code comprises accumulating result checks along multiple timelines of the plurality of faces of the lattice, and for each of the plurality of faces of the lattice: Calculate the resulting code corresponding to the shortening of this surface; and The multiple result checks of the shortened result code are converted into a temporal order, which reduces the overlap between the result checks and / or the duration of one or more result checks in the result check.

8. The method of claim 1, wherein the result code comprises result checks that are non-local within the plane of the lattice or do not belong to any plane of the lattice, and wherein only those result checks that are not within the existing span of the accumulation set are accumulated.

9. The method of claim 1, wherein the Clifford circuit comprises one or more Clifford gates.

10. The method of claim 1, wherein the Clifford circuit includes one or more Pauli measurements.

11. The method of claim 1, further comprising: A topology decoder is constructed based on the topology results. as well as The execution result of the topology result code is decoded via the topology decoder to correct the fault in the application of the Clifford circuit to the qubit register.

12. The method of claim 11, wherein the topology decoder is a minimum weight perfect match or joint search decoder.

13. The method of claim 11, wherein the topology decoder is constructed based on the circuit data.

14. A computer system (94) operatively coupled to a quantum computer (10), said computer system comprising: Processor (96); as well as A computer memory (98) operably coupled to the processor has instructions that cause the processor to correct faults in the qubit register (12) of the quantum computer using a Clifford circuit, the instructions including: Instructions for receiving (52) the circuit data defining the Clifford circuit, Instructions for receiving (56) additional data, which identifies one or more measurements belonging to each of the plurality of faces of the lattice. Instructions for issuing (58) result codes based on the circuit data, the result codes comprising a series of result checks, each result check corresponding to an expected error checker for the application of the Clifford circuit to the qubit register, and Instructions for issuing (60) topology result codes based on the circuit data, the additional data, and the result codes, the topology result codes including a series of checking operators that support quantum error correction via a topology decoder, thereby enabling fault correction in the application of the Clifford circuit to the qubit register.

15. The computer system of claim 14, wherein the instructions further include instructions for selecting a lattice based on the type of the Clifford circuit and the quantum error-correcting code.

16. The computer system of claim 14, wherein issuing the topology result code comprises accumulating result checks along multiple timelines of the plurality of faces of the lattice, and for each of the plurality of faces of the lattice: Calculate the resulting code corresponding to the shortening of this surface; and The multiple result checks of the shortened result code are converted into a temporal order, which reduces the overlap between the result checks and / or the duration of one or more result checks in the result check.

17. The computer system of claim 14, wherein the instructions further include instructions for: Construct a topology decoder based on the topology result code; and The execution result of the topology result code is decoded via the topology decoder to correct the fault in the application of the Clifford circuit to the qubit register.

18. The computer system of claim 17, wherein the topology decoder is a minimum weight perfect match or joint search decoder.

19. The computer system of claim 17, wherein the topology decoder is constructed based on the circuit data.

20. A method (50) for correcting faults in a qubit register (12) of a quantum computer (10) using a Clifford circuit, the method comprising: Receive (52) the circuit data defining the Clifford circuit; Receive (56) additional data, which identifies one or more measurements belonging to each of the multiple faces (48) of the lattice (44); Based on the circuit data, a result code (58) is issued, the result code comprising a series of result checks, each result check corresponding to an expected error checker for the application of the Clifford circuit to the qubit register; as well as Based on the circuit data, the additional data, and the result code, a (60) topology result code is issued, which includes a series of checking operators supported by a topology decoder to enable fault correction in the application of the Clifford circuit to the qubit register. The issuance of the topology result code includes accumulating (62) result checks along multiple timelines of the plurality of faces of the lattice, and for each of the plurality of faces of the lattice, Calculate (64) the result code corresponding to the shortening of the face, and The multiple result checks of the shortened result code are converted (66) into a temporal order, which reduces the overlap between the result checks and / or the duration of one or more result checks in the result check.

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