Semiconductor device having first and second dopant diffusion regions

Abstract

The invention relates to a semiconductor device (100), the semiconductor device (100) comprising: a chip layer (101); the groove (111) extends into the chip layer (101), and the groove (111) comprises a groove bottom (111a) and a groove side wall (111b); a first dopant injection region (5a) arranged below the trench bottom (111a); a second dopant injection region (5b) arranged below the first dopant injection region (5a); a first dopant diffusion layer (5d) extending in a lateral direction of the first dopant injection region (5a); and a second dopant diffusion layer (5c) extending in a lateral direction of the second dopant injection region (5b), in which an extension (105c) of the second dopant diffusion region (5c) in the lateral direction matches an extension of the first dopant diffusion layer (5d) in the lateral direction.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology for power device applications (e.g., wide-bandgap power devices). The invention specifically relates to a semiconductor device having a first doped diffusion region and a second doped diffusion region, and a method for manufacturing such a semiconductor device using spacers. Background Technology

[0002] Vertical power semiconductor devices, such as currently available SiC devices, exhibit a specific design window for optimizing drain-source on-resistance (Rdson) performance. To further reduce Rdson, it is generally planned to reduce the pitch in next-generation semiconductor devices. Due to the presence of a host / well in MOS structures, the JFET effect is enhanced, leading to a strong reverse increase in Rdson. To date, there is no solution to address this JFET effect when reducing the pitch. Summary of the Invention

[0003] The present invention provides a solution to overcome the limitations caused by the enhanced JFET effect.

[0004] This invention provides a method for reducing the spacing of vertical power semiconductor devices without significantly enhancing the JFET effect.

[0005] The above and other objectives are achieved through the features of the independent claim. Other implementations will be apparent from the dependent claims, the description, and the drawings.

[0006] Embodiments of the present invention provide a method for controlling the distance between substrates by reducing misalignment sensitivity, thereby controlling the JFET effect. The present invention discloses a silicon carbide (SiC) multiple self-aligned substrate using spacers.

[0007] The presence of a host / well in vertical power devices is unavoidable because the host / well has the following basic functions: (1) providing a host for forming the channel region; (2) shielding the dielectric of the device (such as the gate dielectric); (3) serving as the preferred location for impact ionization, etc.

[0008] The distance between the substrates is one of the key parameters controlling the JFET effect: the longer the distance, the weaker the JFET effect, and therefore the more favorable it is for current conduction. In this sense, one can understand that the longer the distance, the better. However, advanced next-generation technologies require shrinking device size / spacing (basic unit) to reduce device area, thereby reducing the cost and resistance per chip. This reduction in spacing directly leads to a shorter distance between the substrates.

[0009] These competing effects result in an optimal design window (spacing range) within which the minimum Rdson value (maximum current capacity) can be achieved. Figure 1 This situation is illustrated.

[0010] The subject / well is typically implanted into regions defined by photolithography. Controlling the distance between subjects is crucial, which becomes increasingly difficult in advanced technologies because the spacing (and all distances) shrinks.

[0011] As described above, the continued reduction in the required spacing for future technologies leads to the following consequences: a larger Rdson value results in a stronger JFET effect, which is counterproductive; lithographic misalignment effects are amplified, making device performance difficult to control. Embodiments of this invention provide a scheme for controlling this JFET effect.

[0012] The following describes a process for forming a host through self-aligned implantation using spacers, which is less sensitive to misalignment compared to photolithography. The implantation of the self-aligned host is divided into more than one step, using spacers that are thicker (wider) than the shallower portions to implant the deeper portions of the host.

[0013] The solution described in this article is applicable to any power conversion system or architecture that uses semiconductor power devices. It is suitable for scenarios requiring high blocking voltage, high current density, and high switching frequency. For example, it is applicable to inductive switching circuits where current freewheeling is required during the power semiconductor device's turn-off period, i.e., reverse conduction mode. This solution is applicable to all power electronic systems where the goal is to reduce energy loss, application scale, and total cost of ownership.

[0014] Products using this solution include all power electronic products, especially DC and AC converters used in photovoltaic, electric vehicles, chargers and on-board chargers, data centers, railways, telecommunications, servers and other fields.

[0015] The following terms and symbols are used to describe the invention in detail.

[0016] MOS (Metal Oxide Semiconductor) FET (Field Effect Transistor) MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) IGBT (Insulated Gate Bipolar Junction Transistor) SiC (Silicon Carbide) CSL Current Spreading Layer JFET (Junction Field Effect Transistor) SBD Schottky Barrier Diode JSBD Junction Schottky Barrier Diode SSF Shockley Stacking Faults Basal Plane Dislocation (BPD) Device active area: The region that conducts forward current; the device active area is smaller than the total device area. Device total area: This can be understood as the chip / die area; it consists of the active area and all peripheral areas, such as edge terminations, scribe lines (cut tracks), contact pads (e.g., gate contacts), etc. Forward electric current: The main current flowing through the device when it is in the on state. Edge termination: The area extending beyond the active region. The function of edge termination is to reduce the electric field outside the device. Source: The region in a MOSFET that injects majority carriers when the MOSFET is on. Drain: The region in a MOSFET that collects majority carriers when the MOSFET is on. Emitter: A region in an IGBT that injects majority carriers when the IGBT is on. Collector: The region in an IGBT that collects majority carriers and injects minority carriers when the IGBT is on. Majority carriers: Electric carriers (electrons or holes) that dominate forward current conduction; the density of majority carriers is much greater than the density of minority carriers. Minority carriers: Electric carriers (electrons or holes) whose density is much smaller than that of majority carriers. Gate: The voltage control region in a MOSFET or IGBT, used to switch the device between on and off states. Drift layer: A region in a MOSFET or IGBT that conducts current in the on-state and withstands the maximum applied voltage (blocking voltage) in the off-state (blocking state). Channel: A region in the body region of a MOSFET or the base region of an IGBT, where charge carriers are injected from either the source or the emitter. The conduction of the channel is controlled by the gate. Body region: A region in a MOSFET where the doping type is opposite to that of the source and drift layer. The body region contains the channel and forms a pn junction with the drift layer. Base region: The region in an IGBT. The doping type of the base region is opposite to that of the source and drift layers. The base region contains the channel and forms a pn junction with the drift layer. JFET region: The region located between the body region or base region of the MOSFET or IGBT. CSL: The region below the JFET region. The function of CSL is to disperse current to reduce on-state resistance. According to a first aspect, the present invention relates to a semiconductor device, the semiconductor device comprising: a chip layer; a trench extending into the chip layer, wherein the trench includes a trench bottom and trench sidewalls; a first dopant implantation region disposed below the trench bottom; a second dopant implantation region disposed below the first dopant implantation region; a first dopant diffusion layer extending in a lateral direction along the first dopant implantation region; and a second dopant diffusion layer extending in a lateral direction along the second dopant implantation region; wherein the extension of the second dopant diffusion region in the lateral direction matches the extension of the first dopant diffusion layer in the lateral direction.

[0017] This device provides a way to precisely control the host without being affected by unwanted misalignment; this improves device performance and reduces performance variations in the wafer chip.

[0018] The term "matching" here refers not only to alignment, i.e., the lateral extension of two dopant diffusion regions such that their lateral surfaces lie on the same plane, but also to a design where the first and second diffusion layers have a predetermined width relationship, i.e., a predetermined distance exists between the lateral surfaces of the first and second diffusion layers. This width relationship design is illustrated in the embodiment shown below.

[0019] In one exemplary implementation of the semiconductor device, the first dopant implantation region is obtained by first implanting a dopant into the trench; the second dopant implantation region is obtained by second implanting a dopant into the trench after forming a spacer on the trench sidewall; the first dopant diffusion layer is obtained by diffusion or scattering of the first dopant implantation region in the lateral direction; and the second dopant diffusion layer is obtained by diffusion or scattering of the second dopant implantation region in the lateral direction.

[0020] By using appropriate spacers, the extension of the second dopant diffusion region in the lateral direction can be efficiently matched with the extension of the first dopant diffusion layer in the lateral direction. Through such implantation and diffusion / scattering steps, along with the spacers, the width of the diffusion layer can be optimally controlled or designed.

[0021] Dopant diffusion can also occur in the vertical direction, but since it is irrelevant to this invention, it will not be discussed further. It is understood that this invention also covers such vertical diffusion.

[0022] In one exemplary implementation of the semiconductor device, the first dopant implantation region is formed by a first self-aligned implantation of the trench; the second dopant implantation region is formed by a second self-aligned implantation of the trench, wherein the trench sidewalls are covered by the spacer.

[0023] These self-alignment processing steps provide precise control over the main design and are not affected by unwanted misalignment, which improves device performance and reduces performance variations in wafer chips.

[0024] In one exemplary implementation of the semiconductor device, the semiconductor device includes: a substrate of a first semiconductor doping type; a buffer layer of the first semiconductor doping type located on top of the substrate; a drift layer of the first semiconductor doping type located on top of the buffer layer; a current spreading layer of the first semiconductor doping type located on top of the drift layer; a trench body region of the second semiconductor doping type formed in the trench located on top of the current spreading layer; a trench source region of the first semiconductor doping type formed in the trench body region; a mesa Schottky region of the first semiconductor doping type formed in the mesa portion of the semiconductor device; and a spacer gate region formed on the trench sidewall, wherein the first dopant implantation region, the second dopant implantation region, the first dopant diffusion layer, and the second dopant diffusion layer form the trench body region.

[0025] In this semiconductor device, the trench body region can be precisely formed through the design of the dopant diffusion layer described above.

[0026] This implementation corresponds to Embodiment 1, which will be further described below with reference to Figure 4a.

[0027] In one exemplary implementation of the semiconductor device, the edge of the trench body region is separated from the edge of the trench sidewall.

[0028] In this type of semiconductor device, the space between the edge of the trench body region and the trench sidewall can be precisely designed.

[0029] This implementation corresponds to Embodiment 1, which will be further described below with reference to Figure 4a.

[0030] In one exemplary implementation of the semiconductor device, the semiconductor device includes: a substrate of a first semiconductor doping type; a buffer layer of the first semiconductor doping type located on top of the substrate; a drift layer of the first semiconductor doping type located on top of the buffer layer; a current spreading layer of the first semiconductor doping type located on top of the drift layer; a trench body region of the second semiconductor doping type formed in the trench located on top of the current spreading layer; a trench source region of the first semiconductor doping type formed in the trench body region; a mesa separation region of the first semiconductor doping type formed in the mesa portion of the semiconductor device; a mesa body region of the second semiconductor doping type formed on top of the mesa separation region; a mesa source region of the first semiconductor doping type formed on top of the mesa body region; and a spacer gate region formed on the trench sidewall, wherein the first dopant implantation region, the second dopant implantation region, the first dopant diffusion layer, and the second dopant diffusion layer form the trench body region.

[0031] In this semiconductor device, the trench body region can be precisely formed through the design of the dopant diffusion layer described above.

[0032] This implementation corresponds to Embodiment 2, which will be further described below with reference to Figure 4b.

[0033] In one exemplary implementation of the semiconductor device, the edge of the trench body region is separated from the edge of the trench sidewall.

[0034] Similar to the above embodiments, in this embodiment of the semiconductor device, the space between the edge of the trench body region and the trench sidewall can also be precisely designed.

[0035] This implementation corresponds to Embodiment 2, which will be further described below with reference to Figure 4b.

[0036] In one exemplary implementation of the semiconductor device, the semiconductor device includes: a substrate of a first semiconductor doping type; a buffer layer of the first semiconductor doping type located on top of the substrate; a drift layer of the first semiconductor doping type located on top of the buffer layer; a current spreading layer of the first semiconductor doping type located on top of the drift layer; a trench body region of the second semiconductor doping type formed in the trench located on top of the current spreading layer; a trench source region of the first semiconductor doping type formed in the trench body region; a mesa separation region of the first semiconductor doping type formed in the mesa portion of the semiconductor device; a mesa body region of the second semiconductor doping type formed on top of the mesa separation region; a mesa source region of the first semiconductor doping type formed on top of the mesa body region; a mesa body contact formed on top of the mesa body region and used for electrically connecting the mesa body region; and a spacer gate region formed on the trench sidewall, wherein the trench body region is formed by the first dopant implantation region, the second dopant implantation region, the first dopant diffusion layer, and the second dopant diffusion layer.

[0037] In this implementation of a semiconductor device with mesa body contacts, the trench body region can also be precisely generated, as described above.

[0038] This implementation corresponds to Embodiment 3, which will be further described below without referring to the accompanying drawings.

[0039] In one exemplary implementation of the semiconductor device, the edge of the trench body region is separated from the edge of the trench sidewall.

[0040] In this embodiment of the semiconductor device, the space between the edge of the trench body region and the trench sidewall can also be precisely designed, as described above.

[0041] This implementation corresponds to Embodiment 3, which will be further described below without referring to the accompanying drawings.

[0042] In one exemplary implementation of the semiconductor device, the edge of the trench body region is aligned with the edge of the trench sidewall.

[0043] The edges of the main trench area and the edges of the trench sidewalls can be precisely aligned so that both can be located on a common plane.

[0044] This implementation corresponds to Embodiments 4 and 5. Embodiments 4 and 5 will be further described below with reference to Figures 5a and 5b. This implementation also corresponds to Embodiment 6, which is not shown in the figures.

[0045] In one exemplary implementation, the semiconductor device includes a second trench body region formed below the trench body region; wherein the edge of the second trench body region is spaced apart from the edge of the trench sidewall.

[0046] This implementation corresponds to Embodiment 7, which will be further described below with reference to Figure 6a.

[0047] In one exemplary implementation of the semiconductor device, the second trench body region is formed by another first dopant implantation region, another second dopant implantation region, another first dopant diffusion layer, and another second dopant diffusion layer.

[0048] This implementation corresponds to Embodiment 7, which will be further described below with reference to Figure 6a.

[0049] In one exemplary implementation, the semiconductor device includes a second trench body region formed below the trench body region; wherein the edge of the second trench body region is spaced apart from the edge of the trench sidewall.

[0050] This implementation corresponds to Embodiment 8, which will be further described below with reference to Figure 6b.

[0051] In one exemplary implementation of the semiconductor device, the second trench body region is formed by another first dopant implantation region, another second dopant implantation region, another first dopant diffusion layer, and another second dopant diffusion layer.

[0052] This implementation corresponds to Embodiment 8, which will be further described below with reference to Figure 6b.

[0053] In one exemplary implementation, the semiconductor device includes a second trench body region formed below the trench body region; wherein the edge of the second trench body region is spaced apart from the edge of the trench sidewall.

[0054] This implementation corresponds to Example 9, which is not shown in the figure.

[0055] In one exemplary implementation of the semiconductor device, the second trench body region is formed by another first dopant implantation region, another second dopant implantation region, another first dopant diffusion layer, and another second dopant diffusion layer.

[0056] This implementation corresponds to Example 9, which is not shown in the figure.

[0057] In one exemplary implementation, the semiconductor device includes a second trench body region formed below the trench body region; wherein the edge of the second trench body region is spaced apart from the edge of the trench sidewall.

[0058] This implementation corresponds to Embodiment 10, which will be further described below with reference to Figure 7a.

[0059] In one exemplary implementation of the semiconductor device, the second trench body region is formed by another first dopant implantation region, another second dopant implantation region, another first dopant diffusion layer, and another second dopant diffusion layer.

[0060] This implementation corresponds to Embodiment 10, which will be further described below with reference to Figure 7a.

[0061] In one exemplary implementation, the semiconductor device includes a second trench body region formed below the trench body region; wherein the edge of the second trench body region is spaced apart from the edge of the trench sidewall.

[0062] This implementation corresponds to Embodiment 11, which will be further described below with reference to Figure 7b.

[0063] In one exemplary implementation of the semiconductor device, the second trench body region is formed by another first dopant implantation region, another second dopant implantation region, another first dopant diffusion layer, and another second dopant diffusion layer.

[0064] This implementation corresponds to Embodiment 11, which will be further described below with reference to Figure 7b.

[0065] In one exemplary implementation, the semiconductor device includes a second trench body region formed below the trench body region; wherein the edge of the second trench body region is spaced apart from the edge of the trench sidewall.

[0066] This implementation corresponds to Example 12, which is not shown in the figure.

[0067] In one exemplary implementation of the semiconductor device, the second trench body region is formed by another first dopant implantation region, another second dopant implantation region, another first dopant diffusion layer, and another second dopant diffusion layer.

[0068] This implementation corresponds to Example 12, which is not shown in the figure.

[0069] According to a second aspect, the present invention relates to a method for manufacturing a semiconductor device, the method comprising: forming a chip layer; forming a trench in the chip layer, wherein the trench includes a trench bottom and trench sidewalls; injecting a dopant into the trench to form a first dopant injection region below the trench bottom; forming spacers at the trench sidewalls; injecting a dopant into the trench, wherein the trench sidewalls are covered by the spacers to form a second dopant injection region below the first dopant injection region; wherein the thickness of the spacers matches the width of a second dopant diffusion layer, the second dopant diffusion layer being formed by diffusion in the lateral direction of the second dopant injection region.

[0070] This approach provides a method for precisely controlling the host design without being affected by unwanted misalignments; this improves device performance and reduces performance variations on the wafer. The method is based on a spacer design that allows for precise control of the diffusion layer dimensions.

[0071] In an exemplary implementation of the method, the first dopant injection region is formed by performing a first self-aligned injection on the trench; the second dopant injection region is formed by performing a second self-aligned injection on the trench, and the trench sidewalls are covered by the spacer.

[0072] These self-alignment processing steps provide precise control over the main design and are not affected by unwanted misalignment, which improves device performance and reduces performance variations in wafer chips. Attached Figure Description

[0073] Other embodiments of the invention will be described with reference to the following figures, in which: Figure 1 A schematic diagram is shown showing how the drain-source on-resistance (Rdson) varies with the spacing of the mesa portions in a SiC trench planar Schottky barrier diode semiconductor device; Figure 2 A schematic cross-sectional view of a semiconductor device 100 according to the present invention is shown; Figure 3 A schematic diagram of an exemplary process flow for a method of manufacturing a semiconductor device according to the present invention is shown; Figure 4a shows a schematic cross-sectional view of the semiconductor device 100a according to the first embodiment; Figure 4b shows a schematic cross-sectional view of the semiconductor device 100b according to the second embodiment; Figure 5a shows a schematic cross-sectional view of the semiconductor device 100c according to the fourth embodiment; Figure 5b shows a schematic cross-sectional view of the semiconductor device 100d according to the fifth embodiment; Figure 6a shows a schematic cross-sectional view of the semiconductor device 100e according to the seventh embodiment; Figure 6b shows a schematic cross-sectional view of the semiconductor device 100f according to the eighth embodiment; Figure 7a shows a schematic cross-sectional view of the semiconductor device 100g according to the tenth embodiment; Figure 7b shows a schematic cross-sectional view of the semiconductor device 100h according to the eleventh embodiment. Detailed Implementation

[0074] In the following detailed description, reference is made to the accompanying drawings, which form part of this invention, and which illustrate specific aspects in which the invention may be practiced by way of illustration. It should be understood that other aspects and changes to the structure or logic may be made without departing from the scope of the invention. Therefore, the following detailed description should not be construed in a limiting sense, and the scope of the invention is defined by the appended claims.

[0075] It should be understood that the description relating to the described method also applies to the corresponding device or system for performing the method, and vice versa. For example, if specific method steps are described, the corresponding device may include a unit that performs the described method steps, even if that unit is not explicitly described or shown in the figures. Furthermore, it should be understood that, unless otherwise expressly stated, features of the various exemplary aspects described herein can be combined with each other.

[0076] Figure 1 This diagram illustrates how the drain-source on-resistance (Rdson) varies with the spacing of the mesa portions in a SiC trench planar Schottky barrier diode semiconductor device.

[0077] from Figure 1 As can be seen, SiC devices exhibit a specific process window for optimizing Rdson performance. To further reduce Rdson, it is planned to reduce the spacing in next-generation semiconductor devices. This will lead to a strong reverse increase in Rdson due to the enhanced JFET effect.

[0078] from Figure 1 As can be seen, by reducing the pitch (e.g., in next-generation semiconductor devices), Rdson decreases until it reaches its minimum value. Further reducing the pitch leads to an increase in Rdson, due to the enhanced JFET effect.

[0079] The present invention provides a scheme for designing a semiconductor device that can better control the operation of a JFET in order to extend the minimum value of Rdson to a smaller pitch value (in other words, reducing the pitch while keeping the operation of the JFET under control).

[0080] Figure 2 A schematic cross-sectional view of a semiconductor device 100 according to the present invention is shown.

[0081] Semiconductor device 100 includes a chip layer 101 and a trench 111 extending into the chip layer 101. The trench 111 includes a trench bottom 111a and trench sidewalls 111b. Figure 2 The example shown has two trenches 111. Chip layer 101 may include any other number of trenches 111.

[0082] The semiconductor device 100 includes a first dopant implantation region 5a disposed below the bottom of a trench 111a, a second dopant implantation region 5b disposed below the first dopant implantation region 5a, a first dopant diffusion layer 5d extending in the lateral direction of the first dopant implantation region 5a, and a second dopant diffusion layer 5c extending in the lateral direction of the second dopant implantation region 5b.

[0083] The lateral extension 105c of the second dopant diffusion region 5c matches the lateral extension of the first dopant diffusion layer 5d.

[0084] This device provides a way to precisely control the main body design without being affected by unnecessary misalignment; this improves device performance and reduces performance variations in the wafer chip.

[0085] The term “matching” here not only means alignment, i.e., the lateral extension of the two dopant diffusion regions 5c and 5d such that their lateral surfaces lie on the same plane, but also indicates a design in which the first diffusion layer and the second diffusion layer have a predetermined width relationship, i.e., there is a predetermined distance between the lateral surfaces of the first diffusion layer and the lateral surfaces of the second diffusion layer.

[0086] The design of this width relationship is illustrated in the embodiment shown below.

[0087] The first dopant implantation region 5a can be obtained by first implanting dopant into the trench 111. The second dopant implantation region 5b can be obtained by forming spacers at the trench sidewall 111b (e.g., as described below). Figure 3 The dopant was obtained by injecting the spacer 154 shown into the trench 111 a second time.

[0088] The first dopant diffusion layer 5d can be obtained by diffusion or scattering in the lateral direction through the first dopant implantation region 5a. The second dopant diffusion layer 5c can be obtained by diffusion or scattering in the lateral direction through the second dopant implantation region 5b.

[0089] It should be noted that dopant diffusion can also occur in the vertical direction (which will not be discussed further as it is not relevant to this invention).

[0090] The first dopant implantation region 5a can be formed by performing a first self-aligned implantation on the trench 111 as described below. The second dopant implantation region 5b can be formed by performing a second self-aligned implantation on the trench 111, wherein the trench sidewall 111b is covered by spacers 154, as described below.

[0091] Figure 3 A schematic diagram of an exemplary process flow for a method of manufacturing a semiconductor device according to the present invention is shown.

[0092] The proposed solution relies on the following two main aspects: (1) a process for forming the subject by self-aligned injection through spacers, which is less sensitive to misalignment compared to photolithography; (2) the injection of the self-aligned subject is divided into more than one step, and the deep part of the subject is injected through spacers that are thicker (wider) than the shallow part.

[0093] This method is in Figure 3 The diagram is shown in a simplified form, in which the standard process 300a is compared with the proposed improved process 300b of the present invention.

[0094] Figure 3 The top portion shows standard process 300a, including steps 301, 302, 303, and 304.

[0095] Step 1 (Photolithography) 301: In this step 301, a photolithographic mask is applied and developed to form an opening on the region on top of the semiconductor surface where the future trench will be formed.

[0096] Step 2 (Trench Etching) 302: Forming trenches.

[0097] Step 3 (Injection) 303: Inject one or more different doses and energies into the body. Several injectables are typically required to define the threshold voltage and form the bottom body / shield.

[0098] Step 4, or 304: This step encompasses all subsequent steps in the process flow. A relevant issue to mention is that scattering (e.g., in the case of SiC) or diffusion (e.g., in the case of Si) causes the implanted body to extend in space. For clarity, only the extension at 311 is shown. In reality, 310 also extends; however, the deeper the implant (the higher the energy), the more it extends.

[0099] Figure 3 The bottom portion shows a new concept or improved process 300b according to the present invention, including steps 301, 302, 302a, 302b, 303a, 303b, 304a, and 304b.

[0100] Step 1 (Photolithography) 301: In this step 301, a photolithographic mask is applied and developed to form an opening on the region on top of the semiconductor surface where the future trench will be formed. This step 1 is similar to step 1 in the standard method described above.

[0101] Step 2 (Trench Etching) 302: Forming trenches. This step 2 is similar to step 2 in the standard method described above.

[0102] Step 2.a (Injection 1) 302a: Self-align the shallow portion 310 of the body into the trench, or a thin sacrificial dielectric may be deposited prior to injection to avoid unnecessary injection at the sidewalls.

[0103] Step 2.b (Layer Deposition) 302b: Deposit a layer in a conformal manner. This layer can be any material that can block the injected material. This layer can be a dielectric (such as oxides, nitrides, etc.), metal, alloy, etc.

[0104] Step 3.a (Layer Etching) 303a: Spacers 154 are formed on the sidewalls of the trench by a combination of anisotropic and isotropic etching of the deposited layer.

[0105] Step 3.b (Injection 2) 303b: The deep portion 311 of the body is self-aligned and injected into the spacer 154. The spacer 154 serves as a mask. The formed deep body 311 retracts toward the shallow body 310, and the retracted portion is proportional to the width of the spacer 154, which in turn is proportional to the thickness of the deposited layer.

[0106] Step 4a, or 304a: Remove spacer 154 and proceed with the remaining processes.

[0107] Step 4b, or 304b: A relevant issue to mention is that scattering (e.g., in the case of SiC) or diffusion (e.g., in the case of Si) causes the injected body to extend in space. However, the controllable retraction of the deep body 311 can be adjusted to control the deep body 311 toward the final edge of the shallow body 310. The space 312 between the bodies can also be controlled.

[0108] It should be noted that in the simplified improved process flow 300b described above (including steps 301, 302, 302a, 302b, 303a, 303b, 304a, and 304b), the shallow body 310 is injected first. It should be understood that any order is acceptable.

[0109] It should also be noted that in the simplified process described above, the shallow body 310 is self-aligned and injected into the trench. It should be understood that injection via spacers is also possible, in the same manner described for the deep body 311. The thickness of the spacers can be adjusted to produce any desired effect on the final edge of the shallow body 310.

[0110] The advantage of the idea proposed in this invention is that it provides a solution for precisely controlling the main body design without being affected by unnecessary misalignment; this improves device performance and reduces performance variations in wafer chips.

[0111] The process steps 301, 302, 302a, 302b, 303a, 303b, 304a, and 304b of the above-mentioned improved process flow 300b can be formulated into a method based on the following content.

[0112] A method for manufacturing semiconductor devices (e.g.) Figure 2 The method of the semiconductor device 100 shown or any one of the semiconductor devices 100a, 100b, 100c, 100d, 100e, 100f, 100g, 100h described below includes: Forming chip layer 101; A trench 111 is formed in the chip layer 101, wherein the trench 111 includes a trench bottom 111a and a trench sidewall 111b, as shown below. Figure 2 As shown; Dopant is injected into trench 111 to form a first dopant injection region 5a below the bottom 111a of the trench; Spacers 154 are formed at the trench sidewall 111b, such as Figure 3 As shown; Dopant is injected into trench 111, wherein the trench sidewall 111b is covered by spacers to form a second dopant injection region 5b below the first dopant injection region 5a; The thickness of the spacer matches the width of the second dopant diffusion layer 5c, which is formed by diffusion of the second dopant injection region 5b in the lateral direction.

[0113] The method also includes: The first dopant implantation region 5a is formed by performing a first self-aligned implantation in trench 111; A second dopant implantation region 5b is formed by a second self-aligned implantation into trench 111, and the trench sidewall 111b is covered by spacers.

[0114] Figure 4a shows a schematic cross-sectional view of the semiconductor device 100a according to the first embodiment. The semiconductor device 100a is described above in conjunction with... Figure 2 An embodiment of the general design of the proposed and described semiconductor device 100.

[0115] Semiconductor device 100a includes: a substrate 1 of a first semiconductor doping type, denoted here by reference numeral n(1); a buffer layer 2 of a first semiconductor doping type, denoted here by reference numeral n(2), located on top of the substrate 1; a drift layer 3 of a first semiconductor doping type, denoted here by reference numeral n(3), located on top of the buffer layer 2; a current spreading layer 4 of a first semiconductor doping type, denoted here by reference numeral n(4), located on top of the drift layer 3; a trench body region 5 of a second semiconductor doping type, denoted here by reference numeral p(5), formed in a trench 111 located on top of the current spreading layer 4; a trench source region 6 of a first semiconductor doping type, denoted here by reference numeral n(6), formed in the trench body region 5; a mesa Schottky region 9 of a first semiconductor doping type, denoted here by reference numeral n(9), formed in the mesa portion of semiconductor device 100a; and a spacer gate region 10, denoted here by reference numeral G(10), formed on the trench sidewall 111b.

[0116] For example Figure 2 The first dopant implantation region 5a, the second dopant implantation region 5b, the first dopant diffusion layer 5d, and the second dopant diffusion layer 5c of the semiconductor device 100 shown form a trench body region 5.

[0117] The edge of the main trench area 5 is separated from the edge of the trench sidewall 111b by 151. In this context, the trench sidewall and the edge of the trench sidewall have the same meaning.

[0118] For example, the first embodiment of the semiconductor device 100a shown in FIG. 4a can be a vertical device. As described above, the semiconductor device 100a can be composed of a substrate of the first semiconductor doping type 1, a buffer layer of the first semiconductor doping type 2, a drift layer of the first semiconductor doping type 3, and a current spreading layer (CSL) of the first semiconductor doping type 4. Furthermore, the device 100a can be composed of a trench body region of the second semiconductor doping type 5, a trench source region of the first semiconductor doping type 6, a mesa Schottky region of the first semiconductor doping type 9, and a spacer gate region 10.

[0119] The main trench area 5 can be connected by spacers 154 (as described above). Figure 3 (The explanation given) is performed by injection to form the trench. The edge of the main trench area 5 can be separated from the edge of the trench sidewall by 151, as shown in Figure 4a.

[0120] The connection of the trench body (region 51, not shown in FIG. 4a) can be made in different ways. This connection can be achieved in the third dimension, i.e., into the drawing plane of FIG. 4a (not shown in FIG. 4a), where region 51 can be injected or regrowed. Regions 51 can be self-aligned to the trench edge or spaced at a distance between 0 and the width of the trench region. It should be understood that regions 51 can be distributed in the z-direction (multiple regions). More than one region 51 can exist in the z-direction (i.e., the direction into the drawing plane). The shape of region 51 can also be arbitrary. Any closed shape (circle, hexagon, triangle, rectangle, etc.) or any combination can be used. The connecting region 51 can be a strip parallel to the trench source region 6. For example, region 51 can be as deep as (or deeper than) region 6 (to achieve contact with region 5).

[0121] Figure 4b shows a schematic cross-sectional view of the semiconductor device 100b according to the second embodiment. The semiconductor device 100b is described above in conjunction with... Figure 2 An embodiment of the general design of the proposed and described semiconductor device 100.

[0122] Semiconductor device 100b includes: a substrate 1 of a first semiconductor doping type; a buffer layer 2 of a first semiconductor doping type located on top of the substrate 1; a drift layer 3 of a first semiconductor doping type located on top of the buffer layer 2; a current spreading layer 4 of a first semiconductor doping type located on top of the drift layer 3; a trench body region 5 of a second semiconductor doping type formed in a trench 111 located on top of the current spreading layer 4; a trench source region 6 of a first semiconductor doping type formed in the trench body region 5; a mesa separation region 7 of a first semiconductor doping type formed in a mesa portion of the semiconductor device 100; a mesa body region 8 of a second semiconductor doping type formed on top of the mesa separation region 7; a mesa source region 9 of a first semiconductor doping type formed on top of the mesa body region 8; and a spacer gate region 10 formed on the trench sidewall 111b.

[0123] The first dopant implantation region 5a, the second dopant implantation region 5b, the first dopant diffusion layer 5d, and the second dopant diffusion layer 5c form the trench body region 5.

[0124] The edge of the main trench area 5 can be separated from the edge of the trench sidewall 111b by 151, as shown in Figure 4b.

[0125] The second embodiment of the semiconductor device 100b shown in Figure 4b can be a vertical device. As described above, the semiconductor device 100b can be composed of a substrate of the first semiconductor doping type 1, a buffer layer of the first semiconductor doping type 2, a drift layer of the first semiconductor doping type 3, and a current spreading layer (CSL) of the first semiconductor doping type 4. Furthermore, the device 100b can be composed of a trench body region of the second semiconductor doping type 5, a trench source region of the first semiconductor doping type 6, an inter-body separation region of the first semiconductor doping type 7, a mesa body region of the second semiconductor doping type 8, a mesa source region of the first semiconductor doping type 9, and a spacer gate region 10, as shown in Figure 4b.

[0126] The connection between the mesa main body region 8 and the trench main body region 5 can be made in the third dimension via region 51 (not shown in Figure 4b), i.e., entering the drawing plane of Figure 4b. The connection between the mesa main body region 8 and the trench main body region 5 can also be implemented separately, in the third dimension, i.e., entering the drawing plane of Figure 4b. The main body region 8 can be connected via region 52 (not shown in Figure 4b), and the trench main body region 5 can be connected via region 51 (not shown in Figure 4b). Here, region 51 can be implemented in the trench portion, while region 52 can be implemented in the mesa portion of the semiconductor device. Other configurations of region 51 can also be applied.

[0127] The main trench area 5 can be formed by injecting through spacers 154, such as... Figure 3As shown. The edge of the trench body region 5 can be separated from the edge of the trench sidewall. In all cases, regions 51 and 52 can be electrically contacted by metallization (not shown here for clarity).

[0128] The following description Figure 2 The third embodiment of the semiconductor device 100 shown. The third embodiment is not shown in the figure. The reference numerals in the third embodiment correspond to those in the other embodiments.

[0129] In the third embodiment, the semiconductor device includes: a substrate 1 of a first semiconductor doping type; a buffer layer 2 of a first semiconductor doping type located on top of the substrate 1; a drift layer 3 of a first semiconductor doping type located on top of the buffer layer 2; a current spreading layer 4 of a first semiconductor doping type located on top of the drift layer 3; a trench body region 5 of a second semiconductor doping type formed in a trench 111 located on top of the current spreading layer 4; a trench source region 6 of a first semiconductor doping type formed in the trench body region 5; a body separation region 7 of a first semiconductor doping type formed in a mesa portion of the semiconductor device; a mesa body region 8 of a second semiconductor doping type formed on top of the body separation region 7; a mesa source region 9 of a first semiconductor doping type formed on top of the mesa body region 8; a mesa body contact formed on top of the mesa body region 8 and used for electrically connecting the mesa body region 8; and a spacer gate region 10 formed on the trench sidewall 111b.

[0130] The trench body region 5 is formed by a first dopant implantation region 5a, a second dopant implantation region 5b, a first dopant diffusion layer 5d, and a second dopant diffusion layer 5c, as shown below. Figure 2 As shown.

[0131] The edge of the main trench area 5 is separated from the edge of the trench sidewall 111b.

[0132] Figure 5a shows a schematic cross-sectional view of the semiconductor device 100c according to the fourth embodiment. The semiconductor device 100c is described above in conjunction with... Figure 2 An embodiment of a general design for the proposed and described semiconductor device 100 is shown. This embodiment differs from the embodiment shown in FIG. 4a (and FIG. 4b) in that, in the embodiment of FIG. 4a (and FIG. 4b), the trench body region 5 is not aligned with the trench sidewall 111b, i.e., there is a space 151 between the edge of the trench body region 5 and the trench sidewall 111b. Conversely, in the embodiment shown in FIG. 5a (and FIG. 5b), the trench body region 5 is aligned with the trench sidewall 111b, i.e., there is no space between the edge of the trench body region 5 and the trench sidewall 111b, i.e., the trench body region 5 extends laterally to the trench sidewall 111b.

[0133] Semiconductor device 100c includes: a substrate 1 of a first semiconductor doping type; a buffer layer 2 of a first semiconductor doping type located on top of the substrate 1; a drift layer 3 of a first semiconductor doping type located on top of the buffer layer 2; a current spreading layer 4 of a first semiconductor doping type located on top of the drift layer 3; a trench body region 5 of a second semiconductor doping type formed in a trench 111 located on top of the current spreading layer 4; a trench source region 6 of a first semiconductor doping type formed in the trench body region 5; a mesa source region 9 of a first semiconductor doping type formed on top of the current spreading layer 4 in the mesa portion; and a spacer gate region 10 formed on the trench sidewall 111b.

[0134] As can be seen from Figure 5a, the edge 152 of the main trench area 5 is aligned with the edge of the trench sidewall 111b.

[0135] The fourth embodiment is similar to the first embodiment. However, the main trench region 5 is injected with a spacer of thickness, such that the edge of region 5 is aligned with the trench sidewall after scattering or diffusion.

[0136] Figure 5b shows a schematic cross-sectional view of the semiconductor device 100d according to the fifth embodiment. The semiconductor device 100d is described above in conjunction with... Figure 2 An embodiment of the general design of the proposed and described semiconductor device 100.

[0137] Semiconductor device 100d includes: a substrate 1 of a first semiconductor doping type; a buffer layer 2 of a first semiconductor doping type located on top of the substrate 1; a drift layer 3 of a first semiconductor doping type located on top of the buffer layer 2; a current spreading layer 4 of a first semiconductor doping type located on top of the drift layer 3; a trench body region 5 of a second semiconductor doping type formed in a trench 111 located on top of the current spreading layer 4; a trench source region 6 of a first semiconductor doping type formed in the trench body region 5; a body separation region 7 of a first semiconductor doping type formed in a mesa portion of the semiconductor device 100; a mesa body region 8 of a second semiconductor doping type formed on top of the body separation region 7; a mesa source region 9 of a first semiconductor doping type formed on top of the mesa body region 8; and a spacer gate region 10 formed on the trench sidewall 111b.

[0138] The edge 152 of the main trench area 5 can be aligned with the edge of the trench sidewall 111b.

[0139] The fifth embodiment is similar to the second embodiment. However, the main trench region 5 is injected with a spacer of thickness, for example, the edge of region 5 is aligned with the trench sidewall after scattering or diffusion.

[0140] In a sixth embodiment of the semiconductor device (not shown in the figure), the semiconductor device includes: a substrate 1 of a first semiconductor doping type; a buffer layer 2 of a first semiconductor doping type located on top of the substrate 1; a drift layer 3 of a first semiconductor doping type located on top of the buffer layer 2; a current spreading layer 4 of a first semiconductor doping type located on top of the drift layer 3; a trench body region 5 of a second semiconductor doping type formed in a trench 111 located on top of the current spreading layer 4; a trench source region 6 of a first semiconductor doping type formed in the trench body region 5; a body separation region 7 of a first semiconductor doping type formed in a mesa portion of the semiconductor device; a mesa body region 8 of a second semiconductor doping type formed on top of the body separation region 7; a mesa source region 9 of a first semiconductor doping type formed on top of the mesa body region 8; a mesa body contact formed on top of the mesa body region 8 and used for electrically connecting the mesa body region 8; and a spacer gate region 10 formed on the trench sidewall 111b.

[0141] The edge 152 of the main trench area 5 can be aligned with the edge of the trench sidewall 111b.

[0142] The sixth embodiment is similar to the third embodiment. However, the main trench region 5 is injected with a spacer of thickness, for example, the edge of region 5 is aligned with the trench sidewall after scattering or diffusion.

[0143] Figure 6a shows a schematic cross-sectional view of the semiconductor device 100e according to the seventh embodiment. The semiconductor device 100e is described above in conjunction with... Figure 2 An embodiment of the general design of the proposed and described semiconductor device 100.

[0144] Semiconductor device 100e includes: a substrate 1 of a first semiconductor doping type; a buffer layer 2 of a first semiconductor doping type located on top of the substrate 1; a drift layer 3 of a first semiconductor doping type located on top of the buffer layer 2; a current spreading layer 4 of a first semiconductor doping type located on top of the drift layer 3; a trench body region 5 of a second semiconductor doping type formed in a trench 111 located above the current spreading layer 4; a trench source region 6 of a first semiconductor doping type formed in the trench body region 5; a mesa source region 9 of a first semiconductor doping type formed on top of the current spreading layer 4 in the mesa portion; and a spacer gate region 10 formed on the trench sidewall 111b.

[0145] Semiconductor device 100e includes a second trench body region 12 formed below the trench body region 5. The edge 153 of the second trench body region 12 may be spaced apart from the edge of the trench sidewall 111b, as shown in FIG6a.

[0146] according to Figure 2The second trench body region 12 can be formed by another first dopant implantation region 5a, another second dopant implantation region 5b, another first dopant diffusion layer 5d, and another second dopant diffusion layer 5c. Alternatively, the first dopant implantation region 5a and the first dopant diffusion layer 5d can be skipped.

[0147] The seventh embodiment is similar to the fourth embodiment. Furthermore, the seventh embodiment includes another main body region 12 (represented in this invention as a second trench main body region 12), which is deeper than the main body region 5 (represented in this invention as a trench main body region 5 or a first trench main body region 5). The main body region 12 (represented in this invention as a second trench main body region 12) is formed in a similar manner to the main body region 5 (by injecting spacers). The spacers in the main body region 12 are thicker (wider) than the spacers in the main body region 5. It is also possible that the spacers in the main body region 12 are narrower than the spacers in the main body region 5.

[0148] Main area 5 can be combined as described above Figure 3 The spacer is injected to generate the spacer, but the main body region 5 can also be a combination of shallow injection 310 and deep injection 311, as described above. Figure 3 As described above. In a preferred implementation, deep injection 311 is completed solely through spacer 154, as... Figure 3 As shown.

[0149] Figure 6b shows a schematic cross-sectional view of the semiconductor device 100f according to the eighth embodiment. The semiconductor device 100f is described above in conjunction with... Figure 2 An embodiment of the general design of the proposed and described semiconductor device 100.

[0150] Semiconductor device 100f includes: a substrate 1 of a first semiconductor doping type; a buffer layer 2 of a first semiconductor doping type located on top of the substrate 1; a drift layer 3 of a first semiconductor doping type located on top of the buffer layer 2; a current spreading layer 4 of a first semiconductor doping type located on top of the drift layer 3; a trench body region 5 of a second semiconductor doping type formed in a trench 111 located above the current spreading layer 4; a trench source region 6 of a first semiconductor doping type formed in the trench body region 5; a body separation region 7 of a first semiconductor doping type formed in a mesa portion of the semiconductor device 100; a mesa body region 8 of a second semiconductor doping type formed on top of the body separation region 7; a mesa source region 9 of a first semiconductor doping type formed on top of the mesa body region 8; and a spacer gate region 10 formed on the trench sidewall 111b.

[0151] Semiconductor device 100f includes a second trench body region 12 formed below the trench body region 5. The edge 153 of the second trench body region 12 may be spaced apart from the edge of the trench sidewall 111b, as shown in FIG6b.

[0152] The second trench body region 12 can be formed by another first dopant implantation region 5a, another second dopant implantation region 5b, another first dopant diffusion layer 5d, and another second dopant diffusion layer 5c, such as Figure 2 As shown. Alternatively, the first dopant implantation region 5a and the first dopant diffusion layer 5d can be skipped.

[0153] The eighth embodiment is similar to the fifth embodiment. Furthermore, the eighth embodiment includes another body region 12 that is deeper than the body region 5. The body region 12 is formed in a similar manner to the body region 5 (via spacer injection). The spacers in the body region 12 are thicker (wider) than the spacers in the body region 5. It is also possible that the spacers in the body region 12 are narrower than the spacers in the body region 5.

[0154] In the ninth embodiment (not shown in the figure), the semiconductor device includes: a substrate 1 of a first semiconductor doping type; a buffer layer 2 of a first semiconductor doping type located on top of the substrate 1; a drift layer 3 of a first semiconductor doping type located on top of the buffer layer 2; a current spreading layer 4 of a first semiconductor doping type located on top of the drift layer 3; a trench body region 5 of a second semiconductor doping type formed in a trench 111 located above the current spreading layer 4; a trench source region 6 of a first semiconductor doping type formed in the trench body region 5; a body separation region 7 of a first semiconductor doping type formed in a mesa portion of the semiconductor device 100; a mesa body region 8 of a second semiconductor doping type formed on top of the body separation region 7; a mesa source region 9 of a first semiconductor doping type formed on top of the mesa body region 8; and a spacer gate region 10 formed on the trench sidewall 111b.

[0155] The semiconductor device includes a second trench body region 12 formed below the trench body region 5. The edge 153 of the second trench body region 12 may be spaced apart from the edge of the trench sidewall 111b.

[0156] The second trench body region 12 can be formed by another first dopant implantation region 5a, another second dopant implantation region 5b, another first dopant diffusion layer 5d, and another second dopant diffusion layer 5c, such as Figure 2 As shown. Alternatively, the first dopant implantation region 5a and the first dopant diffusion layer 5d can be skipped.

[0157] The ninth embodiment is similar to the sixth embodiment. Furthermore, the ninth embodiment includes another body region 12 that is deeper than the body region 5. The body region 12 is formed in a similar manner to the body region 5 (via spacer injection). The spacers in the body region 12 are thicker (wider) than the spacers in the body region 5. It is also possible that the spacers in the body region 12 are narrower than the spacers in the body region 5.

[0158] Figure 7a shows a schematic cross-sectional view of the semiconductor device 100g according to the tenth embodiment. The semiconductor device 100g is described above in conjunction with... Figure 2 An embodiment of a general design for the proposed and described semiconductor device 100 is shown. This embodiment differs from the embodiment shown in FIG. 6a in that, in the embodiment of FIG. 7a, the trench body region 5 is not aligned with the trench sidewall 111b, i.e., there is a space between the edge of the trench body region 5 and the trench sidewall 111b. Conversely, in the embodiment shown in FIG. 6a, the trench body region 5 is aligned with the trench sidewall 111b, i.e., there is no space between the edge of the trench body region 5 and the trench sidewall 111b, i.e., the trench body region 5 extends laterally to the trench sidewall 111b.

[0159] Semiconductor device 100g includes: a substrate 1 of a first semiconductor doping type, denoted here by reference numeral n(1); a buffer layer 2 of a first semiconductor doping type, denoted here by reference numeral n(2), located on top of the substrate 1; a drift layer 3 of a first semiconductor doping type, denoted here by reference numeral n(3), located on top of the buffer layer 2; a current spreading layer 4 of a first semiconductor doping type, denoted here by reference numeral n(4), located on top of the drift layer 3; a trench body region 5 of a second semiconductor doping type, denoted here by reference numeral p(5), formed in a trench 111 located above the current spreading layer 4; a trench source region 6 of a first semiconductor doping type, denoted here by reference numeral n(6), formed in the trench body region 5; a mesa Schottky region 9 of a first semiconductor doping type, denoted here by reference numeral n(9), formed in the mesa portion of semiconductor device 100a; and a spacer gate region 10, denoted here by reference numeral G(10), formed on the trench sidewall 111b.

[0160] The semiconductor device 100g includes a second trench body region 12 formed below the trench body region 5.

[0161] The edge 153 of the second trench main area 12 can be separated from the edge of the trench sidewall 111b, as shown in Figure 7a.

[0162] The second trench body region 12 can be formed by another first dopant implantation region 5a, another second dopant implantation region 5b, another first dopant diffusion layer 5d, and another second dopant diffusion layer 5c, such as Figure 2 As shown.

[0163] The tenth embodiment is similar to the first embodiment. Furthermore, the tenth embodiment includes another body region 12 that is deeper than the body region 5. The body region 12 is formed in a similar manner to the body region 5 (via spacer injection). The spacers in the body region 12 are thicker (wider) than the spacers in the body region 5. It is also possible that the spacers in the body region 12 are narrower than the spacers in the body region 5.

[0164] Figure 7b shows a schematic cross-sectional view of the semiconductor device 100h according to the eleventh embodiment. The semiconductor device 100h is described above in conjunction with... Figure 2 An embodiment of a general design for the proposed and described semiconductor device 100 is shown. This embodiment differs from the embodiment shown in FIG. 6b in that, in the embodiment shown in FIG. 7b, the trench body region 5 is not aligned with the trench sidewall 111b, i.e., there is a space between the edge of the trench body region 5 and the trench sidewall 111b. Conversely, in the embodiment shown in FIG. 6b, the trench body region 5 is aligned with the trench sidewall 111b, i.e., there is no space between the edge of the trench body region 5 and the trench sidewall 111b, i.e., the trench body region 5 extends laterally to the trench sidewall 111b.

[0165] Semiconductor device 100h includes: a substrate 1 of a first semiconductor doping type; a buffer layer 2 of a first semiconductor doping type located on top of the substrate 1; a drift layer 3 of a first semiconductor doping type located on top of the buffer layer 2; a current spreading layer 4 of a first semiconductor doping type located on top of the drift layer 3; a trench body region 5 of a second semiconductor doping type formed in a trench 111 located above the current spreading layer 4; a trench source region 6 of a first semiconductor doping type formed in the trench body region 5; a body separation region 7 of a first semiconductor doping type formed in a mesa portion of the semiconductor device 100; a mesa body region 8 of a second semiconductor doping type formed on top of the body separation region 7; a mesa source region 9 of a first semiconductor doping type formed on top of the mesa body region 8; and a spacer gate region 10 formed on the trench sidewall 111b.

[0166] The semiconductor device 100h includes a second trench body region 12 formed below the trench body region 5.

[0167] The edge 153 of the second trench main area 12 is separated from the edge of the trench sidewall 111b.

[0168] The second trench body region 12 can be formed by another first dopant implantation region 5a, another second dopant implantation region 5b, another first dopant diffusion layer 5d, and another second dopant diffusion layer 5c, such as Figure 2 As shown.

[0169] The eleventh embodiment is similar to the second embodiment. Furthermore, the eleventh embodiment includes another body region 12 that is deeper than the body region 5. The body region 12 is formed in a similar manner to the body region 5 (via spacer injection). The spacers in the body region 12 are thicker (wider) than the spacers in the body region 5. It is also possible that the spacers in the body region 12 are narrower than the spacers in the body region 5.

[0170] In the twelfth embodiment (not shown in the figure), the semiconductor device includes: a substrate 1 of a first semiconductor doping type; a buffer layer 2 of a first semiconductor doping type located on top of the substrate 1; a drift layer 3 of a first semiconductor doping type located on top of the buffer layer 2; a current spreading layer 4 of a first semiconductor doping type located on top of the drift layer 3; a trench body region 5 of a second semiconductor doping type formed in a trench 111 located above the current spreading layer 4; a trench source region 6 of a first semiconductor doping type formed in the trench body region 5; a body separation region 7 of a first semiconductor doping type formed in a mesa portion of the semiconductor device 100; a mesa body region 8 of a second semiconductor doping type formed on top of the body separation region 7; a mesa source region 9 of a first semiconductor doping type formed on top of the mesa body region 8; and a spacer gate region 10 formed on the trench sidewall 111b. Furthermore, the semiconductor device may include a mesa body contact (not shown in the figure). This mesa body contact may be drawn to be the same depth as region 9, but it may also be deeper than region 9.

[0171] The mezzanine body contact is included in the mezzanine region and is electrically connected to the mezzanine body region 8. The mezzanine body contact can also be implemented as a disconnected island in the mezzanine region (not shown here for simplicity). The mezzanine body contact can be implemented in the center of the mezzanine region (preferably), but can also be offset to one side. The mezzanine body contact can even partially and completely consume the trench source region 6 on one side and / or the other side.

[0172] The trench body contacts (not shown here) can be formed in the third dimension (below the drawing plane shown in the figure) or by metallization (not shown here for clarity). Strip configuration is also possible.

[0173] The main trench area 5 can be formed by injecting spacers, for example, as described above. Figure 3 In the twelfth embodiment, the edge of the trench body region 5 is separated from the edge of the trench sidewall 111b.

[0174] The semiconductor device includes a second trench body region 12 formed below the trench body region 5.

[0175] The edge 153 of the second trench main area 12 is separated from the edge of the trench sidewall 111b.

[0176] The second trench body region 12 can be formed by another first dopant implantation region 5a, another second dopant implantation region 5b, another first dopant diffusion layer 5d, and another second dopant diffusion layer 5c, such as Figure 2 As shown.

[0177] The twelfth embodiment is similar to the third embodiment. Furthermore, the twelfth embodiment includes another body region 12 that is deeper than the body region 5. The body region 12 is formed in a similar manner to the body region 5 (via spacer injection). The spacers in the body region 12 are thicker (wider) than the spacers in the body region 5. It is also possible that the spacers in the body region 12 are narrower than the spacers in the body region 5.

[0178] In the thirteenth embodiment (not shown in the figure), the semiconductor device can be a vertical device, wherein the doping type of the substrate 1 of the vertical device is opposite to the doping type of the drift layer 3. The device forms an IGBT structure.

[0179] In the fourteenth embodiment (not shown in the figure), the semiconductor device may be a complementary vertical device, in which all semiconductor regions of embodiments 1 to 13 are reverse-doped.

[0180] In the fifteenth embodiment (not shown in the figures), implantation of the body of the semiconductor device can be performed using any number of spacers (not limited to two). Each implantation through a spacer can be a sequence of multiple sub-implants with different energies and / or doses.

[0181] In the sixteenth embodiment (not shown in the figure), all previous embodiments may involve silicon, SiC, GaN or Ga2O3.

[0182] In the seventeenth embodiment (not shown in the figure), all previous embodiments may involve devices other than vertical devices (lateral devices, semi-vertical devices).

[0183] In the eighteenth embodiment (not shown in the figures), all previous embodiments can involve devices without mesa regions (e.g., planar gate MOSFETs). In this case, the process is initiated by forming a step with a specific height using any material (standard hard mask, oxide, nitride, metal, alloy, etc.). This step serves as a seed for forming spacers (similar to mesa regions in previous embodiments).

[0184] In the nineteenth embodiment (not shown in the figure), all previous embodiments may involve a device in which the depth of the CSL region 4 is less than the depth of the body region 12, the body region 5, or the source region 6.

[0185] This invention provides a method for aligning and controlling the subject region, thereby controlling the subject spacing, even for deep subjects. This allows for minimizing JFET effects, thereby improving Rdson to reduce spacing (expand the initial design window) in advanced technologies. This invention proposes a method for using spacers. This eliminates unwanted lithographic misalignment and improves wafer uniformity. This invention proposes a mechanism for combining multiple spacers with increasing thickness. This forms straight subject edges (box-shaped profiles) or open triangular JFET regions.

[0186] The technical solutions described in this invention can be applied to other semiconductor trench devices, such as MOSFETs and IGBTs manufactured using silicon, gallium oxide, or other semiconductor material technologies.

[0187] While a particular feature or aspect of the invention may have been disclosed in combination with only one of several implementations, that feature or aspect may be combined with one or more other features or aspects of other implementations that are necessary or advantageous for any given or particular application. Furthermore, if the terms “comprising,” “having,” “having,” or other variations of these terms are used in the detailed description or claims, such terms, like the term “comprising,” are intended to be inclusive. Similarly, the terms “exemplary” and “for example” indicate only examples and not best or optimal ones. The terms “coupled” and “connected” and their derivatives may have been used. It should be understood that these terms can be used to indicate that two elements cooperate or interact with each other, whether the two elements are in direct physical contact or electrical contact, or not in direct contact with each other.

[0188] While specific aspects have been shown and described herein, those skilled in the art will understand that various alternatives and / or equivalent implementations may be used instead of the specific aspects shown and described without departing from the scope of the invention. This application is intended to cover any modifications or alterations to the specific aspects discussed herein.

[0189] Although the elements in the following claims are listed in a particular order using their respective labels, these elements are not necessarily limited to being implemented in that particular order unless the description of the claims otherwise implies a particular order for implementing some or all of these elements.

[0190] Based on the foregoing teachings, many substitutions, modifications, and alterations will be apparent to those skilled in the art. Of course, those skilled in the art will readily recognize that the invention has many applications beyond those described herein. Although the invention has been described with reference to one or more specific embodiments, those skilled in the art will recognize that many modifications can be made thereto without departing from the scope of the invention. Therefore, it should be understood that the invention can be implemented in ways other than those specifically described herein, within the scope of the appended claims and their equivalents.

Claims

1. A semiconductor device (100), characterized in that, The semiconductor device (100) includes: Chip layer (101); A trench (111) extends into the chip layer (101), wherein the trench (111) includes a trench bottom (111a) and a trench sidewall (111b). A first dopant injection region (5a) is arranged below the bottom (111a) of the trench; A second dopant injection region (5b) is arranged below the first dopant injection region (5a); A first dopant diffusion layer (5d) extending in the lateral direction along the first dopant implantation region (5a); A second dopant diffusion layer (5c) extends in the lateral direction of the second dopant implantation region (5b). The extension (105c) of the second dopant diffusion region (5c) in the lateral direction matches the extension of the first dopant diffusion layer (5d) in the lateral direction.

2. The semiconductor device (100) according to claim 1, characterized in that, The first dopant implantation region (5a) is obtained by first implanting the dopant into the trench (111); The second dopant injection region (5b) is obtained by injecting dopant into the trench (111) a second time after forming spacers at the trench sidewall (111b); The first dopant diffusion layer (5d) is obtained by diffusion or scattering of the first dopant injection region (5a) in the lateral direction; The second dopant diffusion layer (5c) is obtained by diffusion or scattering of the second dopant injection region (5b) in the lateral direction.

3. The semiconductor device (100) according to claim 1 or 2, characterized in that, The first dopant implantation region (5a) is formed by performing a first self-aligned implantation into the trench (111); The second dopant injection region (5b) is formed by a second self-aligned injection of the trench (111), the trench sidewall (111b) being covered by the spacer.

4. The semiconductor device (100) according to any one of the preceding claims, characterized in that, The semiconductor device (100) includes: Substrate of the first semiconductor doping type (1); A buffer layer (2) of the first semiconductor doping type is located on top of the substrate (1); A drift layer (3) of the first semiconductor doping type is located on top of the buffer layer (2); A first semiconductor doped current spreading layer (4) is located on top of the drift layer (3); A second semiconductor doped type trench body region (5) is formed in the trench (111) located on top of the current spreading layer (4); A trench source region (6) of the first semiconductor doping type is formed in the trench body region (5); A mesa Schottky region (9) of the first semiconductor doping type is formed in the mesa portion of the semiconductor device (100); A spacer gate region (10) is formed on the trench sidewall (111b). The first dopant implantation region (5a), the second dopant implantation region (5b), the first dopant diffusion layer (5d), and the second dopant diffusion layer (5c) form the trench body region (5).

5. The semiconductor device (100) according to claim 4, characterized in that, The edge of the main trench area (5) is separated from the edge of the trench sidewall (111b) (151).

6. The semiconductor device (100) according to any one of claims 1 to 3, characterized in that, The semiconductor device (100) includes: Substrate of the first semiconductor doping type (1); A buffer layer (2) of the first semiconductor doping type is located on top of the substrate (1); A drift layer (3) of the first semiconductor doping type is located on top of the buffer layer (2); A first semiconductor doped current spreading layer (4) is located on top of the drift layer (3); A second semiconductor doped type trench body region (5) is formed in the trench (111) located on top of the current spreading layer (4); A trench source region (6) of the first semiconductor doping type is formed in the trench body region (5); A first semiconductor doping type interbody separation region (7) is formed in the mesa portion of the semiconductor device (100); A mesa body region (8) of the second semiconductor doping type is formed on top of the interbody separation region (7); A mesa source region (9) of the first semiconductor doping type is formed on top of the mesa body region (8); A spacer gate region (10) is formed on the trench sidewall (111b). The first dopant implantation region (5a), the second dopant implantation region (5b), the first dopant diffusion layer (5d), and the second dopant diffusion layer (5c) form the trench body region (5).

7. The semiconductor device (100) according to claim 6, characterized in that, The edge of the main trench area (5) is separated from the edge of the trench sidewall (111b) (151).

8. The semiconductor device (100) according to any one of claims 1 to 3, characterized in that, The semiconductor device (100) includes: Substrate of the first semiconductor doping type (1); A buffer layer (2) of the first semiconductor doping type is located on top of the substrate (1); A drift layer (3) of the first semiconductor doping type is located on top of the buffer layer (2); A first semiconductor doped current spreading layer (4) is located on top of the drift layer (3); A second semiconductor doped type trench body region (5) is formed in the trench (111) located on top of the current spreading layer (4); A trench source region (6) of the first semiconductor doping type is formed in the trench body region (5); A first semiconductor doping type interbody separation region (7) is formed in the mesa portion of the semiconductor device (100); A mesa body region (8) of the second semiconductor doping type is formed on top of the interbody separation region (7); A mesa source region (9) of the first semiconductor doping type is formed on top of the mesa body region (8); The tabletop body contact is formed on the top of the tabletop body area (8) and is used to electrically connect the tabletop body area (8). A spacer gate region (10) is formed on the trench sidewall (111b). The trench body region (5) is formed by the first dopant injection region (5a), the second dopant injection region (5b), the first dopant diffusion layer (5d), and the second dopant diffusion layer (5c).

9. The semiconductor device (100) according to claim 8, characterized in that, The edge of the main trench area (5) is separated from the edge of the trench sidewall (111b) (151).

10. The semiconductor device (100) according to claim 4, characterized in that, The edge (152) of the main trench area (5) is aligned with the edge of the trench sidewall (111b).

11. The semiconductor device (100) according to claim 6, characterized in that, The edge (152) of the main trench area (5) is aligned with the edge of the trench sidewall (111b).

12. The semiconductor device (100) according to claim 8, characterized in that, The edge (152) of the main trench area (5) is aligned with the edge of the trench sidewall (111b).

13. A method for manufacturing a semiconductor device (100), characterized in that, The method includes: Form a chip layer (101); A trench (111) is formed in the chip layer (101), wherein the trench (111) includes a trench bottom (111a) and a trench sidewall (111b). Dopant is injected into the trench (111) to form a first dopant injection region (5a) below the bottom (111a) of the trench. Spacers (154) are formed at the sidewall (111b) of the trench. Dopant is injected into the trench (111), wherein the trench sidewall (111b) is covered by the spacer to form a second dopant injection region (5b) below the first dopant injection region (5a). The thickness of the spacer is matched with the width of the second dopant diffusion layer (5c), which is formed by diffusion of the second dopant injection region (5b) in the lateral direction.

14. The method according to claim 13, characterized in that, The first dopant implantation region (5a) is formed by performing a first self-aligned implantation into the trench (111); The second dopant injection region (5b) is formed by a second self-aligned injection of the trench (111), the trench sidewall (111b) being covered by the spacer.

Images