Semiconductor package

Abstract

A semiconductor package is provided. In one example, a semiconductor package includes a base having a first surface and a second surface opposite the first surface. The semiconductor package includes at least one semiconductor die attached to the second surface of the base. The semiconductor package includes an insulating portion on the second surface of the base and on the at least one semiconductor die. The insulating portion forms a first outer surface of the semiconductor package. The semiconductor package includes at least one through-mold via extending from the first outer surface through the insulating portion to at least one of the semiconductor die or the base.

Description

[0001] priority

[0002] This application is based on and claims priority to U.S. Patent Application No. 18 / 336,358, filed June 16, 2023. This application claims priority and the benefit of the referenced application, the entire contents of which are incorporated by reference. Technical Field

[0003] This disclosure generally relates to semiconductor packages. Background Technology

[0004] Semiconductor devices such as transistors and diodes are ubiquitous in modern electronic devices. Wide-bandgap semiconductor materials such as gallium arsenide (GaAs), gallium nitride (GaN), and silicon carbide (SiC) are increasingly being used in semiconductor devices to overcome performance limitations in areas such as switching speed, power handling capability, and thermal conductivity. Example semiconductor devices can include metal-oxide-semiconductor field-effect transistors (MOSFETs), insulated-gate bipolar transistors (IGBTs), Schottky barrier diodes, PiN diodes, thyristors, and high electron mobility transistors (HEMTs). Packaging technology can play a significant role in the performance of power semiconductor devices. Summary of the Invention

[0005] Aspects and advantages of embodiments of this disclosure will be set forth in part in the description which follows, or may be learned from the description or from practice of the embodiments.

[0006] One exemplary embodiment of this disclosure relates to a semiconductor package. The semiconductor package includes a base having a first surface and a second surface opposite to the first surface. The semiconductor package includes at least one semiconductor die attached to the second surface of the base. The semiconductor package includes insulating portions on the second surface of the base and on at least one semiconductor die. The insulating portions form a first outer surface of the semiconductor package. The semiconductor package includes at least one through-mold via extending from the first outer surface through the insulating portion to at least one of the semiconductor die or the base.

[0007] Another exemplary embodiment of this disclosure relates to a base having a first surface and a second surface. The second surface is opposite to the first surface. A semiconductor package includes at least one semiconductor die. The at least one semiconductor die includes a first die surface having a drain contact and a second die surface having a source contact and a gate contact. The drain contact is coupled to the first surface of the base. The semiconductor package includes insulating portions on the base and on the semiconductor die, the insulating portions forming a first outer surface of the semiconductor package. The semiconductor package includes a first through-hole extending from the first outer surface through the insulating portion to the gate contact. The semiconductor package includes a second through-hole extending from the first outer surface through the insulating portion to the drain contact. The semiconductor package includes a third through-hole extending from the first outer surface through the insulating portion to the base. The drain contact is coupled to the third through-hole through the base.

[0008] Another exemplary embodiment of this disclosure relates to a method of forming a semiconductor package. The method includes coupling at least one semiconductor die to a first surface of a substrate. The substrate has a second surface opposite to the first surface. The method includes forming an insulating portion on the substrate such that the insulating portion is on at least one semiconductor die. The insulating portion forms a first outer surface of the semiconductor package. The method includes forming at least one through-hole extending from the first outer surface through the insulating portion to at least one semiconductor die or substrate.

[0009] These and other features, aspects, and advantages of the various embodiments will become better understood with reference to the following description and the appended claims. The accompanying drawings, which are incorporated in and form a part of this specification, illustrate embodiments of the present disclosure and, together with the specification, explain the relevant principles. Attached Figure Description

[0010] A detailed discussion of embodiments for those skilled in the art is set forth in the description with reference to the accompanying drawings, in which: Figure 1 A cross-sectional view of a semiconductor package according to an exemplary embodiment of the present disclosure is depicted.

[0011] Figure 2 A top perspective view of a semiconductor package according to an exemplary embodiment of the present disclosure is depicted.

[0012] Figure 3 A cross-sectional view of a semiconductor package according to an exemplary embodiment of the present disclosure is depicted.

[0013] Figure 4 A cross-sectional view of a semiconductor package according to an exemplary embodiment of the present disclosure is depicted.

[0014] Figure 5A cross-sectional view of a system including a semiconductor package mounted to a circuit board, according to an exemplary embodiment of the present disclosure, is depicted.

[0015] Figure 6 A flowchart illustrating an exemplary embodiment of a method according to this disclosure is provided.

[0016] Figure 7 A flowchart illustrating an exemplary embodiment of a method according to this disclosure is provided. Detailed Implementation

[0017] The embodiments will now be described in detail with reference to the accompanying drawings, in which one or more examples are illustrated. Each example is provided by way of explanation and not by way of limitation. In fact, it will be apparent to those skilled in the art that various modifications and variations can be made to the embodiments without departing from the scope or spirit of this disclosure. For example, a feature shown or described as part of one embodiment may be used with another embodiment to produce yet another embodiment. Therefore, various aspects of this disclosure are intended to cover such modifications and variations.

[0018] Semiconductor packages comprising one or more semiconductor dies have been developed, such as discrete semiconductor packages and power modules. The semiconductor die may include one or more semiconductor devices, such as MOSFETs, Schottky diodes, and HEMT devices. These semiconductor packages can be used in a variety of applications to achieve higher switching frequencies, reduced associated losses, higher blocking voltages, and improved avalanche capability. Example applications may include high-performance industrial power supplies, server / telecom power supplies, electric vehicle charging systems, energy storage systems, uninterruptible power supplies, high-voltage DC / DC converters, electric vehicles, battery management systems, radio frequency applications, wireless communication infrastructure, radar, telecommunications systems (e.g., 5G communication systems), amplifiers, satellite communications, data links, and more.

[0019] Packaging technology plays a crucial role in defining the performance of semiconductor devices. For example, the packaging of a semiconductor die can limit its ability to dissipate heat, conduct current, or even switch at a specific speed (e.g., due to parasitic inductance). Ineffective heat dissipation can cause problems for semiconductor devices (e.g., miniaturized semiconductor devices) or for semiconductor devices in close contact with their housings. Excessive heat can adversely affect the operation of the semiconductor device itself and the electronic systems that use it.

[0020] Some power semiconductor packages may be primarily based on leadframes. For example, some existing semiconductor packages may include one or more wire bonds for interconnection to couple a semiconductor die to the leads or other connection structures of the semiconductor package. Semiconductor packages that include leadframes and wire bonds may require expensive tooling. Furthermore, semiconductor packages may suffer from parasitic effects (e.g., parasitic resistance or parasitic inductance) from package interconnects (e.g., wire bonds).

[0021] Various aspects of this disclosure relate to semiconductor packages based on, for example, lead-frame-free wafer-level packages (e.g., fan-out wafer-level packages). In some examples, the semiconductor package does not require wire bonding. The semiconductor package can provide top-side cooling, resulting in enhanced thermal performance.

[0022] In some examples, the semiconductor package may include an insulating portion on a semiconductor die and form a first outer surface of the package. The semiconductor package may include a base that serves as a second outer surface of the semiconductor package. The second outer surface may also provide top-side cooling for the semiconductor package. One or more semiconductor dies may be attached to the base (e.g., using a die-attachment material). A through-hole extending from the first outer surface through the insulating portion to at least one of the semiconductor die or the base may be used to connect to the semiconductor die from the first outer surface.

[0023] In some examples, the connections of the semiconductor package (e.g., pads, solder bumps, etc.) can be located on the first outer surface of the package. This allows the semiconductor package to be "flip-chip" mounted to the circuit board by attaching the connections on the first outer surface of the package to the circuit board. An underfill material can be disposed between the first outer surface of the semiconductor package and the circuit board. Underfilling the semiconductor package eliminates creepage distance considerations for the semiconductor package. More specifically, creepage distance is the distance between two opposite polarity conductors along the outer surface (exposed to air). By underfilling the semiconductor package, the opposite polarity conductors of the surface are not exposed to air, thus eliminating any creepage distance considerations for the semiconductor package. Furthermore, in some examples, a heat dissipation element (e.g., a heat sink) can be mounted in contact with the first outer surface.

[0024] The various aspects of this disclosure provide numerous technical effects and benefits. For example, the semiconductor package according to the examples of this disclosure can be manufactured using a wafer-level process, which reduces the need for lead frames and wire bonding in the semiconductor package, resulting in reduced parasitic resistance and inductance. Lower parasitic inductance leads to faster switching speeds. Compared to other surface mount packages, semiconductor packages can provide top-side cooling, thereby improving system-level thermal performance. Because semiconductor packages can be formed using wafer-level processes, they allow for custom package form factors tailored to the individual semiconductor die size, unlike conventional packages which are limited to fixed dimensions without considering the semiconductor die being packaged. This customization can further reduce costs because the bill of materials can be customized based on the semiconductor die size. For example, the amount of molding compound used as insulation can be customized based on the semiconductor die size.

[0025] It should be understood that although the terms first, second, third, etc., may be used herein to describe various elements, these elements should not be limited by these terms. These terms are used only to distinguish one element from another. For example, without departing from the scope of this disclosure, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0026] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the invention. As used herein, the singular forms “a,” “an,” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It should also be understood that the terms “comprises,” “comprising,” “includes,” and / or “including” as used herein specify the presence of the stated feature, integer, step, operation, element, and / or component, but do not exclude the presence or additional one or more other features, integers, steps, operations, elements, components, and / or combinations thereof.

[0027] Unless otherwise specified, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. It should also be understood that the terms used herein should be interpreted as having the same meaning as they would in the context of this specification and the relevant field, and should not be interpreted in an idealized or overly formal sense unless expressly defined herein.

[0028] It should be understood that when an element of a layer, region, or substrate is referred to as being "on" or extending "on" another element, it may be directly on or extending directly onto the other element, or intermediate elements may be present. Conversely, when an element is referred to as being "directly on" or "directly extending" from another element, there are no intermediate elements, except in some examples where adhering materials (e.g., die-attachment material, solder, paste, adhesive, sintering material, or other materials) may be present. It should also be understood that when an element is referred to as being "connected" or "coupled" to another element, it may be directly connected or coupled to the other element, or intermediate elements may be present. Conversely, when an element is referred to as being "directly connected" or "directly coupled" to another element, there are no intermediate elements, except in some examples where adhering materials (e.g., die-attachment material, solder, paste, adhesive, sintering material, or other materials) may be present.

[0029] As shown in the figures, relative terms such as “below,” “above,” “upper,” “lower,” “horizontal,” “lateral,” or “vertical” may be used herein to describe the relationship of one element, layer, or region to another. It should be understood that these terms are intended to include different orientations of the device other than those depicted in the figures.

[0030] Embodiments of this disclosure are described herein with reference to cross-sectional views, which are schematic diagrams of idealized embodiments of this disclosure. For clarity, the thicknesses of layers and regions in the figures may be enlarged. Furthermore, shapes different from those illustrated may be expected due to, for example, manufacturing techniques and / or tolerances. Therefore, embodiments of this disclosure should not be construed as limited to the specific shapes of the regions shown herein, but rather include, for example, shape deviations due to manufacturing processes. Similarly, it should be understood that dimensional variations are expected based on standard deviations during the manufacturing process. As used herein, “about” or “approximately” includes values ​​within 10% of the nominal value.

[0031] Throughout the text, the same reference numerals refer to the same elements. Therefore, even if the same or similar reference numerals are neither mentioned nor described in the corresponding figures, they can be described with reference to other figures. Furthermore, elements not represented by reference numerals can be described with reference to other figures.

[0032] Some embodiments of the present invention are described with reference to semiconductor layers and / or regions characterized by having a conductivity type, such as n-type or p-type, which refers to the majority carrier concentration in the layer and / or region. Thus, N-type materials have a majority equilibrium concentration of negatively charged electrons, while p-type materials have a majority equilibrium concentration of positively charged holes. Some materials may be indicated by "+" or "-" (e.g., N+, N-, P+, P-, N++, N--, P++, P--, etc.) to indicate a relatively large ("+") or small ("-") majority carrier concentration compared to another layer or region. However, such notation does not imply the presence of a specific concentration of majority or minority carriers in a layer or region.

[0033] Various aspects of this disclosure are discussed with reference to silicon carbide-based semiconductor structures, such as silicon carbide-based MOSFETs. Using the disclosure provided herein, those skilled in the art will understand that the power semiconductor packages according to exemplary embodiments of this disclosure can be used with any semiconductor material, such as other wide-bandgap semiconductor materials, without departing from the scope of this disclosure. Example wide-bandgap semiconductor materials include silicon carbide (e.g., α-silicon carbide with a bandgap of 2.996 eV at room temperature) and group III nitrides (e.g., gallium nitride with a bandgap of 3.36 eV at room temperature).

[0034] Typical embodiments have been disclosed in the accompanying drawings and description, and although specific terminology has been used, it is for general and descriptive purposes only and not for limiting the scope set forth in the appended claims.

[0035] Figure 1 A cross-sectional view of a semiconductor package 100 according to an exemplary embodiment of the present disclosure is depicted. The semiconductor package 100 may include a semiconductor die 102 in thermal and / or electrical contact with a base 106. The base 106 may have a first surface 106A and a second surface 106B. The second surface 106B may be opposite to the first surface 106A. The semiconductor die 102 may be attached to the second surface 106B of the base 106 (e.g., using a die attachment material 104). The first surface 106A of the base 106 may be a second outer surface 100A of the semiconductor package 100. The semiconductor package 100 may also define a first outer surface 100B opposite to the second outer surface 100A.

[0036] The base 106 may be or may include thermally and electrically conductive materials. For example, the base 106 may form a thermally conductive cooling layer for the semiconductor package 100. As an example, the base 106 may be or may include a metal, such as copper, silver, gold, titanium, or other conductive materials. For example, in some embodiments, the base 106 may be or may include materials such as those referenced. Figure 2The discussion focuses on directly bonded copper (DBC) substrates or active metal brazing (AMB) substrates.

[0037] Semiconductor die 102 may include one or more semiconductor devices, such as MOSFET devices, Schottky diodes (e.g., silicon carbide-based Schottky diodes), high electron mobility transistors (HEMTs) based on group III nitrides, or other devices. In some examples, semiconductor die 102 may be based on or may include wide-bandgap semiconductors, such as silicon carbide and / or group III nitrides (e.g., gallium nitride). For example, in some examples, semiconductor die 102 may include a silicon carbide-based MOSFET located between source and drain contacts to form, for example, a vertical structure semiconductor device. Some aspects of this disclosure have been discussed for illustrative and discussion purposes with reference to specific semiconductor devices, such as HEMT devices, silicon carbide-based MOSFET devices, silicon carbide-based Schottky diodes, etc. Using the disclosure provided herein, those skilled in the art will understand that semiconductor die may include other semiconductor devices without departing from the scope of this disclosure, such as diodes (e.g., Schottky diodes, PiN diodes, etc.), insulated-gate bipolar transistors, or other devices.

[0038] Semiconductor die 102 may be, for example, a 7mm × 7mm semiconductor die. However, aspects of this disclosure are applicable to many different semiconductor die sizes, such as, as some examples, semiconductor dies ranging from 1mm × 1mm to 7mm × 9mm. According to exemplary aspects of this disclosure, in some embodiments, semiconductor package 100 does not include any wire bonding to at least one semiconductor die 102. For example, in some embodiments, through-holes, as further described below, may be used to provide all electrical connections to semiconductor die 102.

[0039] The semiconductor die 102 may include a first die surface 102A and a second die surface 102B opposite to the first die surface 102A. The first die surface 102A may have a first die contact 103 (e.g., a drain contact). The second die surface 102B may have at least one second die contact. Figure 1 In the example, at least one second die contact includes a second die contact 116 (e.g., a gate contact) and a third die contact 119 (e.g., a source contact). It should be understood that some semiconductor dies 102 may include only a single second die contact and / or more than two second die contacts without departing from the scope of this disclosure.

[0040] The first die contact 103 may be coupled to the base 106. For example, in some embodiments, the first die contact 103 may be coupled to the base 106 using a die attachment material 104. The die attachment material 104 may be a thermally and / or electrically conductive material configured to attach the first die contact 103 to the base 106. The die attachment material 104 may include any suitable material, such as solder, paste, sintering material, etc. It should be understood that in some embodiments, the first die contact 103 may (e.g., without using die attachment material 104) be directly connected to the base 106 and / or otherwise coupled to the base 106 without departing from the scope of this disclosure.

[0041] The semiconductor package 100 may additionally include an insulating portion 101. The insulating portion 101 may be formed on a second surface 106B of the base 106 and on the semiconductor die 102. For example, the insulating portion 101 may cover or encapsulate the semiconductor die 102. The insulating portion 101 may form a first outer surface 100B of the semiconductor package 100. The insulating portion 101 may be an electrically insulating material, protecting the semiconductor die 102 from external electrical interference. The insulating portion 101 may be formed by a molding process. The insulating portion 101 may include a material capable of operating at high temperatures (e.g., approximately 200°C). Example materials for the insulating portion 101 may include epoxy materials or epoxy molding compounds (EMC).

[0042] The semiconductor package 100 may additionally include at least one through-hole (e.g., through-hole 111, through-hole 115, through-hole 118) extending from the first outer surface 100B through the insulating portion 101. For example, at least one through-hole (e.g., through-hole 111, through-hole 115, through-hole 118) may extend to at least one of the semiconductor die 102 or the base 106.

[0043] More specifically, the semiconductor package 100 may include a plurality of through-holes 111 extending from a first outer surface 100B of the semiconductor package 100 to a base 106. The through-holes 111 may include a conductive material (e.g., a metal) to provide a conductive path to the base 106. Furthermore, the through-holes 111 may be electrically coupled to a first die contact 103 (e.g., a drain contact) via the base 106. Although in Figure 1 Two through-holes 111 extending to the base 106 are shown, but it should be understood that any suitable number of through-holes may be coupled to each contact on the semiconductor die 102 and / or the base 106 without departing from this disclosure.

[0044] Semiconductor package 100 may include additional through-holes to provide electrical connections to semiconductor die 102. For example, semiconductor package 100 may include a through-hole 115 extending from a first outer surface 100B through an insulating portion 101 to a second die contact 116 (e.g., a gate contact) on semiconductor die 102. Semiconductor package 100 may include a through-hole 118 extending from the first outer surface 100B through an insulating portion 101 to a third die contact 119 (e.g., a source contact). Semiconductor package 100 may include additional through-holes (not shown) to provide further electrical connections to the semiconductor die (e.g., Kelvin connections).

[0045] Each through-hole 111 can be coupled to an interconnect structure 110. The interconnect structure 110 can be configured to form an electrical and / or thermal connection between the through-hole 111 and a surface (such as a printed circuit board (PCB)) where the semiconductor package 100 is mounted. For example, the interconnect structure 110 can be or may include pads, solder bumps, or other suitable interconnect structures. Furthermore, each interconnect structure 110 can be located on a first outer surface 100B of the semiconductor package 100. In some embodiments, each interconnect structure 110 can provide a drain connection for the semiconductor package 100.

[0046] Through-hole 115 can be coupled to interconnect structure 112. Interconnect structure 112 can be configured to form an electrical and / or thermal connection between through-hole 115 and a surface (such as a printed circuit board (PCB)) on which the semiconductor package 100 is mounted. For example, interconnect structure 112 can be or may include pads, solder bumps, or other suitable interconnect structures. Furthermore, interconnect structure 112 can be located on a first outer surface 100B of the semiconductor package 100. In some embodiments, interconnect structure 112 can provide a gate connection for the semiconductor package 100.

[0047] Through-hole 118 can be coupled to interconnect structure 114. Interconnect structure 114 can be configured to form electrical and / or thermal connections between through-hole 118 and a surface (such as a printed circuit board (PCB)) where the semiconductor package 100 is mounted. For example, interconnect structure 114 can be or may include pads, solder bumps, or other suitable interconnect structures. Furthermore, interconnect structure 114 can be located on a first outer surface 100B of the semiconductor package 100. In some embodiments, interconnect structure 114 can provide source connections for the semiconductor package 100. The semiconductor package 100 may include additional interconnect structures on the first outer surface 100B without departing from the scope of this disclosure.

[0048] Figure 2A plan view of a semiconductor package 100 according to an exemplary embodiment of the present disclosure is depicted (e.g., observing a first outer surface 100B). Interconnect structures 112 providing, for example, gate connections and interconnect structures 114 providing, for example, source connections are arranged inside the outer surface 100B of the semiconductor package 100. The semiconductor package 100 includes a plurality of interconnect structures 110 connected to a through-hole 111 to provide, for example, electrical connections to a base 106 and a first die contact 103, thereby providing a drain connection for the semiconductor package 100. The interconnect structures 110 may at least partially surround the interconnect structures 112 and 114. The plurality of interconnect structures 110 may be arranged on a peripheral portion of the outer surface 100B of the semiconductor package 100 relative to the interconnect structures 112 and 114.

[0049] For the purposes of explanation and discussion, Figure 2 An example pattern of interconnect structures 110, 112, and 114 is depicted. Those skilled in the art will understand, using the disclosure provided herein, that any pattern of interconnect structures on the outer surface 100B can be used without departing from the scope of this disclosure.

[0050] In some examples, all interconnect structures 110, 112, and 114 of the semiconductor package 100 are on a first outer surface 100B to provide a flip-chip configuration for the semiconductor package 100. The semiconductor package 100 may be arranged as a surface mount technology (SMT) package, wherein a second outer surface 100A (e.g., a top surface) is positioned opposite an outer surface (such as a printed circuit board (PCB)) on which the semiconductor package 100 is mounted. The first outer surface 100B (e.g., a bottom surface or mounting surface) forms the mounting side of the semiconductor package 100 mounted to the outer surface (such as the PCB). According to an example aspect of this disclosure, the second outer surface 100A is defined by a base 106 comprising a thermally conductive material (such as copper) such that the second outer surface 100A forms a thermally conductive cooling layer for the semiconductor package 100. Furthermore, in some implementations, the second outer surface 100A may be coupled to an external heat sink to further provide top-side cooling for the semiconductor package 100. (See also...) Figure 5 The flip-chip configuration of semiconductor package 100 is discussed in more detail.

[0051] Figure 3 A cross-sectional view of a semiconductor package 300 according to an exemplary embodiment of the present disclosure is depicted. The semiconductor package 300 is similar to... Figure 1The semiconductor package 100. However, in the example semiconductor package 300, the base 106 of the semiconductor package 300 includes multiple metal layers 302, 304, wherein an isolation layer 306 is located between the multiple metal layers 302, 304. In some examples, the base 106 includes a directly bonded copper (DBC) substrate or an active metal brazing (AMB) substrate.

[0052] The base 106 may include (e.g., via die attachment material 104) a first metal layer 302 coupled to the first die contact 103 and / or the semiconductor die 102. The first metal layer 302 may additionally have thermal and / or electrical contact with the through-hole 111. When the semiconductor package 300 is mounted in a flip-chip configuration, an isolation layer 306 may be present on the first metal layer 302 to improve electrical isolation of the first die contact 103 (e.g., drain interconnect structure). A second metal layer 304 may be present on the isolation layer 306. The base 106 may be thermally conductive, allowing it to function as a cooling pad for the semiconductor package 300. It should be understood that this is provided for illustrative and discussion purposes only. Figure 3 The example base 106 is provided, and other suitable bases 106 may be used without departing from the scope of this disclosure.

[0053] Figure 4 A cross-sectional view of a semiconductor package 400 according to an exemplary embodiment of the present disclosure is depicted. Figure 4 The semiconductor package 400 is similar to the semiconductor package 100. However, the semiconductor package 400 includes a plurality of semiconductor dies 102-1 and 102-2. For example, the semiconductor package 400 includes a first semiconductor die 102-1 having a first die contact 103-1, a second die contact 116-1, and a third die contact 119-1 coupled to a base 106 via a die attachment material 104-1. Furthermore, the semiconductor package 400 includes a second semiconductor die 102-2 having a first die contact 103-2, a second die contact 116-2, and a third die contact 119-2 coupled to a base 106 via a die attachment material 104-2. As described above, each semiconductor die 102-1, 102-2 may include a semiconductor device. Furthermore, the semiconductor package 400 may include more or fewer semiconductor dies 102 without departing from the scope of this disclosure. For example, semiconductor package 400 may include three or more semiconductor dies 102.

[0054] The semiconductor package 400 may also include at least one redistribution layer coupling through-holes to a plurality of semiconductor dies 102-1 and 102-2. For example, as Figure 4As shown, a gate interconnect structure 112 and a source interconnect structure 114 are provided, which are connected to corresponding second die contacts 116-1, 116-2 and third die contacts 119-1, 119-2 on each semiconductor die 102-1, 102-2. The semiconductor package 400 may include a first redistribution layer 315 (e.g., a gate redistribution layer) that couples a through-hole via 115 to the second die contacts 116-1, 116-2. For example, the through-hole via 115 may extend to the first redistribution layer 315. Then, the through-holes 115-1, 115-2 may extend from the first redistribution layer 315 to the second die contacts 116-1, 116-2.

[0055] Similarly, the semiconductor package 400 may include a second redistribution layer 318 (e.g., a source redistribution layer) that couples the through-hole 118 to the third die contacts 119-1, 119-2. For example, the through-hole 118 may extend into the second redistribution layer 318. In some cases, a hole 305 in the first redistribution layer 315 may accommodate the through-hole 118 such that the through-hole 118 does not contact the first redistribution layer 315. The through-holes 118-1, 118-2 can then extend from the second redistribution layer 318 to the third die contacts 119-1, 119-2.

[0056] The redistribution layers 315 and 318 may be made of a conductive material. In some embodiments, the redistribution layers 315 and 318 may also be thermally conductive. For example, in some embodiments, the redistribution layers 315 and 318 may be metals, such as copper, silver, gold, titanium, or other conductive materials. Furthermore, in some embodiments, the insulating portion 101 may include one or more additional layers (not shown) to improve electrical and / or thermal isolation between the redistribution layers 315 and 318. However, in some embodiments, the insulating portion 101 may provide sufficient isolation between the redistribution layers 315 and 318. With additional contacts on the semiconductor die 102, more redistribution layers may be provided in the semiconductor package 400 without departing from the scope of this disclosure.

[0057] Figure 5 A cross-sectional view of a system 500 including a semiconductor package 100 mounted to a circuit board 502, according to an exemplary embodiment of the present disclosure, is depicted. The semiconductor package 100 may be respectively Figure 1 Semiconductor package 100 and / or Figure 3 and Figure 4 Semiconductor packages 300 and 400. For example... Figure 5As shown, interconnect structures 110, 112, and 114 can all be on a single surface of the semiconductor package 100. This allows the semiconductor package 100 to be “flip-chip” mounted to the circuit board 502 by attaching the interconnect structures 110, 112, and 114 on the second outer surface of the semiconductor package 100 to the circuit board 502. The semiconductor package 100 can therefore be arranged as a surface mount technology (SMT) or “flip-chip” package. The second outer surface 100A formed by the base 106 of the semiconductor package 100 can thereby form a thermally conductive cooling layer for the semiconductor package 100. Furthermore, in some embodiments, the second outer surface 100A formed by the base 106 of the semiconductor package 100 opposite to the circuit board 502 can be coupled to an external heat sink 506 to further provide top-side cooling for the semiconductor package 100.

[0058] Underfill material 504 may be disposed between the first outer surface of semiconductor package 100 and, for example, a circuit board or other substrate. Underfill material 504 may reduce stress on semiconductor package 100 (e.g., stress on interconnect structures 110, 112, and 114) associated with physical forces acting on semiconductor package 100 (e.g., gravity, physical contacts, inertial forces, etc.). Additionally or alternatively, underfill material 504 may exclude creepage distance considerations for semiconductor package 100. For example, interconnect structures 110, 112, and 114 may be placed closer to each other without additional strain. Underfill material 504 may provide isolation between interconnect structures 110, 112, and 114.

[0059] The underfill material 504 can be any suitable material. In some embodiments, the underfill material 504 can be a composite material, for example, made of a polymer (e.g., an epoxy polymer) having fillers and / or additional components. For example, the underfill material 504 can be a polymer-based material, such as an epoxy polymer material. Additionally or alternatively, the underfill material 504 may include fillers or other components, such as flow agents, binders, etc.

[0060] Figure 6 A flowchart depicts an example method 600 for forming a semiconductor package according to an exemplary embodiment of the present disclosure. For illustrative and discussion purposes, Figure 6 Example processing steps are depicted. Using the disclosure provided herein, those skilled in the art will understand that the processing steps of any method described herein can be adjusted, modified, or included in the absence of steps not shown, omitted, and / or rearranged without departing from the scope of this disclosure.

[0061] At 602, method 600 may include coupling at least one semiconductor die to a first surface of a substrate. The substrate may have a second surface opposite to the first surface. Furthermore, the second surface may be a first outer surface of a semiconductor package. (References herein) Figures 1 to 4 Example base 106 and example semiconductor die 102 are discussed. It is worth noting that in some embodiments, the semiconductor package does not include any wire bonding to at least one semiconductor die.

[0062] In some embodiments, at least one semiconductor die may include a first die surface and a second die surface opposite to the first die surface. The first die surface may have a first die contact and / or the second die surface may have a second die contact. Furthermore, in some embodiments, coupling the at least one semiconductor die to the first surface of the base may include coupling the first die contact to the base. For example, in some embodiments, coupling the first die contact to the base includes coupling the first die contact to the base using a die adhesion material.

[0063] At 604, method 600 may include forming an insulating portion on a substrate such that the insulating portion is on at least one semiconductor die. The insulating portion may form a first outer surface of a semiconductor package. The first outer surface may be opposite to another outer surface. The insulating portion may be formed in any suitable manner. For example, in some embodiments, the insulating portion may be molded (e.g., by fan-out wafer-level process). The insulating portion may cover at least one semiconductor die. The insulating portion may include any suitable electrical and / or thermal insulating material. For example, in some embodiments, the insulating portion may be or may include epoxy molding compound.

[0064] At 606, method 600 may include forming at least one through-hole extending from a first outer surface through an insulating portion to at least one semiconductor die or base. For example, in some embodiments, forming at least one through-hole may include coupling at least one through-hole to a second die contact. As an example, a cavity for receiving the through-hole may be formed in the insulating portion, such as by drilling, molding, adding around the cavity, or other means. The cavity may be filled with a conductive material to form the through-hole. As another example, the through-hole may be formed prior to molding the insulating portion.

[0065] Furthermore, in some embodiments, method 600 may also include forming an interconnect structure on a first outer surface of the semiconductor package. The interconnect structure may be electrically coupled to at least one through-hole. For example, one or more solder bumps, pads, etc., electrically coupled to the through-hole may be formed. The interconnect structure can facilitate coupling the semiconductor package to a circuit board.

[0066] In some embodiments, forming at least one through-hole may include forming multiple through-holes. For example, Figure 7 A method for forming a plurality of through-holes according to an exemplary embodiment of the present disclosure is shown. For purposes of illustration and discussion, Figure 7 Example processing steps are depicted. Using the disclosure provided herein, those skilled in the art will understand that the processing steps of any method described herein can be adjusted, modified, or included in the absence of steps not shown, omitted, and / or rearranged without departing from the scope of this disclosure.

[0067] At 702, method 700 may include forming a first through-hole on at least one semiconductor die, extending from a first outer surface through an insulating portion to a second die contact. For example, the first through-hole may be a source via forming a source interconnect structure to a source contact of the semiconductor die.

[0068] At 704, method 700 may include forming a second through-hole extending from the first outer surface through an insulating portion to a base. The second through-hole may be electrically coupled to a first die contact via the base. For example, in some embodiments, the second through-hole may be a drain via forming a drain interconnect structure to a drain contact of a semiconductor die.

[0069] Furthermore, in some embodiments, such as in embodiments where at least one semiconductor die includes a third die contact on a second die surface, method 700 may include forming a third through-hole extending from a first outer surface through an insulating portion to the third die contact. For example, in some embodiments, the third through-hole may be a gate via forming a gate interconnect structure to a gate contact on the semiconductor die.

[0070] Now back Figure 6 Method 600 may further include, at 608, coupling the first outer surface of the semiconductor package to the circuit board in a flip-chip configuration. For example, the semiconductor package may be coupled by bump bonding, soldering, or otherwise such that the first outer surface acts as a cooling pad for the semiconductor package. Furthermore, in some embodiments, method 600 may also include providing an underfill material between the first outer surface and the circuit board.

[0071] In some embodiments, method 600 can be implemented as a fan-out wafer-level process. In a fan-out wafer-level process, a wafer is first diced into one or more semiconductor dies. The semiconductor dies can then be precisely repositioned on a carrier wafer or panel. Space for fan-out can be maintained around the periphery of the dies. Insulating portions can then be formed by reconstructing the carrier, such as by molding. A base or redistribution layer can then be formed on top of the molded area (e.g., on top of the semiconductor die and the adjacent fan-out area). Vias can be formed in the insulating portions after the base is formed. Finally, interconnect structures can then be formed on top of the vias. It should be understood that the steps of method 600 can be performed in any order, such as in the fan-out wafer-level process described above.

[0072] The following describes exemplary aspects of this disclosure. Any of the features or examples below may be used in conjunction with any implementation or feature provided in this disclosure.

[0073] One exemplary embodiment of this disclosure relates to a semiconductor package. The semiconductor package includes a base having a first surface and a second surface opposite to the first surface. The semiconductor package includes at least one semiconductor die attached to the second surface of the base. The semiconductor package includes insulating portions on the second surface of the base and on at least one semiconductor die. The insulating portions form a first outer surface of the semiconductor package. The semiconductor package includes at least one through-hole extending from the first outer surface through the insulating portions to at least one of the semiconductor die or the base.

[0074] In some examples, the first surface of the base is the second outer surface of the semiconductor package. The second outer surface is opposite to the first outer surface.

[0075] In some examples, at least one through-hole includes multiple through-holes. The semiconductor package includes multiple interconnect structures. Each interconnect structure is coupled to at least one of the multiple through-holes. Each interconnect structure is on a first outer surface of the semiconductor package.

[0076] In some examples, all interconnect structures of the semiconductor package are on the first outer surface to provide a flip-chip configuration for the semiconductor package.

[0077] In some examples, each interconnect structure includes pads or solder bumps.

[0078] In some examples, at least one semiconductor die includes a first die surface and a second die surface opposite to the first die surface. The first die surface has a first die contact, and the second die surface has a second die contact. In some examples, the first die contact is coupled to a base. In some examples, the first die contact is coupled to the base using a die attachment material. In some examples, at least one through-hole is coupled to the second die contact.

[0079] In some examples, at least one through-hole includes: a first through-hole extending from a first outer surface through an insulating portion to a second die contact on at least one semiconductor die; and a second through-hole extending from the first outer surface through an insulating portion to a base. The second through-hole is electrically coupled to the first die contact via the base.

[0080] In some examples, at least one semiconductor die includes a third die contact on the die surface. In some examples, at least one through-hole includes a third through-hole extending from a first outer surface through an insulating portion to the third die contact.

[0081] In some examples, the semiconductor package includes a plurality of second through-holes extending from a first outer surface through an insulating portion to a base.

[0082] In some examples, the base comprises a thermally and electrically conductive material. In some examples, the base comprises metal. In some examples, the base comprises multiple metal layers with an insulating layer between the metal layers. In some examples, the base comprises a direct-bonded copper (DBC) substrate or an active metal brazing (AMB) substrate. In some examples, the base forms a thermally conductive cooling layer for a semiconductor package.

[0083] In some examples, the semiconductor package includes multiple semiconductor dies. The semiconductor package also includes a redistribution layer that couples at least one through-hole to the multiple semiconductor dies.

[0084] In some examples, the semiconductor package does not include any wire bonding to at least one semiconductor die.

[0085] In some examples, the insulating portion covers at least one semiconductor die.

[0086] In some examples, the insulation portion includes epoxy molding compound.

[0087] In some examples, at least one semiconductor die includes a wide-bandgap semiconductor. In some examples, the wide-bandgap semiconductor is silicon carbide or a group III nitride.

[0088] In some examples, at least one semiconductor die includes a silicon carbide-based MOSFET. In some examples, at least one semiconductor die includes a silicon carbide-based Schottky diode. In some examples, at least one semiconductor die includes a group III nitride-based high electron mobility transistor.

[0089] Another exemplary embodiment of this disclosure relates to a base having a first surface and a second surface. The second surface is opposite to the first surface. A semiconductor package includes at least one semiconductor die. The at least one semiconductor die includes a first die surface having a drain contact and a second die surface having a source contact and a gate contact. The drain contact is coupled to the first surface of the base. The semiconductor package includes insulating portions on the base and on the semiconductor die, the insulating portions forming a first outer surface of the semiconductor package. The semiconductor package includes a first through-hole extending from the first outer surface through the insulating portion to the gate contact. The semiconductor package includes a second through-hole extending from the first outer surface through the insulating portion to the drain contact. The semiconductor package includes a third through-hole extending from the first outer surface through the insulating portion to the base. The drain contact is coupled to the third through-hole through the base.

[0090] In some examples, the first surface of the base is the second outer surface of the semiconductor package. The second outer surface is opposite to the first outer surface.

[0091] In some examples, the semiconductor package includes a gate interconnect structure, a source interconnect structure, and a drain interconnect structure on a first outer surface.

[0092] In some examples, the gate interconnect structure is coupled to a first through-hole, the source interconnect structure is coupled to a second through-hole, and the drain interconnect structure is coupled to a third through-hole.

[0093] In some examples, the gate interconnect, source interconnect, and drain interconnect all include one or more pads or one or more solder bumps.

[0094] In some examples, the first outer surface of the semiconductor package is mounted onto a printed circuit board in a flip-chip configuration. In some examples, the package includes an underfill material between the semiconductor package and the printed circuit board.

[0095] In some examples, the base comprises a thermally and electrically conductive material. In some examples, the base comprises metal. In some examples, the base comprises multiple metal layers with an insulating layer between the metal layers. In some examples, the base comprises a direct-bonded copper (DBC) substrate or an active metal brazing (AMB) substrate. In some examples, the base forms a thermally conductive cooling layer for a semiconductor package.

[0096] In some examples, the semiconductor package does not include any wire bonding to at least one semiconductor die.

[0097] In some examples, the insulating portion covers at least one semiconductor die.

[0098] In some examples, the insulation portion includes epoxy molding compound.

[0099] In some examples, at least one semiconductor die includes a wide-bandgap semiconductor. In some examples, the wide-bandgap semiconductor is silicon carbide or a group III nitride.

[0100] In some examples, at least one semiconductor die includes a silicon carbide-based MOSFET. In some examples, at least one semiconductor die includes a silicon carbide-based Schottky diode. In some examples, at least one semiconductor die includes a group III nitride-based high electron mobility transistor.

[0101] Another exemplary embodiment of this disclosure relates to a method of forming a semiconductor package. The method includes coupling at least one semiconductor die to a first surface of a substrate. The substrate has a second surface opposite to the first surface. The method includes forming an insulating portion on the substrate such that the insulating portion is on at least one semiconductor die. The insulating portion forms a first outer surface of the semiconductor package. The method includes forming at least one through-hole extending from the first outer surface through the insulating portion to either the at least one semiconductor die or the substrate.

[0102] In some examples, the first surface of the base is the second outer surface of the semiconductor package. The second outer surface is opposite to the first outer surface.

[0103] In some examples, this method is a fan-out wafer-level process.

[0104] In some examples, at least one semiconductor die includes a first die surface and a second die surface opposite to the first die surface. The first die surface has a first die contact, and the second die surface has a second die contact. Coupling the at least one semiconductor die to the first surface of the base includes coupling the first die contact to the base.

[0105] In some examples, the method includes forming at least one through-hole, which includes coupling the at least one through-hole to a second die contact.

[0106] In some examples, forming at least one through-hole includes: forming a first through-hole extending from a first outer surface through an insulating portion to a second die contact on at least one semiconductor die; and forming a second through-hole extending from the first outer surface through an insulating portion to a base. The second through-hole is electrically coupled to the first die contact via the base.

[0107] In some examples, at least one semiconductor die includes a third die contact on the surface of a second die. In some examples, forming at least one through-hole includes forming a third through-hole extending from a first outer surface through an insulating portion to the third die contact.

[0108] In some examples, the base comprises a thermally and electrically conductive material. In some examples, the base comprises metal. In some examples, the base comprises multiple metal layers with an insulating layer between the metal layers. In some examples, the base comprises a direct-bonded copper (DBC) substrate or an active metal brazing (AMB) substrate. In some examples, the base forms a thermally conductive cooling layer for a semiconductor package.

[0109] In some examples, the method includes forming an interconnect structure on a first outer surface of the semiconductor package. The interconnect structure is electrically coupled to at least one through-hole. In some examples, the interconnect structure includes pads or solder bumps.

[0110] In some examples, the method includes coupling a first outer surface of the semiconductor package to a circuit board in a flip-chip configuration. In some examples, the method includes providing an underfill material between the first outer surface and the circuit board.

[0111] In some examples, the semiconductor package does not include any wire bonding to at least one semiconductor die.

[0112] In some examples, the insulating portion covers at least one semiconductor die.

[0113] In some examples, the insulation portion includes epoxy molding compound.

[0114] In some examples, at least one semiconductor die includes a wide-bandgap semiconductor. In some examples, the wide-bandgap semiconductor is silicon carbide or a group III nitride.

[0115] In some examples, at least one semiconductor die includes a silicon carbide-based MOSFET. In some examples, at least one semiconductor die includes a silicon carbide-based Schottky diode. In some examples, at least one semiconductor die includes a group III nitride-based high electron mobility transistor.

[0116] While this subject matter has been described in detail with reference to specific exemplary embodiments, it should be understood that those skilled in the art, upon understanding the foregoing, can readily modify, vary, and make equivalent substitutions to these embodiments. Therefore, the scope of this disclosure is exemplary and not restrictive, and this disclosure does not exclude the inclusion of such modifications, variations, and / or additions to the subject matter, as will be clear to those skilled in the art.

Claims

1. A semiconductor package, comprising: The base has a first surface and a second surface opposite to the first surface; At least one semiconductor die is attached to the second surface of the base; An insulating portion is present on the second surface of the base and on the at least one semiconductor die, the insulating portion forming the first outer surface of the semiconductor package; and At least one through-hole extends from the first outer surface through the insulating portion to at least one of the semiconductor die or the base.

2. The semiconductor package according to claim 1, wherein, The first surface of the base is the second outer surface of the semiconductor package, and the second outer surface is opposite to the first outer surface.

3. The semiconductor package according to claim 2, wherein, The at least one through-hole includes a plurality of through-holes, wherein the semiconductor package further includes a plurality of interconnect structures, each interconnect structure being coupled to at least one of the plurality of through-holes, and each interconnect structure being on the first outer surface of the semiconductor package.

4. The semiconductor package according to claim 3, wherein, All interconnect structures of the semiconductor package are located on the first outer surface to provide a flip-chip configuration for the semiconductor package.

5. The semiconductor package according to claim 3, wherein, Each interconnect structure includes pads or solder bumps.

6. The semiconductor package according to claim 1, wherein, The at least one semiconductor die includes a first die surface and a second die surface opposite to the first die surface, the first die surface having a first die contact, and the second die surface having a second die contact.

7. The semiconductor package according to claim 6, wherein, The first die contact is coupled to the base.

8. The semiconductor package according to claim 7, wherein, The first die contact is coupled to the base using die attachment material.

9. The semiconductor package according to claim 6, wherein, The at least one through-hole is coupled to the second core contact.

10. The semiconductor package according to claim 6, wherein, The at least one through-hole includes: A first through-hole extends from the first outer surface through the insulating portion to the second die contact on the at least one semiconductor die; and The second through-hole extends from the first outer surface through the insulating portion to the base, and the second through-hole is electrically coupled to the first die contact through the base.

11. The semiconductor package of claim 10, wherein, The at least one semiconductor die includes a third die contact on the surface of the second die.

12. The semiconductor package of claim 11, wherein, The at least one through-hole includes: The third through-hole extends from the first outer surface through the insulating portion to the third die contact.

13. The semiconductor package of claim 10, wherein, The semiconductor package includes a plurality of second through-holes extending from the first outer surface through the insulating portion to the base.

14. The semiconductor package according to claim 1, wherein, The base is made of a thermally and electrically conductive material.

15. The semiconductor package according to claim 1, wherein, The base is made of metal.

16. The semiconductor package according to claim 1, wherein, The base comprises multiple metal layers, with an insulating layer between the multiple metal layers.

17. The semiconductor package of claim 16, wherein, The base comprises a direct-bonded copper (DBC) substrate or an active metal brazing (AMB) substrate.

18. The semiconductor package according to claim 1, wherein, The base forms a thermally conductive cooling layer for the semiconductor package.

19. The semiconductor package according to claim 1, wherein, The semiconductor package includes a plurality of semiconductor dies, wherein the semiconductor package further includes a redistribution layer that couples the at least one through-hole to the plurality of semiconductor dies.

20. The semiconductor package according to claim 1, wherein, The semiconductor package does not include any wire bonding to the at least one semiconductor die.

21. The semiconductor package according to claim 1, wherein, The insulating portion covers the at least one semiconductor die.

22. The semiconductor package according to claim 1, wherein, The insulating portion includes epoxy molding compound.

23. The semiconductor package according to claim 1, wherein, The at least one semiconductor die includes a wide-bandgap semiconductor.

24. The semiconductor package of claim 23, wherein, The wide-bandgap semiconductor is silicon carbide or a group III nitride.

25. The semiconductor package according to claim 1, wherein, The at least one semiconductor die includes a silicon carbide-based MOSFET.

26. The semiconductor package according to claim 1, wherein, The at least one semiconductor die includes a silicon carbide-based Schottky diode.

27. The semiconductor package according to claim 1, wherein, The at least one semiconductor die includes a high electron mobility transistor based on group III nitrides.

28. A semiconductor package, comprising: The base has a first surface and a second surface, the second surface being opposite to the first surface; At least one semiconductor die, the at least one semiconductor die including a first die surface having a drain contact and a second die surface having a source contact and a gate contact, the drain contact being coupled to the first surface of the base; An insulating portion, on the base and the semiconductor die, forms the first outer surface of the semiconductor package; A first through-hole extends from the first outer surface through the insulating portion to the gate contact; The second through-hole extends from the first outer surface through the insulating portion to the drain contact; and A third through-hole extends from the first outer surface through the insulating portion to the base, wherein the drain contact is coupled to the third through-hole via the base.

29. The semiconductor package of claim 28, wherein, The first surface of the base is the second outer surface of the semiconductor package, and the second outer surface is opposite to the first outer surface.

30. The semiconductor package of claim 28, further comprising a gate interconnect structure, a source interconnect structure, and a drain interconnect structure on the first outer surface.

31. The semiconductor package of claim 30, wherein, The gate interconnect structure is coupled to the first through-hole, the source interconnect structure is coupled to the second through-hole, and the drain interconnect structure is coupled to the third through-hole.

32. The semiconductor package of claim 30, wherein, The gate interconnect structure, the source interconnect structure, and the drain interconnect structure each include one or more pads or one or more solder bumps.

33. The semiconductor package of claim 30, wherein, The first outer surface of the semiconductor package is mounted to a printed circuit board in a flip-chip configuration.

34. The semiconductor package of claim 33, further comprising an underfill material between the semiconductor package and the printed circuit board.

35. The semiconductor package of claim 28, wherein, The base is made of a thermally and electrically conductive material.

36. The semiconductor package of claim 28, wherein, The base is made of metal.

37. The semiconductor package of claim 28, wherein, The base comprises multiple metal layers, with an insulating layer between the multiple metal layers.

38. The semiconductor package of claim 37, wherein, The base includes a direct-bonded copper (DBC) substrate or an active metal brazing (AMB) substrate.

39. The semiconductor package of claim 28, wherein, The base forms a thermally conductive cooling layer for the semiconductor package.

40. The semiconductor package of claim 28, wherein, The semiconductor package does not include any wire bonding to the at least one semiconductor die.

41. The semiconductor package according to claim 28, wherein, The insulating portion covers the at least one semiconductor die.

42. The semiconductor package of claim 28, wherein, The insulating portion includes epoxy molding compound.

43. The semiconductor package of claim 28, wherein, The at least one semiconductor die includes a wide-bandgap semiconductor.

44. The semiconductor package of claim 43, wherein, The wide-bandgap semiconductor is silicon carbide or a group III nitride.

45. The semiconductor package of claim 28, wherein, The at least one semiconductor die includes a silicon carbide-based MOSFET.

46. ​​The semiconductor package of claim 28, wherein, The at least one semiconductor die includes a high electron mobility transistor based on group III nitrides.

47. A method of forming a semiconductor package, the method comprising: At least one semiconductor die is coupled to a first surface of a base, the base having a second surface opposite to the first surface; An insulating portion is formed on the base such that the insulating portion is on the at least one semiconductor die, and the insulating portion forms the first outer surface of the semiconductor package; and At least one through-hole is formed extending from the first outer surface through the insulating portion to the at least one semiconductor die or the base.

48. The method according to claim 47, wherein, The first surface of the base is the second outer surface of the semiconductor package, and the second outer surface is opposite to the first outer surface.

49. The method according to claim 47, wherein, The method described is a fan-out wafer-level process.

50. The method of claim 47, wherein, The at least one semiconductor die includes a first die surface and a second die surface opposite to the first die surface, the first die surface having a first die contact and the second die surface having a second die contact, wherein coupling the at least one semiconductor die to the first surface of the base includes coupling the first die contact to the base.

51. The method according to claim 49, wherein, Forming the at least one through-hole includes coupling the at least one through-hole to a second die contact.

52. The method according to claim 49, wherein, Forming the at least one through-hole includes: A first through-hole is formed on the at least one semiconductor die, extending from the first outer surface through the insulating portion to the second die contact; and A second through-hole is formed extending from the first outer surface through the insulating portion to the base, and the second through-hole is electrically coupled to the first die contact through the base.

53. The method according to claim 52, wherein, The at least one semiconductor die includes a third die contact on the surface of the second die.

54. The method according to claim 53, wherein, Forming the at least one through-hole includes: A third through-hole is formed, extending from the first outer surface through the insulating portion to the third die contact.

55. The method according to claim 47, wherein, The base is made of a thermally and electrically conductive material.

56. The method according to claim 47, wherein, The base is made of metal.

57. The method of claim 47, wherein, The base comprises multiple metal layers, with an insulating layer between the multiple metal layers.

58. The method according to claim 57, wherein, The base comprises a direct-bonded copper (DBC) substrate or an active metal brazing (AMB) substrate.

59. The method according to claim 47, wherein, The base forms a thermally conductive cooling layer for the semiconductor package.

60. The method of claim 47, further comprising forming an interconnect structure on the first outer surface of the semiconductor package, the interconnect structure being electrically coupled to the at least one through-hole.

61. The method according to claim 60, wherein, The interconnect structure includes pads or solder bumps.

62. The method of claim 47, further comprising coupling the first outer surface of the semiconductor package to a circuit board in a flip-chip configuration.

63. The method of claim 62, further comprising providing an underfill material between the first outer surface and the circuit board.

64. The method of claim 47, wherein, The semiconductor package does not include any wire bonding to the at least one semiconductor die.

65. The method according to claim 47, wherein, The insulating portion covers the at least one semiconductor die.

66. The method according to claim 47, wherein, The insulating portion includes epoxy molding compound.

67. The method of claim 47, wherein, The at least one semiconductor die includes a wide-bandgap semiconductor.

68. The method according to claim 67, wherein, The wide-bandgap semiconductor is silicon carbide or a group III nitride.

69. The method of claim 47, wherein, The at least one semiconductor die includes a silicon carbide-based MOSFET.

70. The method of claim 47, wherein, The at least one semiconductor die includes a silicon carbide-based Schottky diode.

71. The method according to claim 47, wherein, The at least one semiconductor die includes a high electron mobility transistor based on group III nitrides.

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