Induction detection circuit and electronic equipment

Abstract

The invention discloses an induction detection circuit and electronic equipment. The induction detection circuit comprises a reference voltage output end, a first switching circuit, an inductive charge generation module and a charge integration module, the first end of the first switch circuit is connected with the reference voltage output end, the second end of the first switch circuit is connected with the inductive charge generation module, the third end of the first switch circuit is connected with the charge integration module, and when the first end and the second end of the first switch circuit are conducted, the inductive detection circuit is in a charge sampling state; when the second end and the third end of the first switch circuit are conducted, the induction detection circuit is in a charge integration state. The induction detection circuit is alternately switched between the charge sampling state and the charge integration state, and after the charge sampling state appears for the first time and the charge integration state appears for at least two times, the detection signal corresponding to the inductive charge quantity of the current integration is output, so that the integration frequency of the charge quantity is increased, and the intensity of the detection signal is improved; and the detection sensitivity is improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of inductive detection, and in particular to an inductive detection circuit and an electronic device. BACKGROUND

[0002] With the development of inductive detection technology, capacitive inductive detection technology has been applied in many types of devices, which can include capacitive touch screen devices and capacitive water level measurement devices. In the capacitive touch screen device, when a finger touches and slides on the operation screen, the human body electric field will cause the capacitor to generate induced charge, and the integration of the induced charge will obtain the capacitance change, i.e., a detection signal, and the operation screen can be determined according to the capacitance change whether there is a touch operation. In the capacitive water level measurement device, when the electrode is immersed in water, the change of water level will cause the dielectric constant to change and also generate induced charge, and the integration of the induced charge will obtain the capacitance change, so the water level measurement can also be realized according to the capacitance change.

[0003] In the related art, when determining the capacitance change, each integration of the induced charge will output an inductive detection signal. When the number of induced charges is small, the output detection signal is also weak, which leads to that the detection signal cannot be obtained and the detection sensitivity is low. SUMMARY

[0004] The technical problem solved by the present application is that when determining the capacitance change, each integration of the induced charge will output an inductive detection signal, which leads to that the detection signal cannot be obtained and the detection sensitivity is low when the number of induced charges is small.

[0005] According to a first aspect, an embodiment of the present application provides an inductive detection circuit, comprising a reference voltage output end, a first switch circuit, an induced charge generation module and a charge integration module; The first switch circuit comprises a first end, a second end and a third end, the first end of the first switch circuit is connected to the reference voltage output end, the second end of the first switch circuit is connected to the induced charge generation module, and the third end of the first switch circuit is connected to the charge integration module. The first switch circuit is used to conduct between its first end and second end, or conduct between its second end and third end. When the first end and the second end of the first switch circuit are conducted, the inductive detection circuit is in a charge sampling state; when the second end and the third end of the first switch circuit are conducted, the inductive detection circuit is in a charge integration state; The induced charge generation module is used to generate induced charge when the inductive detection circuit is in the charge sampling state, and the induced charge generation module is also used to transfer the induced charge to the charge integration module when the inductive detection circuit is in the charge integration state; The charge integration module is used to receive the induced charge transferred by the induced charge generation module when the induction detection circuit is in the charge integration state, and to integrate the induced charge; The sensing detection circuit alternately switches between the charge sampling state and the charge integration state, and the charge integration module, after the charge sampling state appears for the first time, appears at least twice in the charge integration state, and then responds to the first control signal to output a detection signal corresponding to the number of induced charges being integrated.

[0006] In one embodiment, the sensing detection circuit further includes: A parasitic charge cancellation module is connected between the third terminal of the first switching circuit and the charge integration module. The parasitic charge cancellation module is used to generate cancellation charge when the sensing detection circuit is in the charge sampling state, and to transfer the cancellation charge to the charge integration module when the sensing detection circuit is in the charge integration state. The polarity of the cancellation charge is different from the polarity of the parasitic charge generated by the sensing charge generation module when the sensing detection circuit is in the charge integration state, so that the parasitic charge generated by the sensing charge generation module is canceled by the cancellation charge when the sensing detection circuit is in the charge integration state.

[0007] In one embodiment, the number of parasitic charges generated by the induced charge generating module is equal to the number of offset charges generated by the parasitic charge cancelling module, or the difference between the number of parasitic charges generated by the induced charge generating module and the number of offset charges generated by the parasitic charge cancelling module is within a preset range.

[0008] In one embodiment, the parasitic charge cancellation module includes: at least one charge cancellation generation unit and a second switching circuit; The charge cancellation generating unit includes a third switching circuit and a compensation capacitor bank; The second switching circuit includes a first terminal, a second terminal, and a third terminal. The first terminal of the second switching circuit is connected to the compensation capacitor group in each of the said charge cancellation generating units. The second terminal of the second switching circuit is grounded. The third terminal of the second switching circuit is connected to the third terminal of the first switching circuit. The third switching circuit includes a first terminal, a second terminal, a third terminal, and a fourth terminal. The first terminal of the third switching circuit in each of the charge-canceling units is connected to the compensation capacitor group in the same charge-canceling unit. The second terminal of the third switching circuit is used to connect to the reference voltage output terminal. Both the third terminal and the fourth terminal of the third switching circuit are grounded. Specifically, when the sensing detection circuit is in the charge sampling state, the first and second terminals of the third switching circuit in one or more of the at least one canceling charge generating units are turned on, as are the first and second terminals of the second switching circuit, thereby generating canceling charge in the compensation capacitor group of the one or more canceling charge generating units; when the sensing detection circuit is in the charge integration state, the first and fourth terminals of the third switching circuit corresponding to the one or more canceling charge generating units are turned on, as are the first and third terminals of the second switching circuit, to cancel the parasitic charge generated by the sensing charge generating module.

[0009] In one embodiment, when multiple offset charge generating units are provided, the number of offset charges generated by the compensation capacitor group in each offset charge generating unit is equal when generating offset charges.

[0010] In one embodiment, when multiple offset charge generating units are provided, the number of offset charges generated by the compensation capacitor groups in at least two of the multiple offset charge generating units gradually increases when offset charges are generated.

[0011] In one embodiment, the second switching circuit includes: a first switch and a second switch; one end of the first switch is grounded, the other end of the first switch is connected to one end of the second switch, and the other end of the second switch is connected to a third end of the first switching circuit, wherein the connection end of the first switch and the second switch is the first end of the second switching circuit, one end of the first switch is the second end of the second switching circuit, and the other end of the second switch is the third end of the second switching circuit. The third switching circuit includes a third switch, a fourth switch, and a switching switch; one end of the third switch is grounded, and the other end of the third switch and one end of the fourth switch are connected to the compensation capacitor bank; the switching switch includes a first end, a second end, and a common end, the common end of the switching switch is connected to the other end of the fourth switch, the first end of the switching switch is connected to the reference voltage output terminal, and the second end of the switching switch is grounded, wherein the connection end of the third switch and the fourth switch is the first end of the third switching circuit, the grounding end of the third switch is the third end of the third switching circuit, the first end of the switching switch is the second end of the third switching circuit, and the second end of the switching switch is the fourth end of the third switching circuit.

[0012] In one embodiment, the charge integration module includes: an integrator, an integrating capacitor, and a reset switch; The third terminal of the first switching circuit is connected to the inverting input terminal of the integrator, and the non-inverting input terminal of the integrator is grounded; One end of the integrating capacitor is connected to the inverting input terminal of the integrator, and the other end of the integrating capacitor is connected to the output terminal of the integrator. One end of the reset switch is connected to one end of the integrating capacitor, and the other end of the reset switch is connected to the other end of the integrating capacitor.

[0013] In one embodiment, the first switching circuit includes a fifth switch and a sixth switch; one end of the fifth switch is connected to the reference voltage output terminal, the other end of the fifth switch is connected to one end of the sixth switch, the other end of the sixth switch is connected to the charge integration module, and the connection terminal of the fifth switch and the sixth switch is connected to the induced charge generation module, wherein one end of the fifth switch is the first terminal of the first switching circuit, the connection terminal of the fifth switch and the sixth switch is the second terminal of the first switching circuit, and the other end of the sixth switch is the third terminal of the first switching circuit.

[0014] According to a second aspect, one embodiment of this application provides an electronic device, including: a sensing detection circuit as described above.

[0015] According to the induction detection circuit and device of the above embodiment, the induction detection circuit alternates between charge sampling state and charge integration state, and the charge integration module outputs a detection signal corresponding to the number of induction charges integrated at the moment after the first occurrence of charge sampling state and at least two charge integration states. It can be seen that when outputting the detection signal, the number of times the number of charges is integrated is increased, the strength of the detection signal is improved, and the detection sensitivity is increased. Attached Figure Description

[0016] Figure 1 A circuit diagram of a sensing detection circuit according to one embodiment; Figure 2 A circuit diagram of an induction detection circuit equipped with a parasitic charge cancellation module according to one embodiment; Figure 3 This is a circuit diagram of a parasitic charge cancellation module according to one embodiment; Figure 4 This is a diagram showing the relationship between a reset switch, a first switch circuit, a second switch circuit, a third switch circuit, and a detection signal, according to one embodiment.

[0017] Reference numerals: 100, Induced charge generation module; 200, First switching circuit; 300, Charge integration module; 400, Parasitic charge cancellation module; 401, Second switching circuit; 402, Cancelling charge generation unit; 4021, Compensation capacitor bank; 4022, Third switching circuit; S1, First switch; S2, Second switch; S3, Third switch; S4, Fourth switch; S5, Fifth switch; S6, Sixth switch; SRST 1. Reset switch; △C; 2. Sensing capacitor; C f Integrating capacitor; C PAD Parasitic capacitance; AMP, integrator. Detailed Implementation

[0018] The present invention will now be described in further detail with reference to specific embodiments and accompanying drawings. Similar elements in different embodiments are referred to by associated similar element reference numerals. In the following embodiments, many details are described to facilitate a better understanding of this application. However, those skilled in the art will readily recognize that some features may be omitted in different situations, or may be replaced by other elements, materials, or methods. In some cases, certain operations related to this application are not shown or described in the specification. This is to avoid obscuring the core parts of this application with excessive description. For those skilled in the art, detailed description of these related operations is not necessary; they can fully understand the related operations based on the description in the specification and general technical knowledge in the art.

[0019] Furthermore, the features, operations, or characteristics described in the specification can be combined in any suitable manner to form various embodiments. At the same time, the steps or actions in the method description can be rearranged or adjusted in a manner obvious to those skilled in the art. Therefore, the various orders in the specification and drawings are only for the clear description of a particular embodiment and do not imply a necessary order, unless otherwise stated that a particular order must be followed.

[0020] The serial numbers assigned to components in this document, such as "first" and "second," are used only to distinguish the described objects and have no sequential or technical meaning. The terms "connection" and "linkage" used in this application, unless otherwise specified, include both direct and indirect connections (linkages).

[0021] This application provides an inductive detection circuit that alternates between a charge sampling state and a charge integration state. The charge integration module 300 outputs a detection signal corresponding to the number of induced charges being integrated after at least two charge integration states following the first occurrence of the charge sampling state. Thus, when outputting the detection signal, the number of times the charge is integrated is increased, thereby improving the strength of the detection signal and increasing the detection sensitivity.

[0022] In some embodiments, such as Figure 1 As shown, the induction detection circuit may include a reference voltage output terminal, a first switching circuit 200, an induction charge generation module 100, and a charge integration module 300.

[0023] The first switching circuit 200 includes a first terminal, a second terminal, and a third terminal. The first terminal of the first switching circuit 200 is connected to the reference voltage output terminal VREF. The second terminal of the first switching circuit 200 is connected to the induced charge generation module 100. The third terminal of the first switching circuit 200 is connected to the charge integration module 300. The first switching circuit 200 is used to connect its first terminal and second terminal, or its second terminal and third terminal. When the first terminal and second terminal of the first switching circuit 200 are connected, the inductive detection circuit is in a charge sampling state. When the second terminal and third terminal of the first switching circuit 200 are connected, the inductive detection circuit is in a charge integration state.

[0024] The induced charge generation module 100 is used to generate induced charge when the induction detection circuit is in a charge sampling state. The induced charge generation module 100 is also used to transfer the induced charge to the charge integration module 300 when the induction detection circuit is in a charge integration state. The charge integration module 300 is used to receive the induced charge transferred by the induced charge generation module 100 and integrate the induced charge when the induction detection circuit is in a charge integration state. The induction detection circuit alternates between the charge sampling state and the charge integration state, and the charge integration module 300, after at least two charge integration states following the first occurrence of the charge sampling state, outputs a detection signal corresponding to the currently integrated amount of induced charge in response to a first control signal.

[0025] In some embodiments, the inductive detection circuit alternates between a charge sampling state and a charge integration state; that is, the first and second terminals, and the second and third terminals of the first switching circuit 200 are alternately turned on. Specifically, when the first and second terminals of the first switching circuit 200 are on, a reference voltage output from the reference voltage output terminal VREF is connected to the induced charge generation module 100, enabling the induced charge generation module 100 to generate induced charge. When the second and third terminals of the first switching circuit 200 are on, the induced charge generation module 100 can transfer the generated induced charge to the charge integration module 300.

[0026] Furthermore, when the second and third terminals of the first switching circuit 200 are turned on, the charge integration module 300 can integrate the induced charge transferred from the induced charge generation module 100. After performing at least two effective integrations, the charge integration module 300 can output a detection signal corresponding to the currently integrated induced charge quantity in response to the first control signal. That is, after the first occurrence of the charge sampling state, the charge integration module 300 will output a detection signal corresponding to the currently integrated induced charge quantity after at least two charge integration states. This detection signal is a voltage signal. When acquiring this voltage signal, it can be converted into a digital signal by an analog-to-digital converter (ADC) and output to the main control circuit of the electronic device using this sensing detection circuit to calculate the capacitance change.

[0027] In some embodiments, when controlling the charge integration module 300, a timer in an electronic device using the induction detection circuit can count the number of occurrences of the charge sampling state and / or charge integration state. After reaching a preset number of occurrences, the main control circuit in the electronic device outputs a first control signal to the charge integration module 300, so that the charge integration module 300 outputs a detection signal corresponding to the current amount of induced charge integrated. The preset number of occurrences is set in the main control circuit, and those skilled in the art can determine the specific value of the preset number of occurrences according to actual conditions. For example, when the amount of induced charge generated each time is large, a relatively small preset number of occurrences can be set; when the amount of induced charge generated each time is small, a relatively large preset number of occurrences can be set. The specific value of the preset number of occurrences is not limited here.

[0028] In some embodiments, such as Figure 1 , Figure 2 As shown, the charge integration module 300 may include an integrator AMP, an integrating capacitor Cf, and a reset switch SRST; the third terminal of the first switching circuit 200 is connected to the inverting input terminal of the integrator AMP, and the non-inverting input terminal of the integrator AMP is grounded; one end of the integrating capacitor Cf is connected to the inverting input terminal of the integrator AMP, and the other end of the integrating capacitor Cf is connected to the output terminal of the integrator AMP; one end of the reset switch SRST is connected to one end of the integrating capacitor Cf, and the other end of the reset switch SRST is connected to the other end of the integrating capacitor Cf.

[0029] After a detection signal is output, the charge integration module 300 needs to be reset. During the reset operation, the induction detection circuit is put into charge sampling state. By controlling the reset switch SRST to close, the charge in the integrator AMP can be cleared to zero, avoiding the influence of the previously integrated induced charge in the integrator AMP when the next detection signal is output, and further improving the accuracy of the induction detection circuit.

[0030] In some embodiments, such as Figure 1 , Figure 2 As shown, the induced charge generation module 100 may include an induced capacitor ΔC and a parasitic capacitor CPAD. The induced capacitor ΔC is used to generate induced charge, and the charge generated by the parasitic capacitor CPAD is equivalent to the parasitic charge generated by the induced charge generation module 100.

[0031] Specifically, during the first cycle, the total charge of the charge sampling state is as follows: ; in, This represents the total charge sampled during the charge sampling state in the first cycle; This indicates the reference voltage output at the reference voltage output terminal VREF; Indicates induced charge; This represents parasitic charge.

[0032] The total charge after charge integration is as follows: ; in, This represents the total charge integrated during the charge integration state in the first period; This indicates the currently output detection signal; This indicates the capacitance value of the integrating capacitor.

[0033] Therefore, the expressions for the detection signal and induced charge output by the charge integration module 300 when the preset number of cycles is M (i.e., after M cycles) can be derived as follows: ; ; in, This represents the detection signal output after M cycles.

[0034] In some embodiments, the capacitance of the parasitic capacitor CPAD may be very large in practical applications. When the capacitance of CPAD is large, the voltage signal converted from CPAD may saturate the output of the charge integration module 300, thus failing to detect the induced charge and making it impossible to calculate the change in capacitance ΔC. Another scenario is that when the capacitance of ΔC is much smaller than that of CPAD, the voltage signal converted from ΔC accounts for a low proportion of the detection signal output by the charge integration module 300. Whether the voltage signal converted from CPAD saturates the output of the charge integration module 300 or the voltage signal converted from ΔC accounts for a low proportion of the detection signal output by the charge integration module 300, both will lead to reduced detection sensitivity, as can be seen from the above derivation formula.

[0035] To address the aforementioned problems, some embodiments, such as Figure 2 As shown, the inductive detection circuit also includes a parasitic charge cancellation module 400. The parasitic charge cancellation module 400 is connected between the third terminal of the first switching circuit 200 and the charge integration module 300. The parasitic charge cancellation module 400 generates a cancellation charge when the inductive detection circuit is in a charge sampling state. The parasitic charge cancellation module 400 also transfers the cancellation charge to the charge integration module 300 when the inductive detection circuit is in a charge integration state. The polarity of the cancellation charge is different from the polarity of the parasitic charge generated by the inductive charge generation module 100 when the inductive detection circuit is in a charge integration state, so that the parasitic charge generated by the inductive charge generation module 100 is canceled by the cancellation charge when the inductive detection circuit is in a charge integration state.

[0036] In this embodiment, when the sensing detection circuit is in the charge integration state, the parasitic charge cancellation module 400 can transfer the parasitic charge generated by the sensing charge generation module 100 to cancel the parasitic charge generated by the sensing charge generation module 100. Therefore, the influence of parasitic charge can be reduced and the detection sensitivity is increased, that is, it has higher detection sensitivity.

[0037] In some embodiments, the amount of parasitic charge generated by the induced charge generation module 100 is equal to the amount of offset charge generated by the parasitic charge cancellation module 400. That is, the offset charge generated by the parasitic charge cancellation module 400 can completely cancel the parasitic charge generated by the induced charge generation module 100. Therefore, in this case, the parasitic charge can be ignored, thereby further increasing the detection sensitivity.

[0038] In some embodiments, such as Figure 2 As shown, the parasitic charge cancellation module 400 may include at least one cancellation charge generating unit 402 and a second switching circuit 401; the cancellation charge generating unit 402 includes a third switching circuit 4022 and a compensation capacitor group 4021; the second switching circuit 401 includes a first terminal, a second terminal and a third terminal, the first terminal of the second switching circuit 401 is connected to the compensation capacitor group 4021 in each cancellation charge generating unit 402, the second terminal of the second switching circuit 401 is grounded, and the third terminal of the second switching circuit 401 is connected to the third terminal of the first switching circuit 200; the third switching circuit 4022 includes a first terminal, a second terminal, a third terminal and a fourth terminal, the first terminal of the third switching circuit 4022 in each cancellation charge generating unit 402 is connected to the compensation capacitor group 4021 in the same cancellation charge generating unit 402, the second terminal of the third switching circuit 4022 is used to connect to the reference voltage output terminal VREF, and both the third terminal and the fourth terminal of the third switching circuit 4022 are grounded.

[0039] When the sensing detection circuit is in the charge sampling state, the first and second terminals of the third switching circuit 4022 in one or more of the offset charge generation units 402 are turned on, and the first and second terminals of the second switching circuit 401 are turned on, thereby generating offset charge in the compensation capacitor group 4021 in one or more offset charge generation units 402; when the sensing detection circuit is in the charge integration state, the first and fourth terminals of the third switching circuit 4022 corresponding to one or more offset charge generation units 402 are turned on, and the first and third terminals of the second switching circuit 401 are turned on, so as to offset the parasitic charge generated by the sensing charge generation module 100.

[0040] When one charge cancellation generating unit 402 is provided, a third switching circuit 4022 and a compensation capacitor group 4021 are correspondingly provided. The specific capacitance value of the compensation capacitor group 4021 can be determined based on the amount of parasitic charge generated by the parasitic capacitor CPAD. For example, if the amount of parasitic charge generated by the induced charge generating module 100 is equal to the amount of cancellation charge generated by the parasitic charge cancellation module 400, the specific capacitance value of the compensation capacitor group 4021 can be determined based on the amount of parasitic charge.

[0041] When determining the specific compensation capacitor group 4021, the sensing capacitor ΔC is removed, and the appropriate capacitance value of the compensation capacitor group 4021 is determined by the detection signal output by the charge integration module 300. For example, if the detection signal output by the charge integration module 300 after multiple integrations is 0, it indicates that the offsetting charge generated by the compensation capacitor group 4021 can completely offset the parasitic charge generated by the parasitic capacitor CPAD.

[0042] Of course, a range can also be set. If the detection signal output after more than 300 integrations by the charge integration module is within this range, it is considered that the parasitic charge generated by the parasitic capacitor CPAD is insufficient to affect the capacitance change of the detected sensing capacitor ΔC. That is, if the detection signal converted from the compensation capacitor group 4021 after the compensation charge cancels the parasitic charge is within this range, it is considered that the parasitic charge generated by the parasitic capacitor CPAD is insufficient to affect the capacitance change of the detected sensing capacitor ΔC.

[0043] In some embodiments, such as Figure 3 As shown, multiple charge generation units 402 can be provided.

[0044] In one embodiment, when multiple offset charge generating units 402 are provided, the amount of offset charge generated by the compensation capacitor group 4021 in each offset charge generating unit 402 is equal when generating offset charge. In this embodiment, it is necessary to determine the amount of offset charge to be generated in the multiple offset charge generating units 402 based on the amount of parasitic charge. For example, if the parasitic capacitor CPAD generates 2C of parasitic charge, and each compensation capacitor group 4021 in the offset charge generating unit 402 generates 1C of offset charge, then in this case, it can be configured that the compensation capacitor groups 4021 in two offset charge generating units 402 generate offset charge.

[0045] Similarly, when specifically determining which of the multiple charge generation units 402 needs to generate charge, the sensing capacitor ΔC is removed, and the detection signal output by the charge integration module after more than 300 integrations is used to determine whether the specific capacitance value of the compensation capacitor group 4021 is appropriate. For example, if some of the charge generation units 402 generate charge, and the detection signal output by the charge integration module after more than 300 integrations is 0, it indicates that the partial charge generation unit 402 can completely cancel the parasitic charge generated by the parasitic capacitor CPAD. That is, when canceling parasitic charge, the partial charge generation unit 402 can generate charge.

[0046] Of course, a range can also be set. If the detection signal output by the charge integration module after more than 300 integrations is within this range when the partial offset charge generation unit 402 generates offset charge, then it is considered that the parasitic charge generated by the parasitic capacitor CPAD is insufficient to affect the capacitance change of the detected sensing capacitor ΔC. In this case, offset charge can be generated by the partial offset charge generation unit 402 when offset charge is generated.

[0047] In another embodiment, when multiple offset charge generating units 402 are provided, the number of offset charges generated gradually increases when the compensation capacitor group 4021 of the multiple offset charge generating units 402 generates offset charges.

[0048] like Figure 3As shown, the compensation capacitor group 4021 in the multiple compensation capacitor generating units 402 is a binary capacitor array. In this embodiment, the capacitance values ​​of the multiple compensation capacitor groups 4021 gradually increase in a geometric progression. When determining the compensation capacitor generating unit 402 that generates the compensation charge, a binary search method can be used. Specifically, by removing the sensing capacitor ΔC, a binary search method can be used to traverse the different cancellation charge generation units 402 among multiple cancellation charge generation units 402 to generate cancellation charges. When one of the cancellation charge generation units 402 generates cancellation charges, if the detection signal output by the charge integration module 300 after multiple integrations is 0, that is, no parasitic charges are transferred to the output of the charge integration module 300, it indicates that the cancellation charges generated in this case can cancel the parasitic charges. Then, the conduction status of the second terminal and the first terminal of the third switch circuit 4022 in the integration sampling stage in this case can be used as the first preset value. When the connected cancellation charge generation unit 402 (i.e., the connected compensation capacitor group 4021) changes, the integrator AMP needs to be reset to zero before multiple integrations are performed.

[0049] It should be noted that the first preset value refers to: if four offset charge generating units 402 are provided, and if the third offset charge generating unit 402 generates offset charge, the detection signal output by the charge integration module 300 after multiple integrations is 0, then the first preset value is 0010 (1 indicates that the second terminal and the first terminal of the third switch circuit 4022 are connected, and 0 indicates that the second terminal and the first terminal of the third switch circuit 4022 are disconnected); if the second offset charge generating unit 402 generates offset charge, and the detection signal output by the charge integration module 300 after multiple integrations is 0, then the first preset value is 0100. This first preset value can be set in the main control circuit of the sensing detection circuit, and the main control circuit controls the connection and disconnection of the second terminal and the first terminal of the third switch circuit 4022.

[0050] In this embodiment, when the number of canceling charges and the number of parasitic charges are equal, the relationship between the parasitic charges and the canceling charges is as follows: ; in, Indicates the cancellation of charge; Indicates parasitic charge; This represents a canceling charge of 1 unit, C.

[0051] With the parasitic charge cancellation module 400 in place, the total charge in the integral sampling state during the first cycle is as follows: ; in, This represents the total charge in the first period of charge sampling.

[0052] The total charge in the charge integral state of the first period is as follows: ; in, This represents the total charge in the first period of charge integration.

[0053] Based on the law of charge conservation, the following can be derived: .

[0054] Therefore, it can be deduced that after M operating cycles, the voltage at the output of the charge integration module 300 and The expression is as follows: ; .

[0055] Based on the above expression, it can be seen that the parasitic charge is canceled by the canceling charge, and the charge integration module 300 can integrate the voltage generated by the induced capacitor ΔC multiple times. That is, integrating the induced charge multiple times is equivalent to amplifying the changing voltage signal generated by the induced capacitor ΔC, ensuring that a voltage signal suitable for subsequent processing (amplified voltage signal) is obtained, thereby achieving more accurate detection. At the same time, the capacitance value of the induced capacitor ΔC can also be calculated using known parameters.

[0056] In some embodiments, such as Figure 2 As shown, the second switch circuit 401 may include a first switch S1 and a second switch S2.

[0057] One end of the first switch S1 is grounded, and the other end of the first switch S1 is connected to one end of the second switch S2. The other end of the second switch S2 is connected to the third end of the first switch circuit 200. The connection point of the first switch S1 and the second switch S2 forms the first end of the second switch circuit 401, one end of the first switch S1 forms the second end of the second switch circuit 401, and the other end of the second switch S2 forms the third end of the second switch circuit 401. When the first switch S1 is closed, the second end of the second switch circuit 401 and the first end of the second switch circuit 401 are connected; when the second switch S2 is closed, the third end of the second switch circuit 401 and the first end of the second switch circuit 401 are connected.

[0058] In some embodiments, such as Figure 2 , Figure 3 As shown, the third switch circuit 4022 may include a third switch S3, a fourth switch S4, and a switching switch.

[0059] One end of the third switch S3 is grounded, and the other end of the third switch S3 and one end of the fourth switch S4 are connected to the compensation capacitor group 4021. The switching switch includes a first end, a second end and a common end. The common end of the switching switch is connected to the other end of the fourth switch S4. The first end of the switching switch is connected to the reference voltage output end, and the second end of the switching switch is grounded. The connection end of the third switch S3 and the fourth switch S4 is the first end of the third switch circuit 4022. The grounding end of the third switch S3 is the third end of the third switch circuit 4022. The first end of the switching switch is the second end of the third switch circuit 4022, and the second end of the switching switch is the fourth end of the third switch circuit 4022. Specifically, when the third switch S3 is closed, the third terminal of the third switch circuit 4022 and the first terminal of the third switch circuit 4022 are connected; when the fourth switch S4 is closed and the common terminal of the switching switch and the first terminal of the switching switch are connected, the first terminal of the third switch circuit 4022 and the second terminal of the third switch circuit 4022 are connected; when the fourth switch S4 is closed and the common terminal of the switching switch and the second terminal of the switching switch are connected, the first terminal of the third switch circuit 4022 and the fourth terminal of the third switch circuit 4022 are connected.

[0060] In some embodiments, such as Figure 1 , Figure 2 As shown, the first switching circuit 200 may include a fifth switch S5 and a sixth switch S6. One end of the fifth switch S5 is connected to the reference voltage output terminal, and the other end of the fifth switch S5 is connected to one end of the sixth switch S6. The other end of the sixth switch S6 is connected to the charge integration module 300. The connection terminal of the fifth switch S5 and the sixth switch S6 is connected to the induced charge generation module 100. Specifically, one end of the fifth switch S5 is the first terminal of the first switching circuit 200, the connection terminal of the fifth switch S5 and the sixth switch S6 is the second terminal of the first switching circuit 200, and the other end of the sixth switch S6 is the third terminal of the first switching circuit 200. When the fifth switch S5 is closed, the first terminal and the second terminal of the first switching circuit 200 are connected; when the sixth switch S6 is closed, the second terminal and the third terminal of the first switching circuit 200 are connected.

[0061] In some embodiments, the first switch S1, the fourth switch S4, and the fifth switch S5 are closed synchronously; that is, when the first switch S1 is closed, the fourth switch S4 and the fifth switch S5 are also closed, and when the first switch S1 is open, the fourth switch S4 and the fifth switch S5 are also open. Similarly, the second switch S2, the third switch S3, and the sixth switch S6 are closed synchronously; that is, when the second switch S2 is closed, the third switch S3 and the sixth switch S6 are also closed, and when the second switch S2 is open, the third switch S3 and the sixth switch S6 are also open. When the sensing detection circuit is in the charge sampling state, the common terminal of the switching switch in the offset charge generation unit 402, which needs to generate offset charge, and the first terminal of the switching switch are connected. When the sensing detection circuit is in the charge integration state, the common terminal of the switching switch in the offset charge generation unit 402, which needs to generate offset charge, and the second terminal of the switching switch are connected.

[0062] In some embodiments, when controlling the reset switch SRST, a counter can be used to count the number of times the charge integration state or charge sampling state occurs. After the counter reaches a second preset value, the main control circuit in the electronic device using the sensing detection circuit controls the reset switch SRST to close, and the charge in the integrator AMP is cleared to zero. The second preset value is set in the main control circuit and can be, but is not limited to, 10, 20, 25, 28, 30, etc. Those skilled in the art can determine the second preset value according to the actual situation. When controlling the switching switch, a first preset value can be set by the main control circuit in the electronic device using the sensing detection circuit, and the switching switch is controlled according to the first preset value. When controlling the first switch S1, the fourth switch S4, and the fifth switch S5, as well as the second switch S2, the third switch S3, and the sixth switch S6, control can be achieved using a clock generation circuit in the sensing detection circuit. Figure 4 The diagram shown illustrates the control signals generated by the clock generation circuit and the control signals for the reset switch SRST generated by the main control circuit in one embodiment. Figure 4 In the circuit, when the signals corresponding to S1, S4, and S5 are high, it indicates that the first switch S1, the fourth switch S4, and the fifth switch S5 are closed; when they are low, it indicates that the first switch S1, the fourth switch S4, and the fifth switch S5 are open. When the signals corresponding to S2, S3, and S6 are high, it indicates that the second switch S2, the third switch S3, and the sixth switch S6 are closed; when they are low, it indicates that the second switch S2, the third switch S3, and the sixth switch S6 are open.

[0063] To further understand the working process of this sensing detection circuit, the following explanation is provided.

[0064] In the initial stage, the sensing circuit is in charge sampling mode. At this time, the reset switch is closed to reset the integrator. Furthermore, the sensing circuit alternates between charge sampling and charge integration modes. In charge sampling mode, the switching terminal and the first terminal of the switch corresponding to the compensation capacitor group that needs to generate the offset charge are connected. By setting the initial potential of the left plate of different compensation capacitor groups, when the common terminal and the first terminal of the switch are connected, the corresponding compensation capacitor group is connected for compensation; when the common terminal and the second terminal of the switch are connected, the corresponding compensation capacitor group is not connected for compensation. In charge integration mode, the common terminal and the second terminal of the switch are connected, transferring the offset charge to the charge integration module 300 to offset parasitic charges. When the occurrence coefficient of the charge integration mode reaches a preset number, the charge integration module 300 outputs a detection signal.

[0065] In some embodiments, this application also provides an electronic device that includes the sensing detection circuit described above. Specific details are as described in the above embodiment of the sensing detection circuit, and will not be repeated here.

[0066] In some embodiments, the electronic device may be a device with a capacitive touchscreen, such as a mobile phone or tablet. Alternatively, it may be a device without a touchscreen, such as a capacitive water level gauge.

[0067] In summary, this application provides a sensing detection circuit and electronic device, which have the following beneficial effects: The inductive detection circuit alternates between charge sampling state and charge integration state. After the charge sampling state appears for the first time, the charge integration module 300 will output a detection signal corresponding to the number of induced charges being integrated at the moment after at least two charge integration states. It can be seen that when outputting the detection signal, the number of times the number of charges is integrated is increased, which improves the strength of the detection signal and increases the detection sensitivity.

[0068] The above examples illustrate the present invention only to aid in understanding it and are not intended to limit the scope of the invention. Those skilled in the art can make various simple deductions, modifications, or substitutions based on the principles of this invention.

Claims

1. A sensing detection circuit, characterized in that, It includes a reference voltage output terminal, a first switching circuit, an induced charge generation module, and a charge integration module; The first switching circuit includes a first terminal, a second terminal, and a third terminal. The first terminal of the first switching circuit is connected to the reference voltage output terminal, the second terminal of the first switching circuit is connected to the induced charge generation module, and the third terminal of the first switching circuit is connected to the charge integration module. The first switching circuit is used to connect its first terminal and second terminal, or its second terminal and third terminal. When the first terminal and second terminal of the first switching circuit are connected, the inductive detection circuit is in a charge sampling state; when the second terminal and third terminal of the first switching circuit are connected, the inductive detection circuit is in a charge integration state. The induced charge generation module is used to generate induced charge when the sensing detection circuit is in the charge sampling state, and the induced charge generation module is also used to transfer the induced charge to the charge integration module when the sensing detection circuit is in the charge integration state; The charge integration module is used to receive the induced charge transferred by the induced charge generation module when the induction detection circuit is in the charge integration state, and to integrate the induced charge; The sensing detection circuit alternately switches between the charge sampling state and the charge integration state, and the charge integration module, after the charge sampling state appears for the first time, appears at least twice in the charge integration state, and then responds to the first control signal to output a detection signal corresponding to the number of induced charges being integrated.

2. The sensing detection circuit as described in claim 1, characterized in that, The sensing detection circuit also includes: A parasitic charge cancellation module is connected between the third terminal of the first switching circuit and the charge integration module. The parasitic charge cancellation module is used to generate cancellation charge when the sensing detection circuit is in the charge sampling state, and to transfer the cancellation charge to the charge integration module when the sensing detection circuit is in the charge integration state. The polarity of the cancellation charge is different from the polarity of the parasitic charge generated by the sensing charge generation module when the sensing detection circuit is in the charge integration state, so that the parasitic charge generated by the sensing charge generation module is canceled by the cancellation charge when the sensing detection circuit is in the charge integration state.

3. The sensing detection circuit as described in claim 2, characterized in that, The number of parasitic charges generated by the induced charge generation module is equal to the number of offset charges generated by the parasitic charge cancellation module, or the difference between the number of parasitic charges generated by the induced charge generation module and the number of offset charges generated by the parasitic charge cancellation module is within a preset range.

4. The sensing detection circuit as described in claim 2 or 3, characterized in that, The parasitic charge cancellation module includes: at least one charge cancellation generation unit and a second switching circuit; The charge cancellation generating unit includes a third switching circuit and a compensation capacitor bank; The second switching circuit includes a first terminal, a second terminal, and a third terminal. The first terminal of the second switching circuit is connected to the compensation capacitor group in each of the said charge cancellation generating units. The second terminal of the second switching circuit is grounded. The third terminal of the second switching circuit is connected to the third terminal of the first switching circuit. The third switching circuit includes a first terminal, a second terminal, a third terminal, and a fourth terminal. The first terminal of the third switching circuit in each of the charge-canceling units is connected to the compensation capacitor group in the same charge-canceling unit. The second terminal of the third switching circuit is used to connect to the reference voltage output terminal. Both the third terminal and the fourth terminal of the third switching circuit are grounded. Specifically, when the sensing detection circuit is in the charge sampling state, the first and second terminals of the third switching circuit in one or more of the at least one canceling charge generating units are turned on, as are the first and second terminals of the second switching circuit, thereby generating canceling charge in the compensation capacitor group of the one or more canceling charge generating units; when the sensing detection circuit is in the charge integration state, the first and fourth terminals of the third switching circuit corresponding to the one or more canceling charge generating units are turned on, as are the first and third terminals of the second switching circuit, to cancel the parasitic charge generated by the sensing charge generating module.

5. The sensing detection circuit as described in claim 4, characterized in that, When multiple offset charge generating units are provided, the number of offset charges generated by the compensation capacitor group in each offset charge generating unit is equal.

6. The sensing detection circuit as described in claim 4, characterized in that, When multiple offset charge generating units are provided, the number of offset charges generated by the compensation capacitor groups in at least two of the multiple offset charge generating units gradually increases when offset charges are generated.

7. The sensing detection circuit as described in claim 4, characterized in that, The second switching circuit includes: a first switch and a second switch; one end of the first switch is grounded, the other end of the first switch is connected to one end of the second switch, and the other end of the second switch is connected to the third end of the first switching circuit, wherein the connection end of the first switch and the second switch is the first end of the second switching circuit, one end of the first switch is the second end of the second switching circuit, and the other end of the second switch is the third end of the second switching circuit. The third switching circuit includes a third switch, a fourth switch, and a switching switch; one end of the third switch is grounded, and the other end of the third switch and one end of the fourth switch are connected to the compensation capacitor bank; the switching switch includes a first end, a second end, and a common end, the common end of the switching switch is connected to the other end of the fourth switch, the first end of the switching switch is connected to the reference voltage output terminal, and the second end of the switching switch is grounded, wherein the connection end of the third switch and the fourth switch is the first end of the third switching circuit, the grounding end of the third switch is the third end of the third switching circuit, the first end of the switching switch is the second end of the third switching circuit, and the second end of the switching switch is the fourth end of the third switching circuit.

8. The sensing detection circuit as described in claim 1, characterized in that, The charge integration module includes: an integrator, an integrating capacitor, and a reset switch; The third terminal of the first switching circuit is connected to the inverting input terminal of the integrator, and the non-inverting input terminal of the integrator is grounded; One end of the integrating capacitor is connected to the inverting input terminal of the integrator, and the other end of the integrating capacitor is connected to the output terminal of the integrator. One end of the reset switch is connected to one end of the integrating capacitor, and the other end of the reset switch is connected to the other end of the integrating capacitor.

9. The sensing detection circuit as described in claim 1, characterized in that, The first switching circuit includes a fifth switch and a sixth switch; one end of the fifth switch is connected to the reference voltage output terminal, the other end of the fifth switch is connected to one end of the sixth switch, the other end of the sixth switch is connected to the charge integration module, and the connection terminal of the fifth switch and the sixth switch is connected to the induced charge generation module. Specifically, one end of the fifth switch is the first terminal of the first switching circuit, the connection terminal of the fifth switch and the sixth switch is the second terminal of the first switching circuit, and the other end of the sixth switch is the third terminal of the first switching circuit.

10. An electronic device, characterized in that, include: The sensing detection circuit as described in any one of claims 1-9.

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