Threshold voltage test method and device of MOS transistor and storage medium

Abstract

The invention provides a threshold voltage testing method and device of an MOS transistor and a storage medium, and relates to the technical field of integrated circuit testing. The method comprises the following steps: performing a first voltage test on a grid electrode of a to-be-tested MOS tube according to a preset minimum voltage to obtain a grid electrode threshold voltage of the to-be-tested MOS tube in a saturation region; and according to the gate threshold voltage of the saturation region, performing a second voltage test on the gate of the to-be-tested MOS tube to obtain the gate threshold voltage of the to-be-tested MOS tube in the linear region. According to the invention, the measured threshold voltage Vtsat of the saturation region is taken as the gate scanning initial voltage for testing the threshold voltage Vtlin of the linear region, so that the overall testing time of the Vtlin and the Vtsat can be shortened by about 50% on the premise of completely ensuring the original testing precision, the core problems of high time cost and low efficiency in the threshold voltage testing of the MOS tube are effectively solved, and the testing efficiency of the threshold voltage of the MOS tube is improved. And an efficient and reliable test scheme is provided for the SPICE model development of the semiconductor device.

Description

Technical Field

[0001] This application relates to the field of integrated circuit testing technology, and more specifically, to a method, apparatus, and storage medium for testing the threshold voltage of a MOSFET. Background Technology

[0002] In the field of integrated circuit manufacturing, wafer foundries not only need to provide customers with chip manufacturing services that meet design requirements, but also need to deliver accurate and reliable semiconductor device models (Simulation Program with Integrated Circuit Emphasis Model, SPICE). As the core foundation of circuit design simulation, the SPICE model directly determines the accuracy of downstream design teams in circuit function verification, performance optimization, and reliability assessment. In the construction of the SPICE model, the threshold voltage of the MOSFET is one of the most critical core electrical parameters. Its accuracy directly affects the accuracy of the model's description of the MOSFET's switching characteristics, conductivity, and linear / saturation region operating states. Therefore, accurate measurement of the threshold voltage is of irreplaceable importance for MOSFET SPICE modeling.

[0003] However, current threshold voltage testing for multi-size MOSFETs faces significant efficiency bottlenecks, resulting in high development costs for SPICE models. Taking MOSFET mismatch model testing as an example, this test requires measuring four core electrical parameters (Vtlin, Vtsat, Idlin, Idsat) of a large number of MOSFETs to analyze the statistical regularities of device characteristics. The testing logic for Idlin (linear region drain current) and Idsat (saturation region drain current) is "directly applying a fixed voltage and measuring the current," which is fast and requires relatively little time. However, Vtlin (linear region threshold voltage) and Vtsat (saturation region threshold voltage), as key indicators of threshold voltage, require the testing process to determine the critical values ​​by scanning the gate voltage and monitoring changes in the drain current. Conventional testing methods typically start from 0V and gradually increase the gate voltage, covering the entire process from the device's cutoff region to the conduction region, leading to a significant increase in testing time.

[0004] Furthermore, the mismatch model requires significantly higher accuracy for the threshold voltage than the standard model. To obtain more accurate threshold voltage data, a shorter gate voltage scan step size needs to be set during testing (e.g., a normal step size of 0.002V needs to be reduced to 0.001V or even smaller in mismatch testing). This further extends the testing time for Vtlin and Vtsat. In the scenario of full-wafer full-mapping testing of multi-size MOSFETs, the aforementioned time cost is amplified, ultimately resulting in the entire threshold voltage testing process consuming a large amount of equipment resources and significantly increasing the development cycle and cost of the SPICE model.

[0005] In summary, how to shorten the testing time and reduce the model development cost while ensuring the accuracy of threshold voltage testing has become a key issue that urgently needs to be addressed by those skilled in the art. Summary of the Invention

[0006] This application addresses the shortcomings of the prior art by providing a method, apparatus, and storage medium for testing the threshold voltage of a MOSFET, thereby resolving the problems existing in the prior art.

[0007] The technical solution adopted in the embodiments of this application is as follows: In a first aspect, embodiments of this application provide a method for testing the threshold voltage of a MOSFET, including: Obtain the MOS transistor under test, with the source and body terminals of the MOS transistor under test shorted; A preset minimum voltage is provided to the source and gate of the MOS transistor under test, respectively; Based on the preset minimum voltage, a first voltage test is performed on the gate of the MOSFET under test to obtain the gate threshold voltage of the MOSFET under test in the saturation region. Based on the gate threshold voltage in the saturation region, a second voltage test is performed on the gate of the MOS transistor under test to obtain the gate threshold voltage of the MOS transistor under test in the linear region.

[0008] In one embodiment, the step of performing a second voltage test on the gate of the MOSFET under test based on the gate threshold voltage in the saturation region to obtain the gate threshold voltage of the MOSFET under test in the linear region includes: The critical channel length of the MOSFET under test is determined based on the process parameters corresponding to the MOSFET under test. The target voltage is determined based on the critical channel length, the actual channel length of the MOS transistor under test, and the gate threshold voltage of the saturation region. Using the target voltage as the gate start voltage of the MOSFET under test, a second voltage test is performed on the gate of the MOSFET under test to obtain the gate threshold voltage of the MOSFET under test in the linear region.

[0009] In one embodiment, the process parameters include: electrical oxide layer thickness and channel doping concentration; determining the critical channel length of the MOSFET under test based on the process parameters corresponding to the MOSFET under test includes: The depletion layer depth is determined based on the channel doping concentration; The short-channel feature size is determined based on the depletion layer depth and the electrical oxide layer thickness; The critical channel length is determined based on the characteristic dimensions of the short channel.

[0010] In one embodiment, determining the critical channel length based on the short channel characteristic dimensions includes: Based on the short-channel characteristic dimensions, a target curve for the channel length of the MOSFET under test is constructed; the target curve for the channel length is used to represent the correspondence between the channel length and the threshold voltage of the MOSFET under test. The critical channel length of the MOS transistor under test is determined based on the target channel length curve.

[0011] In one embodiment, determining the target voltage based on the critical channel length, the actual channel length of the MOS transistor under test, and the gate threshold voltage of the saturation region includes: If the actual channel length is greater than or equal to the critical channel length, the gate threshold voltage of the saturation region is determined to be the target voltage. If the actual channel length is less than the critical channel length, the gate threshold voltage of the saturation region and the preset voltage difference are summed to obtain the target voltage.

[0012] In one embodiment, the step of using the target voltage as the gate start voltage of the MOSFET under test and performing a second voltage test on the gate of the MOSFET under test to obtain the gate threshold voltage of the MOSFET under test in the linear region includes: The source-drain voltage of the MOSFET under test is fixed to a second preset voltage so that the MOSFET under test operates in the linear region. Starting from the target voltage, the gate voltage of the MOSFET under test is increased by a second preset step size, and the drain current of the MOSFET under test is monitored in real time. Determine the gate voltage when the drain current reaches the target current value, and use the gate voltage as the gate threshold voltage of the linear region.

[0013] In one embodiment, the step of performing a first voltage test on the gate of the MOSFET under test according to the preset minimum voltage to obtain the gate threshold voltage of the MOSFET under test in the saturation region includes: The source-drain voltage of the MOSFET under test is fixed to a first preset voltage so that the MOSFET under test operates in the saturation region. Starting from the preset minimum voltage, the gate voltage of the MOSFET under test is increased by a first preset step size, and the drain current of the MOSFET under test is monitored in real time. Determine the gate voltage when the drain current reaches the target current value, and use the gate voltage as the gate threshold voltage of the MOS transistor under test in the saturation region.

[0014] In one embodiment, the method further includes: Based on the gate threshold voltage of the MOSFET under test in the saturation region and the gate threshold voltage of the MOSFET under test in the linear region, a simulation model of the MOSFET under test is performed to obtain the semiconductor device model of the MOSFET under test.

[0015] Secondly, this application also provides an electronic device, including: a processor, a storage medium and a bus, wherein the storage medium stores program instructions executable by the processor, and when the electronic device is running, the processor communicates with the storage medium via the bus, and the processor executes the program instructions to implement the threshold voltage test method for the MOS transistor described in any of the above embodiments.

[0016] Thirdly, this application also provides a readable storage medium storing program instructions, which, when executed by a processor, implement the threshold voltage testing method for the MOS transistor described in any of the above embodiments.

[0017] The beneficial effects of this application are as follows: This application provides a threshold voltage testing method for MOSFETs. Based on the physical characteristic of MOSFETs that "the threshold voltage Vtlin in the linear region is always greater than the threshold voltage Vtsat in the saturation region", the measured threshold voltage Vtsat in the saturation region is used as the gate scan start voltage for testing the threshold voltage Vtlin in the linear region. Without introducing complex algorithm logic, the overall testing time for Vtlin and Vtsat can be shortened by nearly 50% while fully ensuring the original testing accuracy. This effectively solves the core problems of high time cost and low efficiency in MOSFET threshold voltage testing, and provides an efficient and reliable testing solution for the development of SPICE models for semiconductor devices. Attached Figure Description

[0018] To more clearly illustrate the technical solutions of the embodiments of this application, the accompanying drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of this application and should not be regarded as a limitation of the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0019] Figure 1a This is a schematic diagram of an NMOS transistor; Figure 1b This is a schematic diagram showing the relationship between the drain current and gate voltage of an NMOS transistor. Figure 2 This is one of the flowcharts illustrating the threshold voltage testing method for a MOSFET provided in an embodiment of this application. Figure 3 This is a second schematic flowchart illustrating the threshold voltage testing method for a MOSFET provided in an embodiment of this application. Figure 4 The third schematic flowchart illustrates the threshold voltage testing method for a MOSFET provided in this application embodiment. Figure 5 The fourth schematic flowchart of the threshold voltage test method for a MOSFET provided in the embodiments of this application; Figure 6 Fifth schematic flowchart of the threshold voltage test method for MOSFET provided in the embodiments of this application; Figure 7 This is the sixth flowchart illustrating the threshold voltage testing method for a MOSFET provided in this application embodiment; Figure 8 The seventh flowchart illustrates the threshold voltage testing method for a MOSFET provided in this application embodiment. Figure 9 The target image of the channel length provided in the embodiments of this application; Figure 10 A schematic diagram of the threshold voltage testing device for the MOSFET provided in this application; Figure 11 This is a schematic diagram of the structure of an electronic device provided in an embodiment of this application. Detailed Implementation

[0020] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are some embodiments of this application, but not all embodiments.

[0021] Therefore, the following detailed description of the embodiments of this application provided in the accompanying drawings is not intended to limit the scope of the claimed application, but merely to illustrate selected embodiments of the application. All other embodiments obtained by those skilled in the art based on the embodiments of this application without inventive effort are within the scope of protection of this application.

[0022] Furthermore, the terms "first," "second," etc., used in the specification, claims, and accompanying drawings of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of this application described herein can be implemented in orders other than those illustrated or described herein. Additionally, the terms "comprising" and "having," and any variations thereof, are intended to cover a non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0023] It should be noted that, where there is no conflict, the features in the embodiments of this application can be combined with each other.

[0024] The threshold voltages of MOSFETs (gate threshold voltage Vtsat in the saturation region and gate threshold voltage Vtlin in the linear region) are generally scanned starting from 0V, which is slow and consumes too much test time. In addition, the size of the MOSFET will significantly affect the magnitude of the threshold voltage, and there may be a small number of MOSFETs whose threshold voltages deviate significantly from the normal value. These issues need to be reflected in the test, so the test time cannot be shortened simply by modifying the starting voltage of the threshold voltage scan range.

[0025] To address this issue, this application provides a method for testing the threshold voltage of a MOSFET. This method can be generated by any electronic device with computing and processing capabilities, such as a terminal-facing computer or a backend server.

[0026] The threshold voltage test method for MOSFETs provided in this application is illustrated below with reference to the accompanying drawings and several examples.

[0027] First, let's explain MOSFETs. For MOSFETs, increasing the source-drain voltage lowers the potential barrier between the source and the channel, thus reducing the MOSFET's threshold voltage. This phenomenon is called drain-induced barrier lowering (DIBL). During the testing of the gate threshold voltage Vtsat in the saturation region of a MOSFET, the voltage across the source and drain is greater than that during the testing of the gate threshold voltage Vtlin in the linear region. Therefore, Vtlin > Vtsat always holds true. A semi-quantitative threshold voltage... The empirical formula is as follows: (1) Where V t-long V is the threshold voltage of a long-channel MOSFET (i.e., a larger L). ds The voltage across the source and drain terminals is l, where L is the channel length of the MOSFET. d This refers to the specific length of the DIBL channel. Clearly, the smaller the channel length L, the greater the difference between Vtsat and Vtlin.

[0028] Figure 1a This is a schematic diagram of an NMOS transistor. Figure 1b This is a schematic diagram showing the relationship between the drain current and gate voltage of an NMOS transistor. Figure 1a Middle I D The drain current is represented by the number of terminals. An NMOS transistor has four terminals: D (drain), G (gate), S (source), and B (body).

[0029] Figure 2This is one of the flowcharts illustrating the threshold voltage testing method for a MOSFET provided in an embodiment of this application, such as... Figure 2 As shown, the method may include S101~S102: S101. Obtain the MOSFET under test, and short-circuit the source and body terminals of the MOSFET under test.

[0030] The MOSFET under test can be an NMOS transistor as mentioned above. The MOSFET under test can include four ports, namely D (drain), G (gate), S (source), and B (body), and the source S and body B of the MOSFET under test are shorted together.

[0031] S102. Provide a preset minimum voltage to the source and gate of the MOSFET under test.

[0032] The preset minimum voltage can be 0V.

[0033] In this embodiment, a preset minimum voltage of 0V can be provided to the source and gate of the MOS transistor under test, that is, the voltage of the source and gate is set to 0V. At this time, since the body terminal B and the source terminal S are shorted, the voltage of the body terminal B is also 0V.

[0034] S103. Based on the preset minimum voltage, perform a first voltage test on the gate of the MOSFET under test to obtain the gate threshold voltage of the MOSFET under test in the saturation region.

[0035] Specifically, the gate voltage of the MOSFET under test can be tested starting from the preset minimum voltage, that is, from 0V, to obtain the gate threshold voltage of the MOSFET under test in the saturation region, denoted as Vtsat.

[0036] S104. Based on the gate threshold voltage in the saturation region, perform a second voltage test on the gate of the MOSFET under test to obtain the gate threshold voltage of the MOSFET under test in the linear region.

[0037] In this embodiment, the MOSFET has the physical characteristic that "the threshold voltage Vtlin in the linear region is always greater than the threshold voltage Vtsat in the saturation region". Therefore, the second voltage test is performed on the gate of the MOSFET under test starting from the gate threshold voltage Vtsat in the saturation region to obtain the gate threshold voltage Vtlin in the linear region of the MOSFET under test, which can shorten the test time.

[0038] In summary, this embodiment provides a threshold voltage testing method for MOSFETs. Based on the physical characteristic of MOSFETs that "the threshold voltage Vtlin in the linear region is always greater than the threshold voltage Vtsat in the saturation region," the linear region threshold voltage Vtlin is tested based on the measured threshold voltage Vtsat in the saturation region. This method eliminates the need for complex algorithm logic and, while fully maintaining the original testing accuracy, reduces the overall testing time for Vtlin and Vtsat by nearly 50%. It effectively solves the core problems of high time cost and low efficiency in MOSFET threshold voltage testing, providing an efficient and reliable testing solution for the development of SPICE models for semiconductor devices.

[0039] Figure 3 This is the second flowchart illustrating the threshold voltage testing method for a MOSFET provided in this application embodiment, refer to... Figure 3 S103 may include S201~S203: S201. Fix the source-drain voltage of the MOSFET under test to a first preset voltage so that the MOSFET under test operates in the saturation region.

[0040] In this embodiment, the source-drain voltage V of the MOSFET under test is... DS The voltage between the source and drain is fixed at a first preset voltage of 5V, that is, the source voltage is 0V and the drain voltage is 5V, so that the MOSFET under test can operate in the saturation region.

[0041] S202. Starting from the preset minimum voltage, increase the gate voltage of the MOSFET under test according to the first preset step size, and monitor the drain current of the MOSFET under test in real time.

[0042] In this embodiment, the gate voltage of the MOSFET under test is gradually increased from the preset minimum voltage (0V) according to a first preset step size (e.g., 0.002V), and the drain current change of the MOSFET under test is monitored in real time.

[0043] S203. Determine the gate voltage when the drain current reaches the target current value, and use the gate voltage as the gate threshold voltage of the MOSFET under test in the saturation region.

[0044] Reference Figure 1b When the drain current reaches the target current value Itarget, the current gate voltage VG is used as the gate threshold voltage Vtsat of the saturation region. In this application, the target current value is 0.1uA*W / L.

[0045] Figure 4 This is the third flowchart illustrating the threshold voltage testing method for a MOSFET provided in this application. Figure 4 As shown, S104 may include S301~S303: S301. Determine the critical channel length of the MOSFET under test based on the corresponding process parameters.

[0046] The process parameters may include, but are not limited to, the electrical oxide layer thickness (TOXE) and the channel doping concentration (NDEP).

[0047] In this embodiment, the critical channel length corresponding to the MOSFET under test (this type of MOSFET) can be determined based on these process parameters, and is denoted as L`.

[0048] The critical channel length L' is a key length threshold used to distinguish the influence of the actual channel length L of a MOSFET on the difference between the gate threshold voltage in the saturation region and the gate threshold voltage in the linear region, Vtlin-Vtsat. When the actual channel length L of the MOSFET under test is greater than or equal to the critical channel length L', the difference between the gate threshold voltage in the saturation region and the gate threshold voltage in the linear region, Vtlin-Vtsat, is small; when the actual channel length L of the MOSFET under test is less than the critical channel length L', the difference between the gate threshold voltage in the saturation region and the gate threshold voltage in the linear region, Vtlin-Vtsat, is large.

[0049] S302. Determine the target voltage based on the critical channel length, the actual channel length of the MOSFET under test, and the gate threshold voltage in the saturation region.

[0050] In one embodiment, such as Figure 5 As shown, S302 may include S401~S402, and S401 and S402 do not represent restrictions on the execution order.

[0051] S401. If the actual channel length is greater than or equal to the critical channel length, determine the gate threshold voltage of the saturation region as the target voltage.

[0052] In this embodiment, when the actual channel length L of the MOS transistor under test is greater than or equal to the critical channel length L', the difference Vtlin-Vtsat between the gate threshold voltage of the saturation region and the gate threshold voltage of the linear region is small. Therefore, the gate threshold voltage Vtsat of the saturation region can be used as the target voltage.

[0053] S402. If the actual channel length is less than the critical channel length, sum the gate threshold voltage of the saturation region and the preset voltage difference to obtain the target voltage.

[0054] In this embodiment, when the actual channel length L of the MOSFET under test is less than the critical channel length L`, the difference Vtlin-Vtsat between the gate threshold voltage of the saturation region and the gate threshold voltage of the linear region is large. In order to reduce the test time for the gate threshold voltage Vtlin of the linear region, the target voltage can be determined based on the gate threshold voltage Vtsat of the saturation region and the preset voltage difference ΔVt, so that when the second voltage test is performed later, the test starts from the target voltage to shorten the test time.

[0055] Specifically, the gate threshold voltage Vtsat in the saturation region can be added to a preset voltage difference ΔVt to obtain the target voltage.

[0056] In this embodiment, the preset voltage difference ΔVt can vary depending on the MOSFET under test. For example, for a 5V NMOS transistor, the preset voltage difference ΔVt can be set to 15mV.

[0057] S303. Using the target voltage as the gate start voltage of the MOSFET under test, perform a second voltage test on the gate of the MOSFET under test to obtain the gate threshold voltage of the MOSFET under test in the linear region.

[0058] Specifically, such as Figure 6 As shown, S303 may include S501~S503: S501. Fix the source-drain voltage of the MOSFET under test to the second preset voltage so that the MOSFET under test operates in the linear region.

[0059] In this embodiment, the source-drain voltage V of the MOSFET under test is... DS The voltage between the source and drain is fixed at a second preset voltage (0.1V or 0.05V), that is, the source voltage is 0V and the drain voltage is 0.1V or 0.05V, so that the MOSFET under test can operate in the linear region.

[0060] In this embodiment, the second preset voltage is less than the first preset voltage (5V).

[0061] S502. Starting from the target voltage, increase the gate voltage of the MOSFET under test according to the second preset step size, and monitor the drain current of the MOSFET under test in real time.

[0062] To improve measurement accuracy in the linear region, the second preset step size is less than or equal to the first preset step size. For example, starting from the target voltage (which is the gate threshold voltage of the saturation region, or the sum of the gate threshold voltage of the saturation region and the preset voltage difference) according to the second preset step size (e.g., 0.001V), the gate voltage of the MOSFET under test is gradually increased, and the drain current change of the MOSFET under test is monitored in real time. S503. Determine the gate voltage when the drain current reaches the target current value, and use the gate voltage as the gate threshold voltage of the linear region.

[0063] Reference Figure 1b When the drain current reaches the target current value Itarget, the current gate voltage VG is used as the gate threshold voltage Vtlin of the linear region.

[0064] In another embodiment, based on the gate threshold voltage Vtsat of the MOSFET under test in the saturation region and the gate threshold voltage Vtlin of the MOSFET under test in the linear region, combined with other electrical parameters of the NMOS transistor under test (such as the drain current Idsat in the saturation region and the drain current Idlin in the linear region), the MOSFET under test is simulated and modeled to obtain the semiconductor device model of the MOSFET under test.

[0065] Figure 7 This is the sixth flowchart illustrating the threshold voltage testing method for a MOSFET provided in this application embodiment. Figure 7 As shown in step S301, determining the critical channel length of the MOSFET under test based on its corresponding process parameters may include: S601. Determine the depletion layer depth based on the channel doping concentration.

[0066] Specifically, the depletion layer depth can be determined using the following formula (2): (2) in, For the surface potential of the channel, It is the dielectric constant of the substrate. It is the charge carried by an electron (in coulombs), and NDEP is the channel doping concentration. This represents the depth of the depleted layer.

[0067] S602. Determine the short channel feature size based on the depletion layer depth and the electrical oxide layer thickness.

[0068] In this embodiment, the characteristic dimensions of the short channel can be determined by the following formula (3).

[0069] (3) in, TOXE is the dielectric constant of the oxide layer material SiO2, and TOXE is the thickness of the electrical oxide layer. This refers to the characteristic dimensions of the short channel.

[0070] S603. Determine the critical channel length based on the characteristic dimensions of the short channel.

[0071] Specifically, refer to Figure 8 S603 may include: S701. Construct a target curve of the channel length of the MOS transistor to be measured according to the short-channel characteristic size.

[0072] Among them, the target curve of the channel length is used to represent the corresponding relationship between the channel length of the MOS transistor to be measured and the threshold voltage.

[0073] In this embodiment, the target curve of the channel length can be as Figure 9 shown, and it can be expressed as .

[0074] In this embodiment, Vtlin - Vtsat is proportional to , that is, is a parameter related to the actual channel length L. According to , the difference between the effective channel length L eff and L (L eff ≈ L) can be ignored, and the target curve of the channel length changing with L can be plotted. Among them,

[0075] where is a length-dependent parameter (for the DIBL effect of Vth).

[0076] S702. Determine the critical channel length of the MOS transistor to be measured according to the target curve of the channel length.

[0077] In this embodiment, when L ≥ L`, is smaller, corresponding to a smaller Vtlin - Vtsat; when L < L`, is larger, corresponding to a larger Vtlin - Vtsat. Since exhibits exponential change characteristics, it is very easy to judge the critical channel length L` according to the image in actual operation.

[0078] In summary, the present application provides a method for testing the threshold voltage of a MOS transistor, which has the following advantages: 1. Based on the physical property that the threshold voltage Vtlin in the linear region of the MOS transistor is always greater than the threshold voltage Vtsat in the saturation region, the measured threshold voltage Vtsat in the saturation region is used as the starting voltage of the gate sweep for testing the threshold voltage Vtlin in the linear region. Without introducing complex algorithmic logic, on the premise of fully ensuring the original test accuracy, the overall test time of Vtlin and Vtsat can be shortened by nearly 50%, effectively solving the core problem of "high time cost and low efficiency" in the test of the threshold voltage of the MOS transistor, and providing an efficient and reliable test scheme for the development of the SPICE model of semiconductor devices.

[0079] 2. In multiple tests of the same MOSFET, even slight changes in the test equipment or pin piercing conditions can affect the threshold voltage test results. For MOSFETs of the same size, test results may also fluctuate between different dies (die-to-die variation). This application avoids these two situations by conducting joint Vtlin and Vtsat tests on the same MOSFET under a single pin piercing, thus ensuring no impact on the test results.

[0080] The following will continue to explain the apparatus, device, and storage medium for performing the threshold voltage test method of the MOS transistor provided in any of the above embodiments of this application. The specific implementation process and the resulting technical effects are the same as those in the corresponding method embodiments. For the sake of brevity, the parts not mentioned in the following embodiments can be referred to the corresponding content in the method embodiments.

[0081] Figure 10 This is a schematic diagram of the threshold voltage testing device for the MOSFET provided in this application, as shown below. Figure 10 As shown, this application also provides a threshold voltage testing device for a MOSFET, which may include: The acquisition module 10 is used to acquire the MOS transistor under test, wherein the source and body terminals of the MOS transistor under test are short-circuited.

[0082] Voltage module 20 is used to provide a preset minimum voltage to the source and gate of the MOS transistor under test, respectively.

[0083] The first test module 30 is used to perform a first voltage test on the gate of the MOS transistor under test according to a preset minimum voltage, so as to obtain the gate threshold voltage of the MOS transistor under test in the saturation region.

[0084] The second test module 40 is used to perform a second voltage test on the gate of the MOS transistor under test based on the gate threshold voltage in the saturation region, so as to obtain the gate threshold voltage of the MOS transistor under test in the linear region.

[0085] Optionally, the second test module 40 is further configured to determine the critical channel length of the MOSFET under test based on the process parameters corresponding to the MOSFET under test; determine the target voltage based on the critical channel length, the actual channel length of the MOSFET under test, and the gate threshold voltage of the saturation region; and perform a second voltage test on the gate of the MOSFET under test using the target voltage as the gate starting voltage of the MOSFET under test to obtain the gate threshold voltage of the MOSFET under test in the linear region.

[0086] Optionally, the process parameters include: electrical oxide layer thickness and channel doping concentration; the second test module 40 is further configured to determine the depletion layer depth based on the channel doping concentration; determine the short channel feature size based on the depletion layer depth and the electrical oxide layer thickness; and determine the critical channel length based on the short channel feature size.

[0087] Optionally, the second test module 40 is further configured to construct a target channel length curve for the MOSFET under test based on the short channel characteristic dimensions; the target channel length curve is used to represent the correspondence between the channel length of the MOSFET under test and the threshold voltage; and to determine the critical channel length of the MOSFET under test based on the target channel length curve.

[0088] Optionally, the second test module 40 is further configured to determine the gate threshold voltage of the saturation region as the target voltage if the actual channel length is greater than or equal to the critical channel length; and to sum the gate threshold voltage of the saturation region and the preset voltage difference to obtain the target voltage if the actual channel length is less than the critical channel length.

[0089] Optionally, the second test module 40 is further configured to fix the source-drain voltage of the MOSFET under test to a second preset voltage so that the MOSFET under test operates in the linear region; starting from the target voltage, increase the gate voltage of the MOSFET under test according to a second preset step size, and monitor the drain current of the MOSFET under test in real time; determine the gate voltage when the drain current reaches the target current value, and use the gate voltage as the gate threshold voltage of the linear region.

[0090] Optionally, the first test module 30 is further configured to fix the source-drain voltage of the MOSFET under test to a first preset voltage so that the MOSFET under test operates in the saturation region; starting from the preset minimum voltage, increase the gate voltage of the MOSFET under test according to a first preset step size, and monitor the drain current of the MOSFET under test in real time; determine the gate voltage when the drain current reaches the target current value, and use the gate voltage as the gate threshold voltage of the MOSFET under test in the saturation region.

[0091] Optionally, the device further includes a simulation modeling module, used to perform simulation modeling on the MOSFET under test based on the gate threshold voltage in the saturation region and the gate threshold voltage in the linear region of the MOSFET under test, to obtain a semiconductor device model of the MOSFET under test.

[0092] The above-described device is used to execute the method provided in the foregoing embodiments, and its implementation principle and technical effect are similar, so they will not be described again here.

[0093] These modules can be one or more integrated circuits configured to implement the above methods, such as one or more Application Specific Integrated Circuits (ASICs), one or more microprocessors, or one or more Field Programmable Gate Arrays (FPGAs). Alternatively, when a module is implemented using processing element scheduler code, the processing element can be a general-purpose processor, such as a Central Processing Unit (CPU) or other processor capable of calling program code. Furthermore, these modules can be integrated together as a system-on-a-chip (SOC).

[0094] Figure 11 This is a schematic diagram of the structure of the electronic device provided in the embodiments of this application, such as... Figure 11 As shown, this application also provides an electronic device, including a processor 100, a storage medium 200, and a bus 300. The storage medium stores program instructions executable by the processor. When the electronic device is running, the processor communicates with the storage medium via the bus, and the processor executes the program instructions to implement the threshold voltage test method for the MOS transistor described in any of the above embodiments.

[0095] This application also provides a readable storage medium storing program instructions, which, when executed by a processor, implement the threshold voltage testing method for the MOS transistor described in any of the above embodiments.

[0096] In the several embodiments provided in this application, it should be understood that the disclosed apparatus and methods can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative; for instance, the division of units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be through some interfaces; the indirect coupling or communication connection between apparatuses or units may be electrical, mechanical, or other forms.

[0097] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0098] Furthermore, the functional units in the various embodiments of this application can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or in a combination of hardware and software functional units.

[0099] The integrated units implemented as software functional units described above can be stored in a computer-readable storage medium. These software functional units, stored in a storage medium, include several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) or processor to execute some steps of the methods described in the various embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0100] The above are merely specific embodiments of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A method for testing the threshold voltage of a MOSFET, characterized in that, include: Obtain the MOS transistor under test, with the source and body terminals of the MOS transistor under test shorted; A preset minimum voltage is provided to the source and gate of the MOS transistor under test, respectively; Based on the preset minimum voltage, a first voltage test is performed on the gate of the MOSFET under test to obtain the gate threshold voltage of the MOSFET under test in the saturation region. Based on the gate threshold voltage in the saturation region, a second voltage test is performed on the gate of the MOS transistor under test to obtain the gate threshold voltage of the MOS transistor under test in the linear region.

2. The method according to claim 1, characterized in that, The step of performing a second voltage test on the gate of the MOSFET under test based on the gate threshold voltage in the saturation region to obtain the gate threshold voltage of the MOSFET under test in the linear region includes: The critical channel length of the MOSFET under test is determined based on the process parameters corresponding to the MOSFET under test. The target voltage is determined based on the critical channel length, the actual channel length of the MOS transistor under test, and the gate threshold voltage of the saturation region. Using the target voltage as the gate start voltage of the MOSFET under test, a second voltage test is performed on the gate of the MOSFET under test to obtain the gate threshold voltage of the MOSFET under test in the linear region.

3. The method according to claim 2, characterized in that, The process parameters include: electrical oxide layer thickness and channel doping concentration; determining the critical channel length of the MOS transistor under test based on the process parameters includes: The depletion layer depth is determined based on the channel doping concentration; The short-channel feature size is determined based on the depletion layer depth and the electrical oxide layer thickness; The critical channel length is determined based on the characteristic dimensions of the short channel.

4. The method according to claim 3, characterized in that, Determining the critical channel length based on the short channel characteristic dimensions includes: Based on the short-channel characteristic dimensions, a target curve for the channel length of the MOSFET under test is constructed; the target curve for the channel length is used to represent the correspondence between the channel length and the threshold voltage of the MOSFET under test. The critical channel length of the MOS transistor under test is determined based on the target channel length curve.

5. The method according to claim 2, characterized in that, The step of determining the target voltage based on the critical channel length, the actual channel length of the MOSFET under test, and the gate threshold voltage of the saturation region includes: If the actual channel length is greater than or equal to the critical channel length, the gate threshold voltage of the saturation region is determined to be the target voltage. If the actual channel length is less than the critical channel length, the gate threshold voltage of the saturation region and the preset voltage difference are summed to obtain the target voltage.

6. The method according to claim 2, characterized in that, The step of using the target voltage as the gate start voltage of the MOSFET under test, and performing a second voltage test on the gate of the MOSFET under test to obtain the gate threshold voltage of the MOSFET under test in the linear region, includes: The source-drain voltage of the MOSFET under test is fixed to a second preset voltage so that the MOSFET under test operates in the linear region. Starting from the target voltage, the gate voltage of the MOSFET under test is increased by a second preset step size, and the drain current of the MOSFET under test is monitored in real time. Determine the gate voltage when the drain current reaches the target current value, and use the gate voltage as the gate threshold voltage of the linear region.

7. The method according to claim 1, characterized in that, The step of performing a first voltage test on the gate of the MOSFET under test according to the preset minimum voltage to obtain the gate threshold voltage of the MOSFET under test in the saturation region includes: The source-drain voltage of the MOSFET under test is fixed to a first preset voltage so that the MOSFET under test operates in the saturation region. Starting from the preset minimum voltage, the gate voltage of the MOSFET under test is increased by a first preset step size, and the drain current of the MOSFET under test is monitored in real time. Determine the gate voltage when the drain current reaches the target current value, and use the gate voltage as the gate threshold voltage of the MOS transistor under test in the saturation region.

8. The method according to claim 1, characterized in that, The method further includes: Based on the gate threshold voltage of the MOSFET under test in the saturation region and the gate threshold voltage of the MOSFET under test in the linear region, a simulation model of the MOSFET under test is performed to obtain the semiconductor device model of the MOSFET under test.

9. An electronic device, characterized in that, include: The device includes a processor, a storage medium, and a bus. The storage medium stores program instructions executable by the processor. When the electronic device is running, the processor communicates with the storage medium via the bus, and the processor executes the program instructions to implement the threshold voltage test method for a MOS transistor as described in any one of claims 1 to 8.

10. A readable storage medium, characterized in that, The readable storage medium stores program instructions that, when executed by a processor, implement the threshold voltage testing method for the MOS transistor according to any one of claims 1 to 8.

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