Online upgrading method and system for energy storage system

Abstract

The invention relates to the technical field of energy storage system upgrading, and provides an energy storage system online upgrading method and system.The method comprises the steps that an FPGA management module receives upgrading data sent by an upper computer; the FPGA management module writes the upgrading data into the corresponding FLASH of the corresponding chip and verifies the upgrading data, after verification succeeds, the corresponding FLASH is connected to the corresponding chip, and then the chip restarting process is started; judging a restart supporting mode of each chip, and configuring a corresponding mode for restarting according to the restart supporting mode; and after chip restarting is completed, the FPGA management module is informed of an upgrading success mark through the communication bus, the FPGA management module receives the upgrading state of the chip and then sends the upgrading state to the upper computer, and chip upgrading is completed. According to the method, the flexibility and the reliability of software program management of the energy storage system are improved, the on-line upgrading function of each chip is managed by using the FPGA, continuous updating and maintenance of the system are ensured, and physical contact or hardware replacement is not needed.

Description

Technical Field

[0001] This invention relates to the field of energy storage system upgrade technology, and in particular to an online upgrade method and system for energy storage systems. Background Technology

[0002] Against the backdrop of an accelerated transition to clean energy, energy storage technology has become crucial for resolving the energy supply and demand imbalance and ensuring grid stability. As the core equipment of an energy storage system, the PCS (Power Conversion System) achieves efficient energy storage and release through the conversion, regulation, and control of electrical energy. In the context of the ongoing energy transition, PCS has broad application prospects. By improving energy conversion efficiency, increasing storage capacity, and enhancing intelligent control, PCS will further promote the development of energy storage technology and play a vital role in achieving sustainable energy utilization.

[0003] As energy storage products require continuous functional improvements throughout their lifecycle, traditional system maintenance and firmware upgrades present the following challenges: The first method involves downloading the firmware to the chip's internal Flash memory using a dedicated emulator and specialized chip development software. This requires on-site operation by energy storage technicians. The system is powered off, the emulator is plugged in, and then powered on again for the upgrade. After the upgrade is complete, the power is turned off again, the emulator is unplugged, and then the system is powered on again to start. This method is extremely labor-intensive, time-consuming, and involves cumbersome steps, significantly increasing the equipment's maintenance costs.

[0004] The second method involves using CAN communication to achieve online upgrades of the energy storage system. Each energy storage PCS board has a CAN communication interface. Upgrades are performed on each device by setting different ID numbers. However, the CAN bus is limited by length, reaching only 1 Mbps within 40 meters. This is unsuitable for devices located over long distances and also results in slow transmission speeds.

[0005] The third method involves using network communication to upgrade the energy storage system online. Each chip on the board has network communication capabilities. Each chip corresponds to a network port, and upgrades are performed one by one using a network cable. Although the upgrade speed for a single chip is increased, this method is cumbersome due to the large number of chips in the system, and it also significantly increases the maintenance costs of the equipment. Summary of the Invention

[0006] The purpose of this invention is to solve at least one technical problem in the background art and to provide an online upgrade method and system for energy storage systems.

[0007] To achieve the above objectives, the present invention provides an online upgrade method for an energy storage system, comprising: Upgrade data is generated according to the online upgrade protocol and sent to the FPGA management module via the host computer. The FPGA management module receives the upgrade data sent by the host computer. The FPGA management module obtains the status information of each chip to be upgraded in the energy storage system through the communication bus, determines whether the status of each chip to be upgraded allows the upgrade, and when the upgrade is allowed, the FPGA management module writes the upgrade data to the corresponding FLASH of the corresponding chip and verifies it. After successful verification, the corresponding FLASH is connected to the corresponding chip, and then the restart process of each chip is started. When the restart process for each chip is enabled, it determines the restart methods supported by each chip and configures the corresponding mode to restart according to the supported restart methods. After the chip restarts, it initializes the system and performs a self-test. Once all tasks start normally, it notifies the FPGA management module of the upgrade success status via the communication bus. After receiving the chip's upgrade status, the FPGA management module sends it to the host computer, and the chip upgrade is complete.

[0008] According to one aspect of the present invention, the step of generating upgrade data according to an online upgrade protocol and sending the upgrade data to the FPGA management module via a host computer includes: Generate the binary data stream file required for chip upgrade according to the format agreed in the online upgrade protocol; The binary data stream file is packaged according to the agreed format in the upgrade protocol, expanded into data frames with data format, and a data stream transmission frame sequence is generated. The data stream transmission frame sequence is sent to the FPGA management module via the host computer.

[0009] According to one aspect of the present invention, the FPGA management module receives upgrade data sent by a host computer, including: The FPGA management module establishes a network connection with the host computer; The host computer requests and issues upgrade instructions to each chip. The FPGA obtains the chip information that needs to be upgraded based on the upgrade instructions. The FPGA management module queries the operating status of each chip and responds to the host computer. If the chip is running, the upgrade is not allowed; if the chip is not running, the upgrade is allowed. When an upgrade is allowed, the host computer sends upgrade data. The FPGA management module performs CRC verification on the upgrade data and responds based on the CRC verification result. If the verification of a frame of data in the upgrade data fails, it returns a response indicating that the current frame is not received and waits for the host computer to retransmit the current frame data until all upgrade data is successfully verified. After the upgrade data verification is completed, the FPGA management module returns the CRC verification result to the host computer, the upgrade data transmission is completed, and the FPGA management module saves the upgrade data of each chip to the designated SRAM.

[0010] According to one aspect of the present invention, the FPGA management module obtains the status information of each chip to be upgraded in the energy storage system through a communication bus, determines whether the status of each chip to be upgraded allows for upgrading, and if upgrading is allowed, the FPGA management module writes the upgrade data to the corresponding FLASH of the corresponding chip and performs verification. After successful verification, the corresponding FLASH is connected to the corresponding chip, and then the restart process of each chip is initiated, including: The FPGA management module obtains the status of each chip through the EMIF bus and / or serial bus. If the status allows for upgrade, the FPGA management module connects the SPI interface of the FLASH corresponding to each chip to the FPGA management module itself and disconnects the connection with each chip. The FPGA management module writes the upgrade data into the corresponding chip's FLASH via the SPI interface; After reading and writing, the upgrade data is verified. If the verification fails, the upgrade failure status of each chip is reported. If the verification succeeds, the corresponding FLASH of each chip is connected to each chip, and then the restart process of each chip is started.

[0011] According to one aspect of the present invention, determining the restart support method of each chip and configuring the corresponding mode for restarting according to the restart support method includes: Determine the restart mode supported by each chip. If the chip supports external SPI NOR FLASH boot, configure it to restart in this mode. If the chip supports booting from built-in SPI NOR FLASH, a secondary BOOTLOADER is written into the built-in FLASH of the corresponding chip. Then, the chip is powered on and started. The chip jumps to the 0 address entry of the built-in FLASH according to the boot method, runs the BOOT program, loads the upgrade data from the external FLASH connected to the chip, moves it to the specified area, and finally jumps to the entry address to run the APP.

[0012] To achieve the above objectives, the present invention also provides an online upgrade system for an energy storage system, comprising: The upgrade data interaction module generates upgrade data according to the online upgrade protocol, and sends the upgrade data to the FPGA management module through the host computer. The FPGA management module receives the upgrade data sent by the host computer. The upgrade data is written to the verification module. The FPGA management module obtains the status information of each chip to be upgraded in the energy storage system through the communication bus, determines whether the status of each chip to be upgraded allows the upgrade. If the upgrade is allowed, the FPGA management module writes the upgrade data to the corresponding FLASH of the corresponding chip and performs verification. After successful verification, the corresponding FLASH is connected to the corresponding chip, and then the restart process of each chip is started. The restart method determination module determines the restart methods supported by each chip when the restart process of each chip is enabled, and configures the corresponding mode to restart according to the supported restart methods. The chip restarts and upgrades the module. After the chip restarts, it initializes the system and performs a self-test. Once all tasks start normally, it notifies the FPGA management module of the upgrade success status via the communication bus. After receiving the chip's upgrade status, the FPGA management module sends it to the host computer, and the chip upgrade is complete.

[0013] To achieve the above objectives, the present invention also provides an electronic device, including a processor, a memory, and a computer program stored in the memory and executable on the processor, wherein the computer program, when executed by the processor, implements the online upgrade method for the energy storage system as described above.

[0014] To achieve the above objectives, the present invention also provides a computer-readable storage medium storing a computer program, which, when executed by a processor, implements the online upgrade method for an energy storage system as described above.

[0015] According to the solution of the present invention, the present invention uses FPGA to manage the online upgrade function of each chip, which is simple and convenient, without the need for physical contact or hardware replacement, thereby reducing maintenance costs and improving system availability.

[0016] This invention uses a network interface to save the upgrade data of all chips and writes it to FLASH in a unified manner through the FPGA management module, which can improve the writing of upgrade files and greatly shorten the upgrade time.

[0017] This invention supports both built-in and external FLASH boot methods and is applicable to various types of chips.

[0018] This invention improves the flexibility and reliability of software program management for energy storage systems. By using FPGA to manage the online upgrade function of each chip, it ensures continuous system updates and maintenance without the need for physical contact or hardware replacement, thereby reducing maintenance costs and improving system availability. Attached Figure Description

[0019] Figure 1 A flowchart illustrating an online upgrade method for an energy storage system according to an embodiment of the present invention is shown. Figure 2 This diagram schematically illustrates the connection of an FPGA management module according to one embodiment of the present invention. Detailed Implementation

[0020] The invention will now be discussed with reference to exemplary embodiments. It should be understood that the described embodiments are merely intended to enable those skilled in the art to better understand and thus implement the invention, and are not intended to imply any limitation on the scope of the invention.

[0021] As used herein, the term "comprising" and its variations are to be interpreted as open-ended terms meaning "including but not limited to". The term "based on" is to be interpreted as "at least partially based on". The terms "one embodiment" and "an embodiment" are to be interpreted as "at least one embodiment".

[0022] Figure 1 A flowchart illustrating an online upgrade method for an energy storage system according to an embodiment of the present invention is shown. Figure 1 As shown, in this embodiment, the online upgrade method for the energy storage system includes: Upgrade data is generated according to the online upgrade protocol and sent to the FPGA management module (composed of an FPGA chip) via the host computer. The FPGA management module receives the upgrade data sent by the host computer. The FPGA management module obtains the status information of each chip to be upgraded in the energy storage system through the communication bus, determines whether the status of each chip to be upgraded allows the upgrade, and when the upgrade is allowed, the FPGA management module writes the upgrade data to the corresponding FLASH of the corresponding chip and verifies it. After successful verification, the corresponding FLASH is connected to the corresponding chip, and then the restart process of each chip is started. When the restart process for each chip is enabled, it determines the restart methods supported by each chip and configures the corresponding mode to restart according to the supported restart methods. After the chip restarts, it initializes the system and performs a self-test. Once all tasks start normally (if the upgrade file has issues, such as a status or register in the application code not being cleared before the upgrade, an online upgrade without power interruption, although the upgrade file is successfully written to FLASH, may cause some functions to malfunction. Therefore, "all tasks starting normally" here refers to the normal operation of all tasks created in the APP code for the chip upgrade to be considered complete), the chip upgrade is successfully communicated to the FPGA management module via the communication bus. Upon receiving the chip's upgrade status, the FPGA management module sends it to the host computer. The chip upgrade (including writing upgrade data to FLASH and ensuring all tasks in the APP code start successfully to prevent issues with the upgrade file from causing some functions to fail) is complete.

[0023] Furthermore, according to one embodiment of the present invention, upgrading data is generated according to an online upgrading protocol, and the upgrading data is sent to the FPGA management module via a host computer, including: Generate the binary data stream file required for chip upgrade according to the format agreed in the online upgrade protocol; The binary data stream file is packaged according to the agreed format in the upgrade protocol, expanded into data frames with data format, and a data stream transmission frame sequence is generated. The data stream transmission frame sequence is sent to the FPGA management module via the host computer.

[0024] Furthermore, according to one embodiment of the present invention, the FPGA management module receives upgrade data sent by the host computer, including: The FPGA management module establishes a network connection with the host computer; The host computer requests and issues upgrade instructions to each chip. The FPGA obtains the chip information that needs to be upgraded based on the upgrade instructions. The FPGA management module queries the operating status of each chip and responds to the host computer. If the chip is running, the upgrade is not allowed; if the chip is not running, the upgrade is allowed. When an upgrade is allowed, the host computer sends upgrade data. The FPGA management module performs CRC verification on the upgrade data and responds based on the CRC verification result. If the verification of a frame of data in the upgrade data fails, it returns a response indicating that the current frame is not received and waits for the host computer to retransmit the current frame data until all upgrade data is successfully verified. After the upgrade data verification is completed, the FPGA management module returns the CRC verification result to the host computer, the upgrade data transmission is completed, and the FPGA management module saves the upgrade data of each chip to the designated SRAM.

[0025] Furthermore, according to one embodiment of the present invention, the FPGA management module obtains the status information of each chip to be upgraded in the energy storage system through the communication bus, determines whether the status of each chip to be upgraded allows for upgrading, and if upgrading is allowed, the FPGA management module writes the upgrade data to the corresponding FLASH of the corresponding chip and performs verification. After successful verification, the corresponding FLASH is connected to the corresponding chip, and then the restart process of each chip is initiated, including: The FPGA management module obtains the status of each chip through the EMIF bus and / or serial bus. If the status allows for upgrade, the FPGA management module connects the SPI interface of the FLASH corresponding to each chip to the FPGA management module itself and disconnects the connection with each chip. The FPGA management module writes the upgrade data into the corresponding chip's FLASH via the SPI interface; After reading and writing, the upgrade data is verified (the entire upgrade data is checked using CRC). If the verification fails, the upgrade failure status of each chip is reported. If the verification succeeds, the corresponding FLASH of each chip is connected to each chip, and then the restart process of each chip is started.

[0026] In this embodiment, the FPGA management module establishes network communication with the host computer, which can query the version information and status information of each chip.

[0027] Furthermore, according to one embodiment of the present invention, determining the restart support mode of each chip and configuring the corresponding mode for restarting according to the restart support mode includes: Determine the restart mode supported by each chip. If the chip supports external SPI NOR FLASH boot, configure it to restart in this mode. If the chip supports booting from built-in SPI NOR FLASH, a secondary BOOTLOADER is written into the built-in FLASH of the corresponding chip. Then, the chip is powered on and started. The chip jumps to the 0 address entry of the built-in FLASH according to the boot method, runs the BOOT program, loads the upgrade data from the external FLASH connected to the chip, moves it to the specified area, and finally jumps to the entry address to run the APP.

[0028] In this implementation, in addition to its built-in bootloader, the chip also has a secondary bootloader, which is programmed to address 0 of the chip's FLASH memory via an emulator. This ensures that the chip loads the data at address 0 of the FLASH memory upon power-up and starts the secondary bootloader. The code within the secondary bootloader loads the external FLASH data, parses it, moves it to a designated area, and then jumps to the application's entry address to run.

[0029] Furthermore, according to one embodiment of the present invention, the present invention also supports multi-version upgrade management, that is, redundant storage is adopted in the energy storage system, that is, multiple versions of APP files are stored in the FLASH of the energy storage system, and the system can switch to the required version for operation according to actual needs.

[0030] According to the above-described scheme of the present invention, the present invention uses an FPGA management module to realize the online upgrade function of the energy storage system. For example... Figure 2 As shown, the FLASH interface is connected to the FPGA management module, and the FLASH communication interface of each chip is also connected to the FPGA management module. The FPGA management module is internally programmed to implement the switching function of each FLASH. Upon power-up, the FLASH interface switches to the respective chip by default, and each chip loads the data in its FLASH to complete the startup process. During upgrades, the FLASH interface switches to the FPGA management module, which receives upgrade data sent from the host computer and then writes the upgrade data to the corresponding chip's FLASH. This invention improves the flexibility and reliability of the energy storage system's software program management. By using FPGA to manage the online upgrade function of each chip, it ensures continuous system updates and maintenance without physical contact or hardware replacement, thereby reducing maintenance costs and improving system availability.

[0031] According to the above-described solution of the present invention, the present invention uses FPGA to manage the online upgrade function of each chip, which is simple and convenient, without the need for physical contact or hardware replacement, thereby reducing maintenance costs and improving system availability.

[0032] This invention uses a network interface to save the upgrade data of all chips and writes it to FLASH in a unified manner through the FPGA management module, which can improve the writing of upgrade files and greatly shorten the upgrade time.

[0033] This invention supports both built-in and external FLASH boot methods and is applicable to various types of chips.

[0034] Furthermore, to achieve the above objectives, the present invention also provides an online upgrade system for an energy storage system, comprising: The upgrade data interaction module generates upgrade data according to the online upgrade protocol, and sends the upgrade data to the FPGA management module through the host computer. The FPGA management module receives the upgrade data sent by the host computer. The upgrade data is written to the verification module. The FPGA management module obtains the status information of each chip to be upgraded in the energy storage system through the communication bus, determines whether the status of each chip to be upgraded allows the upgrade. If the upgrade is allowed, the FPGA management module writes the upgrade data to the corresponding FLASH of the corresponding chip and performs verification. After successful verification, the corresponding FLASH is connected to the corresponding chip, and then the restart process of each chip is started. The restart method determination module determines the restart methods supported by each chip when the restart process of each chip is enabled, and configures the corresponding mode to restart according to the supported restart methods. The chip restarts and upgrades the module. After the chip restarts, it initializes the system and performs a self-test. Once all tasks start normally, it notifies the FPGA management module of the upgrade success status via the communication bus. After receiving the chip's upgrade status, the FPGA management module sends it to the host computer, and the chip upgrade is complete.

[0035] The online upgrade system for energy storage systems according to the present invention can realize the online upgrade method for energy storage systems. The specific process steps are as described above and will not be repeated here.

[0036] Furthermore, to achieve the above objectives, the present invention also provides an electronic device, including a processor, a memory, and a computer program stored in the memory and executable on the processor. When the computer program is executed by the processor, it implements the online upgrade method for the energy storage system as described above.

[0037] Furthermore, to achieve the above objectives, the present invention also provides a computer-readable storage medium storing a computer program, which, when executed by a processor, implements the online upgrade method for the energy storage system as described above.

[0038] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely one preferred embodiment of the invention and are only used to explain the invention. They do not limit the scope of protection of the invention. All other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this invention.

[0039] Example 1 This embodiment uses the commonly used FPGA (FPGA management module) + DSP1 + DSP2 + ARM architecture in energy storage converters as an example for illustration. In this embodiment, the online upgrade method for the energy storage system includes: 1. Design the software transmission protocol for each chip: S110: Design an online upgrade communication protocol for energy storage system chip software, and complete the transmission of upgrade data based on the host computer; S120: Design the communication protocol between the FPGA management module and each chip, and complete the interaction of commands based on different communication interfaces; S130: Design the upgrade data file protocol for each chip, and complete the parsing and loading of chip data based on different chips.

[0040] In this embodiment, step S110 includes: Step 1: Generate the binary data stream file of the chip software to be upgraded according to the format agreed in the online upgrade protocol; Step 2: Pack the binary data stream file according to the agreed format in the upgrade protocol, expand it into data frames with a specific format, and generate a data stream transmission frame sequence; Step 3: According to the upgrade interaction process, the data stream transmission frame sequence is sent to the FPGA management module.

[0041] In this embodiment, step S120 includes: Step 1: DSP1 and FPGA are connected via EMIF bus and exchange version information and status information data according to the agreed format in the communication protocol; Step 2: DSP2 and FPGA are connected via EMIF bus and exchange version information and status information data according to the agreed format in the communication protocol; Step 3: The ARM and FPGA are connected via a serial bus and exchange version information and status information data according to the agreed format in the communication protocol; The FPGA establishes network communication with the host computer, which can then query the version and status information of the FPGA, DSP1, DSP2, and ARM.

[0042] In this embodiment, step S130 includes: Step 1: Generate the binary data stream file to be upgraded for the DSP according to the agreed format in the chip upgrade data file protocol; Step 2: Generate the binary data stream file to be upgraded for the ARM according to the agreed format in the chip upgrade data file protocol; Step 3: Generate the binary data stream file to be upgraded for the FPGA according to the agreed format in the chip upgrade data file protocol; Each chip reads the binary data stream upgrade file from the FLASH memory, parses it according to the upgrade data file protocol of each chip, and moves it to the designated memory location.

[0043] 2. Online upgrade of energy storage software: Step 1: Power-on startup. Set the reset pins of DSP1, DSP2, and ARM to high. First, the FPGA starts up by loading data from the FLASH memory into the designated memory location. After startup, connect the FLASH interfaces of DSP1, DSP2, and ARM to their respective chips. Then, pull the reset pins of DSP1, DSP2, and ARM low for 100ms and then pull them high again. At this point, the DSP1, DSP2, and ARM chips will start up sequentially until completion.

[0044] Step 2: After the FPGA powers on and starts up, all peripherals are initialized, and the FPGA enters normal operating state; after the DSP1 powers on and starts up, all peripherals are initialized, and the DSP1 enters normal operating state; after the DSP2 powers on and starts up, all peripherals are initialized, and the DSP2 enters normal operating state; after the ARM powers on and starts up, all peripherals are initialized, and the ARM enters normal operating state; DSP1 and FPGA are connected via EMIF bus; DSP2 and FPGA are connected via EMIF bus; ARM and FPGA are connected via serial bus; the FPGA establishes network communication with the host computer, and queries the version information and chip self-test status information of the FPGA, DSP1, DSP2, and ARM according to the software protocol.

[0045] Step 3: Upgrade File Creation. Generate the binary data stream file to be upgraded for each chip according to the agreed format in the chip upgrade data file protocol. In this embodiment, the upgrade file format includes the total CRC checksum, total upgrade length, starting address, length, and data. After decoding according to the agreed format, the chip moves the data to the designated memory location.

[0046] Step 4: The FPGA management module receives the upgrade data sent by the host computer; the specific interaction process for receiving upgrade data is as follows: S1. The host computer requests the download of upgrade programs for each chip. The FPGA management module responds to the file download request based on the operating status of each chip. If the device is running, the upgrade is not allowed. S2. If the upgrade is allowed, the host computer starts sending file segment data according to the protocol, and the FPGA management module responds according to the CRC check result; if the check of a certain frame fails, it returns an error message for receiving the current frame and waits for the host computer to retransmit the current frame data.

[0047] S3. After the host computer completes the transmission, the FPGA management module performs a CRC check on the entire upgrade file and returns the CRC check result, indicating that the upgrade file transmission is complete. The FPGA management module saves the upgrade files for each chip to the designated SRAM. The SRAM is divided into four areas, representing the upgrade files for FPGA, DSP1, DSP2, and ARM in that order. Step 5: The FPGA management module receives the upgrade and activation command from the host computer; At this point, the FPGA management module obtains the status of each chip through the EMIF bus. If the status allows for upgrade, the FPGA management module connects the SPI interface of the corresponding FLASH of each chip to its own end and disconnects from the chips. The FPGA management module begins to write the upgrade data to the corresponding FLASH area through the SPI interface; after reading and writing, it performs verification; if the verification fails, it reports the upgrade failure status of each chip; if the verification succeeds, it connects the corresponding FLASH of each chip to the chip, and after successful connection, it pulls the reset pin of each chip low for 100ms and then pulls it high, and each chip begins to restart. Step 6: If each chip supports external SPI NOR FLASH boot, simply configure it to this mode. Taking a DSP as an example, the DSP boot process is as follows: 1. When the DSP powers on / resets, the CPU jumps to execute the instruction in the reset vector; 2. Run the internal boot loader and select the boot mode; 3. Jump to the program entry address; 3. Turn off the watchdog; 4. Jump to the _c_int00 program; 5. Execute the _c_int00 program; 6. Execute the main function.

[0048] After the DSP starts up, it initializes the system, performs a self-test, and all tasks start normally. It then notifies the FPGA management module of the upgrade success status via the EMIF bus. Upon receiving the DSP's upgrade status, the FPGA management module sends it to the host computer. At this point, the DSP upgrade is successful. This method supports DSP, ARM, and FPGA software.

[0049] Step 7: If the chips do not support external SPI NOR FLASH boot, but instead support internal SPI NOR FLASH boot; for chips with internal FLASH boot, a secondary BOOTLOADER needs to be written into the internal FLASH; upon power-on, the chip jumps to address 0 of the internal FLASH according to the boot method, runs the BOOT program, loads the data from the external FLASH, decodes and verifies it, moves it to the designated area, and finally jumps to the entry address to run the APP. Taking a DSP as an example, if the DSP is configured with internal SPI NOR FLASH boot, the DSP boot process is as follows: 1. When the DSP powers on / resets, the CPU jumps to execute the instruction in the reset vector; 2. Run the internal boot loader and select the boot mode; 3. Jump to the secondary boot loader entry address; 3. Turn off the watchdog; 4. Jump to the _c_int00 program; 5. Execute the _c_int00 program; 6. Execute the main function; 7. Initialize the FLASH interface; 8. Move data from FLASH to the specified memory; 9. Verification; 10. Redirect to the app's entry address; 11. Execute the main function.

[0050] Similarly, after the DSP starts up, it initializes the system, performs a self-test, and all tasks start normally. Then, it notifies the FPGA management module of the upgrade success status via the EMIF bus. Upon receiving the DSP's upgrade status, the FPGA management module sends it to the host computer. At this point, the DSP upgrade is successful. This method supports DSP, ARM, and FPGA software.

[0051] Furthermore, in this embodiment, the method for online upgrade of the energy storage system's chip software also supports multi-version upgrade management, that is, storing multiple versions of APP files in the energy storage system's chip software FLASH, and switching to the required version for operation according to actual needs. In a specific embodiment, the process includes the following steps: Step 1: The FPGA management module switches the FLASH interface to connect to itself, and sets the reset pins of each chip to high level; Step 2: The FPGA management module establishes a network connection with the host computer and writes the application versions of multiple chips into the designated memory location of the corresponding FLASH according to the protocol. Step 3: The FPGA management module establishes communication with each chip and sends the version information to be started to the corresponding chip according to the protocol. Step 4: After decoding each chip, save the version information to the EEPROM; Step 5: The FPGA management module switches the FLASH to the corresponding chip interface; Step 6: The FPGA management module performs a hard reset of all chips; Step 7: After each chip powers on, it runs the secondary BOOTLOADER. The chip jumps to the 0 address of the built-in FLASH according to the boot method, runs the BOOT program, reads the version information in the EEPROM, loads the version data of the specified area in the FLASH, moves and parses it, and finally jumps to the entry address to run the APP.

[0052] Those skilled in the art will recognize that the modules and algorithm steps described in conjunction with the embodiments disclosed herein can be implemented using electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementations should not be considered beyond the scope of this invention.

[0053] Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the specific working process of the above-described apparatus and equipment can be referred to the corresponding process in the foregoing method implementation, and will not be repeated here.

[0054] In the embodiments provided in this application, it should be understood that the disclosed apparatus and methods can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative; for instance, the division of modules is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple modules or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be through some interfaces; the indirect coupling or communication connection between apparatuses or modules may be electrical, mechanical, or other forms.

[0055] The modules described as separate components may or may not be physically separate. The components shown as modules may or may not be physical modules; that is, they may be located in one place or distributed across multiple network modules. Some or all of the modules can be selected to achieve the purpose of the embodiments of the present invention, depending on actual needs.

[0056] In addition, the functional modules in the embodiments of the present invention can be integrated into one processing module, or each module can exist physically separately, or two or more modules can be integrated into one module.

[0057] If the aforementioned functions are implemented as software functional modules and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this invention, essentially, or the part that contributes to the prior art, or a portion of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the sending / receiving methods of various embodiments of this invention. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, ROM, RAM, magnetic disks, or optical disks.

[0058] The above description is merely a preferred embodiment of this application and an explanation of the technical principles employed. Those skilled in the art should understand that the scope of the invention involved in this application is not limited to technical solutions formed by specific combinations of the above-described technical features, but should also cover other technical solutions formed by arbitrary combinations of the above-described technical features or their equivalents without departing from the inventive concept. For example, technical solutions formed by substituting the above-described features with (but not limited to) technical features with similar functions disclosed in this application.

[0059] It should be understood that the sequence number of each step in the invention and its embodiments does not absolutely imply the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present invention.

Claims

1. An online upgrade method for an energy storage system, characterized in that, include: Upgrade data is generated according to the online upgrade protocol and sent to the FPGA management module via the host computer. The FPGA management module receives the upgrade data sent by the host computer. The FPGA management module obtains the status information of each chip to be upgraded in the energy storage system through the communication bus, determines whether the status of each chip to be upgraded allows the upgrade, and when the upgrade is allowed, the FPGA management module writes the upgrade data to the corresponding FLASH of the corresponding chip and verifies it. After successful verification, the corresponding FLASH is connected to the corresponding chip, and then the restart process of each chip is started. When the restart process for each chip is enabled, it determines the restart methods supported by each chip and configures the corresponding mode to restart according to the supported restart methods. After the chip restarts, it initializes the system and performs a self-test. Once all tasks start normally, it notifies the FPGA management module of the upgrade success status via the communication bus. After receiving the chip's upgrade status, the FPGA management module sends it to the host computer, and the chip upgrade is complete.

2. The online upgrade method for an energy storage system according to claim 1, characterized in that, The step of generating upgrade data according to the online upgrade protocol and sending the upgrade data to the FPGA management module via the host computer includes: Generate the binary data stream file required for chip upgrade according to the format agreed in the online upgrade protocol; The binary data stream file is packaged according to the agreed format in the upgrade protocol, expanded into data frames with data format, and a data stream transmission frame sequence is generated. The data stream transmission frame sequence is sent to the FPGA management module via the host computer.

3. The online upgrade method for an energy storage system according to claim 2, characterized in that, The FPGA management module receives upgrade data sent by the host computer, including: The FPGA management module establishes a network connection with the host computer; The host computer requests and issues upgrade instructions for each chip. The FPGA management module obtains the chip information that needs to be upgraded based on the upgrade instructions. The FPGA management module queries the operating status of each chip and responds to the host computer. If the chip is running, the upgrade is not allowed; if the chip is not running, the upgrade is allowed. When an upgrade is allowed, the host computer sends upgrade data. The FPGA management module performs CRC verification on the upgrade data and responds based on the CRC verification result. If the verification of a frame of data in the upgrade data fails, it returns a response indicating that the current frame is not received and waits for the host computer to retransmit the current frame data until all upgrade data is successfully verified. After the upgrade data verification is completed, the FPGA management module returns the CRC verification result to the host computer, the upgrade data transmission is completed, and the FPGA management module saves the upgrade data of each chip to the designated SRAM.

4. The online upgrade method for an energy storage system according to claim 3, characterized in that, The FPGA management module obtains the status information of each chip to be upgraded in the energy storage system through the communication bus, determines whether the status of each chip allows the upgrade, and if the upgrade is allowed, the FPGA management module writes the upgrade data to the corresponding FLASH of the corresponding chip and verifies it. After successful verification, the corresponding FLASH is connected to the corresponding chip, and then the restart process of each chip is initiated, including: The FPGA management module obtains the status of each chip through the EMIF bus and / or serial bus. If the status allows for upgrade, the FPGA management module connects the SPI interface of the FLASH corresponding to each chip to the FPGA management module itself and disconnects the connection with each chip. The FPGA management module writes the upgrade data into the corresponding chip's FLASH via the SPI interface; After reading and writing, the upgrade data is verified. If the verification fails, the upgrade failure status of each chip is reported. If the verification succeeds, the corresponding FLASH of each chip is connected to each chip, and then the restart process of each chip is started.

5. The online upgrade method for an energy storage system according to claim 4, characterized in that, The method for determining the restart support of each chip, and configuring the corresponding mode for restarting according to the supported restart method, includes: Determine the restart mode supported by each chip. If the chip supports external SPI NOR FLASH boot, configure it to restart in this mode. If the chip supports booting from built-in SPI NOR FLASH, a secondary BOOTLOADER is written into the built-in FLASH of the corresponding chip. Then, the chip is powered on and started. The chip jumps to the 0 address entry of the built-in FLASH according to the boot method, runs the BOOT program, loads the upgrade data from the external FLASH connected to the chip, moves it to the specified area, and finally jumps to the entry address to run the APP.

6. An online upgrade system for energy storage systems, characterized in that, include: The upgrade data interaction module generates upgrade data according to the online upgrade protocol, and sends the upgrade data to the FPGA management module through the host computer. The FPGA management module receives the upgrade data sent by the host computer. The upgrade data is written to the verification module. The FPGA management module obtains the status information of each chip to be upgraded in the energy storage system through the communication bus, determines whether the status of each chip to be upgraded allows the upgrade. If the upgrade is allowed, the FPGA management module writes the upgrade data to the corresponding FLASH of the corresponding chip and performs verification. After successful verification, the corresponding FLASH is connected to the corresponding chip, and then the restart process of each chip is started. The restart method determination module determines the restart methods supported by each chip when the restart process of each chip is enabled, and configures the corresponding mode to restart according to the supported restart methods. The chip restarts and upgrades the module. After the chip restarts, it initializes the system and performs a self-test. Once all tasks start normally, it notifies the FPGA management module of the upgrade success status via the communication bus. After receiving the chip's upgrade status, the FPGA management module sends it to the host computer, and the chip upgrade is complete.

7. An electronic device, characterized in that, It includes a processor, a memory, and a computer program stored in the memory and executable on the processor, wherein the computer program, when executed by the processor, implements the online upgrade method for an energy storage system as described in any one of claims 1-5.

8. A computer-readable storage medium, characterized in that, A computer program is stored on the computer-readable storage medium, and when the computer program is executed by a processor, it implements the online upgrade method for the energy storage system as described in any one of claims 1-5.

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