Thermal simulation method, device, equipment and computer program

Abstract

The invention provides a thermal simulation method and device, equipment and a computer program. The method comprises the following steps: dividing each layer of chip based on material types, determining a plurality of material areas, and determining the average temperature of each material area; based on the average temperature of each material region in each layer of chip, determining the equivalent thermal conductivity of each layer of chip in the first direction; wherein the first direction is a chip stacking direction; and calculating the equivalent thermal conductivity of the chip stacking structure based on the equivalent thermal conductivity of each layer of chip in the first direction. According to the method and the device, the simulation precision of the heat distribution condition of the 3D integrated circuit chip under different power consumption can be improved, so that the calculation accuracy of parameters such as equivalent heat conductivity and equivalent heat resistance is improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the semiconductor technology, and particularly to a thermal simulation method, device, equipment and computer program. BACKGROUND

[0002] For 3D integrated circuits, the stacking of multiple chips leads to a substantial increase in integration, an increase in the number of devices integrated per unit volume, an aggravation of the self-heating problem of interconnection lines, and a substantial increase in the amount of heat generated per unit area. Predicting the temperature distribution under different stacking structures, layouts, and power consumption distributions through simulation can be beneficial for thermal risk assessment at the design stage.

[0003] Variation of material thermal conductivity with temperature: the thermal conductivity of materials such as silicon and silicon oxide varies significantly with temperature, while traditional finite element simulation only sets a fixed thermal conductivity, making it difficult to accurately simulate the thermal distribution of the chip under different power consumptions, thereby affecting the calculation accuracy of parameters such as equivalent thermal conductivity and equivalent thermal resistance. The latest method for thermal simulation of 3D integrated circuits is to establish an equivalent thermal conductivity calculation model for different interconnection structures to simplify the thermal simulation of complex three-dimensional structures, but the temperature corresponding to the equivalent thermal conductivity calculation model is the average temperature or the maximum temperature of the entire stacked structure, which can cause errors in the thermal conductivity of the materials referred to, thereby affecting the calculation accuracy of the equivalent thermal conductivity. SUMMARY

[0004] The embodiments of the present application provide a thermal simulation method, device, equipment and computer program, which can improve the simulation accuracy of the thermal distribution of a 3D integrated circuit chip under different power consumptions, thereby improving the calculation accuracy of parameters such as equivalent thermal conductivity and equivalent thermal resistance.

[0005] The technical solutions of the embodiments of the present application are implemented as follows: In a first aspect, the embodiments of the present application provide a thermal simulation method applied to a chip stacking structure comprising a plurality of stacked chips, comprising the following steps: dividing each layer of chips based on the type of material, determining a plurality of material regions, and determining the average temperature of each material region; determining the equivalent thermal conductivity of each layer of chips in a first direction based on the average temperature of each material region in each layer of chips; wherein the first direction is the stacking direction of the chips; calculating the equivalent thermal conductivity of the chip stacking structure based on the equivalent thermal conductivity of each layer of chips in the first direction.

[0006] In a second aspect, the embodiments of the present application provide a thermal simulation device applied to a chip stacking structure comprising a plurality of stacked chips, comprising the following modules: a first calculation module configured to divide each layer of chips based on the type of material, determine a plurality of material regions, and determine the average temperature of each material region; The second calculation module is configured to determine the equivalent thermal conductivity of each layer of chips in the first direction based on the average temperature of each material region in each layer of chips. The third calculation module is configured to calculate the equivalent thermal conductivity of the chip stacking structure based on the equivalent thermal conductivity of each layer of chips in the first direction.

[0007] In a third aspect, an electronic device is provided, which includes a memory and a processor; wherein, The memory is configured to store computer executable instructions or computer programs. The processor is configured to execute the computer executable instructions or computer programs stored in the memory to implement the steps of the method of the first aspect.

[0008] In a fourth aspect, a computer program is provided, which, when executed by a processor, implements the steps of the method of the first aspect.

[0009] The embodiments of the present application have the following beneficial effects: The embodiments of the present application provide a thermal simulation method, device, equipment and computer program, which divides each layer of chips based on the material type, determines a plurality of material regions, and determines the average temperature of each material region; determines the equivalent thermal conductivity of each layer of chips in the first direction based on the average temperature of each material region in each layer of chips; wherein the first direction is the chip stacking direction; calculates the equivalent thermal conductivity of the chip stacking structure based on the equivalent thermal conductivity of each layer of chips in the first direction, which can improve the simulation accuracy of the thermal distribution of the 3D integrated circuit chip under different power consumptions, thereby improving the calculation accuracy of the equivalent thermal conductivity, equivalent thermal resistance and other parameters. BRIEF DESCRIPTION OF DRAWINGS

[0010] Figure 1 is a flowchart of a thermal simulation method provided by the embodiments of the present application; Figure 2 is a schematic diagram of a chip stacking structure provided by the embodiments of the present application; Figure 3 is a flowchart of another thermal simulation method provided by the embodiments of the present application; Figure 4 is a flowchart of another thermal simulation method provided by the embodiments of the present application; Figure 5 is a schematic diagram of the change of material thermal conductivity with temperature provided by the embodiments of the present application; Figure 6 is a flowchart of another thermal simulation method provided by the embodiments of the present application; Figure 7 is a schematic diagram of the composition structure of a thermal simulation device provided by the embodiments of the present application; Figure 8 is a hardware structure schematic diagram of an electronic device provided by an embodiment of the present application; Figure 9 is a component structure schematic diagram of an electronic device provided by an embodiment of the present application.

[0011] It should be noted that the above "first", "second" are only used to distinguish different schemes, and do not represent the degree of superiority or priority in the implementation process. DETAILED DESCRIPTION

[0012] In order to make the purpose, technical scheme and advantages of the present application clearer, the present application will be described in further detail below with reference to the drawings, and the described embodiments should not be regarded as limiting the present application. All other embodiments obtained by a person of ordinary skill in the art without making creative labor fall within the scope of protection of the present application.

[0013] In the following description, "some embodiments" are related to a subset of all possible embodiments, but it can be understood that "some embodiments" can be the same subset or different subset of all possible embodiments, and can be combined with each other without conflict.

[0014] In the following description, the terms "first\second\third" are only used to distinguish similar objects, and do not represent a specific order of the objects. It can be understood that "first\second\third" can interchange the specific order or sequence as allowed, so that the embodiments of the present application described herein can be implemented in an order other than that illustrated or described herein. In the embodiments of the present application, the term "module" or "unit" refers to a computer program or a part of a computer program with a predetermined function, and works with other related parts to achieve a predetermined target, and can be implemented entirely or partially by using software, hardware (such as processing circuit or memory) or combination thereof. Similarly, one processor (or multiple processors or memory) can be used to implement one or more modules or units. In addition, each module or unit can be a part of an integral module or unit that includes the function of the module or unit.

[0015] Unless otherwise defined, all technical and scientific terms used in the embodiments of the present application have the same meaning as commonly understood by a person skilled in the art. The terms used in the embodiments of the present application are only for the purpose of describing the embodiments of the present application, and are not intended to limit the present application.

[0016] The related data collection and processing in the embodiments of the present application should strictly comply with the requirements of relevant laws and regulations, obtain the informed consent or separate consent of the personal information subject, and carry out subsequent data use and processing within the scope of authorization of laws and regulations and the personal information subject.

[0017] The embodiments of the present application provide a thermal simulation method, device, equipment and computer program, which can improve the simulation accuracy of the thermal distribution of a 3D integrated circuit chip under different power consumptions, thereby improving the calculation accuracy of equivalent thermal conductivity, equivalent thermal resistance and the like.

[0018] For a 3D integrated circuit, the thermal conductivity of different material regions in a chip varies with temperature: the thermal conductivity of materials such as silicon and silicon oxide varies significantly with temperature, however, the traditional finite element simulation only sets a fixed thermal conductivity, which is difficult to accurately simulate the thermal distribution of the chip under different power consumptions, thereby affecting the calculation accuracy of equivalent thermal conductivity, equivalent thermal resistance and the like.

[0019] The latest thermal simulation of a 3D integrated circuit realizes the simplification of thermal simulation of a complex three-dimensional structure by establishing an equivalent thermal conductivity calculation model of different interconnection structures, but the temperature corresponding to the equivalent thermal conductivity calculation model is the average temperature or the highest temperature of the stacked structure, which leads to a deviation in the thermal conductivity of different material regions in the queried chip, thereby affecting the accuracy of the equivalent thermal conductivity calculation.

[0020] Based on this, the embodiments of the present application provide a thermal simulation method, the basic idea of which is: dividing each layer of chip based on material type, determining a plurality of material regions, and determining the average temperature of each material region; determining the equivalent thermal conductivity of each layer of chip in a first direction based on the average temperature of each material region in each layer of chip; wherein the first direction is the stacking direction of the chip; calculating the equivalent thermal conductivity of the chip stacking structure based on the equivalent thermal conductivity of each layer of chip in the first direction. In this way, by determining the temperature data of different material regions in each layer of chip in the chip stacking structure, determining the equivalent thermal conductivity of each layer of chip in the first direction, and then calculating the equivalent thermal conductivity of the chip stacking structure, the simulation accuracy of the thermal distribution of a 3D integrated circuit chip under different power consumptions can be improved, thereby improving the calculation accuracy of equivalent thermal conductivity, equivalent thermal resistance and the like.

[0021] The embodiments of the present application will be described in detail below with reference to the accompanying drawings.

[0022] In an embodiment of the present application, referring to Figure 1 which shows a flowchart of a thermal simulation method provided by an embodiment of the present application. As shown in Figure 1 , the method can include: S10: dividing each layer of chip based on material type, determining a plurality of material regions, and determining the average temperature of each material region.

[0023] It should be noted that the thermal simulation method provided by the embodiments of the present application is applied to a chip stack structure comprising a plurality of stacked chips.

[0024] It should be noted that, referring to Figure 2 , a schematic diagram of a chip stack structure is shown. As Figure 2 shown, the chip stack structure in the embodiment comprises a plurality of stacked chips along a first direction, including a first chip, a second chip, a third chip, a fourth chip, a fifth chip, and an nth chip. The first chip is located at the top of the chip stack structure, and the nth chip is located at the bottom of the chip stack structure. A through-silicon via vertically penetrates the silicon body of the chip to establish the shortest electrical connection between the top surface and the bottom surface of the chip. The plurality of stacked chips in the chip stack structure achieve electrical connection between metals and mechanical connection between dielectric layers through hybrid bonding.

[0025] It should be noted that the materials of the chips in the embodiment mainly include metal materials (copper), semiconductors (silicon), and insulators (silicon dioxide). The thermal conductivities of copper, silicon, and silicon dioxide all decrease with increasing temperature.

[0026] Specifically, in some embodiments, referring to Figure 3 , a flowchart of another thermal simulation method provided by the embodiments of the present application is shown. As Figure 3 shown, the average temperature of each material region is determined, specifically including: S101: receiving and determining thermal setting parameters and the thermal conductivity of each material region based on the initial setting parameters sent by the user; wherein the thermal setting parameters are used to describe the thermal environment in which the chip stack structure is located; S102: based on the thermal setting parameters and the thermal conductivity of each material region, the thermal distribution data of each chip layer is determined by simulation; S103: based on the thermal distribution data of each chip layer, the average temperature of each material region in each chip layer is determined.

[0027] It should be noted that the thermal setting parameters of each chip layer in the chip stack structure include top heat source power consumption parameters, four-around natural heat exchange parameters, and bottom constant temperature parameters. The top heat source power consumption parameters are based on applying power in the top region of each chip layer to simulate the self-heating unit in the stacked chip. The four-around natural heat exchange parameters simulate the natural convection and radiation heat dissipation between the package shell and the surrounding air, and simulate the effect of the heat sink. The bottom constant temperature parameters simulate the effective conduction of heat to the external environment.

[0028] Here, since the heat source is arranged at the top of the chip stack structure, the temperature of each layer of chips in the chip stack structure decreases along the first direction, and the accuracy of directly obtaining the equivalent thermal conductivity according to the temperature data of the chip stack structure will be reduced.

[0029] In this embodiment, the thermal distribution data of each layer of chips is determined by finite element simulation. First, the applied load and boundary conditions, i.e., the set thermal setting parameters, are set. The finite element simulation divides each layer of chips into a plurality of unit regions. Second, the thermal distribution data of each layer of chips is determined according to the initial thermal conductivity of the main material in each unit region and the thermal setting parameters.

[0030] Specifically, the thermal distribution data includes the temperature difference between the top surface and the bottom surface of the chip along the first direction, and the total heat flow passing through the chip along the first direction.

[0031] It should be noted that the total heat flow refers to the total heat power emitted from the heat source inside the chip (mainly the calculation unit on the top surface of the chip) and finally passing through the specified surface (usually the bottom surface of the chip) into the external heat dissipation system under steady-state working conditions. It reflects the efficiency of the package design in guiding heat from the heat source to the main heat dissipation path.

[0032] It should be noted that for a multi-material structure of a chip, when performing finite element simulation, the chip containing multiple materials is meshed, i.e., divided into a plurality of unit regions. According to the geometric position of the unit region, the corresponding material properties are assigned. For example, a unit completely located in the silicon substrate has a material property of "silicon"; a unit spanning the boundary between silicon and the silicon dioxide layer above it will be determined to belong to a certain main material according to the position of its barycenter or integral point; a unit completely located in the copper interconnect line has a material property of "copper". Therefore, the main materials of different unit regions in the chip are not consistent. In addition, the heat source is arranged at the top of the chip, and the distribution of the heat source on the chip is highly uneven. Heat flows from high-temperature areas to low-temperature areas, and the driving force of heat flow is the temperature gradient. The average temperature of different material regions in each layer of chips in the chip stack structure needs to be determined.

[0033] S20: Determine the equivalent thermal conductivity of each layer of chips in the first direction based on the average temperature of each material region in each layer of chips; wherein the first direction is the stacking direction of the chips.

[0034] It should be noted that the average temperature of different material regions in the chip has a corresponding equivalent thermal conductivity.

[0035] Specifically, in some embodiments, referring to Figure 4 which shows a flowchart of another thermal simulation method provided by an embodiment of the present application. As shown in Figure 4As shown, determining the equivalent thermal conductivity of each layer of chips in the first direction specifically includes: S201: updating the thermal conductivities of different material regions in each layer of chips based on the respective average temperatures of each material region in each layer of chips and a preset mapping relationship; wherein the preset mapping relationship indicates the change of the thermal conductivity of different materials with temperature; S202: returning to execute "simulating determining the thermal distribution data of each layer of chips based on the thermal setting parameters and the respective thermal conductivities of each material region"; S203: the difference between the equivalent thermal conductivity of each layer of chips in the first direction and the equivalent thermal conductivity calculated last time is less than or equal to a preset value.

[0036] It should be noted that the preset mapping relationship refers to the change relationship between the thermal conductivity of the material and the temperature. In some embodiments, referring to Figure 5 which shows a schematic diagram of the change of the thermal conductivity of a material with temperature provided by an embodiment of the present application. As shown in Figure 5 When performing chip thermal simulation, the thermal conductivities of different materials increase first and then decrease with the increase of temperature, showing a "hump" curve. As can be seen, when the temperature is 1-10℃, the thermal conductivities of Cu, Si, GaAs, SiC and diamond (II type) are all in the rising stage, and the thermal conductivity of Cu is obviously higher than that of other materials; when the temperature is 10-100℃, the thermal conductivities of Cu and GaAs begin to decrease with the temperature, the thermal conductivities of Si, SiC and diamond (II type) increase first and then decrease with the increase of temperature, and the thermal conductivity of GaN always increases; when the temperature is 100-1000℃, except that the thermal conductivity of GaN increases first and then decreases with the increase of temperature, the thermal conductivities of other materials decrease with the increase of temperature.

[0037] Here, according to the preset mapping relationship, the thermal conductivity corresponding to the average temperature of each material region in each layer of chips is queried, and the equivalent thermal conductivity of each material region in each layer of chips at the current temperature can be obtained. The initial thermal conductivity of different material regions in each layer of chips is replaced with the equivalent thermal conductivity.

[0038] Further, the thermal distribution data of the current each layer of chips is obtained again by combining finite element simulation, and the equivalent thermal conductivity of each layer of chips in the first direction is calculated according to the temperature difference between the top surface and the bottom surface of the chip along the first direction determined in the thermal distribution data and the total heat flow passing through the chip along the first direction.

[0039] It should be noted that the calculation formula for calculating the equivalent thermal conductivity of each layer of chips in the first direction is: ………………………………(1) wherein, This represents the horizontal cross-sectional area of ​​the chip; This represents the total heat flow through the chip along the first direction; Indicates the thickness of the chip; This indicates the temperature difference between the upper and lower surfaces of the chip along the first direction.

[0040] Here, based on the current thermal distribution data of each chip layer, the equivalent thermal conductivity of each chip layer in the first direction is repeatedly calculated until the difference between the equivalent thermal conductivity of each chip layer in the first direction and the previously calculated equivalent thermal conductivity is less than or equal to a preset value. The equivalent thermal conductivity of each chip layer in the first direction obtained from the last calculation is then output as the equivalent thermal conductivity of that chip layer. In this embodiment, the preset value is 0.5%, but the preset value can be other values ​​in other embodiments, and this embodiment is not limited to any specific value.

[0041] S30: Calculate the equivalent thermal conductivity of the chip stack structure based on the equivalent thermal conductivity of each chip layer in the first direction.

[0042] Here, the chip stack structure is achieved by connecting multiple layers of chips through hybrid bonding. The equivalent thermal conductivity of the chip stack structure is directly related to the equivalent thermal conductivity of each layer of chip in the first direction.

[0043] It should be noted that the formula for calculating the equivalent thermal conductivity of a chip stack structure is as follows: ………………………………(2) in, Indicates the first The thickness of the chip layer; Indicates the first The equivalent thermal conductivity of the chip.

[0044] In summary, the embodiments of this application provide a thermal simulation method, see [link to relevant documentation]. Figure 6 This illustrates a flowchart of another thermal simulation method provided in an embodiment of this application. Figure 6 As shown, the thermal simulation method specifically includes: S501: Divide each chip layer based on material type, determine multiple material regions, receive and determine thermal setting parameters and the thermal conductivity of each material region based on the initial setting parameters sent by the user.

[0045] Among them, the thermal setting parameters are used to describe the thermal environment of the chip stack structure.

[0046] S502: Based on thermal setting parameters and the thermal conductivity of each material region, the thermal distribution data of each chip layer is determined by simulation.

[0047] S503: Determine the average temperature of each material region in each layer of chips based on the thermal distribution data of each layer of chips.

[0048] S504: Update the thermal conductivity of different material regions in each layer of chips based on the average temperature of each material region in each layer of chips and the preset mapping relationship.

[0049] The preset mapping relationship indicates the change of thermal conductivity of different materials with temperature.

[0050] S505: Determine whether the difference between the equivalent thermal conductivity of each layer of chips in the first direction and the equivalent thermal conductivity calculated last time is less than or equal to a preset value.

[0051] When the difference between the equivalent thermal conductivity of each layer of chips in the first direction and the equivalent thermal conductivity calculated last time is greater than the preset value, return to execute S502; when the difference between the equivalent thermal conductivity of each layer of chips in the first direction and the equivalent thermal conductivity calculated last time is less than or equal to the preset value, execute the next step.

[0052] S506: Output the equivalent thermal conductivity of each layer of chips in the first direction calculated last time.

[0053] S507: Calculate the equivalent thermal conductivity of the chip stack structure.

[0054] Through the above thermal simulation process, the simulation accuracy of the thermal distribution of the 3D integrated circuit chip under different power consumptions is improved, thereby improving the calculation accuracy of the equivalent thermal conductivity, equivalent thermal resistance and other parameters.

[0055] In another embodiment of the present application, referring to Figure 7 which shows a schematic diagram of the composition structure of a thermal simulation device 30 provided by an embodiment of the present application. As Figure 7 shown, the thermal simulation device 30 is applied to a chip stack structure containing a plurality of layers of chips stacked, and includes the following modules: a first calculation module 301, a second calculation module 302 and a third calculation module 303.

[0056] The first calculation module 301 is configured to divide each layer of chips based on the type of material, determine a plurality of material regions, and determine the average temperature of each material region.

[0057] It should be noted that the thermal simulation device provided by the embodiment of the present application is applied to a chip stack structure, and the plurality of layers of chips in the chip stack structure are connected by hybrid bonding.

[0058] It should be noted that please continue to refer to Figure 2The chip stack structure in the embodiment is stacked by multiple chips along a first direction, including a first chip, a second chip, a third chip, a fourth chip, a fifth chip, and an nth chip. The first chip is located at the top of the chip stack structure, and the nth chip is located at the bottom of the chip stack structure. A through-silicon via vertically penetrates the silicon body of the chip to establish the shortest electrical connection between the top surface and the bottom surface of the chip. The multiple chips in the chip stack structure achieve electrical connection between metals and mechanical connection between dielectric layers through hybrid bonding.

[0059] It should be noted that the materials of the chips in the embodiment mainly include metal materials (copper), semiconductors (silicon), and insulators (silicon dioxide). The thermal conductivities of copper, silicon, and silicon dioxide decrease with the increase of temperature.

[0060] In some embodiments, the first computing module 301 is specifically configured to receive and determine, based on the initial setting parameters sent by the user, the thermal setting parameters and the thermal conductivities of each material region; wherein the thermal setting parameters are used to describe the thermal environment in which the chip stack structure is located. Based on the thermal setting parameters and the thermal conductivities of each material region, the thermal distribution data of each chip layer is simulated and determined. Based on the thermal distribution data of each chip layer, the average temperature of each material region in each chip layer is determined.

[0061] It should be noted that the thermal setting parameters of each chip layer in the chip stack structure include a top heat source power consumption parameter, a surrounding natural heat exchange parameter, and a bottom constant temperature parameter. The top heat source power consumption parameter is based on applying power to the top region of each chip layer to simulate the self-heating unit in the stacked chip. The surrounding natural heat exchange parameter simulates the natural convection and radiation heat dissipation between the package shell and the surrounding air, simulating the effect of the heat sink. The bottom constant temperature parameter simulates the effective conduction of heat to the external environment.

[0062] Here, since a heat source is set at the top of the chip stack structure, the temperature of each chip layer in the chip stack structure decreases along the first direction, and the accuracy of obtaining the equivalent thermal conductivity directly from the temperature data of the chip stack structure will decrease.

[0063] The embodiment determines the thermal distribution data of each chip layer through finite element simulation. First, the applied load and boundary conditions, i.e., the thermal setting parameters, are set. The finite element simulation divides each chip layer into a plurality of unit regions. Second, the thermal distribution data of each chip layer is determined according to the initial thermal conductivity of the main material in each unit region and the thermal setting parameters.

[0064] Specifically, the thermal distribution data includes the temperature difference between the top surface and the bottom surface of the chip along the first direction, and the total heat flow through the chip along the first direction.

[0065] It should be noted that the total heat flow refers to the total heat power emitted from the heat source inside the chip (mainly the calculation unit on the top surface of the chip) under steady-state working conditions, and finally passing through the specified surface (usually the bottom surface of the chip) into the external heat dissipation system. Reflects the efficiency of the package design in guiding heat from the heat source to the main heat dissipation path.

[0066] It should be noted that for a multi-material structure of a chip, when performing finite element simulation, the chip containing multiple materials is meshed, that is, divided into a plurality of unit regions, and according to the geometric position of the unit region, the corresponding material properties are assigned, for example, a unit completely located in the silicon substrate has the material property of "silicon"; a unit that crosses the boundary between silicon and the silicon dioxide layer above it will be determined to belong to a certain main material according to the position of its center of gravity or integral point; a unit completely located in the copper interconnect line has the material property of "copper". Therefore, the main materials of different unit regions in the chip are inconsistent. In addition, a heat source is provided on the top of the chip, and the distribution of the heat source on the chip is highly uneven. Heat flows from high-temperature areas to low-temperature areas, and the driving force of heat flow is the temperature gradient. The average temperature of each material region in each layer of the chip stack structure needs to be determined.

[0067] The second calculation module 302 is configured to determine the equivalent thermal conductivity of each layer of the chip in the first direction based on the average temperature of each material region in each layer of the chip.

[0068] It should be noted that the average temperature of each material region in the chip has a corresponding equivalent thermal conductivity.

[0069] In some embodiments, the second calculation module 302 is specifically configured to update the thermal conductivity of different material regions in each layer of the chip based on the average temperature of each material region in each layer of the chip and a preset mapping relationship; wherein the preset mapping relationship indicates the change of the thermal conductivity of different materials with temperature. Return to execute "simulate and determine the thermal distribution data of each layer of the chip based on the heat setting parameters and the thermal conductivity of each material region"; The difference between the equivalent thermal conductivity of each layer of the chip in the first direction and the equivalent thermal conductivity calculated in the previous calculation is less than or equal to a preset value.

[0070] It should be noted that the preset mapping relationship refers to the change relationship between the thermal conductivity of the material and the temperature. In some embodiments, please continue to refer to Figure 4When the thermal simulation of the chip is performed, the thermal conductivities of different materials present a "hump" shaped curve which first increases and then decreases with the increase of temperature. It can be seen that when the temperature is at 1-10℃, the thermal conductivities of Cu, Si, GaAs, SiC and diamond (II type) are all in the rising stage, and the thermal conductivity of Cu is obviously higher than that of other materials. When the temperature is at 10-100℃, the thermal conductivities of Cu and GaAs begin to decrease with the increase of temperature, the thermal conductivities of Si, SiC and diamond (II type) present a trend of increasing in the early stage and decreasing in the later stage with the increase of temperature, and the thermal conductivity of GaN always presents a rising stage. When the temperature is at 100-1000℃, the thermal conductivities of other materials all present a decreasing trend with the increase of temperature except that of GaN which presents a trend of increasing in the early stage and decreasing in the later stage.

[0071] Here, according to the preset mapping relationship, the thermal conductivity corresponding to the average temperature of each material region in each layer of chip is queried, the equivalent thermal conductivity of each material region in each layer of chip at the current temperature is obtained, and the initial thermal conductivity of different material regions in each layer of chip is replaced by the equivalent thermal conductivity.

[0072] Further, the thermal distribution data of the current each layer of chip is obtained again in combination with the finite element simulation, the temperature difference between the top surface and the bottom surface of the chip in the first direction determined according to the thermal distribution data, and the total heat flow passing through the chip in the first direction are used to calculate the equivalent thermal conductivity of each layer of chip in the first direction.

[0073] It should be noted that the calculation formula of the equivalent thermal conductivity of each layer of chip in the first direction is shown in formula (1).

[0074] Here, the equivalent thermal conductivity of each layer of chip in the first direction is repeatedly calculated according to the current thermal distribution data of each layer of chip, until the difference between the equivalent thermal conductivity of each layer of chip in the first direction and the equivalent thermal conductivity calculated in the last time is less than or equal to the preset value, and the equivalent thermal conductivity of each layer of chip in the first direction calculated in the last time is output as the equivalent thermal conductivity of the layer of chip. In the embodiment, the preset value is 0.5%, and the preset value can be other values in other embodiments, which is not limited in the embodiment.

[0075] The third calculation module 303 is configured to calculate the equivalent thermal conductivity of the chip stacking structure based on the equivalent thermal conductivity of each layer of chip in the first direction.

[0076] Here, the chip stacking structure is connected by multiple layers of chips through hybrid bonding, and the equivalent thermal conductivity of the chip stacking structure is directly related to the equivalent thermal conductivity of each layer of chip in the first direction.

[0077] It should be noted that the calculation formula of the equivalent thermal conductivity of the chip stacking structure is shown in formula (2).

[0078] Understandably, in this embodiment, a "module" can be a portion of a circuit, a portion of a processor, a portion of a program or software, etc. Moreover, the components in this embodiment can be integrated into one processing module, or each module can exist physically separately, or two or more modules can be integrated into one module. The integrated module described above can be implemented in hardware or as a software functional module.

[0079] If an integrated module is implemented as a software functional module and is not sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this embodiment, in essence, or the part that contributes to the prior art, or all or part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) or processor to execute all or part of the steps of the method of this embodiment. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0080] Therefore, this embodiment provides a computer program that, when executed by multiple processors, implements the steps of the thermal simulation method in any of the foregoing embodiments.

[0081] Based on the above-described composition of a thermal simulation device 30 and its computer storage medium, see [link to relevant documentation]. Figure 8 This illustrates a schematic diagram of the hardware structure of an electronic device 40 provided in an embodiment of this application. Figure 8 As shown, electronic device 40 may include: a communication interface 401, a memory 402, and a processor 403; the various components are coupled together via a bus device 404. It is understood that the bus device 404 is used to realize the connection and communication between these components, and the bus device 404 includes, in addition to a data bus, a power bus, a control bus, and a status signal bus. However, for clarity, in... Figure 8 All buses are labeled as bus devices 404. Among them, the communication interface 401 is used for receiving and sending signals during information exchange with other external network elements. Memory 402 is used to store computer-executable instructions or computer programs; The processor 403 is configured to execute computer-executable instructions or computer programs stored in the memory to implement the steps of the thermal simulation method in any of the foregoing embodiments.

[0082] It is to be appreciated that the memory 402 in embodiments of the application can be volatile, nonvolatile, or a combination of both. Non-volatile memory can be, for example, read only memory (ROM), programmable ROM (PROM), erasable PROM (EPROM), electrically EPROM (EEPROM), or flash memory. Volatile memory can be, for example, random access memory (RAM), which acts as external cache. By way of example and not limitation, many forms of RAM are available, such as static RAM (SRAM), dynamic RAM (DRAM), synchronous dynamic RAM (SDRAM), double data rate SDRAM (DDR SDRAM), enhanced SDRAM (ESDRAM), Synchlink DRAM (SLDRAM), and direct Rambus RAM (DRRAM). The memory 402 of the devices and methods described herein are intended to include, without being limited to, these and any other suitable types of memory.

[0083] The processor 403 can be an integrated circuit chip having a processing capability of signals. In the implementation process, each step of the above method can be completed by the integrated logic circuit of hardware in the processor 403 or the instruction in the form of software. The processor 403 described above can be a general processor, a digital signal processor (Digital Signal Processor, DSP), an application specific integrated circuit (Application Specific Integrated Circuit, ASIC), a field programmable gate array (Field Programmable Gate Array, FPGA) or other programmable logic device, a discrete gate or transistor logic device, a discrete hardware component. Each method, step and logic block diagram disclosed in the embodiment of the present application can be implemented or executed. The general processor can be a microprocessor or the processor can also be any conventional processor. The steps of the method disclosed in combination with the embodiment of the present application can be directly embodied as a hardware code processor for execution, or a combination of hardware and software modules in the code processor for execution. The software module can be located in a random access memory, a flash memory, a read only memory, a programmable read only memory or an electrically erasable programmable memory, a register or other mature storage medium in the art. The storage medium is located in the memory 402, and the processor 403 reads the information in the memory 402, and combines the hardware to complete the steps of the above method.

[0084] It can be understood that the embodiments described in the present application can be realized by hardware, software, firmware, middleware, microcode or a combination thereof. For hardware implementation, the processing unit can be realized in one or more application specific integrated circuits (Application Specific Integrated Circuits, ASIC), digital signal processors (Digital Signal Processing, DSP), digital signal processing devices (DSP Device, DSPD), programmable logic devices (Programmable Logic Device, PLD), field programmable gate arrays (Field-Programmable Gate Array, FPGA), general processors, controllers, microcontrollers, microprocessors, other electronic units for executing functions of the present application or a combination thereof.

[0085] For software implementation, the technology of the present application can be realized by modules (such as processes, functions, etc.) for executing functions of the present application. The software code can be stored in the memory and executed by the processor. The memory can be implemented in the processor or outside the processor.

[0086] Optionally, as another embodiment, the processor 403 is further configured to execute the steps of the method of any one of the preceding embodiments when running the computer program.

[0087] In yet another embodiment of the present application, based on the composition schematic diagram of the thermal simulation device 30 described above, referring to Figure 9 , a composition structure schematic diagram of an electronic device 40 provided by an embodiment of the present application is shown. As Figure 9 shown, the electronic device 40 at least includes the thermal simulation device 30 of any one of the preceding embodiments.

[0088] An embodiment of the present application provides a computer program stored in a computer readable storage medium. The processor of the electronic device reads the computer program from the computer readable storage medium, and the processor executes the computer program, so that the electronic device executes the thermal simulation method described above in the embodiments of the present application.

[0089] An embodiment of the present application provides a computer program, when the computer program is executed by the processor, will cause the processor to execute the thermal simulation method provided by the embodiments of the present application, for example, as Figure 1 shown, the thermal simulation method.

[0090] In summary, through the embodiments of the present application, the simulation accuracy of the thermal distribution of the 3D integrated circuit chip under different power consumptions can be improved, so as to improve the calculation accuracy of the equivalent thermal conductivity, equivalent thermal resistance and other parameters.

[0091] The above merely describes the embodiments of the present application, but is not intended to limit the protection scope of the present application. Any modification, equivalent replacement and improvement within the spirit and scope of the present application shall be included in the protection scope of the present application.

Claims

1. A thermal simulation method, characterized in that, For chip stacking structures containing multiple chip stacks, the following steps are included: Each chip layer is divided based on the type of material, multiple material regions are identified, and the average temperature of each material region is determined. Based on the average temperature of each material region in each layer of the chip, the equivalent thermal conductivity of each layer of the chip is determined in a first direction; wherein, the first direction is the chip stacking direction; The equivalent thermal conductivity of the chip stack structure is calculated based on the equivalent thermal conductivity of each chip layer in the first direction.

2. The method according to claim 1, characterized in that, Determining the average temperature of each of the material regions specifically includes: Receive and determine thermal setting parameters and the thermal conductivity of each of the material regions based on the initial setting parameters sent by the user; wherein the thermal setting parameters are used to describe the thermal environment of the chip stack structure. Based on the thermal setting parameters and the thermal conductivity of each material region, the thermal distribution data of each layer of the chip is determined by simulation. Based on the thermal distribution data of each layer of the chip, the average temperature of each material region in each layer of the chip is determined.

3. The method according to claim 1, characterized in that, Determining the equivalent thermal conductivity of each chip layer in the first direction specifically includes: Based on the average temperature of each material region in each layer of the chip and a preset mapping relationship, the thermal conductivity of different material regions in each layer of the chip is updated; wherein, the preset mapping relationship indicates the change of thermal conductivity of different materials with temperature; Return to the execution of "Based on the thermal setting parameters and the thermal conductivity of each material region, simulate and determine the thermal distribution data of each layer of the chip"; The difference between the equivalent thermal conductivity of each layer of the chip in the first direction and the previously calculated equivalent thermal conductivity is less than or equal to a preset value.

4. The method according to claim 2, characterized in that, The thermal setting parameters include one or more of the following: (1) top heat source power consumption parameters; (2) surrounding natural heat exchange parameters; (3) bottom constant temperature parameters; The heat distribution data includes one or more of the following: (1) the temperature difference between the top and bottom surfaces of the chip along the first direction; and (2) the total heat flow through the chip along the first direction.

5. The method according to claim 1, characterized in that, The formula for calculating the equivalent thermal conductivity of each layer of the chip in the first direction is as follows: in, This represents the horizontal cross-sectional area of ​​the chip; This represents the total heat flow through the chip in the first direction; Indicates the thickness of the chip; This indicates the temperature difference between the upper and lower surfaces of the chip in the first direction.

6. The method according to claim 1, characterized in that, The formula for calculating the equivalent thermal conductivity of the chip stack structure is as follows: in, Indicates the first The thickness of the chip layer; Indicates the first The equivalent thermal conductivity of the chip.

7. The method according to claim 2, characterized in that, The multi-layered chips in the chip stacking structure are connected through hybrid bonding. The thermal distribution data of each layer of the chip is determined through finite element simulation.

8. A thermal simulation device, characterized in that, Applied to chip stacking structures containing multiple chip stacks, including the following modules: The first calculation module is configured to divide each chip layer based on the material type, determine multiple material regions, and determine the average temperature of each material region. The second calculation module is configured to determine the equivalent thermal conductivity of each layer of the chip in a first direction based on the average temperature of each material region in each layer of the chip; wherein, the first direction is the chip stacking direction; The third calculation module is configured to calculate the equivalent thermal conductivity of the chip stack structure based on the equivalent thermal conductivity of each layer of the chip in a first direction.

9. An electronic device, characterized in that, The electronic device includes a memory and a processor; wherein... Memory is used to store executable instructions or computer programs. A processor, when executing computer-executable instructions or computer programs stored in the memory, implements the steps of the method according to any one of claims 1 to 7.

10. A computer program, characterized in that, When the program is executed by a processor, it implements the steps of the method according to any one of claims 1 to 7.

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