Project state summarization method and device

Abstract

The invention provides a project state summarizing method and device, and belongs to the technical field of DFT (Discrete Fourier Transform), and the project state summarizing method comprises the following steps: distributing a plurality of test tasks to a plurality of predefined categories according to the corresponding test steps according to the mapping relation between the test steps and the predefined categories; and based on the task state of the test task included in each predefined category, determining the category state of the corresponding predefined category. Through a predefined mapping relation, original and scattered test tasks and states thereof are aggregated into classified and macroscopic class states.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to the technical field of Design for Testability (DFT), and particularly relates to a project status summarization method and device. BACKGROUND

[0002] In the chip design of modern very large scale integrated circuits, the design process is increasingly complex, especially the DFT process, which runs through various stages of chip design, verification and testing. The DFT process usually involves the parallel advancement of multiple design projects or modules, and the iteration of multiple milestone versions of a single project in the development cycle. For example, a project may go through multiple milestone versions such as Register Transfer Level (RTL) 35 version, RTL 50 version, RTL 80 version, RTL 100 version, and finally Tape Out (TO).

[0003] In the related art, the progress tracking and status summarization of DFT projects largely depends on manual statistics by DFT engineers. Engineers need to manually check the execution status of each test task, and then make a task list, a progress table or a report for display, but manual statistics is inefficient and prone to errors.

[0004] Therefore, in the DFT process, there is an urgent need for a project status summarization method that can efficiently summarize project progress or status. SUMMARY

[0005] The present disclosure provides a project status summarization method and device, which can solve the problems of DFT project progress tracking relying on manual statistics, low efficiency and error-prone.

[0006] The technical solution of the present disclosure is implemented as follows: In a first aspect, the present disclosure provides a project status summarization method, which comprises: according to a mapping relationship between test steps and predefined categories, assigning multiple test tasks to multiple predefined categories according to corresponding test steps; and determining a category state of each predefined category based on the task state of the test task included in the predefined category. Through the predefined mapping relationship, the original and scattered test tasks and their states are aggregated into classified and macroscopic category states. The category state can dynamically and accurately reflect the overall progress of the project and the health status of the key link. Users can understand the overall progress of the chip project without checking the task state of each test task one by one, thereby solving the problems of low efficiency and error-prone in the prior art.

[0007] In some embodiments, determining the category state of the corresponding predefined category based on the task state of the test task included in each predefined category comprises: when the predefined category is assigned with a task state including a discrete state value, determining the task state with the highest priority as the category state of the corresponding predefined category according to a preset state priority. By adopting such priority aggregation logic, such as "failure" priority, it is ensured that any one underlying, local test task failure is immediately passed to the macro category summary interface. This enables the user to promptly understand the key bottlenecks of the project, greatly enhancing the risk warning capability and the intuitiveness of the project management.

[0008] In some embodiments, when the predefined category is assigned with a task state including a discrete state value, determining the task state with the highest priority as the category state of the corresponding predefined category according to a preset state priority comprises: when the predefined category is assigned with a task state including a discrete state value, determining the high-priority task state with the highest priority according to a preset state priority; determining the criticality of the test step corresponding to the high-priority task state according to a preset test step criticality; and determining the category state of the corresponding predefined category according to the high-priority task state and the criticality of the corresponding test step. For higher risk management application scenarios, the introduction of the criticality of the test step provides a more refined category state, which enables the user to immediately distinguish between serious problems and general problems, so as to preferentially invest limited engineering resources in solving more serious problems, thereby achieving more efficient and more accurate risk management and resource allocation.

[0009] In some embodiments, the predefined categories include at least one of the following: an insertion category, a vector category, a simulation category, a timing category, a post-layout simulation category, and an automatic test vector generation category. In this way, key categories that can reflect the execution progress of various test tasks are covered.

[0010] In some embodiments, determining the category state of the corresponding predefined category based on the task state of the test task included in each predefined category comprises: when the predefined category is assigned with a task state including a numerical value, determining the category state of the corresponding predefined category from a log file associated with the test task corresponding to the numerical value task state. By automatically grabbing and extracting key performance indicators from the log file, the automatic summary of project quality indicators (not just progress states) is achieved, which enables the category summary to simultaneously display the execution progress and quality of the project in a unified view, greatly improving the data dimension and decision-making efficiency of project management.

[0011] In some embodiments, the predefined categories include a coverage category. The coverage, which can reflect the execution quality of the test task, is directly reflected as a predefined category to reflect the execution quality of the test task.

[0012] In some embodiments, the project status summary method further comprises: displaying a set of test task lists associated with the preset category when any category state is a preset trigger state. An automatic drilling function is provided, seamlessly connecting the status summary and the test tasks, and the user does not need to manually switch to locate the failure point after discovering macroscopic problems, greatly simplifying the operation process.

[0013] In some embodiments, according to the mapping relationship between the test steps and the predefined categories, the multiple test tasks are assigned to the multiple predefined categories according to the corresponding test steps, comprising: determining the corresponding predefined category according to the test step corresponding to each test task by a machine learning model, and the machine learning model is trained by multiple samples, and each sample includes a test step and a corresponding predefined category. The mapping relationship can be dynamically learned and predicted, greatly improving flexibility and scalability.

[0014] In some embodiments, the project status summary method further comprises: displaying the visual identifier corresponding to each category state according to the corresponding relationship between the category state and the visual identifier. The category state can be more intuitively displayed.

[0015] In a second aspect, the present disclosure provides a project status summary device, comprising: an assignment part and a determination part; the assignment part is configured to assign multiple test tasks to multiple predefined categories according to the corresponding test steps according to the mapping relationship between the test steps and the predefined categories; the determination part is configured to determine the category state of the corresponding predefined category based on the task state of the test task included in each predefined category.

[0016] In a third aspect, the present disclosure provides an electronic device, comprising a processor, a memory, and a program or instruction stored on the memory and executable on the processor, which, when executed by the processor, implements the steps of the project status summary method of the first aspect.

[0017] In a fourth aspect, the present disclosure provides a computer-readable storage medium, which stores a program or instruction, which, when executed by a processor, implements the steps of the project status summary method of the first aspect.

[0018] In a fifth aspect, the present disclosure provides a computer program product, wherein the computer program product comprises a computer program or instruction, which, when the computer program product is executed on a processor, causes the processor to execute the computer program or instruction, and implements the steps of the project status summary method of the first aspect.

[0019] In a sixth aspect, the present disclosure provides a chip comprising a processor and a communication interface coupled to the processor, the processor being configured to execute programs or instructions to implement the project status aggregation method according to the first aspect.

[0020] The present disclosure provides a project status aggregation method, which aggregates original and scattered test tasks and their statuses into classified and macroscopic category statuses through a predefined mapping relationship, so that the category statuses can dynamically and accurately reflect the overall progress and health status of key links of a project, and a user can understand the overall progress status of a chip project without checking the task status of each test task one by one, thereby solving the problems of low efficiency and high error rate of manual statistics in the prior art. BRIEF DESCRIPTION OF DRAWINGS

[0021] Figure 1 A schematic diagram of an architecture of a project status aggregation system according to the present disclosure.

[0022] Figure 2 A schematic diagram of a flow of a project status aggregation method according to the present disclosure.

[0023] Figure 3 A schematic diagram of a user interface of a task status of a test task according to the present disclosure.

[0024] Figure 4 A schematic diagram of a user interface of an aggregated category status according to the present disclosure.

[0025] Figure 5 A schematic diagram of a flow of a classification aggregation logic according to the present disclosure.

[0026] Figure 6 A schematic diagram of a flow of an aggregation logic combined with a test step criticality according to the present disclosure.

[0027] Figure 7 A schematic diagram of a flow of another project status aggregation method according to the present disclosure.

[0028] Figure 8 A schematic diagram of a user interface of status triggering and detailed list display according to the present disclosure.

[0029] Figure 9 A schematic diagram of a flow of still another project status aggregation method according to the present disclosure.

[0030] Figure 10 A schematic diagram of a user interface of a category status including a visual identifier according to the present disclosure.

[0031] Figure 11 A flowchart of a mapping method based on machine learning according to the present disclosure.

[0032] Figure 12 A structural block diagram of a project status summary device provided by the present disclosure.

[0033] Figure 13 A hardware structure schematic diagram of an electronic device provided by the present disclosure. DETAILED DESCRIPTION

[0034] The technical solutions in the embodiments of the present disclosure will be clearly described below with reference to the drawings in the present disclosure. Obviously, the described embodiments are only part of the embodiments of the present disclosure, rather than all the embodiments. Based on the embodiments in the present disclosure, all other embodiments obtained by a person of ordinary skill in the art belong to the scope of protection of the present disclosure.

[0035] In order to facilitate the understanding of the embodiments of the present disclosure, first, some terms involved in the embodiments of the present disclosure are explained and described.

[0036] DFT is a design technique for integrated circuits, aiming to make the circuit easy to test after manufacturing, to ensure its functional correctness and detect manufacturing defects.

[0037] Automatic Test Pattern Generation (ATPG), a technique for automatically generating test vectors (i.e. signal sequences applied to chip inputs and observed outputs), is used to detect possible faults in the circuit.

[0038] Stuck-at (SA) fault, a common circuit fault model, mainly refers to the fault that the logic state of the signal line is always fixed at logic "0" or logic "1".

[0039] Transition (TR) fault, a common circuit fault model, also known as delay fault, mainly refers to the fault that the logic gate fault node delay causes the failure to observe the correct output result within the expected time.

[0040] Coverage, in the field of DFT, mainly refers to test coverage, i.e. the number of faults detected by the test vector generated by ATPG, accounting for the percentage of the total number of testable faults. Among them, DC Coverage refers to the test coverage of stuck-at fault, and AC Coverage refers to the test coverage of transition fault.

[0041] Layout, refers to the physical design graphics of integrated circuits, which defines the geometric shape and position of components such as transistors and wires in the circuit on the chip.

[0042] Controller Chain Mode (CCM): A specific test mode, under which ATPG vectors are usually used to cover faults in the control logic related to logic self-test.

[0043] Boundary Scan (BSCAN): A DFT technique that enables testing of chip pin connections and inter-chip interconnections by adding serial scan cells at the chip's input / output pins.

[0044] Memory Build-In-Self Test (MBIST): A test mechanism implemented inside the chip to automatically detect memory faults when the chip is powered on or reset. MBIST generates test vectors through an internal test controller, writes these vectors into the memory, and then reads and verifies the results to detect memory errors.

[0045] In-System Test (IST): A structured test that is automatically run in the chip's normal working environment (e.g., during system startup and / or shutdown) to monitor faults caused by field defects.

[0046] Memory Build-In-Self Repair (MBISR): A technique that automatically repairs memory faults when detected. MBISR usually utilizes redundant resources in the memory, such as extra rows, columns, or memory cells, to replace or bypass faulty areas, thereby restoring the normal function of the memory.

[0047] Test Access Port (TAP): Usually refers to a test interface that complies with IEEE 1149.1 standards, used to access DFT logic inside the chip, such as BSCAN, MBIST, etc.

[0048] DFT Intellectual Property (DFT IP): Refers to some pre-designed and verified test modules or logic circuits related to DFT, provided by chip IP vendors or Electronic Design Automation (EDA) vendors.

[0049] On-Chip Clock Control (OCC): A DFT IP used to accurately control various clock signals inside the chip during testing to support testing needs such as ATPG.

[0050] Embedded deterministic test (EDT), a DFT test method, which is to compress and decompress the large number of scan chains inside the chip into a small number of scan channels through the integration of compressors and decompressors inside the chip, and interact with external automatic test equipment through these scan channels, thereby greatly reducing the amount of test data and test time.

[0051] Logic build-in-self test (LBIST), a built-in self-test technology for chip logic circuits, is a way to implement IST. The LBIST module usually includes a pseudo-random vector generator and a multi-input signature register, which is used to automatically generate test vectors and compress responses inside the chip to realize self-test of logic circuits.

[0052] Streaming scan network (SSN), a DFT solution provided by EDA vendors, aims to address the complex test challenges in modern large-scale system-on-chip design, and provides a more flexible and efficient scan data distribution network.

[0053] Formal verification, a static verification method, checks whether a design file meets a certain predefined property or whether two design files are logically equivalent by using mathematical tools.

[0054] Register transfer level (RTL): a design method that uses registers and combinational logic to abstractly describe the function in digital circuits, which is a key bridge between high-level functional requirements and low-level specific circuit implementation, mainly focusing on the process of data transmission from one register to the next register and the intermediate combinational logic operation.

[0055] Synthesis (SYN), an EDA process step, converts the behaviorally described or RTL-level circuit description into a connection composed of unit circuits (such as AND gates, OR gates, flip-flops, etc.) from the specified technology library, i.e. gate-level netlist, under the conditions of meeting the functional, speed and area of the design circuit, etc.

[0056] TO, refers to the completion of all design and verification steps of the chip, and the final design data is submitted to the semiconductor manufacturing plant for physical production.

[0057] Figure 1 An architecture schematic diagram of a project status summary system 10 is provided for the embodiments of the present disclosure. The project status summary system 10 runs on one or more electronic devices.

[0058] As Figure 1 shown, the project status summary system 10 can include a backend server 120, one or more user terminals 110.

[0059] The backend server 120 is the core execution entity of the method of the embodiments of the present disclosure. The backend server 120 executes program instructions stored in the memory through its processor to realize the logic of the project status summary of the embodiments of the present disclosure.

[0060] The user terminal 110 is a device used by the DFT engineer to interact with the project status summary system 10, such as a personal computer or workstation. The user terminal 110 displays a user interface to the user and receives the user's input.

[0061] The task database is used to store a large number of test tasks and their original task states corresponding to all design projects, milestones and test steps, for example, stored in the memory of the backend server 120 or the memory of the user terminal 110. A design project refers to a specific chip design project or a module in a project. A milestone refers to a specific version node of a design project in the development process. Chip development involves multiple version iterations, and different milestones (such as RTL35, RTL50, RTL80, RTL100, TO, etc.) represent different maturity stages and delivery nodes of the design.

[0062] The classification rule database is used to store the mapping relationship (i.e. mapping rule) of the test steps of the embodiments of the present disclosure to the predefined categories, for example, stored in the memory of the backend server 120 or the memory of the user terminal 110.

[0063] The method for realizing the project status summary of the embodiments of the present disclosure can be realized by the backend server 120, which sends the final determined category state of the predefined category to the user terminal 110, and can also be realized by the user terminal 110, which is not limited by the present disclosure.

[0064] The embodiments of the present disclosure provide a method for summarizing project status, which reads original data from the task database, and according to the classification rule database, processes and presents the complex data in the task status interface of the test task on the classification summary interface.

[0065] The project status summary method provided by the present disclosure will be described in detail below in combination with the drawings, through specific embodiments and their application scenarios.

[0066] As Figure 2 shown, the present disclosure provides a project status summary method, the execution subject can be the above-mentioned user terminal 110 or the backend server 120, and the method can include the following steps S201 and S202.

[0067] In step S201, according to the mapping relationship between the test steps and the predefined categories, the multiple test tasks are distributed to the multiple predefined categories according to the corresponding test steps.

[0068] The mapping relationship defines which one or which ones of the predefined categories each test step should be classified into, that is, indicates the test steps included under each predefined category. One test step can be distributed to at least one predefined category.

[0069] The predefined category is a management unit for state summary, which is a logical grouping of multiple test steps with logical correlation from a management perspective. The multiple predefined categories include at least one of the following: an Insertion category, a Pattern category, a Simulation category, an ATPG category, a Timing category, a Gatesim category, a Coverage category, etc. The Coverage category can specifically include a DC Coverage category and an AC Coverage category, etc. The Coverage category can also include other indicators for indicating the DFT execution quality according to needs, which is not specifically limited in the present disclosure.

[0070] Among them, the Insertion category represents all the work related to adding DFT logic to the design. Through this category, the manager can know the progress and status of all DFT IP, such as BSCAN, MBIST, EDT, OCC, etc., and the insertion work of the scan chain. For example, the Insertion category can include the following test steps: Design_release_check, design release check, this test step is used to perform compliance check on the design received by the DFT flow. For example, before DFT insertion, check if the register transfer level code is syntactically correct, if there are uncontrolled clock, combinational logic loop, asynchronous reset, etc. issues that can affect DFT insertion and testing; DFT INSERT1, first stage DFT IP insertion. This step mainly includes inserting some basic or module level DFT IP modules, these IPs can include: BSCAN, MBIST, IST, MBISR, TAP, etc.; DFT INSERT2, second stage DFT IP insertion, this test step mainly includes inserting some higher level or chip level DFT IP, especially the logic related to scan compression and clock control, such as OCC, EDT, LBIST, SSN, etc.; formal verification, after DFT IP insertion, use formal verification tools to check if the inserted design is logically equivalent to the pre-insertion design, to ensure that the introduction of DFT logic does not destroy the original chip function; SYN DFT, DFT synthesis, convert the RTL design inserted with the above DFT IP into a gate level netlist through a synthesis tool; SCAN INSERT, insert test scan chain, connect all or most of the flip-flops into one or more scan chains in the synthesized gate level netlist, which is the basis for implementing scan testing (ATPG, EDT, LBIST, etc.).

[0071] Pattern class represents all the work related to the final test vector generation, through this class, the manager can quickly determine whether the layout-level vectors such as SA, TR, CCM, etc. used for chip testing have been successfully generated. For example, the Pattern class can include the following test steps: ATPG_SA_LAY, layout-level stuck-at ATPG, after the chip is completed, based on the layout netlist containing accurate parasitic parameters (delay information), generate test vectors for detecting stuck-at faults; ATPG_TR_LAY, layout-level transition ATPG, as above, based on the layout netlist, generate test vectors for detecting transition faults; ATPG_CCM_LAY, layout-level CCM mode ATPG, used to cover faults in the LBIST related control logic in the manufacturing stage; full chip vector generation (test pattern generation, TPG), user-defined, refers to some non-standard, user-defined developed, for specific test purposes (such as full chip functional testing) vector generation steps.

[0072] The Simulation class represents all simulation verification work, aggregates all simulation tasks from the register transfer level to the gate level, such as SIM_RTL_BLK, ATPG_SIM_SYN, LBIST_SIM_LAY, and the like, and the manager determines whether the overall simulation verification passes through this class. For example, the Simulation class can include the following test steps: SIM_RTL_BLK, module-level RTL simulation, in the RTL stage, simulating a module containing DFT IP (such as MBIST, BSCAN), verifying the basic functions of the DFT logic, for example, verifying the ICL (Inter-Connect Logic), MBIST, BSCAN, BISR (built-in self-repair) functions, SSN loopback, and the like; SIM_RTL_CHIP, chip-level RTL simulation, in the RTL stage, simulating the entire chip to verify the functions of DFT at the chip level; ATPG_SIM_SYN, pre-simulation of ATPG vectors, gate-level simulation of ATPG vectors generated after synthesis of the netlist, to ensure the correctness of the vectors; LBIST_SIM, dynamic simulation of LBIST vectors, simulating the pseudo-random vectors generated by LBIST to verify their functions and coverage; IST_SIM, dynamic simulation of IST vectors, simulating test vectors in the IST mode; SIM_LAY_CHIP, post-simulation of full-chip vectors, in the layout stage, gate-level simulation of full-chip test vectors containing accurate timing; ATPG_SIM_LAY, post-simulation of ATPG vectors, layout post-gate-level simulation specifically for ATPG vectors; LBIST_SIM_LAY, post-simulation of LBIST vectors; IST_SIM_LAY, post-simulation of IST vectors.

[0073] The ATPG class represents all work related to the ATPG tool chain, including both vector generation test steps and rule checking and vector simulation test steps, and the manager determines whether the ATPG full process is closed-loop through this class. The ATPG class can include the following test steps: ATPG_DRC_SYN, ATPG DRC check on synthesized netlist, after synthesis, use ATPG tool to check if the netlist meets ATPG rules (e.g. if clock is controllable, if reset is correct, etc.); ATPG_SA, ATPG stuck-at after synthesis, generate stuck-at test vectors on the synthesized netlist; ATPG_TR, ATPG transition after synthesis, generate transition test vectors on the synthesized netlist; ATPG_CCM, ATPG CCM mode after synthesis; ATPG_SIM_SYN, ATPG vector before simulation; ATPG_DRC_LAY, ATPG DRC check on placed and routed netlist; ATPG_SA_LAY, ATPG stuck-at after placement and routing; ATPG_TR_LAY, ATPG transition after placement and routing; ATPG_CCM_LAY, ATPG CCM mode after placement and routing; ATPG_SIM_LAY, ATPG vector after simulation.

[0074] Timing class represents all DFT related timing check work, through this class, the manager judges whether the timing of the chip in the DFT mode meets the requirements. Timing class can include the following test steps: DFT_SDC_GEN, DFT SDC file generation, generate timing constraint files required in DFT test mode (such as merge mode, shift mode, dc mode, ac mode, etc.); TIMING_CHK_merge, timing check in merge mode; TIMING_CHK_shift: timing check in scan shift mode; TIMING_CHK_dc, timing check in DC mode; TIMING_CHK_ac, timing check in AC mode (usually used for TR test); TIMING_CHK_eq, equivalence check, for example, check if the module-level SDC is equivalent to the flattened chip-level SDC.

[0075] Gatesim class represents all post-layout simulation work, which is a subset of Simulation class, and is a more focused management aspect. Through this class, the manager specially judges whether the simulation verification closest to the real chip, i.e. post-simulation, passes. Gatesim class can include the following test steps: SIM_LAY_CHIP, ATPG_SIM_LAY, LBIST_SIM_LAY, IST_SIM_LAY: post-simulation of IST vector.

[0076] The above six categories are state-type categories, used to indicate whether the work is in progress and how the progress is.

[0077] From the above description, it can be known that the mapping relationship of the embodiment of the disclosure supports "many-to-many", and one test task is simultaneously mapped into at least two different predefined categories in a plurality of predefined categories, one predefined category can include a plurality of test steps, and meanwhile, one test step can also belong to a plurality of predefined categories at the same time.

[0078] The many-to-many mapping relationship makes the project user can review the status of the same test task from different dimensions (for example, from the dimension of all simulations or from the dimension of all ATPG related work), and provides a more abundant and more conforming to the engineering logic management demand summary perspective.

[0079] DC Coverage represents the test coverage of stuck-at faults, and the manager does not need to manually search in the log file of the test step, but directly sees the key quality indicator of the project on the summary interface. AC Coverage represents the test coverage of transition faults, and is another key quality indicator similar to DC Coverage.

[0080] The above two categories are numerical categories, used to reflect the quality results of the process, On the user interface, a design project and a milestone version selected by a user are received, and the plurality of test tasks are all test tasks under the design project and the milestone version. For example, Figure 3 As shown in the figure, the user selects the design project as "demo_soc" through the "current chip" drop-down menu on the classification summary interface, and selects the milestone version as "RTL50" through the "milestone" drop-down menu, and then the RTL50 is displayed, which includes design module 1 to design module 6, each design module includes test step a to test step f, and the intersection of the design module and the test step corresponds to a test task, Figure 3 The status of each test task displayed in the figure is "not started". The task status of each test task can also be: passed, failed, completed, executing, etc., and the specific task status can be increased or reduced according to actual needs.

[0081] Specifically, the acquired test tasks are traversed, for example, the traversed test task is: test task 1: {test step is 'DFT_INSERT1'}, according to the mapping relationship between the test step and the predefined category, it is determined that DFT_INSERT1 is mapped to the Insertion category, then the test task 1 is assigned to the Insertion category; the test task 5: {test step is 'ATPG_SIM_SYN'} is traversed, the mapping relationship is queried to determine that the test step ATPG_SIM_SYN is mapped to the Simulation category and the ATPG category, two different predefined categories, then the test task 5 is assigned to the Simulation category and the ATPG category.

[0082] In step S202, based on the task state of each test task included in each predefined category, the category state of the corresponding predefined category is determined.

[0083] A group of test tasks is assigned under each predefined category, and each test task under the group of test tasks is currently in a task state. For each predefined category, one or more preset aggregation logics are applied, and a single, general category state is determined according to the current task state of the plurality of test tasks under the predefined category.

[0084] For example, for the Insertion category, the current task state of all test tasks included in the category is determined, such as [test task 1, task state: passed; test task 1, task state: passed; test task 3, task state: executing], according to the preset aggregation logic, the executing is determined as the category state of the Insertion category.

[0085] Exemplarily, as shown in Figure 4 The category states of each design module under the eight preset categories are summarized, for example, the category state of the Insertion category of the design module 1 is not started, the category state of the ATPG category is failed, the category state of the Gatesim is successful, the category state of the AC Coverage category is 0%, and the like.

[0086] As shown in Figure 3 If you want to know whether all insertion work is successful, you must manually check the task state of all test tasks related to the insertion work, and for a large number of test tasks, this process is time-consuming and laborious.

[0087] In the embodiments of the present disclosure, according to a predefined mapping relationship, original and scattered test tasks and their states are aggregated into classified and macroscopic category states, which can dynamically and accurately reflect the overall progress and health status of key links of a project, and a user can understand the overall progress of a chip project without checking the task states of each test task one by one, thereby solving the problems of low efficiency and errors in manual statistics in the prior art.

[0088] In some embodiments, as shown in Figure 5 The project state aggregation method can be implemented through the following steps S501 to S503.

[0089] In step S501, according to a mapping relationship between test steps and predefined categories, a plurality of test tasks are distributed into a plurality of predefined categories according to corresponding test steps.

[0090] In step S502, when a predefined category is assigned with a task state including a discrete state value, according to a preset state priority, a task state with the highest priority is determined as a category state of the corresponding predefined category.

[0091] The discrete state value is used to represent the execution progress, execution result, etc. of a test task, for example, not started, failed, in progress, completed, passed, etc. This kind of state is suitable for a predefined category that needs to judge the execution progress, and the predefined category corresponding to the discrete state value includes at least one of the following: Insertion class, Pattern class, Simulation class, ATPG class, Timing class, and Gatesim class.

[0092] In some implementable manners, the priority can be defined from high to low as: failed > in progress > passed > completed > not started. The priority is only an example, and the specific priority setting can be changed as needed.

[0093] For example, a task state list of all test tasks under the Insertion class is obtained, and it is checked whether there is a failure. If there is, the scanning is immediately stopped, and the category state of the Insertion class is determined as failed.

[0094] If there is no failure in the list, the list is scanned, and it is checked whether there is in progress. If there is, the scanning is immediately stopped, and the category state of the Insertion class is determined as in progress.

[0095] In this embodiment, by using this priority aggregation logic, for example, “failed” is given priority, it is ensured that any underlying and local test task failure will be immediately transmitted to the macroscopic classified aggregation interface, so that the user can timely understand the key bottleneck of the project, and the risk warning ability and the intuitive management of the project are greatly enhanced.

[0096] In step S503, when the predefined category is assigned with a numerical value task status, the category status corresponding to the predefined category is determined from the log file associated with the test task corresponding to the numerical value task status.

[0097] A numerical value, such as a percentage value, is used to represent the execution quality or performance indicator of a test task, and such a status is suitable for judging the execution quality of a test task. The predefined category corresponding to the numerical value includes a Coverage category, such as DC Coverage for indicating the test coverage of stuck-at faults and AC Coverage for indicating the test coverage of transition faults.

[0098] Specifically, the category status of the DC Coverage category is derived from the log file corresponding to a specific test step, such as the log file generated after the execution of the ATPG_SA step or the ATPG_SA_LAY step. The AC Coverage is similar to the DC Coverage, and is derived from the log file generated after the execution of the ATPG_TR step or the ATPG_TR_LAY step.

[0099] A preset parsing rule, such as a regular expression script or a simple keyword search script, is applied to scan the log file. For example, the parsing rule is configured to search for the keyword “Stuck-at Coverage” in the log file. If there is a line of text in the log file with the content “Report: Stuck-at Coverage: 99.85%”, the parsing script will match this line and extract the percentage value 99.85% from it.

[0100] The embodiment realizes the automatic summarization of project quality indicators (not just progress status) by automatically extracting key performance indicators from log files, which enables the classification summary to simultaneously display the execution progress and execution quality of a project in a unified view, greatly improving the data dimension and decision-making efficiency of project management.

[0101] In some application scenarios with high risk management, such as automotive-grade or aerospace-industry-grade chips, it is not enough to know only whether a category fails or succeeds. Users may also need to know the severity of the category status. Therefore, in some embodiments, as shown in FIG. 6, the project status summarization method can be implemented through the following steps S601 to S605. Figure 6

[0102] In step S601, according to the mapping relationship between the test steps and the predefined categories, a plurality of test tasks are assigned to a plurality of predefined categories according to corresponding test steps. ​

[0103] In step S602, when the predefined category is assigned with the task status including the discrete state value, the highest priority task status according to the preset state priority is determined.

[0104] In step S603, the criticality of the test step corresponding to the high priority task status is determined according to the preset test step criticality.

[0105] Each test step stores the preset test step criticality. The preset test step criticality is, for example, divided into three levels of high, medium and low, and can also be divided into more levels or fewer levels, which is not disclosed and is not limited. For example, the TIMING_CHK_merge step can be set as high criticality because the test step is directly related to whether the chip can work at the target frequency, and the TPG step can be set as low criticality because the test step is usually used for auxiliary testing.

[0106] In step S604, the category state corresponding to the predefined category is determined according to the high priority task status and the criticality of the corresponding test step.

[0107] Under the currently determined predefined category, all test steps with the highest state priority are determined, and the preset test step criticality corresponding to each test step in the all test steps is determined. According to the highest preset test step criticality and the highest state priority, the corresponding category state is determined.

[0108] Exemplarily, high criticality failure. The predefined category is Timing category, and the task status of two test tasks under the category is failure, and the priority of failure is the highest, test task A{Step: TIMING_CHK_merge}, task status: failure, test task A{Step: DFT_SDC_GEN}, task status: failure, the criticality of TIMING_CHK_merge is high, and the criticality of DFT_SDC_GEN is medium. According to the combination of failure and high criticality, the category state of Timing category is determined as serious failure.

[0109] Low criticality failure, and the predefined category is Pattern category. There is only one test task with the task status of failure under the Pattern category, test task C, {Step: TPG}, task status: failure, and the criticality of TPG is low. According to the combination of failure and low criticality, the category state of Pattern category is determined as secondary failure.

[0110] In step S605, when the predefined category is assigned with the task status including the numerical value, the category state corresponding to the predefined category is determined from the log file associated with the test task corresponding to the numerical value task status.

[0111] In the embodiments of the present disclosure, for the application scenarios with higher risk management, the criticality of the test steps is introduced, and more refined category states are provided, which enables the user to immediately distinguish between serious problems and general problems, so as to preferentially invest limited engineering resources into solving more serious problems, and to achieve more efficient and more accurate risk management and resource allocation.

[0112] In some embodiments, as shown in Figure 7 The project state summary method can be implemented through the following steps S701 to S703.

[0113] In step S701, according to the mapping relationship between the test steps and the predefined categories, the plurality of test tasks are distributed into the plurality of predefined categories according to the corresponding test steps.

[0114] In step S702, based on the task state of the test tasks included in each predefined category, the category state of the corresponding predefined category is determined.

[0115] In step S703, when any category state is a preset trigger state, a list of a group of test tasks associated with the preset category is displayed.

[0116] While displaying the category states of all predefined categories in the category summary interface, when it is detected that any category state is a preset trigger state, a list of a group of test tasks associated with the preset category is displayed below the category summary interface (or through a pop-up window, expansion, etc.). The preset trigger state can be configured as needed, for example, the preset trigger state is failure, because failure represents the most attention situation.

[0117] In combination with Figure 4 , the category state of the ATPG category of the design module 1 is failure, as shown in Figure 8 Taking test step b, test step c, test step e and test step f included in the ATPG category as an example, the task states of the test tasks (minimum units) determined by the ATPG category and the test steps are triggered to be displayed.

[0118] In the embodiments of the present disclosure, the automatic drilling function is provided, which seamlessly connects the state summary and the test tasks, and the user does not need to manually switch to locate the failure point after discovering the macro problem, greatly simplifying the operation process.

[0119] In some embodiments, as shown in Figure 9 The project state summary method can be implemented through the following steps S901 to S903.

[0120] In step S901, based on the mapping relationship between test steps and predefined categories, multiple test tasks are assigned to multiple predefined categories according to their corresponding test steps.

[0121] In step S902, the category status of the corresponding predefined category is determined based on the task status of the test tasks included in each predefined category.

[0122] In step S903, the visual identifier corresponding to each category status is displayed according to the correspondence between category status and visual identifier.

[0123] A pre-defined mapping between category states and visual identifiers is established. The visual identifiers are used to visually display the category state on the user interface. For example, the visual identifiers include the background color, border style, icon, or text annotation of the cell corresponding to the category state.

[0124] In some feasible implementations, visual identifiers are color-coded. For example, a failure status corresponds to red, progress to yellow, and success to green. Furthermore, the color coding can be more granular, such as a severe failure status for dark red and a moderate failure status for light red.

[0125] like Figure 10 The image shows an example of visual identifiers for status categories displayed in a categorized summary interface. Horizontal lines indicate gray (not started), vertical lines indicate green (success), diagonal lines indicate light red (moderate failure or coverage below 50%), and grid lines indicate dark red (severe failure). This transforms the high cognitive burden of text parsing into the low visual intuition of color recognition, significantly reducing the complexity of information retrieval.

[0126] The mapping relationship between test steps and predefined categories is predefined and statically stored in the classification rule database. However, in some highly complex or rapidly iterating projects (e.g., as mentioned in the [Technical Disclosure Document], different types of designs, such as automotive-grade or aerospace-grade chips, may require "online testing" steps, while ordinary consumer-grade chips do not), new test steps may frequently occur. In this case, manually updating and maintaining the classification rule database may be lagging and error-prone. In some embodiments, such as Figure 11 As shown, the project status summary method can be implemented through the following steps S1101 and S1102.

[0127] In step S1101, a predefined category is determined based on the test steps corresponding to each test task using a machine learning model.

[0128] The machine learning model is trained by multiple samples, and each sample includes a test step and a corresponding predefined category.

[0129] Specifically, in the training phase, first, multiple training samples are extracted from the historical project task database and the classification rule database; each sample includes the features of the test step as the input X of the machine learning model, and the corresponding predefined category as the label Y of the model; the features of the test step can be a vectorized representation of the test step name, for example, using Word2Vec or BERT model to convert the test step name "ATPG_SIM_LAY" into a feature vector [0.1, 0.5, …]; the model label Y, since a test step can belong to multiple predefined categories, is a multi-label classification problem. By inputting multiple (X, Y) sample pairs into the machine learning model, the machine learning model can be a multi-layer perceptron neural network, a set of support vector machines, gradient boosting decision trees (GBT), or any other suitable model for multi-label classification.

[0130] In the inference phase, for example, a new project introduces a new test step that is not defined in the classification rule database, and the corresponding predefined category of the test step is not found in the classification rule database. Then the features of the test step are extracted and input into the trained machine learning model for inference, and the machine learning model outputs one or more predicted predefined categories.

[0131] In step S1102, based on the task state of the test task included in each predefined category, the category state of the corresponding predefined category is determined.

[0132] The embodiment introduces a machine learning model, no longer relies on a static, manually configured classification rule database, but can learn from historical experience and predict the classification of new test steps, realizes the dynamicization of the mapping relationship, greatly improves the flexibility and scalability, and makes it smoothly adapt to unknown test steps introduced by new projects, new chip types (such as automotive-grade chips), or new EDA tools, so that the classification and aggregation method has self-adaptive ability.

[0133] Figure 12 A structural block diagram of a project state aggregation device according to the present disclosure is shown in FIG. 12. Figure 12 As shown in FIG. 12, the device includes an allocation part 1201 configured to allocate multiple test tasks according to corresponding test steps to multiple predefined categories according to the mapping relationship between the test steps and the predefined categories; and a determination part 1202 configured to determine the category state of the corresponding predefined category based on the task state of the test task included in each predefined category.

[0134] In some embodiments, the determining portion 1202 is configured to, when the predefined category is assigned with the task status comprising the discrete state value, determine, according to the preset state priority, a task state with the highest priority as the category state of the corresponding predefined category.

[0135] In some embodiments, the determining portion 1202 is configured to, when the predefined category is assigned with the task status comprising the discrete state value, determine, according to the preset state priority, a high-priority task state with the highest priority; determine, according to the preset test step criticality, a criticality of the test step corresponding to the high-priority task state; and determine, according to the high-priority task state and the criticality of the test step corresponding to the high-priority task state, the category state of the corresponding predefined category.

[0136] In some embodiments, the predefined category comprises at least one of the following: an insertion category, a vector category, a simulation category, a timing category, a post-layout simulation category, and an automatic test vector generation category.

[0137] In some embodiments, the determining portion 1202 is configured to, when the predefined category is assigned with the task status comprising the numerical value, determine, from a log file associated with the test task corresponding to the numerical value task status, the category state of the corresponding predefined category.

[0138] In some embodiments, the predefined category comprises a coverage category.

[0139] In some embodiments, the project status summary apparatus further comprises a displaying portion configured to, when any category state is a preset triggering state, display a list of a group of test tasks associated with the preset category.

[0140] In some embodiments, the assigning portion 1201 is configured to determine, according to the test step corresponding to each test task, the corresponding predefined category by a machine learning model, and the machine learning model is trained by a plurality of samples, and each sample comprises a test step and a corresponding predefined category.

[0141] In some embodiments, the displaying portion is configured to display the visual identifier corresponding to each category state according to the corresponding relationship between the category state and the visual identifier.

[0142] In the embodiments of the present disclosure, each portion can implement the project status summary method provided by the method embodiments, and achieve the same technical effects. To avoid repetition, details are not described herein.

[0143] The present disclosure also provides an electronic device, which is described with reference to Figure 13 FIG. 1 is a schematic diagram of a hardware structure of an electronic device according to an example embodiment of the present disclosure. The electronic device can be used as the electronic device described in the above embodiments. Figure 1The back-end server 120 in the electronic device or the user terminal 110 is configured to execute the project status summarization method provided in the embodiments of the present application. The electronic device can be a smart phone, a desktop computer, a laptop computer, a server, etc.

[0144] As shown in Figure 13 The electronic device in the embodiments of the present application can include one or more of the following components: a processor 1310 and a memory 1320.

[0145] The processor 1310 connects various parts in the entire electronic device by using various interfaces and lines, executes various functions of the electronic device and processes data by running or executing instructions, programs, code sets or instruction sets stored in the memory 1320, and calling data stored in the memory 1320. Alternatively, the processor 1310 can be implemented in at least one of the hardware forms of digital signal processing, field programmable gate array, programmable logic array. The processor 1310 can integrate one or a combination of central processing units, image processors, neural network processors and baseband chips, etc. Among them, the central processing unit mainly processes operating systems, user interfaces and application programs, etc.; the neural network processor is used to implement artificial intelligence functions, such as executing the machine learning model in Embodiment Eight. It can be understood that the baseband chip can also not be integrated into the processor 1310.

[0146] The memory 1320 can include random access memory and read-only memory. Alternatively, the memory 1320 includes a non-transitory computer readable medium. The memory 1320 can be used to store instructions, programs, codes, code sets or instruction sets. The memory 1320 can include a program storage area and a data storage area, wherein the program storage area can store instructions for implementing operating systems, instructions for implementing the project status summarization method of the embodiments of the present application, etc.; the data storage area can store data created according to the use of the electronic device, such as a task database and a classification rule database.

[0147] In the embodiments of the present application, the memory 1320 stores a computer program or instructions, which, when executed by the processor 1310, causes the electronic device to execute the above-mentioned project status summarization method. For example, when the processor 1310 executes the program or instructions, the following steps are implemented: according to the mapping relationship between the test steps and the predefined categories, the plurality of test tasks are allocated to the plurality of predefined categories; based on the task status of the test tasks included in each predefined category, the category status of the corresponding predefined category is determined.

[0148] Those skilled in the art can understand that the structure of the electronic device shown in the above-mentioned drawings does not constitute a limitation on the electronic device, and the electronic device can include more or fewer components than shown in the drawings, or combine certain components, or different component arrangements.

[0149] This disclosure also provides a computer-readable storage medium storing at least one instruction that is executed by a processor to implement the project status summarization method as described in the above embodiments.

[0150] This disclosure also provides a computer program product including computer instructions stored in a computer-readable storage medium; a processor of an electronic device reads the computer instructions from the computer-readable storage medium and executes the computer instructions, causing the electronic device to perform the project status summarization method described in the above embodiments.

[0151] This disclosure also provides a chip, which includes a processor and a communication interface. The communication interface is coupled to the processor. The processor is used to run programs or instructions to implement the various processes of the above-described project status summary method embodiments and achieve the same technical effect. To avoid repetition, it will not be described again here.

[0152] It should be understood that the chip mentioned in the embodiments of this disclosure may also be referred to as a system-on-a-chip, system chip, chip system, or system-on-a-chip, etc.

[0153] In the several embodiments provided in this disclosure, it should be understood that the disclosed systems, apparatuses, servers, and methods can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative; for instance, the division of units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be an indirect coupling or communication connection between apparatuses or units through some interfaces, and may be electrical, mechanical, or other forms.

[0154] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0155] Furthermore, the functional units in the various embodiments of this disclosure can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit.

[0156] Those skilled in the art should be aware that, in the above one or more examples, the functions described in the present disclosure can be implemented in hardware, software, firmware or any combination thereof. When implemented in software, the functions can be stored in a computer readable medium or transmitted as one or more instructions or code on a computer readable medium. The computer readable medium includes computer storage medium and communication medium, and the communication medium includes any medium that facilitates transfer of a computer program from one place to another.

[0157] It should be noted that the technical solutions described in the present disclosure can be combined arbitrarily without conflict.

[0158] The above is merely specific embodiments of the present disclosure, but the protection scope of the present disclosure is not limited thereto, and any person skilled in the art can easily think of changes or replacements within the technical scope disclosed in the present disclosure, which should be covered within the protection scope of the present disclosure.

Claims

1. A method for summarizing project status, characterized in that, The method for summarizing project status includes: Based on the mapping relationship between test steps and predefined categories, multiple test tasks are assigned to multiple predefined categories according to their corresponding test steps; Based on the task status of the test tasks included in each predefined category, determine the category status of the corresponding predefined category.

2. The project status summary method according to claim 1, characterized in that, The process of determining the category status of a corresponding predefined category based on the task status of the test tasks included in each predefined category includes: When the predefined category is assigned a task state that includes discrete state values, the task state with the highest priority is determined as the category state of the corresponding predefined category according to the preset state priority.

3. The project status summary method according to claim 2, characterized in that, When the predefined category is assigned a task state including discrete state values, the task state with the highest priority is determined as the category state of the corresponding predefined category according to the preset state priority, including: When the predefined category is assigned a task state including discrete state values, the highest priority task state is determined according to the preset state priority. The criticality of the test steps corresponding to the high-priority task states is determined based on the preset criticality of the test steps. Based on the high-priority task status and the criticality of the corresponding test step, the category status of the corresponding predefined category is determined.

4. The project status summary method according to claim 2 or 3, characterized in that, The predefined categories include at least one of the following: insertion class, vector class, simulation class, timing class, post-layout simulation class, and automated test vector generation class.

5. The project status summary method according to claim 1, characterized in that, The process of determining the category status of a corresponding predefined category based on the task status of the test tasks included in each predefined category includes: When the predefined category is assigned a task status that includes a numerical value, the category status of the corresponding predefined category is determined from the log file associated with the test task corresponding to the task status with the numerical value.

6. The project status summary method according to claim 5, characterized in that, The predefined categories include: coverage category.

7. The project status summary method according to claim 1, characterized in that, The method for summarizing project status also includes: When any of the categories is in a preset trigger state, a list of test tasks associated with the preset category is displayed.

8. The project status summary method according to claim 1, characterized in that, The step of assigning multiple test tasks to multiple predefined categories based on the mapping relationship between test steps and predefined categories includes: The machine learning model determines the corresponding predefined category based on the test steps for each test task. The machine learning model is trained on multiple samples, and each sample includes the test steps and the corresponding predefined category.

9. The project status summary method according to claim 1, characterized in that, The method for summarizing project status also includes: Based on the correspondence between category status and visual identifier, display the visual identifier corresponding to each category status.

10. A project status summary device, characterized in that, The project status aggregation device includes: an allocation section and a determination section; The allocation section is configured to allocate multiple test tasks to multiple predefined categories according to the mapping relationship between test steps and predefined categories; The determining part is configured to determine the category status of the corresponding predefined category based on the task status of the test tasks included in each predefined category.

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