10t-sram based in-memory computing cell, circuit, chip

Abstract

The application discloses a 10T-SRAM-based double-path in-memory computing unit, circuit and chip, relates to the technical field of SRAM circuit design, and designs a 10T storage unit, connects inverters on two bit lines to generate two control signals A1-A2, and performs one round of charge-discharge switching when the bit line voltage corresponding to MAC=12 is reached according to the discharge of A1 and A2 on the bit line, and obtains high 2-bit quantization result OUT<5:4> based on the switching round number, thereby increasing the bit lines that can participate in discharge to two, repeatedly using the best discharge interval of linearity to significantly improve the linearity; meanwhile, each bit line only needs to bear a discharge process with a span of 12, can use a larger adjacent MAC voltage difference to reduce the ADC quantization pressure, and can save the high 2-bit analog quantization, reduce the area and power consumption by 75%.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of static random access memory (SRAM) circuit design, and more particularly, to: 1. a dual-path in-memory computing unit based on 10T-SRAM; 2. a computing circuit constructed based on the dual-path in-memory computing unit; and 3. an in-memory computing chip based on the layout of the dual-path in-memory computing unit or the dual-bit line in-memory computing circuit. BACKGROUND

[0002] There are two main implementation methods for SRAM in-memory computing, namely digital method (i.e., digital CIM) and analog method (i.e., analog CIM).

[0003] In general, digital CIM has the advantages of high computing accuracy and strong anti-interference ability, but the multi-cycle operation limits the throughput, and the large-area hardware overhead reduces the density. Analog CIM uses analog computing characteristics and simple logic structure to significantly lead in throughput and area density, but when multiple rows are opened in parallel, it not only leads to poor linearity, but also severely limits the discharge margin, and the quantization accuracy also deteriorates. Moreover, analog CIM needs to use an analog-to-digital converter (i.e., ADC) to quantize and read out the multiply-accumulate result, but a multi-bit analog-to-digital converter will bring about large power consumption and area overhead.

[0004] Specifically, the following in-memory computing scenarios exist: up to 16 rows of multiply-accumulate calculations are required, each row of which performs a multiplication calculation of 2-bit activation value and 1-bit weight. Then, the multiply-accumulate value of 16 rows in full parallel is up to 48, which not only requires a 6-bit analog-to-digital converter to output full precision, resulting in large power consumption and area overhead, but also if the multiply-accumulate result is always reflected on a single bit line, the discharge curve will gradually slow down, leading to poor linearity and severely affecting quantization accuracy, and the voltage difference between adjacent multiply-accumulate values needs to be designed to be very small, which puts high requirements on ADC quantization. SUMMARY

[0005] Therefore, it is necessary to provide a dual-path in-memory computing unit, circuit, and chip based on 10T-SRAM to solve the problems of large power consumption and area overhead, poor quantization accuracy, and high requirements on ADC quantization in the above in-memory computing specific scenarios.

[0006] The present application adopts the following technical solutions:

[0007] In a first aspect, the present application provides a dual-path in-memory computing unit based on 10T-SRAM, comprising: 1 column of 16 10T storage units, 2 inverters INV1~INV2, 1 switching control part Control, and 1 output control part OUT_Con.

[0008] 16 10T memory cells share the same bit line RBL and the same bit line RBLB. The k+1th 10T memory cell includes a 6T memory part 6T-SRAM[k] and a 4T calculation part 4T-Cal[k]. The 6T-SRAM[k] is provided with storage nodes Q[k] and QB[k] for storing a 1-bit weight W[k]. The 4T-Cal[k] is provided with two discharge paths and is switched according to W[k], 2-bit activation value RWL[k], control signal S1 and inverted signal S2. k ∈ [0, 15].

[0009] The input end of INV1 is connected to RBL, and the output end is used for outputting control signal A1. The input end of INV2 is connected to RBLB, and the output end is used for outputting control signal A2. The inversion voltage of INV1 and INV2 is set to the bit line voltage corresponding to MAC=12.

[0010] Control is used to: according to A1 and A2, when the bit line discharge reaches the bit line voltage corresponding to MAC=12, a round of charge and discharge switching is performed, and the high 2-bit quantization result OUT<5:4> is obtained based on the switching round number.

[0011] OUT_Con is used to: connect RBL and RBLB with a 4-bit analog-to-digital converter 4bit_ADC to obtain a low 4-bit quantization result OUT<3:0>. OUT_Con is controlled by S1 and S2. When S1 is 1 and S2 is 0, RBL is connected to 4bit_ADC. When S1 is 0 and S2 is 1, RBLB is connected to 4bit_ADC.

[0012] The implementation of the dual-path in-memory calculation unit based on 10T-SRAM is according to the method or process of the embodiment of the present disclosure.

[0013] In a second aspect, the present disclosure discloses a dual-bit line in-memory calculation circuit based on 10T-SRAM, comprising: a plurality of dual-path in-memory calculation units based on 10T-SRAM as disclosed in the first aspect, arranged in columns.

[0014] The implementation of the dual-bit line in-memory calculation circuit based on 10T-SRAM is according to the method or process of the embodiment of the present disclosure.

[0015] In a third aspect, the present disclosure discloses a dual-bit line in-memory calculation chip based on 10T-SRAM, which adopts the circuit layout of the dual-path in-memory calculation unit based on 10T-SRAM as disclosed in the first aspect, or the circuit layout of the dual-bit line in-memory calculation circuit based on 10T-SRAM as disclosed in the second aspect.

[0016] The implementation of the dual-bit line in-memory calculation chip based on 10T-SRAM is according to the method or process of the embodiment of the present disclosure.

[0017] Compared with the prior art, the present application has the following beneficial effects:

[0018] The present application designs a 10T storage unit for the highest 16 rows of multiplication and accumulation calculation of 2bit activation value and 1bit weight, respectively connects inverters on two bit lines to generate two control signals A1~A2, and performs one round of charge and discharge switching when the bit line voltage corresponding to MAC=12 is reached according to the discharge of A1 and A2, obtains high 2-bit quantization result OUT<5:4> based on the switching round number, thereby increasing the bit line that can participate in discharge to two, and repeatedly using the best discharge interval of linearity to significantly improve the linearity; at the same time, each bit line only needs to withstand a discharge process with a span of 12, can use a larger adjacent MAC voltage difference to reduce the ADC quantization pressure, and can save the module quantization of high 2 bits, reduce the area and power consumption by 75%. BRIEF DESCRIPTION OF DRAWINGS

[0019] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the drawings needed to be used in the embodiments or prior art description will be briefly introduced below. Obviously, the drawings in the following description only constitute some embodiments of the present application, and for those skilled in the art, other drawings can also be obtained without creative labor.

[0020] Figure 1 The circuit diagram of the dual-path in-memory computing unit based on 10T-SRAM for embodiment 1 of the present application is provided.

[0021] Figure 2 The circuit diagram of the 6T storage unit 6T-SRAM[k] in the embodiment is provided. Figure 1

[0022] The signal timing diagram of the 2bit activation value RWL[k] in the embodiment is provided. Figure 3 Figure 1 The circuit diagram of the switching control unit Control in the embodiment is provided.

[0023] Figure 4 Figure 1 The circuit diagram of the output control unit OUT_Con in the embodiment is provided.

[0024] Figure 5 The circuit diagram of the output control unit OUT_Con in the embodiment is provided. Figure 1

[0025] The discharge experiment curve diagram provided for embodiment 1 of the present application is provided. Figure 6 DETAILED DESCRIPTION

[0026] ​​​The technical solutions in the embodiments of the present application will be clearly and completely described with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments of the present application. Based on the embodiments of the present application, all other embodiments obtained by a person of ordinary skill in the art without creative effort belong to the scope of the present application.

[0027] It should be noted that when a component is referred to as being "mounted on" another component, it can be directly on the other component or there can be a middle component. When a component is referred to as being "disposed on" another component, it can be directly disposed on the other component or there can be a middle component. When a component is referred to as being "fixed on" another component, it can be directly fixed on the other component or there can be a middle component.

[0028] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used in the description herein is for describing particular embodiments only and is not intended to be limiting of the application. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. The terms "comprises", "comprising", "includes", "including" and "has" are inclusive and therefore specify the presence of stated features, integers, steps, operations, elements, or components but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, or groups thereof.

[0029] Embodiment 1

[0030] Embodiment 1 provides a 10T-SRAM-based dual-path in-memory computing unit, which is designed to implement up to 16 rows of multiply-accumulate calculations, each row performing 2-bit activation value and 1-bit weight multiplication calculations.

[0031] First of all, since there are four cases of 00, 01, 10, and 11 for 2-bit activation values and two cases of 1 and 0 for 1-bit weights, when performing up to 16 rows of parallel calculations, there are up to 48 results of multiply-accumulate values (MAC), i.e., MAC ∈ [1, 48].

[0032] Through experiments, it is known that when a single bit line is discharged, the discharge linearity corresponding to the process of MAC from 1 to 24 is the best, but the discharge process from 24 to 48 is gradually slowed down, resulting in poor linearity. However, the difference between adjacent MAC values is still small when a single bit line bears a span of 24 discharge processes, and the quantization requirement for the ADC is high. Therefore, based on the experimental results, the 10T-SRAM-based dual-path in-memory computing unit selects to switch the bit line charge and discharge, so that the number of bit lines that can participate in the discharge is increased to two, the best discharge interval is reused to significantly improve the linearity, and each bit line only needs to bear a span of 12 discharge processes, and the high 2-bit modulus quantization is saved.

[0033] Referring to Figure 1, the 10T-SRAM-based dual-path in-memory computing unit can be divided into a storage and calculation unit SRAM_Cal, an inverting switch unit SW, a switch control unit Control, and an output control unit OUT_Con according to functional regions.

[0034] The following will be introduced one by one:

[0035] 1. SRAM_Cal is used for reading 16 1-bit weights and multiplying in single-row calculation or multiplying and accumulating in parallel calculation in combination with 2-bit activation values.

[0036] Referring to Figure 1 , the SRAM_Cal includes 16 10T storage units in one column, which share the same bit line BL and the same bit line BLB.

[0037] The structure of each 10T storage unit is the same. Then, taking the k+1th 10T storage unit as an example, it includes a 6T storage unit 6T-SRAM[k] and a 4T calculation unit 4T-Cal[k]; k ∈ [0, 15].

[0038] Referring to Figure 2 , the 6T-SRAM[k] is a conventional 6T storage unit, which includes two PMOS transistors P1[k] and P2[k] and four NMOS transistors N1[k] to N4[k].

[0039] Specifically, P1[k] and N1[k] form an inverter, P2[k] and N2[k] form another inverter, and the two inverters are cross-coupled to form storage nodes Q[k] and QB[k]; QB[k] is connected to the bit line RBLB through N3, and Q[k] is connected to the bit line RBL through N4[k]; the gates of N3[k] and N4[k] are connected to the word line WL[k]; the sources of P1[k] and P2[k] are connected to the power supply VDD; and the sources of N1[k] and N2[k] are connected to GND.

[0040] That is, the 6T-SRAM[k] is provided with storage nodes Q[k] and QB[k] for storing a 1-bit weight W[k]. Specifically, Q[k]=1 and QB[k]=0, then W[k]=1; Q[k]=0 and QB[k]=1, then W[k]=0.

[0041] Wherein, when WL[k]=1, the 6T-SRAM[k] reads and writes W[k]; when WL[k]=0, the 6T-SRAM[k] maintains W[k]. The specific read, write and maintenance refer to the operation of the conventional 6T storage unit, which will not be described here.

[0042] Referring to Figure 1, 4T-Cal[k] includes: 4 NMOS tubes N5[k]~N8[k].

[0043] Specifically, the gate of N8[k] is connected with Q[k], the drain is connected with the source of N7[k], and the source is connected with GND; the gate of N7[k] is connected with 2bit activation value RWL[k], the drain is connected with the source of N5[k] and the source of N6[k]; the gate of N5[k] is connected with inverse signal S2, and the drain is connected with RBLB; the gate of N6[k] is connected with control signal S1, and the drain is connected with RBL.

[0044] N8[k], N7[k], N5[k] constitute a discharge path of RBLB to GND; N8[k], N7[k], N6[k] constitute a discharge path of BLB to GND.

[0045] Wherein, when RWL[k]=1, W[k]=1, S1=1, N7[k], N8[k], N5[k] are all turned on, thereby realizing the discharge of RBL to GND; when RWLB[k]=1, W[k]=1, S2=1, N7[k], N8[k], N5[k] are all turned on, thereby realizing the discharge of RBLB to GND.

[0046] That is to say, 4T-Cal[k] is provided with 2 discharge paths, and is switched according to W[k], RWL[k], S1 and S2, thereby making the corresponding bit line discharge for a corresponding time length to represent the multiplication result of 2bit activation value and 1bit weight.

[0047] It should be noted that since the multiplication is represented based on the discharge of the bit line, it is recommended to use pulse number coding for RWL[k] to form an input signal, so as to control the conduction time of N7[k].

[0048] Specifically, referring to Figure 3 , when RWL[k] is 00, it is a low flat signal without pulse;

[0049] When RWL[k] is 01, it is a square wave signal containing 1 pulse;

[0050] When RWL[k] is 10, it is a square wave signal containing 2 pulses;

[0051] When RWL[k] is 11, it is a square wave signal containing 3 pulses;

[0052] Wherein, the width of the pulse is t.

[0053] 2, SW is used to generate control signal A1 according to RBL voltage and generate control signal A2 according to RBLB voltage.

[0054] Referring to Figure 1SW includes: 2 inverters INV1~INV2.

[0055] Specifically, the input terminal of INV1 is connected to RBL, and the output terminal is used to output control signal A1; the input terminal of INV2 is connected to RBLB, and the output terminal is used to output control signal A2.

[0056] It is important to note that since subsequent bit line charging and discharging switching will be involved, the switching voltages of INV1 and INV2 are both set to the bit line voltage corresponding to the accumulated value MAC=12. This not only ensures that the bit line discharge is always within the range of best linearity, but also ensures that each bit line only needs to withstand a discharge process spanning 12.

[0057] 3. Control is used to: perform a charge / discharge switch when the bit line discharge of A1 and A2 reaches the bit line voltage corresponding to MAC=12, and obtain the high 2-bit quantization result OUT<5:4> based on the number of switching rounds.

[0058] See Figure 4 The Control unit includes: one OR gate, one D flip-flop (DFF), one counter, and one charger.

[0059] In other words, Control uses OR to perform an OR operation on A1 and A2 to form CLK to control the operation of DFF and Counter, and controls S1 and S2 to switch between charging and discharging when necessary.

[0060] Specifically, input one of OR is connected to the output of INV1, input two is connected to the output of INV2, and the output is used to output the clock signal CLK; the clock control terminal of DFF is connected to CLK, the D input is connected to S1, the Q output is used to output S2, and the Q NOT output is used to output S1; the control terminal of Counter is connected to CLK and is used to record the number of switching rounds; Charger is used to charge the corresponding bit line through the power supply VDD when a charge / discharge switch occurs.

[0061] Among them, Charger can adopt such as Figure 4 The PMOS transistor design includes two PMOS transistors, PM1 and PM2. PM1's gate is connected to S1, its drain to RBL, and its source to VDD. PM2's gate is connected to S2, its drain to RBLB, and its source to VDD. Alternatively, an NMOS transistor design can be used for the Charger, but S1 and S2 would need to be interchanged.

[0062] 4. OUT_Con is used to connect RBL, RBLB to a 4-bit analog-to-digital converter (4bit_ADC) to obtain the lower 4-bit quantization result OUT<3:0>.

[0063] OUT_Con switches the connection object according to S1 and S2 to correspond to low 4-bit quantization. OUT_Con is controlled by S1 and S2; when S1 is 1 and S2 is 0, RBL is connected with 4bit_ADC; when S1 is 0 and S2 is 1, RBLB is connected with 4bit_ADC.

[0064] Referring to Figure 5 OUT_Con can adopt a transmission gate design, which includes: 2 transmission gates Gate1~Gate2. The C control end of Gate1 is connected with S1, the C reverse control end is connected with S2, the input end is connected with RBL, and the output end is connected with 4bit_ADC; the C control end of Gate2 is connected with S2, the C reverse control end is connected with S1, the input end is connected with RBLB, and the output end is connected with 4bit_ADC.

[0065] Specifically, Gate1 includes: 1 PMOS tube PM1, 1 NMOS tube NM1; the gate of PM1 as the C reverse control end; the gate of NM1 as the C control end; the source of PM1 and the drain of NM1 are connected together and serve as the input end; the drain of PM1 and the source of NM1 are connected together and serve as the output end.

[0066] Gate2 includes: 2 PMOS tubes PM2, 2 NMOS tubes NM2; the gate of PM2 as the C reverse control end; the gate of NM2 as the C control end; the source of PM2 and the drain of NM2 are connected together and serve as the input end; the drain of PM2 and the source of NM2 are connected together and serve as the output end.

[0067] Of course, OUT_Con can also adopt a strobe or other switch design, as long as it meets the above on-off logic.

[0068] In general, the process of calculation and quantization of the dual-path in-memory computing unit based on the above structure is as follows:

[0069] RBL and RBLB are initially pre-charged to VDD, S1 is initialized to 1 and S2 is initialized to 0;

[0070] According to the actual needs, a number of 10T memory cells participating in the calculation are selected, and the corresponding 2-bit activation value is input in the form of pulse number coding to make RBL discharge first. In order to facilitate understanding, take the k+1th 10T memory cell participating in multiplication calculation as an example: S1 is 1 at this time, S2 is 0 at this time, N6[k] is on, N5[k] is off; N7[k] is on (when RWL[k]=1), N8[k] is on (when W[k]=1), RBL discharges first, and RBLB does not discharge.

[0071] The several 10T memory cells participating in the calculation make RBL discharge to GND, and the voltage of RBL is constantly reduced. Since RBL is discharged from VDD, the discharge process is in the best linear region.

[0072] If the multiplication-accumulation value MAC does not reach 12, the multiplication-accumulation result is all reflected on RBL, and it also indicates that the high 2-bit quantization result OUT<5:4> = 00 (because the 5th and 6th bits of the binary number corresponding to MAC = [1, 12] are both 0), at this time, INV1 is not flipped (because the voltage of RBL is lower than the flip voltage of INV1), S1 and S2 remain unchanged, CLK does not generate a rising edge, and the Counter count remains 00. 4bit_ADC connects RBL and quantizes the voltage of RBL to obtain the low 4-bit quantization result OUT<3:0>. Then, OUT<5:4> = 00 and OUT<3:0> constitute the 6-bit quantization result OUT<5:0>. It can be seen that, in this case, the Counter count and OUT<5:4> are consistent.

[0073] When MAC exceeds 12, then INV1 flips (because the voltage of RBL reaches the flip voltage of INV1), A1 and A2 form the rising edge of CLK through OR operation, DFF works and makes S1 switch to 0 and S2 switch to 1, the first round of charge-discharge switching occurs - RBL stops discharging and connects VDD for charging, and RBLB immediately discharges; the Counter count is incremented from 00 to 01. For ease of understanding, still take the above k+1th 10T memory cell participating in multiplication calculation as an example: since S1 switches to 0 and S2 switches to 1, N6[k] is off and N5[k] is on; N7[k] is on (when RWL[k] = 1), and N8[k] is on (when W[k] = 1), RBL stops discharging and connects VDD for charging through PM1, and RBLB immediately discharges.

[0074] The several 10T memory cells participating in the calculation make RBLB discharge to GND, and the voltage of RBLB is constantly reduced. Similarly, since RBLB is also discharged from VDD, the discharge process is also in the best linear region. Since the first round of charge-discharge switching occurs, it indicates that the high 2-bit of the binary number corresponding to MAC is 01, that is, the high 2-bit quantization result OUT<5:4> = 01. And S1 switches to 0 and S2 switches to 1, 4bit_ADC connects RBLB and quantizes the voltage of RBLB to obtain the low 5-bit quantization result OUT<3:0>. Then, OUT<5:4> = 01 and OUT<3:0> constitute the 6-bit quantization result OUT<5:0>. It can be seen that, in this case, the Counter count and OUT<5:4> are also consistent.

[0075] When MAC exceeds 24, INV2 flips (because the RBLB voltage reaches the flip voltage of INV2). A1 and A2 form the rising edge of CLK through the OR operation, DFF starts working and switches S1 to 1 and S2 to 0, causing the second round of charge / discharge switching—RBLB stops discharging and connects to VDD for charging, and RBL then starts discharging; the Counter count is incremented by 1, changing from 01 to 10. For ease of understanding, let's take the (k+1)th 10T memory cell participating in the multiplication calculation as an example: Since S1 switches to 1 and S2 switches to 0, N5[k] is off and N6[k] is on; N7[k] is on (when RWL[k]=1), N8[k] is on (when W[k]=1), RBLB stops discharging and connects to VDD through PM2 for charging, and RBL then starts discharging.

[0076] Several 10T memory cells involved in the calculation cause RBL to discharge to GND, and the voltage of RBL continuously decreases. Similarly, since RBL still discharges from VDD, the discharge process is still in the region with the best linearity. Due to the occurrence of the second round of charge-discharge switching, it means that the high 2 bits of the binary number corresponding to MAC must be 10, that is, the high 2-bit quantization result OUT<5:4>=10. When S1 switches to 1 and S2 switches to 0, the 4-bit ADC is connected to RBL and the voltage of RBL is quantized to obtain the low 5-bit quantization result OUT<3:0>. Therefore, OUT<5:4>=10 and OUT<3:0> form the 6-bit quantization result OUT<5:0>. It can be seen that in this case, the Counter count is still consistent with OUT<5:4>.

[0077] When MAC exceeds 36, INV1 flips (because the RBL voltage reaches the flip voltage of INV1). A1 and A2 form the rising edge of CLK through the OR operation, DFF starts working, and S1 switches to 0 and S2 switches to 1, causing the third round of charge-discharge switching—RBL stops discharging and connects to VDD for charging, and RBLB then discharges; the Counter count is incremented by 1, changing from 10 to 11. For ease of understanding, let's take the (k+1)th 10T memory cell participating in the multiplication calculation as an example: Since S1 switches to 0 and S2 switches to 1, N6[k] is off and N5[k] is on; N7[k] is on (when RWL[k]=1), N8[k] is on (when W[k]=1), RBL stops discharging and connects to VDD through PM1 for charging, and RBLB then discharges.

[0078] The several 10T memory cells participating in the calculation discharge the RBLB to the GND, and the voltage of the RBLB is constantly reduced. Similarly, since the RBLB is still discharged from the VDD, the discharge process is still in the region with the best linearity. Since the third round of charge-discharge switching occurs, it is certain that the high 2 bits of the binary number corresponding to the MAC are 11, i.e., the high 2-bit quantization result OUT<5:4> = 11. S1 is switched to 0, S2 is switched to 1, 4bit_ADC is connected to the RBLB, and the voltage of the RBLB is quantized to obtain the low 5-bit quantization result OUT<3:0>. Then, OUT<5:4> = 11, OUT<3:0> form a 6-bit quantization result OUT<5:0>. It can be seen that, in this case, the Counter count and OUT<5:4> are still consistent.

[0079] That is, the Counter count is the switching round of charge-discharge, and the value of OUT<5:4> can be determined according to the Counter count. Since the high 2 bits do not need to be quantized by modulo, the 10T-SRAM-based dual-path in-memory computing unit only needs 4-bit ADC to complete the quantization, reducing the area and power consumption by 75%; moreover, as mentioned above, each bit line only needs to withstand a discharge process with a span of 12, and a larger adjacent MAC voltage difference can be used to reduce the ADC quantization pressure.

[0080] In order to quantify the effect of the 10T-SRAM-based dual-path in-memory computing unit, the embodiment 1 also performs experimental simulation, and compares the traditional unit line discharge with the above-mentioned double-bit line discharge. The results are shown in Figure 6 .

[0081] Referring to Figure 6 , which shows the discharge curve difference between the unit line discharge and the double-bit line discharge. It should be noted that the double-bit line discharge adopts simultaneous input of every 4 2-bit activation values.

[0082] As can be seen from Figure 6 , when the RBL is discharged all the time, the voltage difference of adjacent MAC values gradually decreases from the initial 145mV to 22mV in the later stage, and is still decreasing, so that it is difficult to distinguish at last, indicating that the linearity will become very poor and may not be able to meet the discharge process with a span of 48. When the double-bit line discharge is used, the RBL and the RRBL discharge alternately, and the voltage difference of adjacent MAC values remains at about 145mV during discharge, which not only significantly improves the linearity, but also uses a larger adjacent MAC voltage difference to reduce the ADC quantization pressure.

[0083] Embodiment 2

[0084] In view of the array application of SRAM, the embodiment 2 provides a 10T-SRAM-based dual-bit line in-memory computing circuit, which comprises a plurality of 10T-SRAM-based dual-path in-memory computing units as disclosed in the embodiment 1, which are arranged in columns. Specifically, the 10T memory units in the same row share the same word line WL, and specifically, the 10T memory units in the k+1 row share WL[k].

[0085] Of course, these 10T-SRAM-based dual-path in-memory computing units can also share the same 4bit_ADC. However, in order to ensure the normal quantization of the 4bit_ADC, a gate or switch needs to be additionally arranged between the dual-path in-memory computing unit and the 4bit_ADC to control the input of the multiplication and accumulation result of only one column into the 4bit_ADC.

[0086] Embodiment 3

[0087] The embodiment 3 synchronously discloses a 10T-SRAM-based dual-bit line in-memory computing chip, which adopts the circuit layout of the 10T-SRAM-based dual-path in-memory computing unit disclosed in the embodiment 1 or the circuit layout of the 10T-SRAM-based dual-bit line in-memory computing unit disclosed in the embodiment 1. The chip is packaged in a mode, which is more conducive to the popularization and application of the above-mentioned circuit.

[0088] Of course, the above-mentioned 10T-SRAM-based dual-path in-memory computing unit and circuit can also be designed into a module. When designed into a module, the corresponding pin can be designed into a terminal.

[0089] The technical features of the above-mentioned embodiments can be combined in any manner. In order to make the description concise, all possible combinations of the technical features in the above-mentioned embodiments are not described, however, as long as the combination of the technical features does not exist contradictory, it should be considered as the scope of the present disclosure.

[0090] The above-mentioned embodiments only express several embodiments of the present disclosure, which are described in a more specific and detailed manner. However, it should not be understood as a limitation to the scope of the patent. It should be pointed out that for ordinary skilled in the art, without departing from the concept of the present disclosure, a number of modifications and improvements can be made, which are all within the protection scope of the present disclosure. Therefore, the protection scope of the present patent should be subject to the appended claims.

Claims

1. A dual-channel in-memory computing unit based on 10T-SRAM, characterized in that, It includes: One column contains 16 10T memory cells, which share the same bit line RBL and the same bit line RBLB; The (k+1)th 10T memory cell includes: a 6T storage unit (6T-SRAM[k]) and a 4T computing unit (4T-Cal[k]); the 6T-SRAM[k] is equipped with storage nodes Q[k] and QB[k], which are used to store 1-bit weight W[k]; the 4T-Cal[k] is equipped with 2 discharge paths, which are switched according to W[k], 2-bit activation value RWL[k], control signal S1, and inverting signal S2; k∈[0,15]; Two inverters, INV1 and INV2; the input of INV1 is connected to RBL, and the output is used to output control signal A1; the input of INV2 is connected to RBLB, and the output is used to output control signal A2; the flip voltage of both INV1 and INV2 is set to the bit line voltage corresponding to the accumulated value MAC=12. One switching control unit, Control, is used to: perform a charge / discharge switching cycle when the bit line discharge of A1 and A2 reaches the bit line voltage corresponding to MAC=12, and obtain the high 2-bit quantization result OUT<5:4> based on the number of switching cycles; and One output control unit OUT_Con is used to: connect RBL, RBLB and 4-bit analog-to-digital converter (4bit_ADC) to obtain the lower 4-bit quantization result OUT<3:0>; OUT_Con is controlled by S1 and S2; when S1 is 1 and S2 is 0, RBL is connected to 4bit_ADC; when S1 is 0 and S2 is 1, RBLB is connected to 4bit_ADC.

2. The dual-channel in-memory computing unit based on 10T-SRAM according to claim 1, characterized in that, The 6T-SRAM[k] includes: 2 PMOS transistors P1[k]~P2[k] and 4 NMOS transistors N1[k]~N4[k]; P1[k] and N1[k] form one inverter, and P2[k] and N2[k] form another inverter. The two inverters are cross-coupled to form memory nodes Q[k] and QB[k]. QB[k] is connected to bit line RBLB through N3, and Q[k] is connected to bit line RBL through N4[k]. The gates of N3[k] and N4[k] are connected to word line WL[k]. The sources of P1[k] and P2[k] are connected to power supply VDD. The sources of N1[k] and N2[k] are connected to GND. When WL[k]=1, 6T-SRAM[k] performs read and write operations on W[k]; when WL[k]=0, 6T-SRAM[k] holds W[k].

3. The dual-channel in-memory computing unit based on 10T-SRAM according to claim 1, characterized in that, When RWL[k] is 00, it is a low-level signal without pulses; When RWL[k] is 0 or 1, it is a square wave signal containing one pulse; When RWL[k] is 10, it is a square wave signal containing 2 pulses; When RWL[k] is 11, it is a square wave signal containing 3 pulses; The pulse width is t.

4. The dual-channel in-memory computing unit based on 10T-SRAM according to claim 3, characterized in that, 4T-Cal[k] includes: 4 NMOS transistors N5[k]~N8[k]; The gate of N8[k] is connected to Q[k], and the drain is connected to the source of N7[k]. The source is grounded to GND. The gate of N7[k] is connected to RWL[k], and the drain is connected to the source of N5[k] and the source of N6[k]. The gate of N5[k] is connected to S2, and the drain is connected to RBLB. The gate of N6[k] is connected to S1, and the drain is connected to RBL. N8[k], N7[k], and N5[k] constitute the discharge path of RBLB to GND; N8[k], N7[k], and N6[k] constitute the discharge path of BLB to GND.

5. The dual-channel in-memory computing unit based on 10T-SRAM according to claim 1, characterized in that, The control unit includes: one OR gate, one D flip-flop (DFF), one counter, and one charger. The OR input terminal 1 is connected to the output terminal of INV1, and the input terminal 2 is connected to the output terminal of INV2. The output terminal is used to output the clock signal CLK. The clock control terminal of DFF is connected to CLK, the D input terminal is connected to S1, the Q output terminal is used to output S2, and the Q NOT output terminal is used to output S1. The control terminal of Counter is connected to CLK and is used to record the number of switching rounds. Charger is used to charge the corresponding bit line through the power supply VDD when a charge / discharge switch occurs. Charger is controlled by S1 and S2. When S1 is 1 and S2 is 0, RBLB is connected to VDD. When S1 is 0 and S2 is 1, RBL is connected to VDD.

6. The dual-channel in-memory computing unit based on 10T-SRAM according to claim 5, characterized in that, The charger includes two PMOS transistors, PM1 and PM2. The gate of PM1 is connected to S1, the drain is connected to RBL, and the source is connected to VDD; the gate of PM2 is connected to S2, the drain is connected to RBLB, and the source is connected to VDD.

7. The dual-channel in-memory computing unit based on 10T-SRAM according to claim 1, characterized in that, OUT_Con includes: two transmission gates, Gate1 and Gate2; The C control terminal of Gate1 is connected to S1, the C inverse control terminal is connected to S2, the input terminal is connected to RBL, and the output terminal is connected to 4-bit ADC. The C control terminal of Gate2 is connected to S2, the C inverse control terminal is connected to S1, the input terminal is connected to RBLB, and the output terminal is connected to the 4-bit ADC.

8. The dual-channel in-memory computing unit based on 10T-SRAM according to claim 1, characterized in that, When performing multiplication and accumulation calculations, S1 is initially set to 1, S2 is initially set to 0, and RBL discharges first; If MAC does not reach 12, the multiplication and accumulation results are all reflected on RBL, no charge / discharge switching occurs, OUT<5:4>=00, the 3-bit ADC quantizes the voltage of RBL to obtain OUT<3:0>, OUT<5:4>=00 and OUT<3:0> form a 6-bit quantization result OUT<5:0>; When MAC exceeds 12, the first round of charge-discharge switching occurs. RBL stops discharging and connects VDD for charging. RBLB then discharges. OUT<5:4>=01. The 3-bit ADC quantizes the voltage of RBLB to obtain OUT<3:0>. OUT<5:4>=01 and OUT<3:0> form a 6-bit quantization result OUT<5:0>. When MAC exceeds 24, the second round of charge / discharge switching occurs. RBLB stops discharging and connects VDD for charging. RBL then discharges. OUT<5:4>=10. The 3-bit ADC quantizes the voltage of RBLB to obtain OUT<3:0>. OUT<5:4>=10 and OUT<3:0> form a 6-bit quantization result OUT<5:0>. When MAC exceeds 36, the third round of charge-discharge switching occurs. RBL stops discharging and connects VDD for charging. RBLB then discharges. OUT<5:4>=11. The 3-bit ADC quantizes the voltage of RBLB to obtain OUT<3:0>. OUT<5:4>=11 and OUT<3:0> form the 6-bit quantization result OUT<5:0>.

9. A dual-bit in-memory computing circuit based on 10T-SRAM, characterized in that, It includes: Several dual-channel in-memory computing units based on 10T-SRAM as described in any one of claims 1-8 are arranged in columns.

10. A dual-bit in-memory computing chip based on 10T-SRAM, characterized in that, The circuit layout of the dual-channel in-memory computing unit based on 10T-SRAM as described in any one of claims 1-8, or the circuit layout of the dual-bit-line in-memory computing circuit based on 10T-SRAM as described in claim 9, is adopted.

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