Iread measurement method

Abstract

The invention discloses an Iread measurement method, which is used for Two port SRAM 8T, and comprises the following steps of: providing a 4 + 4 array design scheme of Two port SRAM Iread; the RPWL, the RPBL and the SNL of the four SRAM Bit cells are connected to the PAD1, the PAD1 is connected with the Vdd, the PW and the VSS are connected to the PAD2 and the GND, and RPIread is measured; wL, BL and SNR of the four SRAM Bit cells are connected to PAD3 and Vdd, PW and VSS are connected to PAD2 and GND, and 6TIread is measured. According to the invention, the number of measured SRAM Bit cells can be increased, the number of Pads required by measurement can be reduced, and the utilization rate of TSK can be improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of integrated circuits, and in particular to a method for measuring Iread. BACKGROUND

[0002] Two Port SRAM (8T) is a type of static random access memory (SRAM) that has two independent ports, each of which can perform read and write operations independently. The memory cell of 8T SRAM is composed of 8 transistors, usually including two cross-coupled inverters (composed of 4 transistors), and 4 additional transistors for controlling read and write operations. This structure separates the read and write paths, avoiding the problem of read disturb, thereby improving the stability and read speed of the memory cell.

[0003] Iread refers to the current flowing through the read path of the memory cell during the read operation. This current is crucial for fast data reading, as it directly affects the read time. By optimizing Iread, faster read speed and higher memory cell stability can be achieved, thereby improving the overall performance of Two Port SRAM (8T). Therefore, accurate measurement of Iread is of great significance to improving the overall performance of Two Port SRAM (8T).

[0004] The existing method for measuring Two port SRAM (8T) Iread has some technical limitations. Specifically, the existing measurement method requires multiple PADs to complete the measurement, and the connection method of these PADs is as follows:

[0005] 1. VDD and NW are connected to Vvdd [0.9] V.

[0006] 2. BL is connected to Vbl [0.9] V.

[0007] 3. WL is connected to Vwl [0.9] V.

[0008] 4. SNR is connected to Vgate [0.9] V.

[0009] 5. VSS and PW are connected to GND.

[0010] When measuring IBL, RPBL is connected to Vbl [0.9] V, RPWL is connected to Vwl [0.9] V, SNR is connected to Vgate [0.9] V, and VSS and PW are connected to GND.

[0011] When measuring IRPBL, RPBL is connected to Vbl [0.9] V, RPWL is connected to Vwl [0.9] V, SNR is connected to Vgate [0.9] V, and VSS and PW are connected to GND.

[0012] The existing measurement method has the following technical problems:

[0013] 1) Large number of PADs: multiple PADs are required to complete the measurement, which increases the complexity and cost of measurement.

[0014] 2) Low measurement efficiency: only one SRAM cell can be measured at a time, the accuracy of the measurement result is limited, and the measurement efficiency is low. SUMMARY

[0015] A series of simplified concepts are introduced in the summary section, which are simplifications of existing technologies in the art, which will be described in detail in the specific embodiments section. The summary section of the present application does not mean to attempt to limit the key features and necessary technical features of the claimed technical solutions, nor does it attempt to determine the protection scope of the claimed technical solutions.

[0016] The technical problem to be solved by the present application is to provide an Iread measurement method that can simultaneously measure multiple SRAM Bitcells, reduce the number of PADs required for measurement, and reduce the cost of measurement.

[0017] To solve the above technical problems, the Iread measurement method provided by the present application is used for Two port SRAM 8T, and includes the following steps:

[0018] A 4+4 array design scheme of Two port SRAM Iread is provided;

[0019] The RPWL, RPBL, and SNL of the four SRAM Bitcells are connected to PAD1, PAD1 is connected to Vdd, PW and VSS are connected to PAD2 connected to GND, and RP_Iread is measured;

[0020] The WL, BL, and SNR of the four SRAM Bitcells are connected to PAD3 connected to Vdd, PW and VSS are connected to PAD2 connected to GND, and 6T_Iread is measured.

[0021] Optionally, the Iread measurement method is further improved, which can be applied to Two port SRAM 8T with a process node less than or equal to 28nm.

[0022] Optionally, the Iread measurement method is further improved, and further includes: recording the Iread measurement result, and evaluating the performance and reliability of the SRAM Bitcell through data analysis.

[0023] Optionally, the Iread measurement method is further improved, and the data analysis is performed by at least one of the following methods: mean method, standard deviation method, median method, histogram method, and linear regression method.

[0024] Optionally, the Iread measurement method is further improved, and the measurement of all Twoport SRAM 8T in the same batch is performed under the same measurement environment condition.

[0025] Optionally, the Iread measurement method is further improved, and the measurement environment condition includes temperature and humidity.

[0026] The present application measures RP_Iread by connecting the RPWL, RPBL, and SNL of four SRAM Bitcells to PAD1, connecting PAD1 to Vdd, connecting PW and VSS to PAD2, and connecting PAD2 to GND, and measures 6T_Iread by connecting the WL, BL, and SNR of four SRAM Bitcells to PAD3, connecting PAD3 to Vdd, connecting PW and VSS to PAD2, and connecting PAD2 to GND. The 4+4 array design scheme can simultaneously measure multiple SRAM Bitcells, reduces the number of pads required for measurement, and improves the measurement efficiency and accuracy.

[0027] The present application can at least achieve the following technical effects:

[0028] 1. The present application can increase the number of measured SRAM Bitcells: through the 4+4 array design scheme, multiple SRAM Bitcells can be measured simultaneously, reducing the limitations of single SRAM cell measurement, increasing the number of measured SRAM Bitcells to 4+4, and thus improving the representativeness and accuracy of the measurement results.

[0029] 2. The present application can reduce the number of pads required for measurement: through the optimized connection mode, the RPWL, RPBL, SNL, and WL, BL, and SNR of multiple SRAM Bitcells are connected to different PAD, reducing the number of pads required for measurement to three, and improving the utilization rate of TSK. BRIEF DESCRIPTION OF DRAWINGS

[0030] The drawings accompanying the present invention are intended to illustrate the general characteristics of the methods, structures and / or materials used in certain example embodiments according to the present invention and to supplement the description in the present specification. However, the present drawings are diagrammatic and as such are not intended to precisely illustrate the precise structural or performance characteristics of any given embodiment, and the present drawings should not be interpreted as limiting or restricting the scope of the numerical or property values encompassed by the example embodiments according to the present invention. The present invention will be further described in connection with the drawings and the detailed description below, wherein:

[0031] Figure 1 Prior art measurement schematic Figure Two .

[0032] Figure 2 Prior art measurement schematic Figure One .

[0033] Figure 3 Schematic diagram of the structure of the present invention. DETAILED DESCRIPTION

[0034] The embodiments of the present invention will be described in detail with specific reference felt to the drawings, and the advantages of the present invention will be apparent from the following description and attached drawings. Other advantages of the present invention will be realized and attained by the embodiments of the present invention, especially with reference to the description and drawings. The present invention can be embodied in many different forms and should not be construed as being limited to the specific embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the inventive concept to those skilled in the art.

[0035] First embodiment;

[0036] Referring to Figure 1 The present invention provides an Iread measurement method for a Two port SRAM 8T, comprising the following steps:

[0037] A 4+4 array design scheme for a Two port SRAM Iread is provided;

[0038] The RPWL, RPBL, SNL of 4 SRAM Bitcells are connected to PAD1, PAD1 is connected to Vdd, PW and VSS are connected to PAD2, PAD2 is connected to GND, and RP_Iread is measured;

[0039] WL, BL, SNR of 4 SRAM Bitcells are connected to PAD3 to Vdd, PW and VSS are connected to PAD2 to GND, 6T_Iread is measured.

[0040] Alternatively, the above embodiments can be applied to Two port SRAM 8T with process nodes less than or equal to 28nm.

[0041] Second embodiment

[0042] With continued reference to Figure 1 As shown, the present application provides a method for Iread measurement of Two port SRAM 8T, comprising the following steps:

[0043] A 4+4 array design of Two port SRAM Iread is provided.

[0044] RPWL, RPBL, SNL of 4 SRAM Bitcells are connected to PAD1, PAD1 is connected to Vdd, PW and VSS are connected to PAD2 to GND, RP_Iread is measured.

[0045] WL, BL, SNR of 4 SRAM Bitcells are connected to PAD3 to Vdd, PW and VSS are connected to PAD2 to GND, 6T_Iread is measured.

[0046] The Iread measurement results are recorded, and data analysis is performed to evaluate the performance and reliability of the SRAM Bitcells. The data analysis can be performed using at least one of the following methods: mean method, standard deviation method, median method, histogram method, and linear regression method.

[0047] Mean method: Calculate the average value of Iread to obtain the typical read current.

[0048] Standard deviation method: Evaluate the variation of Iread to obtain the dispersion of data.

[0049] Median method: Obtain the median value of Iread to avoid the influence of extreme values.

[0050] Histogram method: Draw a frequency distribution graph of Iread to obtain the distribution form of data.

[0051] Linear regression method: Establish a linear relationship between Iread and time or other variables to predict future Iread values.

[0052] Alternatively, the above embodiments can be applied to Two port SRAM 8T with process nodes less than or equal to 28nm.

[0053] Preferably, all Two port SRAM 8T in the same batch are measured under the same measurement environmental conditions, including temperature and humidity.

[0054] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

[0055] The above detailed description has shown, by way of illustration, the application as described herein but is not construed in a limiting sense as the application is susceptible to numerous variations, combinations, and modifications as would be known to one skilled in the art.

Claims

1. A read measurement method for a two-port SRAM 8T, characterized by, The method comprises the following steps: Providing a 4+4 array design of Two port SRAM Iread; Connecting the RPWL, RPBL, SNL of 4 SRAM Bitcells to PAD1, connecting PAD1 to Vdd, connecting PW and VSS to PAD2 to GND, and measuring RP_Iread; Connecting the WL, BL, SNR of 4 SRAM Bitcells to PAD3 to Vdd, connecting PW and VSS to PAD2 to GND, and measuring 6T_Iread.

2. The Iread metrology method of claim 1, wherein: It can be applied to Two port SRAM 8T of process nodes less than or equal to 28 nm.

3. The Iread metrology method of claim 1, wherein, Further comprising: Recording the Iread measurement results, and evaluating the performance and reliability of the SRAM Bitcell through data analysis.

4. The Iread metrology method of claim 3, wherein, The data analysis at least adopts one of the following methods: mean method, standard deviation method, median method, histogram method, and linear regression method.

5. The Iread metrology method of claim 1, wherein, Further comprising: All Two port SRAM 8Ts in the same batch are measured under the same measurement environment conditions.

6. The Iread metrology method of claim 5, wherein, The measurement environment conditions include temperature and humidity.

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